inline-verilog clarification

Author: bitonic

inline-verilog/README.md

@@ -7,4 +7,6 @@ Currently missing or untested:
 * Multidimensional input/output port, e.g. `reg [15:0] foo [3:0][3:0]` .
 * Importing.
 
-All of the above should be easy, I just didn't bother yet.
+All of the above should be easy, I just didn't bother yet.
+
+Also, `inline-verilog` does not make much sense for non-combinatorial circuits (e.g. stuff that does IO).