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qemu emulate stm32p103 got "Reached end of schedule()" #123

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louisom opened this issue Oct 4, 2016 · 2 comments
Closed

qemu emulate stm32p103 got "Reached end of schedule()" #123

louisom opened this issue Oct 4, 2016 · 2 comments
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@georgekang

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@louisom
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louisom commented Oct 4, 2016 •
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Using QEMU-stm32 to run stm32p103, got reached end of schedule()

using default config file. with arm-none-eabi-gcc version 6.2.0 (I've check this version toolchain can work on stm32f429)

➜  f9-kernel git:(master) ✗ make qemu
  CC      platform/stm32-common/gpio-f1.o
  CC      platform/stm32-common/rcc.o
  CC      platform/stm32-common/mpu.o
  CC      platform/stm32-common/nvic.o
  CC      platform/stm32-common/systick.o
  CC      platform/stm32-common/hwtimer.o
  CC      platform/stm32-common/usart.o
  CC      board/stm32p103/board.o
  CC      platform/bitops.o
  CC      platform/debug_device.o
  CC      platform/mpu.o
  CC      platform/spinlock.o
  CC      platform/irq.o
  CC      platform/debug_uart.o
  CC      platform/kprobes-arch.o
  CC      platform/breakpoint.o
  CC      platform/breakpoint-hard.o
  CC      platform/breakpoint-soft.o
  CC      platform/hw_debug.o
  CC      kernel/lib/queue.o
  CC      kernel/lib/ktable.o
  CC      kernel/lib/stdio.o
  CC      kernel/lib/bsearch.o
  CC      kernel/lib/sort.o
  CC      kernel/lib/memcpy.o
  CC      kernel/lib/memset.o
  CC      kernel/debug.o
  CC      kernel/error.o
  CC      kernel/fpage.o
  CC      kernel/init.o
  CC      kernel/ipc.o
  CC      kernel/kip.o
  CC      kernel/ktimer.o
  CC      kernel/memory.o
  CC      kernel/sched.o
  CC      kernel/softirq.o
  CC      kernel/start.o
  CC      kernel/syscall.o
  CC      kernel/systhread.o
  CC      kernel/thread.o
  CC      kernel/user-log.o
  CC      kernel/interrupt.o
  CC      kernel/kdb.o
  CC      kernel/kprobes.o
  CC      kernel/ksym.o
  CC      kernel/sampling.o
  CC      kernel/sampling-kdb.o
  CC      user/root_thread.o
  CC      user/lib/l4/platform/syscalls.o
  CC      user/lib/l4/pager.o
  CC      user/lib/io/l4io.o
  CC      user/lib/io/user_interrupt.o
  CC      user/lib/libposix/fork.o
  CC      user/lib/libposix/pthread.o
  CC      user/apps/pingpong/main.o
  CC      user/apps/l4test/string.o
  CC      user/apps/l4test/ipc.o
  CC      user/apps/l4test/assert.o
  CC      user/apps/l4test/main.o
  CC      user/apps/spinlock_test/main.o
  LD      f9_nosym.elf
  NM      f9.symmap.o
  LD      f9.elf
  OBJCOPY f9.elf.bin
  CAT     f9.bin
killall -q qemu-system-arm
make: [mk/generic.mk:94: qemu] Error 1 (ignored)
../qemu_stm32/arm-softmmu/qemu-system-arm -M stm32-p103 -kernel build/stm32p103/f9.bin -serial stdio -semihosting

(process:5999): GLib-WARNING **: gmem.c:483: custom memory allocation vtable not supported
STM32_UART: UART1 clock is set to 0 Hz.
STM32_UART: UART1 BRR set to 0.
STM32_UART: UART1 Baud is set to 0 bits per sec.
STM32_UART: UART2 clock is set to 0 Hz.
STM32_UART: UART2 BRR set to 0.
STM32_UART: UART2 Baud is set to 0 bits per sec.
STM32_UART: UART3 clock is set to 0 Hz.
STM32_UART: UART3 BRR set to 0.
STM32_UART: UART3 Baud is set to 0 bits per sec.
STM32_UART: UART4 clock is set to 0 Hz.
STM32_UART: UART4 BRR set to 0.
STM32_UART: UART4 Baud is set to 0 bits per sec.
STM32_UART: UART5 clock is set to 0 Hz.
STM32_UART: UART5 BRR set to 0.
STM32_UART: UART5 Baud is set to 0 bits per sec.
STM32_UART: UART5 clock is set to 0 Hz.
STM32_UART: UART5 BRR set to 0.
STM32_UART: UART5 Baud is set to 0 bits per sec.
STM32_UART: UART4 clock is set to 0 Hz.
STM32_UART: UART4 BRR set to 0.
STM32_UART: UART4 Baud is set to 0 bits per sec.
STM32_UART: UART3 clock is set to 0 Hz.
STM32_UART: UART3 BRR set to 0.
STM32_UART: UART3 Baud is set to 0 bits per sec.
STM32_UART: UART2 clock is set to 0 Hz.
STM32_UART: UART2 BRR set to 0.
STM32_UART: UART2 Baud is set to 0 bits per sec.
STM32_UART: UART1 clock is set to 0 Hz.
STM32_UART: UART1 BRR set to 0.
STM32_UART: UART1 Baud is set to 0 bits per sec.
LED Off
CLKTREE: HSI Output Change (SrcClk:None InFreq:8000000 OutFreq:8000000 Mul:1 Div:1 Enabled:1)
CLKTREE: HSI/2 Output Change (SrcClk:HSI InFreq:8000000 OutFreq:4000000 Mul:1 Div:2 Enabled:1)
CLKTREE: SYSCLK Output Change (SrcClk:HSI InFreq:8000000 OutFreq:8000000 Mul:1 Div:1 Enabled:1)
CLKTREE: HCLK Output Change (SrcClk:SYSCLK InFreq:8000000 OutFreq:8000000 Mul:1 Div:1 Enabled:1)
STM32_RCC: Cortex SYSTICK frequency set to 8000000 Hz (scale set to 125).
STM32_RCC: Cortex SYSTICK ext ref frequency set to 1000000 Hz (scale set to 1000).
CLKTREE: PCLK1 Output Change (SrcClk:HCLK InFreq:8000000 OutFreq:8000000 Mul:1 Div:1 Enabled:1)
CLKTREE: PCLK2 Output Change (SrcClk:HCLK InFreq:8000000 OutFreq:8000000 Mul:1 Div:1 Enabled:1)
CLKTREE: HSE Output Change (SrcClk:None InFreq:8000000 OutFreq:8000000 Mul:1 Div:1 Enabled:1)
CLKTREE: HSE/2 Output Change (SrcClk:HSE InFreq:8000000 OutFreq:4000000 Mul:1 Div:2 Enabled:1)
CLKTREE: PLLXTPRE Output Change (SrcClk:HSE InFreq:8000000 OutFreq:8000000 Mul:1 Div:1 Enabled:1)
CLKTREE: PCLK2 Output Change (SrcClk:HCLK InFreq:8000000 OutFreq:4000000 Mul:1 Div:2 Enabled:1)
CLKTREE: PCLK1 Output Change (SrcClk:HCLK InFreq:8000000 OutFreq:2000000 Mul:1 Div:4 Enabled:1)
CLKTREE: PLLCLK Output Change (SrcClk:HSI/2 InFreq:4000000 OutFreq:32000000 Mul:8 Div:1 Enabled:1)
CLKTREE: SYSCLK Output Change (SrcClk:PLLCLK InFreq:32000000 OutFreq:32000000 Mul:1 Div:1 Enabled:1)
CLKTREE: HCLK Output Change (SrcClk:SYSCLK InFreq:32000000 OutFreq:32000000 Mul:1 Div:1 Enabled:1)
STM32_RCC: Cortex SYSTICK frequency set to 32000000 Hz (scale set to 31).
STM32_RCC: Cortex SYSTICK ext ref frequency set to 4000000 Hz (scale set to 250).
CLKTREE: PCLK1 Output Change (SrcClk:HCLK InFreq:32000000 OutFreq:8000000 Mul:1 Div:4 Enabled:1)
CLKTREE: PCLK2 Output Change (SrcClk:HCLK InFreq:32000000 OutFreq:16000000 Mul:1 Div:2 Enabled:1)
CLKTREE: UART2 Output Change (SrcClk:PCLK1 InFreq:8000000 OutFreq:8000000 Mul:1 Div:1 Enabled:1)
STM32_UART: UART2 clock is set to 8000000 Hz.
STM32_UART: UART2 BRR set to 0.
STM32_UART: UART2 Baud is set to 0 bits per sec.
CLKTREE: GPIOA Output Change (SrcClk:PCLK2 InFreq:16000000 OutFreq:16000000 Mul:1 Div:1 Enabled:1)
STM32_UART: UART2 clock is set to 8000000 Hz.
STM32_UART: UART2 BRR set to 364.
STM32_UART: UART2 Baud is set to 21978 bits per sec.
Reached end of schedule()
-------KTABLES------
-------KTIMER------

ktimer events: 
EVENT    DELTA       
-------NOW------
Now is 0
-------SOFTIRQ------
Kernel timer events              not scheduled
Asynchronous events              not scheduled
System calls                     not scheduled
KDB enters                       not scheduled
-------THREADS------
type  global   local    state  parent
-------MEMPOOLS------
NAME       SIZE       [START   :END     ] FLAGS     
KTEXT           20224 [08001000:08005f00] r-x --- N 
UTEXT            7936 [2000f200:20011100] --- r-x M 
KIP               512 [20000400:20000600] rw- r-- S 
KDATA             911 [20000600:2000098f] rw- --- N 
KBSS            59312 [20000a00:2000f1b0] rw- --- N 
UDATA             768 [20011100:20011400] --- rw- M 
UBSS              256 [20011400:20011500] --- rw- M 
MEM0            43720 [20011538:2001c000] --- rw- S 
KBITMAP            56 [20011500:20011538] rw- --- N 
APB1DEV         30720 [40000000:40007800] --- rw- D 
APB2_1DEV       19456 [40010000:40014c00] --- rw- D 
APB2_2DEV        3072 [40014000:40014c00] --- rw- D 
AHB1_1DEV       15360 [40020000:40023c00] --- rw- D 
AHB1_2DEV      115712 [40023c00:40040000] --- rw- D 
AHB2DEV        397312 [50000000:50061000] --- rw- D 
AHB3DEV    1073745920 [60000000:a0001000] --- rw- D 
-------AS------
-------TOP------
Init sampling...


Stack dump:
20000338 200013b0 08003f0f 08005730 000020ac 00000001 00000000 0000202c 
0000000c 20000618 080057c5 200003e8 08001677 fffffff9 40004400 000020ac 
00000001 0000202c 00000006 0800182f 0800148c 01000200 00000000 0000000d 
080017f1 00000000 00000000 080015b7 0000000a 08002035 00000020 00000020 
00000000 0000e7b0 00000000 00000000 00000000 00000000 00000000 00000000 
00000000 08001ed9 080015fd 200003e4 0000e7b0 08004059 080057c4 200007d8 
00000000 20001380 e000ed24 080040f5 00000000 00000000 00000000 %
@louisom
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louisom commented Oct 4, 2016

Linked without user apps got same result

  CC      user/lib/l4/platform/syscalls.o
  CC      user/lib/l4/pager.o
  CC      user/lib/io/l4io.o
  CC      user/lib/io/user_interrupt.o
  CC      user/lib/libposix/fork.o
  CC      user/lib/libposix/pthread.o
  LD      f9_nosym.elf
  NM      f9.symmap.o
  LD      f9.elf
  OBJCOPY f9.elf.bin
  CAT     f9.bin
killall -q qemu-system-arm
make: [mk/generic.mk:94: qemu] Error 1 (ignored)
../qemu_stm32/arm-softmmu/qemu-system-arm -M stm32-p103 -kernel build/stm32p103/f9.bin -serial stdio -semihosting

(process:7715): GLib-WARNING **: gmem.c:483: custom memory allocation vtable not supported
STM32_UART: UART1 clock is set to 0 Hz.
STM32_UART: UART1 BRR set to 0.
STM32_UART: UART1 Baud is set to 0 bits per sec.
STM32_UART: UART2 clock is set to 0 Hz.
STM32_UART: UART2 BRR set to 0.
STM32_UART: UART2 Baud is set to 0 bits per sec.
STM32_UART: UART3 clock is set to 0 Hz.
STM32_UART: UART3 BRR set to 0.
STM32_UART: UART3 Baud is set to 0 bits per sec.
STM32_UART: UART4 clock is set to 0 Hz.
STM32_UART: UART4 BRR set to 0.
STM32_UART: UART4 Baud is set to 0 bits per sec.
STM32_UART: UART5 clock is set to 0 Hz.
STM32_UART: UART5 BRR set to 0.
STM32_UART: UART5 Baud is set to 0 bits per sec.
STM32_UART: UART5 clock is set to 0 Hz.
STM32_UART: UART5 BRR set to 0.
STM32_UART: UART5 Baud is set to 0 bits per sec.
STM32_UART: UART4 clock is set to 0 Hz.
STM32_UART: UART4 BRR set to 0.
STM32_UART: UART4 Baud is set to 0 bits per sec.
STM32_UART: UART3 clock is set to 0 Hz.
STM32_UART: UART3 BRR set to 0.
STM32_UART: UART3 Baud is set to 0 bits per sec.
STM32_UART: UART2 clock is set to 0 Hz.
STM32_UART: UART2 BRR set to 0.
STM32_UART: UART2 Baud is set to 0 bits per sec.
STM32_UART: UART1 clock is set to 0 Hz.
STM32_UART: UART1 BRR set to 0.
STM32_UART: UART1 Baud is set to 0 bits per sec.
LED Off
CLKTREE: HSI Output Change (SrcClk:None InFreq:8000000 OutFreq:8000000 Mul:1 Div:1 Enabled:1)
CLKTREE: HSI/2 Output Change (SrcClk:HSI InFreq:8000000 OutFreq:4000000 Mul:1 Div:2 Enabled:1)
CLKTREE: SYSCLK Output Change (SrcClk:HSI InFreq:8000000 OutFreq:8000000 Mul:1 Div:1 Enabled:1)
CLKTREE: HCLK Output Change (SrcClk:SYSCLK InFreq:8000000 OutFreq:8000000 Mul:1 Div:1 Enabled:1)
STM32_RCC: Cortex SYSTICK frequency set to 8000000 Hz (scale set to 125).
STM32_RCC: Cortex SYSTICK ext ref frequency set to 1000000 Hz (scale set to 1000).
CLKTREE: PCLK1 Output Change (SrcClk:HCLK InFreq:8000000 OutFreq:8000000 Mul:1 Div:1 Enabled:1)
CLKTREE: PCLK2 Output Change (SrcClk:HCLK InFreq:8000000 OutFreq:8000000 Mul:1 Div:1 Enabled:1)
CLKTREE: HSE Output Change (SrcClk:None InFreq:8000000 OutFreq:8000000 Mul:1 Div:1 Enabled:1)
CLKTREE: HSE/2 Output Change (SrcClk:HSE InFreq:8000000 OutFreq:4000000 Mul:1 Div:2 Enabled:1)
CLKTREE: PLLXTPRE Output Change (SrcClk:HSE InFreq:8000000 OutFreq:8000000 Mul:1 Div:1 Enabled:1)
CLKTREE: PCLK2 Output Change (SrcClk:HCLK InFreq:8000000 OutFreq:4000000 Mul:1 Div:2 Enabled:1)
CLKTREE: PCLK1 Output Change (SrcClk:HCLK InFreq:8000000 OutFreq:2000000 Mul:1 Div:4 Enabled:1)
CLKTREE: PLLCLK Output Change (SrcClk:HSI/2 InFreq:4000000 OutFreq:32000000 Mul:8 Div:1 Enabled:1)
CLKTREE: SYSCLK Output Change (SrcClk:PLLCLK InFreq:32000000 OutFreq:32000000 Mul:1 Div:1 Enabled:1)
CLKTREE: HCLK Output Change (SrcClk:SYSCLK InFreq:32000000 OutFreq:32000000 Mul:1 Div:1 Enabled:1)
STM32_RCC: Cortex SYSTICK frequency set to 32000000 Hz (scale set to 31).
STM32_RCC: Cortex SYSTICK ext ref frequency set to 4000000 Hz (scale set to 250).
CLKTREE: PCLK1 Output Change (SrcClk:HCLK InFreq:32000000 OutFreq:8000000 Mul:1 Div:4 Enabled:1)
CLKTREE: PCLK2 Output Change (SrcClk:HCLK InFreq:32000000 OutFreq:16000000 Mul:1 Div:2 Enabled:1)
CLKTREE: UART2 Output Change (SrcClk:PCLK1 InFreq:8000000 OutFreq:8000000 Mul:1 Div:1 Enabled:1)
STM32_UART: UART2 clock is set to 8000000 Hz.
STM32_UART: UART2 BRR set to 0.
STM32_UART: UART2 Baud is set to 0 bits per sec.
CLKTREE: GPIOA Output Change (SrcClk:PCLK2 InFreq:16000000 OutFreq:16000000 Mul:1 Div:1 Enabled:1)
STM32_UART: UART2 clock is set to 8000000 Hz.
STM32_UART: UART2 BRR set to 364.
STM32_UART: UART2 Baud is set to 21978 bits per sec.
Reached end of schedule()
-------KTABLES------
-------KTIMER------

ktimer events: 
EVENT    DELTA       
-------NOW------
Now is 0
-------SOFTIRQ------
Kernel timer events              not scheduled
Asynchronous events              not scheduled
System calls                     not scheduled
KDB enters                       not scheduled
-------THREADS------
type  global   local    state  parent
-------MEMPOOLS------
NAME       SIZE       [START   :END     ] FLAGS     
KTEXT           19340 [08001000:08005b8c] r-x --- N 
UTEXT            1536 [2000f200:2000f800] --- r-x M 
KIP               512 [20000400:20000600] rw- r-- S 
KDATA             911 [20000600:2000098f] rw- --- N 
KBSS            59312 [20000a00:2000f1b0] rw- --- N 
UDATA             768 [2000f800:2000fb00] --- rw- M 
UBSS                0 [2000fb00:2000fb00] --- rw- M 
MEM0            50376 [2000fb38:2001c000] --- rw- S 
KBITMAP            56 [2000fb00:2000fb38] rw- --- N 
APB1DEV         30720 [40000000:40007800] --- rw- D 
APB2_1DEV       19456 [40010000:40014c00] --- rw- D 
APB2_2DEV        3072 [40014000:40014c00] --- rw- D 
AHB1_1DEV       15360 [40020000:40023c00] --- rw- D 
AHB1_2DEV      115712 [40023c00:40040000] --- rw- D 
AHB2DEV        397312 [50000000:50061000] --- rw- D 
AHB3DEV    1073745920 [60000000:a0001000] --- rw- D 
-------AS------
-------TOP------
Init sampling...


Stack dump:
20000338 200013b0 08003f0f 08005730 000020ac 00000001 00000000 0000202c 
0000000c 20000618 080057c5 200003e8 08001677 fffffff9 40004400 000020ac 
00000001 0000202c 00000006 0800182f 0800148c 01000200 00000000 0000000d 
080017f1 00000000 00000000 080015b7 0000000a 08002035 00000020 00000020 
00000000 0000e7b0 00000000 00000000 00000000 00000000 00000000 00000000 
00000000 08001ed9 080015fd 200003e4 0000e7b0 08004059 080057c4 200007d8 
00000000 20001380 e000ed24 080040f5 00000000 00000000 00000000

@louisom
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louisom commented Oct 8, 2016

Root cause in #127

@louisom louisom closed this as completed Oct 8, 2016
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