Add missing riscv attributes (#560)

* Add missing riscv attributes

- Based on RISCV ELF psABI document: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/2092568f7896ceaa1ec0f02569b19eaa42cd51c9/riscv-elf.adoc?plain=1#L1174

Signed-off-by: Jerry Zhang Jian <[email protected]>

* Add test for more riscv attribute

Signed-off-by: Jerry Zhang Jian <[email protected]>

---------

Signed-off-by: Jerry Zhang Jian <[email protected]>

Author: jerryzj

elftools/elf/descriptions.py

@@ -1013,6 +1013,11 @@ def _reverse_dict(d, low_priority=()):
     TAG_STACK_ALIGN='Tag_RISCV_stack_align: ',
     TAG_ARCH='Tag_RISCV_arch: ',
     TAG_UNALIGNED='Tag_RISCV_unaligned_access: ',
+    TAG_PRIV_SPEC='Tag_RISCV_priv_spec: ',
+    TAG_PRIV_SPEC_MINOR='Tag_RISCV_priv_spec_minor: ',
+    TAG_PRIV_SPEC_REVISION='Tag_RISCV_priv_spec_revision: ',
+    TAG_ATOMIC_ABI='Tag_RISCV_atomic_abi: ',
+    TAG_X3_REG_USAGE='Tag_RISCV_x3_reg_usage: ',
 )
 
 _DESCR_ATTR_VAL_RISCV = [
@@ -1028,4 +1033,19 @@ def _reverse_dict(d, low_priority=()):
         0: 'Not Allowed',
         1: 'Allowed',
     },
+    None, #8 TAG_RISCV_priv_spec
+    None, #10 TAG_RISCV_priv_spec_minor
+    None, #12 TAG_RISCV_priv_spec_revision
+    { #14 TAG_RISCV_atomic_abi
+        0: 'UNKNOWN: This object uses unknown atomic ABI.',
+        1: 'A6C: This object uses the A6 classical atomic ABI.',
+        2: 'A6S: This object uses the strengthened A6 ABI.',
+        3: 'A7: This object uses the A7 atomic ABI.'
+    },
+    { #16 TAG_RISCV_x3_reg_usage
+        0: 'This object uses x3 as a fixed register with unknown purpose.',
+        1: 'This object uses x3 as the global pointer, for relaxation purposes.',
+        2: 'This object uses x3 as the shadow stack pointer.',
+        3: 'This object uses X3 as a temporary register.',
+    },
 ]

elftools/elf/enums.py

@@ -1389,6 +1389,11 @@
     TAG_STACK_ALIGN=4,
     TAG_ARCH=5,
     TAG_UNALIGNED_ACCESS=6,
+    TAG_PRIV_SPEC=8,
+    TAG_PRIV_SPEC_MINOR=10,
+    TAG_PRIV_SPEC_REVISION=12,
+    TAG_ATOMIC_ABI=14,
+    TAG_X3_REG_USAGE=16,
 )
 
 # https://openpowerfoundation.org/wp-content/uploads/2016/03/ABI64BitOpenPOWERv1.1_16July2015_pub4.pdf

test/test_riscv_support.py

@@ -43,5 +43,32 @@ def test_build_attributes(self):
             for i in subsubsec.iter_attributes('TAG_ARCH'):
                 self.assertEqual(i.value, 'rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_v1p0_zfh1p0_zfhmin1p0_zba1p0_zbb1p0_zbc1p0_zbs1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0')
 
+        with open(os.path.join('test', 'testfiles_for_unittests',
+                               'simple_clang.elf.riscv'), 'rb') as f:
+            elf = ELFFile(f)
+
+            sec = elf.get_section_by_name('.riscv.attributes')
+            self.assertEqual(sec['sh_type'], 'SHT_RISCV_ATTRIBUTES')
+            self.assertEqual(sec.num_subsections, 1)
+
+            subsec = sec.subsections[0]
+            self.assertEqual(subsec.header['vendor_name'], 'riscv')
+            self.assertEqual(subsec.num_subsubsections, 1)
+
+            subsubsec = subsec.subsubsections[0]
+            self.assertEqual(subsubsec.header.tag, 'TAG_FILE')
+
+            for i in subsubsec.iter_attributes('TAG_STACK_ALIGN'):
+                self.assertEqual(i.value, 16)
+
+            for i in subsubsec.iter_attributes('TAG_ARCH'):
+                self.assertEqual(i.value, 'rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zmmul1p0_zfh1p0_zba1p0_zbb1p0_zbc1p0_zbs1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0')
+
+            for i in subsubsec.iter_attributes('TAG_PRIV_SPEC'):
+                self.assertEqual(i.value, 1)
+
+            for i in subsubsec.iter_attributes('TAG_PRIV_SPEC_MINOR'):
+                self.assertEqual(i.value, 11)
+
 if __name__ == '__main__':
     unittest.main()

test/testfiles_for_unittests/simple_clang.elf.riscv

@@ -0,0 +1,11 @@
+/*
+ * Compiled using https://github.com/riscv-collab/riscv-gnu-toolchain with
+ * multilib support enabled.
+ *
+ * riscv64-unknown-linux-gnu-clang -march=rv64gcv_zba_zbb_zbc_zbs_zfh -static simple_clang.riscv.c -o simple_clang.elf.riscv
+ */
+
+int main()
+{
+    return 42;
+}