Merge pull request #215 from joecrop/sec-1-9-2024

Added filetype icons and support for syntax highlighting of va/vams

Author: joecrop

README.md

@@ -48,7 +48,7 @@ This VS Code extension provides features to read, navigate and write SystemVeril
 
 ## Settings
 
-- `systemverilog.includeIndexing`: _String_, Files included for indexing \([glob pattern](https://code.visualstudio.com/docs/editor/glob-patterns)\). Examples:
+- `systemverilog.includeIndexing`: _Array_, Files included for indexing \([glob pattern](https://code.visualstudio.com/docs/editor/glob-patterns)\). Examples:
   - Include files within the workspace's rtl folder (`*` at front of pattern denotes path is relative to workspace root): `**/rtl/**/*.{sv,v,svh,vh}`
   - Add all files with a '.svp' extension: `**/*.svp`
   - Add files only when in a specific workspace: `/abs/path/to/workspace/rtl/**/*.{sv,v,svh,vh}`

package.json

@@ -53,10 +53,30 @@
                     "Systemverilog"
                 ],
                 "extensions": [
-                    ".sv",
+                    ".sv"
+                ],
+                "configuration": "./language-configuration.json",
+                "icon": {
+                    "light": "./resources/sv.svg",
+                    "dark": "./resources/sv.svg"
+                }
+            },
+            {
+                "id": "systemverilogheader",
+                "aliases": [
+                    "SystemVerilog",
+                    "systemverilog",
+                    "System Verilog",
+                    "Systemverilog"
+                ],
+                "extensions": [
                     ".svh"
                 ],
-                "configuration": "./language-configuration.json"
+                "configuration": "./language-configuration.json",
+                "icon": {
+                    "light": "./resources/svh.svg",
+                    "dark": "./resources/svh.svg"
+                }
             },
             {
                 "id": "verilog",
@@ -65,10 +85,60 @@
                     "verilog"
                 ],
                 "extensions": [
-                    ".v",
+                    ".v"
+                ],
+                "configuration": "./language-configuration.json",
+                "icon": {
+                    "light": "./resources/v.svg",
+                    "dark": "./resources/v.svg"
+                }
+            },
+            {
+                "id": "verilogheader",
+                "aliases": [
+                    "Verilog",
+                    "verilog"
+                ],
+                "extensions": [
                     ".vh"
                 ],
-                "configuration": "./language-configuration.json"
+                "configuration": "./language-configuration.json",
+                "icon": {
+                    "light": "./resources/vh-light.svg",
+                    "dark": "./resources/vh-dark.svg"
+                }
+            },
+            {
+                "id": "verilogams",
+                "aliases": [
+                    "Verilog-AMS",
+                    "VerilogAMS",
+                    "verilogams"
+                ],
+                "extensions": [
+                    ".vams"
+                ],
+                "configuration": "./language-configuration.json",
+                "icon": {
+                    "light": "./resources/vams.svg",
+                    "dark": "./resources/vams.svg"
+                }
+            },
+            {
+                "id": "veriloga",
+                "aliases": [
+                    "Verilog-A",
+                    "VerilogA",
+                    "veriloga"
+                ],
+                "extensions": [
+                    ".va"
+                ],
+                "configuration": "./language-configuration.json",
+                "icon": {
+                    "light": "./resources/va.svg",
+                    "dark": "./resources/va.svg"
+                }
             }
         ],
         "snippets": [
@@ -79,6 +149,14 @@
             {
                 "language": "verilog",
                 "path": "./snippets/systemverilog.json"
+            },
+            {
+                "language": "systemverilogheader",
+                "path": "./snippets/systemverilog.json"
+            },
+            {
+                "language": "verilogheader",
+                "path": "./snippets/systemverilog.json"
             }
         ],
         "grammars": [
@@ -92,6 +170,26 @@
                 "scopeName": "source.systemverilog",
                 "path": "./syntaxes/systemverilog.tmLanguage.json"
             },
+            {
+                "language": "systemverilogheader",
+                "scopeName": "source.systemverilog",
+                "path": "./syntaxes/systemverilog.tmLanguage.json"
+            },
+            {
+                "language": "verilogheader",
+                "scopeName": "source.systemverilog",
+                "path": "./syntaxes/systemverilog.tmLanguage.json"
+            },
+            {
+                "language": "verilogams",
+                "scopeName": "source.systemverilog",
+                "path": "./syntaxes/systemverilog.tmLanguage.json"
+            },
+            {
+                "language": "veriloga",
+                "scopeName": "source.systemverilog",
+                "path": "./syntaxes/systemverilog.tmLanguage.json"
+            },
             {
                 "scopeName": "markdown.verilog.codeblock",
                 "path": "./syntaxes/codeblock.json",
@@ -455,6 +553,7 @@
         "@types/vscode": "^1.61.0",
         "@typescript-eslint/eslint-plugin": "^5.14.0",
         "@typescript-eslint/parser": "^5.14.0",
+        "@vscode/test-electron": "^2.3.8",
         "antlr4ts-cli": "^0.5.0-alpha.4",
         "eslint": "^8.11.0",
         "eslint-config-airbnb-base": "15.0.0",
@@ -477,7 +576,6 @@
         "webpack-cli": "^4.9.2"
     },
     "dependencies": {
-        "@vscode/test-electron": "^2.3.8",
         "antlr4ts": "^0.5.0-alpha.4",
         "child_process": "^1.0.2",
         "glob": "^7.2.0",