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xxhash.c
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/*
* xxHash - Fast Hash algorithm
* Copyright (C) 2012-2016, Yann Collet
*
* BSD 2-Clause License (http://www.opensource.org/licenses/bsd-license.php)
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following disclaimer
* in the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You can contact the author at :
* - xxHash homepage: http://www.xxhash.com
* - xxHash source repository : https://github.com/Cyan4973/xxHash
*/
/* *************************************
* Tuning parameters
***************************************/
/*!XXH_FORCE_MEMORY_ACCESS :
* By default, access to unaligned memory is controlled by `memcpy()`, which is safe and portable.
* Unfortunately, on some target/compiler combinations, the generated assembly is sub-optimal.
* The below switch allow to select different access method for improved performance.
* Method 0 (default) : use `memcpy()`. Safe and portable.
* Method 1 : `__packed` statement. It depends on compiler extension (ie, not portable).
* This method is safe if your compiler supports it, and *generally* as fast or faster than `memcpy`.
* Method 2 : direct access. This method doesn't depend on compiler but violate C standard.
* It can generate buggy code on targets which do not support unaligned memory accesses.
* But in some circumstances, it's the only known way to get the most performance (ie GCC + ARMv6)
* See http://stackoverflow.com/a/32095106/646947 for details.
* Prefer these methods in priority order (0 > 1 > 2)
*/
#ifndef XXH_FORCE_MEMORY_ACCESS /* can be defined externally, on command line for example */
# if defined(__GNUC__) && (defined(__ARM_ARCH) && __ARM_ARCH == 6)
# define XXH_FORCE_MEMORY_ACCESS 2
# elif (defined(__INTEL_COMPILER) && !defined(_WIN32)) || \
(defined(__GNUC__) && \
(defined(__aarch64__) || defined(__arm64__) || \
(defined(__ARM_ARCH) && __ARM_ARCH == 7)) )
# define XXH_FORCE_MEMORY_ACCESS 1
# endif
#endif
/*!XXH_ACCEPT_NULL_INPUT_POINTER :
* If input pointer is NULL, xxHash default behavior is to dereference it, triggering a segfault.
* When this macro is enabled, xxHash actively checks input for null pointer.
* It it is, result for null input pointers is the same as a null-length input.
*/
#ifndef XXH_ACCEPT_NULL_INPUT_POINTER /* can be defined externally */
# define XXH_ACCEPT_NULL_INPUT_POINTER 0
#endif
/*!XXH_FORCE_NATIVE_FORMAT :
* By default, xxHash library provides endian-independent Hash values, based on little-endian convention.
* Results are therefore identical for little-endian and big-endian CPU.
* This comes at a performance cost for big-endian CPU, since some swapping is required to emulate little-endian format.
* Should endian-independence be of no importance for your application, you may set the #define below to 1,
* to improve speed for Big-endian CPU.
* This option has no impact on Little_Endian CPU.
*/
#ifndef XXH_FORCE_NATIVE_FORMAT /* can be defined externally */
# define XXH_FORCE_NATIVE_FORMAT 0
#endif
/*!XXH_FORCE_ALIGN_CHECK :
* This is a minor performance trick, only useful with lots of very small keys
* or on platforms with an unaligned access penalty.
*
* It means : check for aligned/unaligned input.
* The check costs one initial branch per hash;
* set it to 0 when the input is guaranteed to be aligned,
* or when alignment doesn't matter for performance.
*
* For example, Nehalem (SSE4.2) and ARMv7 have no unaligned
* access penalty. Disabling this check can increase performance.
*
* However, on a Core 2, which has an unaligned access penalty, enabling
* these checks is the difference between 3.4 GB/s and 4.9 GB/s in XXH32a
* on GCC 8.1.
*
* We combine this with our dispatch check when not specificially targeting
* Nehalem or newer processors.
*/
#ifndef XXH_FORCE_ALIGN_CHECK /* can be defined externally */
# if defined(__SSE4_2__) || defined(__AVX__) || defined(__ARM_NEON__) || defined(__ARM_NEON)
# define XXH_FORCE_ALIGN_CHECK 0
# elif defined(__i386__) || defined(__x86_64__)
# define XXH_FORCE_ALIGN_CHECK XXH_CPU_IS_PRE_NEHALEM
# else
# define XXH_FORCE_ALIGN_CHECK 1
# endif
#endif
/* *************************************
* Compiler Specific Options
***************************************/
#ifdef _MSC_VER /* Visual Studio */
# pragma warning(disable : 4127) /* disable: C4127: conditional expression is constant */
# define FORCE_INLINE static __forceinline
#else
# if defined (__cplusplus) || defined (__STDC_VERSION__) && __STDC_VERSION__ >= 199901L /* C99 */
# ifdef __GNUC__
# define FORCE_INLINE static inline __attribute__((__always_inline__, __unused__))
# else
# define FORCE_INLINE static inline
# endif
# else
# ifdef __GNUC__
# define FORCE_INLINE static __inline__
# else
# define FORCE_INLINE static
# endif
# endif /* __STDC_VERSION__ */
#endif
/* Inline assembly guards. These are used to disable unwanted vectorization or
* instruction combining. */
#if defined(__GNUC__) && !defined(XXH_FORCE_VECTOR)
# define XXH_FORCE_NORMAL_REG(reg) __asm__ __volatile__("" : "+r" (reg))
# define XXH_FORCE_NORMAL_REG_READONLY(reg) __asm__ __volatile__("" :: "r" (reg))
# if defined(__ARM_NEON__) || defined(__ARM_NEON)
# define XXH_VEC_CONSTRAINT "w"
# elif defined(__SSE2__)
# define XXH_VEC_CONSTRAINT "x"
# else
# define XXH_VEC_CONSTRAINT "g"
# endif
# define XXH_FORCE_VECTOR_REG(reg) __asm__ __volatile__("" : "+" XXH_VEC_CONSTRAINT (reg))
# define XXH_FORCE_VECTOR_REG_READONLY(reg) __asm__ __volatile__("" :: XXH_VEC_CONSTRAINT (reg))
#else
# define XXH_FORCE_NORMAL_REG(reg) do {} while (0)
# define XXH_FORCE_VECTOR_REG(reg) do {} while (0)
# define XXH_FORCE_NORMAL_REG_READONLY(reg) do {} while (0)
# define XXH_FORCE_VECTOR_REG_READONLY(reg) do {} while (0)
#endif
/* *************************************
* Includes & Memory related functions
***************************************/
/*! Modify the local functions below should you wish to use some other memory routines
* for malloc(), free() */
#include <stdlib.h>
FORCE_INLINE void* XXH_malloc(size_t s) { return malloc(s); }
FORCE_INLINE void XXH_free (void* p) { free(p); }
/*! and for memcpy() */
#include <string.h>
#ifdef __GNUC__
/* __builtin_memcpy can often generate better code. */
FORCE_INLINE void* XXH_memcpy(void* dest, const void* src, size_t size) { return __builtin_memcpy(dest,src,size); }
#else
FORCE_INLINE void* XXH_memcpy(void* dest, const void* src, size_t size) { return memcpy(dest,src,size); }
#endif
#include <assert.h> /* assert */
#define XXH_STATIC_LINKING_ONLY
#include "xxhash.h"
/* On Thumb 1, GCC decides that shift/add is __always__ faster than
* multiplication via a constant, even when it generates 8 times as many
* instructions and twice as many CPU cycles.
*
* If we lie to GCC and tell it that the value is not constant, then it
* will disable this "optimization".
* Clang, normal ARM, and Thumb-2 are not affected, and Clang even amusingly
* converts GCC's shift/add mess back into multiplication.
* https://godbolt.org/z/2vc82a */
#if defined(__thumb__) && !defined(__thumb2__) && !defined(__ARM_ARCH_V6M__) \
&& defined(__GNUC__) && !defined(__clang__)
#define CONSTANT __attribute__((visibility("hidden")))
#else
#define CONSTANT static const
#endif
/* *************************************
* Basic Types
***************************************/
#ifndef MEM_MODULE
# if !defined (__VMS) \
&& (defined (__cplusplus) \
|| (defined (__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L) /* C99 */) )
# include <stdint.h>
typedef uint8_t BYTE;
typedef uint16_t U16;
typedef uint32_t U32;
#ifndef XXH_NO_LONG_LONG
typedef uint64_t U64;
#endif
# else
typedef unsigned char BYTE;
typedef unsigned short U16;
typedef unsigned int U32;
#ifndef XXH_NO_LONG_LONG
typedef unsigned long long U64;
#endif
# endif
#endif
#if (defined(XXH_FORCE_MEMORY_ACCESS) && (XXH_FORCE_MEMORY_ACCESS==2))
/* Force direct memory access. Only works on CPU which support unaligned memory access in hardware */
FORCE_INLINE U32 XXH_read32(const void* memPtr) { return *(const U32*) memPtr; }
#elif (defined(XXH_FORCE_MEMORY_ACCESS) && (XXH_FORCE_MEMORY_ACCESS==1))
/* __pack instructions are safer, but compiler specific, hence potentially problematic for some compilers */
/* currently only defined for gcc and icc */
typedef union { U32 u32; } __attribute__((packed)) unalign;
FORCE_INLINE U32 XXH_read32(const void* ptr) { return ((const unalign*)ptr)->u32; }
#else
/* portable and safe solution. Generally efficient.
* see : http://stackoverflow.com/a/32095106/646947
*/
FORCE_INLINE U32 XXH_read32(const void* memPtr)
{
U32 val;
XXH_memcpy(&val, memPtr, sizeof(val));
return val;
}
#endif /* XXH_FORCE_DIRECT_MEMORY_ACCESS */
/* Set up our simple CPU dispatcher. */
#if defined(__GNUC__) && (defined(__x86_64__) || defined(__i386__)) \
&& !defined(XXH_NO_DISPATCH)
/* A friendly bitfield to clarify the eax value for cpuid when
* EAX=1.
* https://en.wikipedia.org/wiki/CPUID */
struct eax_data {
/* cppcheck-suppress unusedStructMember */
unsigned steppingID : 4;
unsigned model : 4;
unsigned familyID : 4;
/* cppcheck-suppress unusedStructMember */
unsigned type : 2;
/* cppcheck-suppress unusedStructMember */
unsigned reserved : 2;
unsigned extModelID : 4;
/* cppcheck-suppress unusedStructMember */
unsigned extFamilyID : 8;
/* cppcheck-suppress unusedStructMember */
unsigned reserved2 : 4;
};
union eax {
struct eax_data eax;
unsigned val;
};
FORCE_INLINE unsigned XXH_parseEAX(union eax eax_val)
{
if (eax_val.eax.familyID != 6) return 0;
return (eax_val.eax.extModelID << 4) + (eax_val.eax.model);
}
/* Nehalem (First gen Core iN) and later have a few handy features that make huge
* differences in the hash performance.
*
* First of all, Nehalem speeds up imulq to a 3 cycle latency, instead of earlier
* 64-bit chips which have a 7 cycle latency. This change is enough to make
* XXH32a/XXH64a faster than XXH64, despite the slower pmulld. We use this
* knowledge to select XXH64a or XXH32a on these processors in the autoselect
* hashes.
*
* Credit goes to https://www.agner.org/optimize/instruction_tables.pdf for this
* information.
*
* Additionally, Nehalem doesn't have a penalty for unaligned SSE reads, so
* checking for aligned inputs ends up being slower than just using unaligned
* reads each time. */
static int XXH_CPU_IS_PRE_NEHALEM = 0;
/* Sandy Bridge sped up the shld instruction to go from slower than rol to faster,
* and it is beneficial for performance. XXH32 is 1.01x faster, but XXH64 is 1.25x
* faster, being the difference between 8.7 GB/s and 10.4 GB/s.
*
* Clang will choose it automatically when targeting Sandy Bridge, however, because
* it incorrectly adds an excessive register swap, it has to be done with inline
* assembly.
*
* To maximize compatibility and speed, we check for this at runtime before doing
* the main loop. */
static int XXH_CPU_USE_SHLD = 0;
static const U32 NEHALEM_ID = 0x1A;
static const U32 SANDY_BRIDGE_ID = 0x2A;
/* This detects the CPU type so we can do some simple dispatching.
* We currently check for two things:
* 1. Is the CPU older than Nehalem (a.k.a. Core 2 or earlier/Penryn family)?
* 2. Is the CPU a Sandy Bridge or newer (2nd gen Core i-series)?
*
* AMD CPUs don't require or benefit from these optimizations.
*
* __attribute__((__constructor__)) is a useful GCC feature which forces a function
* to be called before main(). This is basically the same thing that icc does,
* and it saves us the trouble of checking whether we ran the function. Additionally,
* even if xxhash is dynamically loaded and this does not run, the defaults aren't
* going to break anything.
*
* TODO: maybe add MSVC support. It would probably require a manual hook because
* I don't think MSVC supports a __constructor__ equivalent. */
__attribute__((__constructor__))
FORCE_INLINE void XXH_cpuID(void)
{
/* Call cpuid with a zero for manufacturer ID. */
unsigned a = 0;
unsigned vendor_string[3];
__asm__("cpuid"
: "+a" (a), "=b" (vendor_string[0]), "=c" (vendor_string[2]), "=d" (vendor_string[1]));
assert(a >= 1); /* should always be true, but keeps cppcheck happy */
/* We only want to check Intel chips. AMD doesn't really have much of a penalty. */
if (memcmp(vendor_string, "GenuineIntel", 12) == 0) {
union eax eax_val;
unsigned model;
/* Call it with a 1 for the chip ID. */
a = 1;
__asm__("cpuid" : "+a" (a) :: "%ebx", "%ecx", "%edx");
eax_val.val = a;
model = XXH_parseEAX(eax_val);
if (model >= SANDY_BRIDGE_ID) {
XXH_CPU_USE_SHLD = 1;
}
if (model < NEHALEM_ID) {
XXH_CPU_IS_PRE_NEHALEM = 1;
}
}
}
#else
/* Doesn't really apply. */
#define XXH_CPU_USE_SHLD 0
#define XXH_CPU_IS_PRE_NEHALEM 0
#endif
/* ****************************************
* Compiler-specific Functions and Macros
******************************************/
#define XXH_GCC_VERSION (__GNUC__ * 100 + __GNUC_MINOR__)
/* Clang's __has_builtin because checking clang versions is impossible,
* thank you Apple. */
#ifndef __has_builtin
# define __has_builtin(x) 0
#endif
#if XXH_GCC_VERSION >= 407 || __has_builtin(__builtin_assume_aligned)
# define XXH_assume_aligned(p, align) __builtin_assume_aligned((p), (align))
#else
# define XXH_assume_aligned(p, align) (p)
#endif
/* Unrolling loops, especially on ARM, is beneficial for most cases. We aim for
* 4 unrolls. Doing this with a pragma is much easier and less prone to copy-paste
* errors, as the compiler will put a runtime trip inside to do this.
* We don't unroll with -Os/-Oz, or when XXH_INLINE_ALL. The first is to reduce
* size (obviously), and the second is to avoid cache miss hell. */
#if defined(__OPTIMIZE_SIZE__) || defined(XXH_INLINE_ALL)
# define UNROLL
#elif defined(__clang__)
# define UNROLL _Pragma("clang loop unroll_count(4)")
#elif XXH_GCC_VERSION >= 800
# define UNROLL _Pragma("GCC unroll 4")
#else
# define UNROLL
#endif
/* Note : although _rotl exists for minGW (GCC under windows), performance seems poor */
#if defined(_MSC_VER)
# define XXH_rotl32(x,r) _rotl(x,r)
# define XXH_rotl64(x,r) _rotl64(x,r)
#else
# define XXH_rotl32(x,r) ((x << (r & 31)) | (x >> (32 - (r & 31))))
# define XXH_rotl64(x,r) ((x << (r & 63)) | (x >> (64 - (r & 63))))
#endif
#if defined(_MSC_VER) /* Visual Studio */
# define XXH_swap32 _byteswap_ulong
#elif XXH_GCC_VERSION >= 403
# define XXH_swap32 __builtin_bswap32
#else
static U32 XXH_swap32 (U32 x)
{
return ((x << 24) & 0xff000000 ) |
((x << 8) & 0x00ff0000 ) |
((x >> 8) & 0x0000ff00 ) |
((x >> 24) & 0x000000ff );
}
#endif
/* *************************************
* Architecture Macros
***************************************/
typedef enum { XXH_bigEndian=0, XXH_littleEndian=1 } XXH_endianess;
/* XXH_CPU_LITTLE_ENDIAN can be defined externally, for example on the compiler command line */
#ifndef XXH_CPU_LITTLE_ENDIAN
# if defined(__LITTLE_ENDIAN__) || defined(_WIN32) /* Windows is always little endian */
# define XXH_CPU_LITTLE_ENDIAN XXH_littleEndian
# undef XXH_FORCE_NATIVE_FORMAT /* Force native format */
# define XXH_FORCE_NATIVE_FORMAT 1
# elif defined(__BIG_ENDIAN__)
# define XXH_CPU_LITTLE_ENDIAN XXH_bigEndian
# else
static XXH_endianess XXH_isLittleEndian(void)
{
union { U32 u; BYTE c[4]; } one; /* don't use static : performance detrimental */
one.u = 1;
return one.c[0] ? XXH_littleEndian : XXH_bigEndian;
}
# define XXH_CPU_LITTLE_ENDIAN XXH_isLittleEndian()
# endif
#endif
/* ***************************
* Memory reads
*****************************/
typedef enum { XXH_aligned, XXH_unaligned } XXH_alignment;
FORCE_INLINE U32 XXH_readLE32_align(const void* ptr, XXH_endianess endian, XXH_alignment align)
{
if (align==XXH_unaligned)
return (endian==XXH_littleEndian || XXH_FORCE_NATIVE_FORMAT) ? XXH_read32(ptr) : XXH_swap32(XXH_read32(ptr));
else
return (endian==XXH_littleEndian || XXH_FORCE_NATIVE_FORMAT) ? *(const U32*)ptr : XXH_swap32(*(const U32*)ptr);
}
FORCE_INLINE U32 XXH_readLE32(const void* ptr, XXH_endianess endian)
{
return XXH_readLE32_align(ptr, endian, XXH_unaligned);
}
static U32 XXH_readBE32(const void* ptr)
{
return XXH_CPU_LITTLE_ENDIAN ? XXH_swap32(XXH_read32(ptr)) : XXH_read32(ptr);
}
/* *************************************
* Macros
***************************************/
#define XXH_STATIC_ASSERT(c) { enum { XXH_sa = 1/(int)(!!(c)) }; } /* use after variable declarations */
XXH_PUBLIC_API unsigned XXH_versionNumber (void) { return XXH_VERSION_NUMBER; }
/* *******************************************************************
* 32-bit hash functions
*********************************************************************/
CONSTANT U32 PRIME32_1 = 2654435761U; /* 0b10011110001101110111100110110001 */
CONSTANT U32 PRIME32_2 = 2246822519U; /* 0b10000101111010111100101001110111 */
CONSTANT U32 PRIME32_3 = 3266489917U; /* 0b11000010101100101010111000111101 */
CONSTANT U32 PRIME32_4 = 668265263U; /* 0b00100111110101001110101100101111 */
CONSTANT U32 PRIME32_5 = 374761393U; /* 0b00010110010101100110011110110001 */
#ifndef XXH_NO_LONG_LONG
CONSTANT U64 PRIME64_1 = 11400714785074694791ULL; /* 0b1001111000110111011110011011000110000101111010111100101010000111 */
CONSTANT U64 PRIME64_2 = 14029467366897019727ULL; /* 0b1100001010110010101011100011110100100111110101001110101101001111 */
CONSTANT U64 PRIME64_3 = 1609587929392839161ULL; /* 0b0001011001010110011001111011000110011110001101110111100111111001 */
CONSTANT U64 PRIME64_4 = 9650029242287828579ULL; /* 0b1000010111101011110010100111011111000010101100101010111001100011 */
CONSTANT U64 PRIME64_5 = 2870177450012600261ULL; /* 0b0010011111010100111010110010111100010110010101100110011111000101 */
#endif
#if (defined(__i386__) || defined(__x86_64__)) && defined(__GNUC__) && !defined(XXH_FORCE_VECTOR)
/* Dispatched for Sandy Bridge or later.
* shld went from slower than rol to faster in this iteration
* for some weird reason. */
FORCE_INLINE U32 XXH32_round_shld(U32 seed, U32 input)
{
/* Inline assembly forces the fastest code */
__asm__(
"imull %[prime2], %[input]\n" /* input *= PRIME32_2; */
"addl %[input], %[seed]\n" /* seed += input; */
"shldl $13, %[seed], %[seed]\n" /* seed = XXH_rotl32(seed, 13); */
"imull %[prime1], %[seed]" /* seed *= PRIME32_1; */
: [seed] "+r" (seed), [input] "+r" (input)
: [prime2] "r" (PRIME32_2), [prime1] "r" (PRIME32_1));
return seed;
}
#else
/* shouldn't happen */
#define XXH32_round_shld XXH32_round
#endif
FORCE_INLINE U32 XXH32_round(U32 seed, U32 input)
{
seed += input * PRIME32_2;
seed = XXH_rotl32(seed, 13);
seed *= PRIME32_1;
/* UGLY HACK:
* Clang and GCC don't vectorize XXH32 well for SSE4.1, and will actually slow
* down XXH32 compared to the normal version, which uses instruction level
* parallelism to make up for the lack of vectorization.
*
* Previously, the workaround was to globally disable it with -mno-sse4.
* However, that makes it so XXH32a cannot vectorize, and that the vectorization
* was the whole point of XXH32a.
*
* When we actually intend to use SSE code, we use the rounding code directly.
*
* Define XXH_FORCE_VECTOR to disable. */
XXH_FORCE_NORMAL_REG(seed);
return seed;
}
/* mix all bits */
static U32 XXH32_avalanche(U32 h32)
{
h32 ^= h32 >> 15;
h32 *= PRIME32_2;
h32 ^= h32 >> 13;
h32 *= PRIME32_3;
h32 ^= h32 >> 16;
return(h32);
}
#if (!defined(XXH_VECTORIZE) || XXH_VECTORIZE)
# if defined(__has_include)
# if __has_include("xxhash-vec.h")
# include "xxhash-vec.h"
# else
# undef XXH_VECTORIZE
# define XXH_VECTORIZE 0
# endif
# else
# include "xxhash-vec.h" /* define XXH_VECTORIZE=0 to disable */
# endif
#endif
#define XXH_get32bits(p) XXH_readLE32_align(p, endian, align)
static U32
XXH32_finalize(U32 h32, const void* ptr, size_t len,
XXH_endianess endian, XXH_alignment align)
{
const BYTE* p = (const BYTE*)ptr;
#define PROCESS1 \
h32 += (*p++) * PRIME32_5; \
h32 = XXH_rotl32(h32, 11) * PRIME32_1 ;
#define PROCESS4 \
h32 += XXH_get32bits(p) * PRIME32_3; \
p+=4; \
h32 = XXH_rotl32(h32, 17) * PRIME32_4 ;
switch(len&31) /* or switch(bEnd - p) */
{
case 28: PROCESS4;
/* fallthrough */
case 24: PROCESS4;
/* fallthrough */
case 20: PROCESS4;
/* fallthrough */
case 16: PROCESS4;
/* fallthrough */
case 12: PROCESS4;
/* fallthrough */
case 8: PROCESS4;
/* fallthrough */
case 4: PROCESS4;
return XXH32_avalanche(h32);
case 29: PROCESS4;
/* fallthrough */
case 25: PROCESS4;
/* fallthrough */
case 21: PROCESS4;
/* fallthrough */
case 17: PROCESS4;
/* fallthrough */
case 13: PROCESS4;
/* fallthrough */
case 9: PROCESS4;
/* fallthrough */
case 5: PROCESS4;
PROCESS1;
return XXH32_avalanche(h32);
case 30: PROCESS4;
/* fallthrough */
case 26: PROCESS4;
/* fallthrough */
case 22: PROCESS4;
/* fallthrough */
case 18: PROCESS4;
/* fallthrough */
case 14: PROCESS4;
/* fallthrough */
case 10: PROCESS4;
/* fallthrough */
case 6: PROCESS4;
PROCESS1;
PROCESS1;
return XXH32_avalanche(h32);
case 31: PROCESS4;
/* fallthrough */
case 27: PROCESS4;
/* fallthrough */
case 23: PROCESS4;
/* fallthrough */
case 19: PROCESS4;
/* fallthrough */
case 15: PROCESS4;
/* fallthrough */
case 11: PROCESS4;
/* fallthrough */
case 7: PROCESS4;
/* fallthrough */
case 3: PROCESS1;
/* fallthrough */
case 2: PROCESS1;
/* fallthrough */
case 1: PROCESS1;
/* fallthrough */
case 0: return XXH32_avalanche(h32);
}
assert(0);
return h32; /* reaching this point is deemed impossible */
}
FORCE_INLINE U32
XXH32_endian_align(const void* input, size_t len, U32 seed,
XXH_endianess endian, XXH_alignment align)
{
const BYTE* p = (const BYTE*)input;
const BYTE* bEnd = p + len;
/* cppcheck flags this as unused because it doesn't know how to parse _Pragma. */
/* cppcheck-suppress unusedVariable */
U32 h32;
#if defined(XXH_ACCEPT_NULL_INPUT_POINTER) && (XXH_ACCEPT_NULL_INPUT_POINTER>=1)
if (p==NULL) {
len=0;
bEnd=p=(const BYTE*)(size_t)16;
}
#endif
#ifdef XXH_NEON
if (len>=16 && endian==XXH_littleEndian) {
/* This is where NEON gets its special treatment, as it performs
* terribly with the non-vectorized one. */
XXH_ALIGN_16
U32 vx1[4] = {
PRIME32_1 + PRIME32_2,
PRIME32_2,
0,
-PRIME32_1
};
U32x4 v = XXH_vec_load_unaligned(vx1);
const U32x4 prime1 = vdupq_n_u32(PRIME32_1);
const U32x4 prime2 = vdupq_n_u32(PRIME32_2);
const BYTE* const limit = bEnd - 15;
v += vdupq_n_u32(seed);
UNROLL do {
const U32x4 inp = XXH_vec_load_unaligned((const U32 *)p);
v = v + (inp * prime2);
v = XXH_vec_rotl32(v, 13);
v = v * prime1;
p += 16;
} while (p < limit);
{
const U32x4 r = { 1, 7, 12, 18 };
v = XXH_rotlvec_vec32(v, r);
}
XXH_vec_store_unaligned(vx1, v);
h32 = vx1[0] + vx1[1] + vx1[2] + vx1[3];
} else
#endif /* XXH_NEON */
if (len>=16) {
U32 v1 = seed + PRIME32_1 + PRIME32_2;
U32 v2 = seed + PRIME32_2;
U32 v3 = seed + 0;
U32 v4 = seed - PRIME32_1;
const BYTE* limit = bEnd - 15;
/* Avoid branching when we don't have to. This helps out ARM Thumb a lot. */
if (XXH_FORCE_ALIGN_CHECK && align==XXH_aligned && endian==XXH_littleEndian) {
UNROLL do {
const U32* palign = (const U32*)XXH_assume_aligned(p, 4);
v1 = XXH32_round(v1, palign[0]); p+=4;
v2 = XXH32_round(v2, palign[1]); p+=4;
v3 = XXH32_round(v3, palign[2]); p+=4;
v4 = XXH32_round(v4, palign[3]); p+=4;
} while (p < limit);
} else if (XXH_CPU_USE_SHLD) {
UNROLL do {
v1 = XXH32_round_shld(v1, XXH_get32bits(p)); p+=4;
v2 = XXH32_round_shld(v2, XXH_get32bits(p)); p+=4;
v3 = XXH32_round_shld(v3, XXH_get32bits(p)); p+=4;
v4 = XXH32_round_shld(v4, XXH_get32bits(p)); p+=4;
} while (p < limit);
} else {
UNROLL do {
v1 = XXH32_round(v1, XXH_get32bits(p)); p+=4;
v2 = XXH32_round(v2, XXH_get32bits(p)); p+=4;
v3 = XXH32_round(v3, XXH_get32bits(p)); p+=4;
v4 = XXH32_round(v4, XXH_get32bits(p)); p+=4;
} while (p < limit);
}
h32 = XXH_rotl32(v1, 1) + XXH_rotl32(v2, 7)
+ XXH_rotl32(v3, 12) + XXH_rotl32(v4, 18);
} else {
h32 = seed + PRIME32_5;
}
h32 += (U32)len;
return XXH32_finalize(h32, p, len&15, endian, align);
}
XXH_PUBLIC_API unsigned int XXH32 (const void* input, size_t len, unsigned int seed)
{
#if 0
/* Simple version, good for code maintenance, but unfortunately slow for small inputs */
XXH32_state_t state;
XXH32_reset(&state, seed);
XXH32_update(&state, input, len);
return XXH32_digest(&state);
#else
XXH_endianess endian_detected = (XXH_endianess)XXH_CPU_LITTLE_ENDIAN;
if ((XXH_FORCE_ALIGN_CHECK)
&& (((size_t)input) & 3) == 0) { /* Input is 4-bytes aligned, leverage the speed benefit */
if ((endian_detected==XXH_littleEndian) || XXH_FORCE_NATIVE_FORMAT)
return XXH32_endian_align(input, len, seed, XXH_littleEndian, XXH_aligned);
else
return XXH32_endian_align(input, len, seed, XXH_bigEndian, XXH_aligned);
}
if ((endian_detected==XXH_littleEndian) || XXH_FORCE_NATIVE_FORMAT)
return XXH32_endian_align(input, len, seed, XXH_littleEndian, XXH_unaligned);
else
return XXH32_endian_align(input, len, seed, XXH_bigEndian, XXH_unaligned);
#endif
}
/*====== Hash streaming ======*/
XXH_PUBLIC_API XXH32_state_t* XXH32_createState(void)
{
return (XXH32_state_t*)XXH_malloc(sizeof(XXH32_state_t));
}
XXH_PUBLIC_API XXH_errorcode XXH32_freeState(XXH32_state_t* statePtr)
{
XXH_free(statePtr);
return XXH_OK;
}
XXH_PUBLIC_API void XXH32_copyState(XXH32_state_t* dstState, const XXH32_state_t* srcState)
{
XXH_memcpy(dstState, srcState, sizeof(*dstState));
}
XXH_PUBLIC_API XXH_errorcode XXH32_reset(XXH32_state_t* statePtr, unsigned int seed)
{
XXH32_state_t state; /* using a local state to memcpy() in order to avoid strict-aliasing warnings */
memset(&state, 0, sizeof(state));
state.v1 = seed + PRIME32_1 + PRIME32_2;
state.v2 = seed + PRIME32_2;
state.v3 = seed + 0;
state.v4 = seed - PRIME32_1;
/* do not write into reserved, planned to be removed in a future version */
XXH_memcpy(statePtr, &state, sizeof(state) - sizeof(state.reserved));
return XXH_OK;
}
FORCE_INLINE XXH_errorcode
XXH32_update_endian(XXH32_state_t* state, const void* input, size_t len, XXH_endianess endian)
{
if (input==NULL)
#if defined(XXH_ACCEPT_NULL_INPUT_POINTER) && (XXH_ACCEPT_NULL_INPUT_POINTER>=1)
return XXH_OK;
#else
return XXH_ERROR;
#endif
{ const BYTE* p = (const BYTE*)input;
const BYTE* const bEnd = p + len;
state->total_len_32 += (unsigned)len;
state->large_len |= (len>=16) | (state->total_len_32>=16);
if (state->memsize + len < 16) { /* fill in tmp buffer */
XXH_memcpy((BYTE*)(state->mem32) + state->memsize, input, len);
state->memsize += (unsigned)len;
return XXH_OK;
}
if (state->memsize) { /* some data left from previous update */
XXH_memcpy((BYTE*)(state->mem32) + state->memsize, input, 16-state->memsize);
{ const U32* p32 = state->mem32;
state->v1 = XXH32_round(state->v1, XXH_readLE32(p32, endian)); p32++;
state->v2 = XXH32_round(state->v2, XXH_readLE32(p32, endian)); p32++;
state->v3 = XXH32_round(state->v3, XXH_readLE32(p32, endian)); p32++;
state->v4 = XXH32_round(state->v4, XXH_readLE32(p32, endian));
}
p += 16-state->memsize;
}
state->memsize = 0;
if (p <= bEnd-16) {
XXH_ALIGN_16
U32 v1 = state->v1;
U32 v2 = state->v2;
U32 v3 = state->v3;
U32 v4 = state->v4;
const BYTE* const limit = bEnd - 16;
/* Aligned pointers and fewer branches are very helpful and worth the
* duplication on ARM. */
if (XXH_FORCE_ALIGN_CHECK && ((size_t)p&3)==0 && endian==XXH_littleEndian) {
UNROLL do {
const U32* p_align = (const U32*)XXH_assume_aligned(p, 4);
/* NO SSE */
v1 = XXH32_round(v1, p_align[0]);
v2 = XXH32_round(v2, p_align[1]);
v3 = XXH32_round(v3, p_align[2]);
v4 = XXH32_round(v4, p_align[3]);
p += 16;
} while (p <= limit);
} else {
UNROLL do {
/* NO SSE */
v1 = XXH32_round(v1, XXH_readLE32(p, endian));
v2 = XXH32_round(v2, XXH_readLE32(p + 4, endian));
v3 = XXH32_round(v3, XXH_readLE32(p + 8, endian));
v4 = XXH32_round(v4, XXH_readLE32(p + 12, endian));
p += 16;
} while (p<=limit);
}
state->v1 = v1;
state->v2 = v2;
state->v3 = v3;
state->v4 = v4;
}
if (p < bEnd) {
XXH_memcpy(state->mem32, p, (size_t)(bEnd-p));
state->memsize = (unsigned)(bEnd-p);
}
}
return XXH_OK;
}
XXH_PUBLIC_API XXH_errorcode XXH32_update (XXH32_state_t* state_in, const void* input, size_t len)
{
XXH_endianess endian_detected = (XXH_endianess)XXH_CPU_LITTLE_ENDIAN;
if ((endian_detected==XXH_littleEndian) || XXH_FORCE_NATIVE_FORMAT)
return XXH32_update_endian(state_in, input, len, XXH_littleEndian);
else
return XXH32_update_endian(state_in, input, len, XXH_bigEndian);
}
FORCE_INLINE U32
XXH32_digest_endian (const XXH32_state_t* state, XXH_endianess endian)
{
U32 h32;
if (state->large_len) {
h32 = XXH_rotl32(state->v1, 1)
+ XXH_rotl32(state->v2, 7)
+ XXH_rotl32(state->v3, 12)
+ XXH_rotl32(state->v4, 18);
} else {
h32 = state->v3 /* == seed */ + PRIME32_5;
}
h32 += state->total_len_32;
return XXH32_finalize(h32, state->mem32, state->memsize&15, endian, XXH_aligned);
}
XXH_PUBLIC_API unsigned int XXH32_digest (const XXH32_state_t* state_in)
{
XXH_endianess endian_detected = (XXH_endianess)XXH_CPU_LITTLE_ENDIAN;
if ((endian_detected==XXH_littleEndian) || XXH_FORCE_NATIVE_FORMAT)
return XXH32_digest_endian(state_in, XXH_littleEndian);
else
return XXH32_digest_endian(state_in, XXH_bigEndian);
}
/*====== Canonical representation ======*/
/*! Default XXH result types are basic unsigned 32 and 64 bits.
* The canonical representation follows human-readable write convention, aka big-endian (large digits first).
* These functions allow transformation of hash result into and from its canonical format.
* This way, hash values can be written into a file or buffer, remaining comparable across different systems.
*/
XXH_PUBLIC_API void XXH32_canonicalFromHash(XXH32_canonical_t* dst, XXH32_hash_t hash)
{
XXH_STATIC_ASSERT(sizeof(XXH32_canonical_t) == sizeof(XXH32_hash_t));
if (XXH_CPU_LITTLE_ENDIAN) hash = XXH_swap32(hash);
XXH_memcpy(dst, &hash, sizeof(*dst));
}
XXH_PUBLIC_API XXH32_hash_t XXH32_hashFromCanonical(const XXH32_canonical_t* src)
{
return XXH_readBE32(src);
}
#ifndef XXH_NO_LONG_LONG
/* *******************************************************************
* 64-bit hash functions
*********************************************************************/
/*====== Memory access ======*/
#if (defined(XXH_FORCE_MEMORY_ACCESS) && (XXH_FORCE_MEMORY_ACCESS==2))
/* Force direct memory access. Only works on CPU which support unaligned memory access in hardware */
#if defined(__GNUC__) && defined(__ARM_ARCH) && __ARM_ARCH == 6
/* ARMv6 supports unaligned access in ldr, but not in ldrd. Unfortunately, that is what most compilers
* generate. */
FORCE_INLINE U64 XXH_read64(const void* memPtr)
{
U32 retLo, retHi;
/* Separate statements so the compiler can reorder. */
__asm__("ldr %[retLo], [ %[memPtr] ]" : [retLo] "=r" (retLo) : [memPtr] "r" (memPtr));
__asm__("ldr %[retHi], [ %[memPtr], #4 ]" : [retHi] "=r" (retHi) : [memPtr] "r" (memPtr));
return ((U64)retHi << 32) | retLo;
}
#else
static U64 XXH_read64(const void* memPtr) { return *(const U64*) memPtr; }
#endif
#elif (defined(XXH_FORCE_MEMORY_ACCESS) && (XXH_FORCE_MEMORY_ACCESS==1))
/* __pack instructions are safer, but compiler specific, hence potentially problematic for some compilers */
/* currently only defined for gcc and icc */
typedef union { U32 u32; U64 u64; } __attribute__((packed)) unalign64;
static U64 XXH_read64(const void* ptr) { return ((const unalign64*)ptr)->u64; }
#else
/* portable and safe solution. Generally efficient.
* see : http://stackoverflow.com/a/32095106/646947
*/
static U64 XXH_read64(const void* memPtr)
{
U64 val;
XXH_memcpy(&val, memPtr, sizeof(val));
return val;
}
#endif /* XXH_FORCE_MEMORY_ACCESS */
#if defined(_MSC_VER) /* Visual Studio */
# define XXH_swap64 _byteswap_uint64
#elif XXH_GCC_VERSION >= 403
# define XXH_swap64 __builtin_bswap64
#else
static U64 XXH_swap64 (U64 x)