Summary:
SVE intrinsic tests produce incorrect results under JitStress2+JitStressRegs on ARM64. ExtractVector and SaturatingIncrement/Decrement operations return wrong values with zeroed upper vector halves.
Failed in (2):
Console Log: Console Log
Source: runtime-coreclr jitstress2-jitstressregs / coreclr linux arm64 Checked jitstress2_jitstressregs1 @ AzureLinux.3.Arm64.Open / _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_ExtractVector_Byte_1()
Failed tests:
runtime-coreclr jitstress2-jitstressregs
- coreclr linux arm64 Checked jitstress2_jitstressregs0x80 @ AzureLinux.3.Arm64.Open
- coreclr linux arm64 Checked jitstress2_jitstressregs1 @ AzureLinux.3.Arm64.Open
- coreclr linux arm64 Checked jitstress2_jitstressregs8 @ AzureLinux.3.Arm64.Open
- coreclr windows arm64 Checked jitstress2_jitstressregs0x80 @ Windows.11.Arm64.Open
- coreclr windows arm64 Checked jitstress2_jitstressregs1 @ Windows.11.Arm64.Open
- coreclr windows arm64 Checked jitstress2_jitstressregs8 @ Windows.11.Arm64.Open
runtime-coreclr jitstressregs
- coreclr linux arm64 Checked jitstressregs0x80 @ AzureLinux.3.Arm64.Open
- coreclr linux arm64 Checked jitstressregs1 @ AzureLinux.3.Arm64.Open
- coreclr linux arm64 Checked jitstressregs8 @ AzureLinux.3.Arm64.Open
- coreclr windows arm64 Checked jitstressregs0x80 @ Windows.11.Arm64.Open
- coreclr windows arm64 Checked jitstressregs1 @ Windows.11.Arm64.Open
- coreclr windows arm64 Checked jitstressregs8 @ Windows.11.Arm64.Open
- _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_ExtractVector_Byte_1()
- _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_ExtractVector_Int16_1()
- _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_ExtractVector_Int32_1()
- _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_ExtractVector_SByte_1()
- _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_ExtractVector_Single_1()
- ... and 89 more
Error Message:
System.Exception: One or more scenarios did not complete as expected.
Sve.ExtractVector: Result vectors have upper halves zeroed (e.g., result=(255,116,31,89,233,38,167,218,0,0,0,0,0,0,0,0) instead of expected concatenation).
Sve.SaturatingDecrementBy*ElementCount / SaturatingIncrementBy*ElementCount: Scalar results are wildly wrong (e.g., data=809243706, result=6). Vector results have upper halves zeroed.
Stack Trace:
at JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_ExtractVector_Byte_1() in /__w/1/s/artifacts/tests/coreclr/obj/AnyOS.x64.Checked/Managed/JIT/HardwareIntrinsics/Arm/Sve/Sve_r/Sve_r/gen/Sve.ExtractVector.Byte.1.cs:line 64
at Program.<<Main>$>g__TestExecutor4125|0_4126(StreamWriter tempLogSw, StreamWriter statsCsvSw, <>c__DisplayClass0_0&)
Analysis:
These 972 failures (94 unique test names) all occur on Linux ARM64 under JitStress=2 + JitStressRegs. Two patterns: (1) ExtractVector produces vectors with zeroed upper halves, (2) SaturatingIncrement/Decrement scalar ops return near-zero values. Points to JIT register allocation bug under stress modes failing to preserve SVE scalable vector registers. The SVE tracking issue #93095 lists "Add JitStressRegs mode to always allocate high Z/P register" as incomplete.
- Generated by ci-pipeline-monitor/scripts/generate_report.py *
Summary:
SVE intrinsic tests produce incorrect results under JitStress2+JitStressRegs on ARM64. ExtractVector and SaturatingIncrement/Decrement operations return wrong values with zeroed upper vector halves.
Failed in (2):
runtime-coreclr jitstress2-jitstressregs 20260408.1
runtime-coreclr jitstressregs 20260408.2
Console Log: Console Log
Source: runtime-coreclr jitstress2-jitstressregs / coreclr linux arm64 Checked jitstress2_jitstressregs1 @ AzureLinux.3.Arm64.Open / _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_ExtractVector_Byte_1()
Failed tests:
Error Message:
Stack Trace:
Analysis:
These 972 failures (94 unique test names) all occur on Linux ARM64 under JitStress=2 + JitStressRegs. Two patterns: (1) ExtractVector produces vectors with zeroed upper halves, (2) SaturatingIncrement/Decrement scalar ops return near-zero values. Points to JIT register allocation bug under stress modes failing to preserve SVE scalable vector registers. The SVE tracking issue #93095 lists "Add JitStressRegs mode to always allocate high Z/P register" as incomplete.