From 61880117497099498a3d39a8edb69fba3042ec82 Mon Sep 17 00:00:00 2001 From: Bradley Wood Date: Thu, 12 Sep 2024 05:01:11 -0400 Subject: [PATCH] x86: Fix pmovzxwd binary encoding Signed-off-by: Bradley Wood --- compiler/x/codegen/OMRInstOpCode.enum | 1 + compiler/x/codegen/X86Ops.ins | 15 ++++++++------- fvtest/compilerunittest/x/BinaryEncoder.cpp | 18 ++++++++++++------ 3 files changed, 21 insertions(+), 13 deletions(-) diff --git a/compiler/x/codegen/OMRInstOpCode.enum b/compiler/x/codegen/OMRInstOpCode.enum index 5a68eb586f5..fcfa08b517c 100644 --- a/compiler/x/codegen/OMRInstOpCode.enum +++ b/compiler/x/codegen/OMRInstOpCode.enum @@ -85,3 +85,4 @@ VPRORVDRegRegMem = VPRORVDRegRegReg, VPRORVQRegRegMem = VPRORVQRegRegReg, PMOVSXBDRegMem = PMOVSXBDRegReg, PMOVSXWDRegMem = PMOVSXWDRegReg, +PMOVZXWDRegMem = PMOVZXWDRegReg, diff --git a/compiler/x/codegen/X86Ops.ins b/compiler/x/codegen/X86Ops.ins index fc0ff470612..471f979dc63 100644 --- a/compiler/x/codegen/X86Ops.ins +++ b/compiler/x/codegen/X86Ops.ins @@ -3638,6 +3638,7 @@ INSTRUCTION(PMOVSXWDRegReg, pmovsxwd, X86FeatureProp_EVEX256Supported | X86FeatureProp_EVEX256RequiresAVX512F | X86FeatureProp_EVEX256RequiresAVX512VL | X86FeatureProp_EVEX128RequiresAVX512BW | X86FeatureProp_EVEX512Supported | X86FeatureProp_EVEX512RequiresAVX512F | X86FeatureProp_EVEX128RequiresAVX512BW) ), + INSTRUCTION(PMOVZXBWRegReg, pmovzxbw, BINARY(VEX_L128, VEX_vNONE, PREFIX_66, REX__, ESCAPE_0F38, 0x30, 0, ModRM_RM__, Immediate_0), PROPERTY0(IA32OpProp_SourceRegisterInModRM), @@ -3671,13 +3672,13 @@ INSTRUCTION(PMOVZXBQRegReg, pmovzxbq, INSTRUCTION(PMOVZXWDRegReg, pmovzxwd, BINARY(VEX_L128, VEX_vNONE, PREFIX_66, REX__, ESCAPE_0F38, 0x33, 0, ModRM_RM__, Immediate_0), PROPERTY0(IA32OpProp_SourceRegisterInModRM), - PROPERTY1(IA32OpProp1_XMMSource | IA32OpProp1_XMMTarget), - FEATURES(0)), -INSTRUCTION(PMOVZXWDRegMem, pmovzxwd, - BINARY(VEX_L128, VEX_vNONE, PREFIX_66, REX__, ESCAPE_0F38, 0x33, 0, ModRM_RM__, Immediate_0), - PROPERTY0(0), - PROPERTY1(IA32OpProp1_SourceIsMemRef | IA32OpProp1_XMMTarget), - FEATURES(0)), + PROPERTY1(IA32OpProp1_XMMSource | IA32OpProp1_XMMTarget | IA32OpProp1_SourceCanBeMemRef | IA32OpProp1_SIMDSingleSource), + FEATURES(X86FeatureProp_SSE4_1Supported | + X86FeatureProp_VEX128Supported | X86FeatureProp_VEX128RequiresAVX | X86FeatureProp_VEX256Supported | X86FeatureProp_VEX256RequiresAVX2 | + X86FeatureProp_EVEX128Supported | X86FeatureProp_EVEX128RequiresAVX512F | X86FeatureProp_EVEX128RequiresAVX512VL | X86FeatureProp_EVEX128RequiresAVX512BW | + X86FeatureProp_EVEX256Supported | X86FeatureProp_EVEX256RequiresAVX512F | X86FeatureProp_EVEX256RequiresAVX512VL | X86FeatureProp_EVEX128RequiresAVX512BW | + X86FeatureProp_EVEX512Supported | X86FeatureProp_EVEX512RequiresAVX512F | X86FeatureProp_EVEX128RequiresAVX512BW) +), INSTRUCTION(VPMOVB2MRegReg, vpmovb2m, BINARY(VEX_L128, VEX_vNONE, PREFIX_F3, REX__, ESCAPE_0F38, 0x29, 0, ModRM_RM__, Immediate_0), PROPERTY0(IA32OpProp_ModifiesTarget | IA32OpProp_SourceRegisterInModRM | IA32OpProp_UsesTarget), diff --git a/fvtest/compilerunittest/x/BinaryEncoder.cpp b/fvtest/compilerunittest/x/BinaryEncoder.cpp index 2329761d0c1..13ff92216df 100644 --- a/fvtest/compilerunittest/x/BinaryEncoder.cpp +++ b/fvtest/compilerunittest/x/BinaryEncoder.cpp @@ -301,7 +301,8 @@ INSTANTIATE_TEST_CASE_P(LegacySimdTest, XRegRegEncEncodingTest, ::testing::Value std::make_tuple(TR::InstOpCode::MOVMSKPSRegReg, TR::RealRegister::ecx, TR::RealRegister::xmm7, OMR::X86::Legacy, "0f50cf"), std::make_tuple(TR::InstOpCode::MOVMSKPDRegReg, TR::RealRegister::edx, TR::RealRegister::xmm15, OMR::X86::Legacy, "66410f50d7"), std::make_tuple(TR::InstOpCode::PMOVSXBDRegReg, TR::RealRegister::xmm1, TR::RealRegister::xmm9, OMR::X86::Legacy, "66410f3821c9"), - std::make_tuple(TR::InstOpCode::PMOVSXWDRegReg, TR::RealRegister::xmm8, TR::RealRegister::xmm0, OMR::X86::Legacy, "66440f3823c0") + std::make_tuple(TR::InstOpCode::PMOVSXWDRegReg, TR::RealRegister::xmm8, TR::RealRegister::xmm0, OMR::X86::Legacy, "66440f3823c0"), + std::make_tuple(TR::InstOpCode::PMOVZXWDRegReg, TR::RealRegister::xmm8, TR::RealRegister::xmm0, OMR::X86::Legacy, "66440f3833c0") ))); INSTANTIATE_TEST_CASE_P(AVXSimdRegRegVex128Test, XRegRegEncEncodingTest, ::testing::ValuesIn(*TRTest::MakeVector>( @@ -337,7 +338,8 @@ INSTANTIATE_TEST_CASE_P(AVXSimdRegRegVex128Test, XRegRegEncEncodingTest, ::testi std::make_tuple(TR::InstOpCode::PORRegReg, TR::RealRegister::xmm12, TR::RealRegister::xmm0, OMR::X86::VEX_L128, "c519ebe0"), std::make_tuple(TR::InstOpCode::PXORRegReg, TR::RealRegister::xmm11, TR::RealRegister::xmm15, OMR::X86::VEX_L128, "c44121efdf"), std::make_tuple(TR::InstOpCode::PMOVSXBDRegReg, TR::RealRegister::xmm1, TR::RealRegister::xmm9, OMR::X86::VEX_L128, "c4c27921c9"), - std::make_tuple(TR::InstOpCode::PMOVSXWDRegReg, TR::RealRegister::xmm8, TR::RealRegister::xmm0, OMR::X86::VEX_L128, "c4627923c0") + std::make_tuple(TR::InstOpCode::PMOVSXWDRegReg, TR::RealRegister::xmm8, TR::RealRegister::xmm0, OMR::X86::VEX_L128, "c4627923c0"), + std::make_tuple(TR::InstOpCode::PMOVZXWDRegReg, TR::RealRegister::xmm8, TR::RealRegister::xmm0, OMR::X86::VEX_L128, "c4627933c0") ))); INSTANTIATE_TEST_CASE_P(AVXSimdRegRegVex256Test, XRegRegEncEncodingTest, ::testing::ValuesIn(*TRTest::MakeVector>( @@ -371,7 +373,8 @@ INSTANTIATE_TEST_CASE_P(AVXSimdRegRegVex256Test, XRegRegEncEncodingTest, ::testi std::make_tuple(TR::InstOpCode::PORRegReg, TR::RealRegister::ymm12, TR::RealRegister::ymm0, OMR::X86::VEX_L256, "c51debe0"), std::make_tuple(TR::InstOpCode::PXORRegReg, TR::RealRegister::ymm11, TR::RealRegister::ymm15, OMR::X86::VEX_L256, "c44125efdf"), std::make_tuple(TR::InstOpCode::PMOVSXBDRegReg, TR::RealRegister::ymm1, TR::RealRegister::ymm9, OMR::X86::VEX_L256, "c4c27d21c9"), - std::make_tuple(TR::InstOpCode::PMOVSXWDRegReg, TR::RealRegister::ymm8, TR::RealRegister::ymm0, OMR::X86::VEX_L256, "c4627d23c0") + std::make_tuple(TR::InstOpCode::PMOVSXWDRegReg, TR::RealRegister::ymm8, TR::RealRegister::ymm0, OMR::X86::VEX_L256, "c4627d23c0"), + std::make_tuple(TR::InstOpCode::PMOVZXWDRegReg, TR::RealRegister::ymm8, TR::RealRegister::ymm0, OMR::X86::VEX_L256, "c4627d33c0") ))); INSTANTIATE_TEST_CASE_P(AVXSimdRegRegEVEX128Test, XRegRegEncEncodingTest, ::testing::ValuesIn(*TRTest::MakeVector>( @@ -404,7 +407,8 @@ INSTANTIATE_TEST_CASE_P(AVXSimdRegRegEVEX128Test, XRegRegEncEncodingTest, ::test std::make_tuple(TR::InstOpCode::PORRegReg, TR::RealRegister::xmm12, TR::RealRegister::xmm0, OMR::X86::EVEX_L128, "62711d08ebe0"), std::make_tuple(TR::InstOpCode::PXORRegReg, TR::RealRegister::xmm11, TR::RealRegister::xmm15, OMR::X86::EVEX_L128, "62512508efdf"), std::make_tuple(TR::InstOpCode::PMOVSXBDRegReg, TR::RealRegister::xmm1, TR::RealRegister::xmm9, OMR::X86::EVEX_L128, "62d27d0821c9"), - std::make_tuple(TR::InstOpCode::PMOVSXWDRegReg, TR::RealRegister::xmm8, TR::RealRegister::xmm0, OMR::X86::EVEX_L128, "62727d0823c0") + std::make_tuple(TR::InstOpCode::PMOVSXWDRegReg, TR::RealRegister::xmm8, TR::RealRegister::xmm0, OMR::X86::EVEX_L128, "62727d0823c0"), + std::make_tuple(TR::InstOpCode::PMOVZXWDRegReg, TR::RealRegister::xmm8, TR::RealRegister::xmm0, OMR::X86::EVEX_L128, "62727d0833c0") ))); INSTANTIATE_TEST_CASE_P(AVXSimdRegRegEVEX256Test, XRegRegEncEncodingTest, ::testing::ValuesIn(*TRTest::MakeVector>( @@ -437,7 +441,8 @@ INSTANTIATE_TEST_CASE_P(AVXSimdRegRegEVEX256Test, XRegRegEncEncodingTest, ::test std::make_tuple(TR::InstOpCode::PORRegReg, TR::RealRegister::ymm12, TR::RealRegister::ymm0, OMR::X86::EVEX_L256, "62711d28ebe0"), std::make_tuple(TR::InstOpCode::PXORRegReg, TR::RealRegister::ymm11, TR::RealRegister::ymm15, OMR::X86::EVEX_L256, "62512528efdf"), std::make_tuple(TR::InstOpCode::PMOVSXBDRegReg, TR::RealRegister::ymm1, TR::RealRegister::ymm9, OMR::X86::EVEX_L256, "62d27d2821c9"), - std::make_tuple(TR::InstOpCode::PMOVSXWDRegReg, TR::RealRegister::ymm8, TR::RealRegister::ymm0, OMR::X86::EVEX_L256, "62727d2823c0") + std::make_tuple(TR::InstOpCode::PMOVSXWDRegReg, TR::RealRegister::ymm8, TR::RealRegister::ymm0, OMR::X86::EVEX_L256, "62727d2823c0"), + std::make_tuple(TR::InstOpCode::PMOVZXWDRegReg, TR::RealRegister::ymm8, TR::RealRegister::ymm0, OMR::X86::EVEX_L256, "62727d2833c0") ))); INSTANTIATE_TEST_CASE_P(AVXSimdRegRegEVEX512Test, XRegRegEncEncodingTest, ::testing::ValuesIn(*TRTest::MakeVector>( @@ -471,7 +476,8 @@ INSTANTIATE_TEST_CASE_P(AVXSimdRegRegEVEX512Test, XRegRegEncEncodingTest, ::test std::make_tuple(TR::InstOpCode::PORRegReg, TR::RealRegister::zmm12, TR::RealRegister::zmm0, OMR::X86::EVEX_L512, "62711d48ebe0"), std::make_tuple(TR::InstOpCode::PXORRegReg, TR::RealRegister::zmm11, TR::RealRegister::zmm15, OMR::X86::EVEX_L512, "62512548efdf"), std::make_tuple(TR::InstOpCode::PMOVSXBDRegReg, TR::RealRegister::zmm1, TR::RealRegister::zmm9, OMR::X86::EVEX_L512, "62d27d4821c9"), - std::make_tuple(TR::InstOpCode::PMOVSXWDRegReg, TR::RealRegister::zmm8, TR::RealRegister::zmm0, OMR::X86::EVEX_L512, "62727d4823c0") + std::make_tuple(TR::InstOpCode::PMOVSXWDRegReg, TR::RealRegister::zmm8, TR::RealRegister::zmm0, OMR::X86::EVEX_L512, "62727d4823c0"), + std::make_tuple(TR::InstOpCode::PMOVZXWDRegReg, TR::RealRegister::zmm8, TR::RealRegister::zmm0, OMR::X86::EVEX_L512, "62727d4833c0") ))); INSTANTIATE_TEST_CASE_P(LegacyRegRegImm1SimdTest, XRegRegImm1EncodingTest, ::testing::ValuesIn(*TRTest::MakeVector>(