update

Author: dineshannayya

.gitmodules

@@ -1,9 +1,6 @@
 [submodule "verilog/rtl/qspim"]
 	path = verilog/rtl/qspim
 	url = https://github.com/dineshannayya/qspim.git
-[submodule "verilog/dv/common/riscduino_board"]
-	path = verilog/dv/common/riscduino_board
-	url = https://github.com/dineshannayya/riscduino_board.git
 [submodule "verilog/rtl/yifive/ycr1cr"]
 	path = verilog/rtl/yifive/ycr1c
 	url = https://github.com/dineshannayya/ycr1cr.git
@@ -16,3 +13,6 @@
 [submodule "verilog/rtl/rtc"]
 	path = verilog/rtl/rtc
 	url = https://github.com/dineshannayya/rtc
+[submodule "verilog/dv/common/riscduino_firmware"]
+	path = verilog/dv/common/riscduino_firmware
+	url = https://github.com/dineshannayya/riscduino_firmware