diff --git a/regression/verilog/nettype/nettype1.desc b/regression/verilog/nettype/nettype1.desc
new file mode 100644
index 00000000..13082b2d
--- /dev/null
+++ b/regression/verilog/nettype/nettype1.desc
@@ -0,0 +1,9 @@
+KNOWNBUG
+nettype1.sv
+
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+nettype is not implemented.
diff --git a/regression/verilog/nettype/nettype1.sv b/regression/verilog/nettype/nettype1.sv
new file mode 100644
index 00000000..7d5814d2
--- /dev/null
+++ b/regression/verilog/nettype/nettype1.sv
@@ -0,0 +1,11 @@
+module main;
+
+   nettype logic [31:0] some_word_type;
+   nettype logic signed [31:0] some_signed_type;
+
+   some_word_type some_word;
+   some_signed_type some_signed;
+
+   p0: assert final ($bits(some_word) == 32);
+
+endmodule