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SVA/LTL property instrumentation
This adds --buechi, which triggers an instrumentation pass that turns LTL and select SVA properties into a Buechi automaton. The automaton is then added to the model, and the property is replaced by the Buechi acceptance condition. The translation is done via ltl2tgba. This enables checking arbitrary LTL properties via the BDD engine.
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.github/workflows/pull-request-checks.yaml

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- name: HWMCC08 benchmarks
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run: PATH=$PATH:$PWD/ebmc benchmarking/hwmcc08.sh
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# This job takes approximately 1 minute
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ebmc-spot:
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runs-on: ubuntu-24.04
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needs: check-ubuntu-24_04-make-clang
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steps:
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- uses: actions/checkout@v4
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with:
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submodules: recursive
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- name: Fetch dependencies
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env:
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# This is needed in addition to -yq to prevent apt-get from asking for
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# user input
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DEBIAN_FRONTEND: noninteractive
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run: |
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# spot
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wget -q -O - https://www.lrde.epita.fr/repo/debian.gpg | sudo apt-key add -
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sudo sh -c 'echo "deb http://www.lrde.epita.fr/repo/debian/ stable/" >> /etc/apt/sources.list'
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sudo apt-get update
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sudo apt-get install spot
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- name: Confirm ltl2tgba is available and log the version installed
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run: ltl2tgba --version
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- name: Get the ebmc binary
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uses: actions/download-artifact@v4
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with:
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name: ebmc-binary
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path: ebmc
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- name: Try the ebmc binary
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run: chmod a+x ./ebmc/ebmc ; ./ebmc/ebmc --version
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- name: put the ebmc binary in place
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run: cp ebmc/ebmc src/ebmc/
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- name: run the ebmc-spot tests
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run: make -C regression/ebmc-spot
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# This job takes approximately 1 minute
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examples:
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runs-on: ubuntu-24.04

CHANGELOG

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# EBMC 5.7
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* Verilog: `elsif preprocessor directive
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* LTL/SVA to Buechi with --buechi
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# EBMC 5.6
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lib/cbmc

regression/ebmc-spot/Makefile

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default: test
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TEST_PL = ../../lib/cbmc/regression/test.pl
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test:
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@$(TEST_PL) -e -p -c ../../../src/ebmc/ebmc
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test-z3:
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@$(TEST_PL) -e -p -c "../../../src/ebmc/ebmc --z3" -X broken-smt-backend
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CORE
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FGp1.smv
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--buechi --bdd
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^\[.*\] F G p: PROVED$
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^EXIT=0$
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^SIGNAL=0$
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--
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^warning: ignoring
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--
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MODULE main
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VAR p : boolean;
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ASSIGN init(p) := FALSE;
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next(p) := TRUE;
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-- should pass
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LTLSPEC F G p
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CORE
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Fp1.smv
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--buechi --bdd
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^\[.*\] F p: PROVED$
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^EXIT=0$
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^SIGNAL=0$
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--
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^warning: ignoring
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--
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MODULE main
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VAR p : boolean;
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ASSIGN init(p) := FALSE;
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next(p) := TRUE;
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-- should pass
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LTLSPEC F p
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KNOWNBUG
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GFp1.smv
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--buechi --bdd
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^\[.*\] G F p: PROVED$
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^EXIT=0$
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^SIGNAL=0$
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--
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^warning: ignoring
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--
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BDD engine gives wrong answer.
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MODULE main
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VAR p : boolean;
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ASSIGN init(p) := FALSE;
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next(p) := !p;
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-- should pass
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LTLSPEC G F p
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CORE
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Gp1.smv
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--buechi --bdd
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^\[.*\] G p: PROVED$
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^EXIT=0$
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^SIGNAL=0$
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--
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^warning: ignoring
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--
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MODULE main
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VAR p : boolean;
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ASSIGN init(p) := TRUE;
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next(p) := TRUE;
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-- should pass
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LTLSPEC G p
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CORE
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Gp2.smv
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--buechi
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^\[.*\] G p: REFUTED$
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^EXIT=10$
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^SIGNAL=0$
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--
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^warning: ignoring
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--
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MODULE main
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VAR p : boolean;
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ASSIGN init(p) := TRUE;
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next(p) := FALSE;
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-- should fail
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LTLSPEC G p
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MODULE main
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VAR x : 0..10;
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ASSIGN
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init(x) := 1;
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next(x) :=
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case
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x>=3 : 3;
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TRUE: x+1;
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esac;
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LTLSPEC NAME p1 := x >= 1 R x = 1 -- should pass
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LTLSPEC NAME p2 := FALSE R x != 4 -- should pass
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LTLSPEC NAME p3 := x = 2 R x = 1 -- should fail
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LTLSPEC NAME p4 := (x >= 1 R x = 1) & (FALSE R x != 4) -- should pass
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LTLSPEC NAME p5 := (x = 2 R x = 1) & (x >= 1 R x = 1) -- should fail
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LTLSPEC NAME p6 := (x = 2 R x = 1) | (x >= 1 R x = 1) -- should pass
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CORE
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R1.smv
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--bdd --property p1 --buechi
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^\[p1\] x >= 1 V x = 1: PROVED$
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^EXIT=0$
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^SIGNAL=0$
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--
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^warning: ignoring
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--
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CORE
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R1.smv
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--bdd --property p2 --buechi
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^\[p2\] FALSE V x != 4: PROVED$
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^EXIT=0$
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^SIGNAL=0$
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--
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^warning: ignoring
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--
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CORE
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R1.smv
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--bdd --property p3 --buechi
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^\[p3\] x = 2 V x = 1: REFUTED$
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^EXIT=10$
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^SIGNAL=0$
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--
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^warning: ignoring
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--
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CORE
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R1.smv
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--bdd --property p4 --buechi
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^\[p4\] x >= 1 V x = 1 & FALSE V x != 4: PROVED$
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^EXIT=0$
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^SIGNAL=0$
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--
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^warning: ignoring
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--
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CORE
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R1.smv
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--bdd --property p5 --buechi
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^\[p5\] x = 2 V x = 1 & x >= 1 V x = 1: REFUTED$
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^EXIT=10$
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^SIGNAL=0$
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--
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^warning: ignoring
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--
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CORE
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R1.smv
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--bdd --property p6 --buechi
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^\[p6\] x = 2 V x = 1 \| x >= 1 V x = 1: PROVED$
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^EXIT=0$
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^SIGNAL=0$
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--
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^warning: ignoring
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--
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CORE
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Xp1.smv
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--buechi --bdd
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^\[.*\] X p: PROVED$
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^EXIT=0$
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^SIGNAL=0$
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--
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^warning: ignoring
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--
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MODULE main
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VAR p : boolean;
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ASSIGN init(p) := FALSE;
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next(p) := TRUE;
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-- should pass
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LTLSPEC X p
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CORE
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and1.smv
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--buechi --bdd
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^\[.*\] X p & X q: PROVED$
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^EXIT=0$
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^SIGNAL=0$
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--
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^warning: ignoring
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--
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MODULE main
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VAR p : boolean;
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ASSIGN init(p) := FALSE;
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next(p) := TRUE;
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VAR q : boolean;
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ASSIGN init(q) := FALSE;
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next(q) := TRUE;
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-- should pass
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LTLSPEC X p & X q
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CORE
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and2.smv
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--buechi --bdd
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^\[.*\] X \(p & q\): PROVED$
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^EXIT=0$
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^SIGNAL=0$
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--
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^warning: ignoring
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--
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MODULE main
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VAR p : boolean;
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ASSIGN init(p) := FALSE;
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next(p) := TRUE;
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VAR q : boolean;
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ASSIGN init(q) := FALSE;
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next(q) := TRUE;
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-- should pass
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LTLSPEC X (p & q)
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CORE
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iff1.smv
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--buechi --bdd
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^\[.*\] X p <-> X q: PROVED$
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^EXIT=0$
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^SIGNAL=0$
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--
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^warning: ignoring
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--
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MODULE main
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VAR p : boolean;
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ASSIGN init(p) := TRUE;
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next(p) := FALSE;
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VAR q : boolean;
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ASSIGN init(q) := TRUE;
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next(q) := FALSE;
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-- should pass
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LTLSPEC X p <-> X q
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CORE
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iff2.smv
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--buechi --bdd
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^\[.*\] X \(p <-> q\): PROVED$
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^EXIT=0$
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^SIGNAL=0$
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--
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^warning: ignoring
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--
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MODULE main
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VAR p : boolean;
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ASSIGN init(p) := TRUE;
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next(p) := FALSE;
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VAR q : boolean;
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ASSIGN init(q) := TRUE;
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next(q) := FALSE;
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-- should pass
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LTLSPEC X (p <-> q)
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CORE
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implies1.smv
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--buechi --bdd
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^\[.*\] X p -> X q: PROVED$
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^EXIT=0$
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^SIGNAL=0$
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--
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^warning: ignoring
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--
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MODULE main
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VAR p : boolean;
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ASSIGN init(p) := TRUE;
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next(p) := FALSE;
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VAR q : boolean;
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ASSIGN init(q) := TRUE;
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next(q) := FALSE;
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-- should pass
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LTLSPEC X p -> X q
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CORE
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implies2.smv
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--buechi --bdd
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^\[.*\] X \(p -> q\): PROVED$
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^EXIT=0$
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^SIGNAL=0$
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--
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^warning: ignoring
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--

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