diff --git a/vga/Makefile b/vga/Makefile
index e0affbb..7921e05 100644
--- a/vga/Makefile
+++ b/vga/Makefile
@@ -52,7 +52,7 @@ vgatest.json: $(VHDL_SYN_FILES) $(VERILOG_SYN_FILES)
 		"$(GHDL_SYNTH) $(GHDL_FLAGS) $(VHDL_SYN_FILES) -e; \
 		$(YOSYS_SYNTH) \
 		-top $(BOARD_TOP) \
-		-json $@" 2>&1 board/pll.v | tee yosys-report.txt
+		-json $@" 2>&1 | tee yosys-report.txt
 
 vgatest.asc: vgatest.json
 	$(NEXTPNR) \
diff --git a/vga/board/icestick/Icestick_Top.vhd b/vga/board/icestick/Icestick_Top.vhd
index e27dd7d..b049e80 100644
--- a/vga/board/icestick/Icestick_Top.vhd
+++ b/vga/board/icestick/Icestick_Top.vhd
@@ -36,14 +36,16 @@ architecture arch of Icestick_Top is
 
 begin
 
-  PLL_0: PLL
+  PLL_0: SB_PLL40_CORE
   generic map (
     DIVF => to_unsigned( PLL_cfg.DIVF, 7),
     DIVQ => to_unsigned( PLL_cfg.DIVQ, 3)
   )
   port map (
-    clki => CLK,
-    clko => clki
+    REFERENCECLK => CLK,
+    PLLOUTCORE   => clki,
+    BYPASS       => '0',
+    RESETB       => '1'
   );
 
   UUT: entity work.Design_Top(pattern)
diff --git a/vga/board/pll.v b/vga/board/pll.v
deleted file mode 100644
index cdf2a99..0000000
--- a/vga/board/pll.v
+++ /dev/null
@@ -1,24 +0,0 @@
-module PLL #(
-  parameter DIVF = 7'b0000000,
-  parameter DIVQ = 3'b000
-) (
-  input  wire clki,
-  output wire clko
-);
-
-SB_PLL40_CORE #(
-  .FEEDBACK_PATH("SIMPLE"),
-  .PLLOUT_SELECT("GENCLK"),
-  .DIVR(4'd0),
-  .DIVF(DIVF),
-  .DIVQ(DIVQ),
-  .FILTER_RANGE(3'b001)
-)
-uut (
-  .REFERENCECLK(clki),
-  .PLLOUTCORE(clko),
-  .RESETB(1'b1),
-  .BYPASS(1'b0)
-);
-
-endmodule
diff --git a/vga/board/tinyfpgabx/TinyFPGABX_Top.vhd b/vga/board/tinyfpgabx/TinyFPGABX_Top.vhd
index d2c7395..def32d1 100644
--- a/vga/board/tinyfpgabx/TinyFPGABX_Top.vhd
+++ b/vga/board/tinyfpgabx/TinyFPGABX_Top.vhd
@@ -36,14 +36,16 @@ begin
   -- Drive USB pull-up resistor to '0' to disable USB
   USBPU <= '0';
 
-  PLL_0: PLL
+  PLL_0: SB_PLL40_CORE
   generic map (
     DIVF => to_unsigned( PLL_cfg.DIVF, 7),
     DIVQ => to_unsigned( PLL_cfg.DIVQ, 3)
   )
   port map (
-    clki => CLK,
-    clko => clki
+    REFERENCECLK => CLK,
+    PLLOUTCORE   => clki,
+    BYPASS       => '0',
+    RESETB       => '1'
   );
 
   UUT: entity work.Design_Top(pattern)
diff --git a/vga/device/ICE40/ICE40_components_pkg.vhd b/vga/device/ICE40/ICE40_components_pkg.vhd
index 6c572a4..fff3f64 100644
--- a/vga/device/ICE40/ICE40_components_pkg.vhd
+++ b/vga/device/ICE40/ICE40_components_pkg.vhd
@@ -14,45 +14,45 @@ component PLL
   );
 end component;
 
---component SB_PLL40_CORE
---  generic (
---    --- Feedback
---    FEEDBACK_PATH                  : string := "SIMPLE"; -- String (simple, delay, phase_and_delay, external)
+component SB_PLL40_CORE
+  generic (
+    --- Feedback
+    FEEDBACK_PATH                  : string := "SIMPLE"; -- String (simple, delay, phase_and_delay, external)
 --    DELAY_ADJUSTMENT_MODE_FEEDBACK : string := "FIXED";
 --    DELAY_ADJUSTMENT_MODE_RELATIVE : string := "FIXED";
 --    SHIFTREG_DIV_MODE              : bit_vector(1 downto 0) := "00";   -- 0-->Divide by 4, 1-->Divide by 7, 3 -->Divide by 5
 --    FDA_FEEDBACK                   : bit_vector(3 downto 0) := "0000"; -- Integer (0-15)
 --    FDA_RELATIVE                   : bit_vector(3 downto 0) := "0000"; -- Integer (0-15)
---    PLLOUT_SELECT                  : string := "GENCLK";
---
+    PLLOUT_SELECT                  : string := "GENCLK";
+
 --      --- Use the spread sheet to populate the values below
---    DIVF         : bit_vector(6 downto 0);  -- Determine a good default value
---    DIVR         : bit_vector(3 downto 0);  -- Determine a good default value
---    DIVQ         : bit_vector(2 downto 0);  -- Determine a good default value
---    FILTER_RANGE : bit_vector(2 downto 0);  -- Determine a good default value
---
---    --- Additional C-Bits
+    DIVF         : unsigned(6 downto 0);  -- Determine a good default value
+    DIVR         : unsigned(3 downto 0) := (others=>'0');  -- Determine a good default value
+    DIVQ         : unsigned(2 downto 0);  -- Determine a good default value
+    FILTER_RANGE : unsigned(2 downto 0) := "001"  -- Determine a good default value
+
+    --- Additional C-Bits
 --    ENABLE_ICEGATE : bit := '0';
---
---    --- Test Mode Parameter
+
+    --- Test Mode Parameter
 --    TEST_MODE              : bit := '0';
 --    EXTERNAL_DIVIDE_FACTOR : integer := 1 -- Not Used by model, Added for PLL config GUI
---  );
---  port (
---    REFERENCECLK    : in  std_logic; -- Driven by core logic
---    PLLOUTCORE      : out std_logic; -- PLL output to core logic
+  );
+  port (
+    REFERENCECLK    : in  std_logic; -- Driven by core logic
+    PLLOUTCORE      : out std_logic; -- PLL output to core logic
 --    PLLOUTGLOBAL    : out std_logic; -- PLL output to global network
 --    EXTFEEDBACK     : in  std_logic; -- Driven by core logic
 --    DYNAMICDELAY    : in  std_logic_vector (7 downto 0); -- Driven by core logic
 --    LOCK            : out std_logic; -- Output of PLL
---    BYPASS          : in  std_logic; -- Driven by core logic
---    RESETB          : in  std_logic; -- Driven by core logic
+    BYPASS          : in  std_logic; -- Driven by core logic
+    RESETB          : in  std_logic -- Driven by core logic
 --    LATCHINPUTVALUE : in  std_logic; -- iCEGate Signal
---    -- Test Pins
+    -- Test Pins
 --    SDO  : out std_logic; -- Output of PLL
 --    SDI  : in std_logic;  -- Driven by core logic
 --    SCLK : in std_logic   -- Driven by core logic
---  );
---end component;
+  );
+end component;
 
 end ICE40_components;