Merge pull request icl-utk-edu#285 from Treece-Burgess/11.15.2024-libpfm4-update

Update libpfm4 to commit 07050c

Author: Treece-Burgess

src/libpfm4/README

@@ -82,9 +82,8 @@ The library supports many PMUs. The current version can handle:
 		Applied Micro X-Gene
 		Qualcomm Krait
 		Fujitsu A64FX
-		Arm Neoverse V1
-		Arm Neoverse V2
-		Arm Neoverse V3
+		Arm Neoverse V1, V2, V3
+		Arm Neoverse N1, N2, N3
 		Huawei HiSilicon Kunpeng 920
 
 	- For SPARC

src/libpfm4/docs/Makefile

@@ -155,6 +155,7 @@ ARCH_MAN += libpfm_arm_xgene.3 \
 	    libpfm_arm_qcom_krait.3 \
 	    libpfm_arm_neoverse_n1.3 \
 	    libpfm_arm_neoverse_n2.3 \
+	    libpfm_arm_neoverse_n3.3 \
 	    libpfm_arm_neoverse_v1.3 \
 	    libpfm_arm_neoverse_v2.3 \
 	    libpfm_arm_neoverse_v3.3
@@ -170,6 +171,7 @@ ARCH_MAN += libpfm_arm_xgene.3 \
 	    libpfm_arm_a64fx.3 \
 	    libpfm_arm_neoverse_n1.3 \
 	    libpfm_arm_neoverse_n2.3 \
+	    libpfm_arm_neoverse_n3.3 \
 	    libpfm_arm_neoverse_v1.3 \
 	    libpfm_arm_neoverse_v2.3 \
 	    libpfm_arm_neoverse_v3.3

src/libpfm4/docs/man3/libpfm_arm_neoverse_n3.3

@@ -0,0 +1,36 @@
+.TH LIBPFM 3  "October, 2024" "" "Linux Programmer's Manual"
+.SH NAME
+libpfm_arm_neoverse_n3 - support for ARM Neoverse N2 core PMU
+.SH SYNOPSIS
+.nf
+.B #include <perfmon/pfmlib.h>
+.sp
+.B PMU name: arm_n3
+.B PMU desc: ARM Neoverse N2
+.sp
+.SH DESCRIPTION
+The library supports the ARM Neoverse N2 core PMU.
+
+This PMU supports 6 or 20 64-bit counters and privilege levels filtering.
+It can operate in both 32 and 64 bit modes.
+
+.SH MODIFIERS
+The following modifiers are supported on ARM Neoverse N3:
+.TP
+.B u
+Measure at the user level. This corresponds to \fBPFM_PLM3\fR.
+This is a boolean modifier.
+.TP
+.B k
+Measure at the kernel level. This corresponds to \fBPFM_PLM0\fR.
+This is a boolean modifier.
+.TP
+.B hv
+Measure at the hypervisor level. This corresponds to \fBPFM_PLMH\fR.
+This is a boolean modifier.
+
+.SH AUTHORS
+.nf
+Stephane Eranian <[email protected]>
+.if
+.PP

src/libpfm4/docs/man3/libpfm_intel_gnr.3

@@ -79,6 +79,11 @@ On Intel GraniteRapids, the event is treated as a regular event with a flat set
 It is not possible to combine the various requests, supplier, snoop bits anymore. Therefore the
 library offers the list of validated combinations as per Intel's official event list.
 
+.SH Topdown via PERF_METRICS
+
+Intel GraniteRapids supports the PERF_METRICS MSR which provides support for Topdown Level 1 and 2 via a single PMU counter. This special counter provides percentages of slots for each metric. This feature must be used in conjunction with fixed counter 3 which counts SLOTS in order to work properly. The Linux kernel exposes PERF_METRICS metrics as individual pseudo events counting in slots unit however to operate correctly all events must be programmed together. The Linux kernel requires all PERF_METRICS events to be programmed as a single event group with the first event as SLOTS required. Example: '{slots,topdown-retiring,topdown-bad-spec,topdown-fe-bound,topdown-be-bound,topdown-heavy-ops,topdown-br-mispredict,topdown-fetch-lat,topdown-mem-bound}'. Libpfm4 provides acces to the PERF_METRICS pseudo events via a dedicated event called \fBTOPDOWN_M\fR. This event uses the pseudo encodings assigned by the Linux kernel to PERF_METRICS pseudo events. Using these encodings ensures the kernel detects them as targeting the PERF_METRICS MSR. Note that libpfm4 only provides the encodings and that it is up the user on Linux to group them and order them properly for the perf_events interface. There exists generic counter encodings for most of the Topdown metrics and libpfm4 provides support for those via the \fBTOPDOWN\fR event. Note that all subevents of \fBTOPDOWN_M\fR use fixed counters which have, by definition, no actual event codes. The library uses the Linux pseudo event codes for them, even when compiled on non Linux operating systems.The same holds true for any fixed counters pseudo event exported by libpfm4.
+
+
 .SH AUTHORS
 .nf
 Stephane Eranian <[email protected]>

src/libpfm4/docs/man3/libpfm_intel_icl.3

@@ -77,6 +77,10 @@ On Intel IceLake unlike older processors, the event is treated as a regular even
 It is not possible to combine the various requests, supplier, snoop bits anymore. Therefore the
 library offers the list of validated combinations as per Intel's official event list.
 
+.SH Topdown via PERF_METRICS
+
+Intel Icelake supports the PERF_METRICS MSR which provides support for Topdown Level 1 via a single PMU counter. This special counter provides percentages of slots for each metric. This feature must be used in conjunction with fixed counter 3 which counts SLOTS in order to work properly. The Linux kernel exposes PERF_METRICS metrics as individual pseudo events counting in slots unit however to operate correctly all events must be programmed together. The Linux kernel requires all PERF_METRICS events to be programmed as a single event group with the first event as SLOTS required. Example: '{slots,topdown-retiring,topdown-bad-spec,topdown-fe-bound,topdown-be-bound,topdown-heavy-ops,topdown-br-mispredict,topdown-fetch-lat,topdown-mem-bound}'. Libpfm4 provides acces to the PERF_METRICS pseudo events via a dedicated event called \fBTOPDOWN_M\fR. This event uses the pseudo encodings assigned by the Linux kernel to PERF_METRICS pseudo events. Using these encodings ensures the kernel detects them as targeting the PERF_METRICS MSR. Note that libpfm4 only provides the encodings and that it is up the user on Linux to group them and order them properly for the perf_events interface. There exists generic counter encodings for most of the Topdown metrics and libpfm4 provides support for those via the \fBTOPDOWN\fR event. Note that all subevents of \fBTOPDOWN_M\fR use fixed counters which have, by definition, no actual event codes. The library uses the Linux pseudo event codes for them, even when compiled on non Linux operating systems.The same holds true for any fixed counters pseudo event exported by libpfm4.
+
 .SH AUTHORS
 .nf
 Stephane Eranian <[email protected]>

src/libpfm4/docs/man3/libpfm_intel_spr.3

@@ -1,25 +1,25 @@
 .TH LIBPFM 3  "April, 2022" "" "Linux Programmer's Manual"
 .SH NAME
-libpfm_intel_spr - support for Intel SapphireRapid core PMU
+libpfm_intel_spr - support for Intel SapphireRapids core PMU
 .SH SYNOPSIS
 .nf
 .B #include <perfmon/pfmlib.h>
 .sp
 .B PMU name: spr
-.B PMU desc: Intel SapphireRapid
+.B PMU desc: Intel SapphireRapids
 .sp
 .SH DESCRIPTION
-The library supports the Intel SapphireRapid core PMU. It should be noted that
+The library supports the Intel SapphireRapids core PMU. It should be noted that
 this PMU model only covers each core's PMU and not the socket level
 PMU.
 
-On SapphireRapid, the number of generic counters depends on the Hyperthreading (HT) mode.
+On SapphireRapids, the number of generic counters depends on the Hyperthreading (HT) mode.
 
 The \fBpfm_get_pmu_info()\fR function returns the maximum number
 of generic counters in \fBnum_cntrs\fr.
 
 .SH MODIFIERS
-The following modifiers are supported on Intel SapphireRapid processors:
+The following modifiers are supported on Intel SapphireRapids processors:
 .TP
 .B u
 Measure at user level which includes privilege levels 1, 2, 3. This corresponds to \fBPFM_PLM3\fR.
@@ -62,7 +62,7 @@ counts. It acts as a threshold, i.e., at least a period of N core cycles where t
 be used with the IDQ_*_BUBBLES umasks. If not specified, the default threshold value is 1 cycle. the valid values are in [1-4095].
 
 .SH OFFCORE_RESPONSE events
-Intel SapphireRapid supports two encodings for offcore_response events. In the library, these are called OFFCORE_RESPONSE_0 and OFFCORE_RESPONSE_1.
+Intel SapphireRapids supports two encodings for offcore_response events. In the library, these are called OFFCORE_RESPONSE_0 and OFFCORE_RESPONSE_1.
 
 Those events need special treatment in the performance monitoring infrastructure
 because each event uses an extra register to store some settings. Thus, in
@@ -73,10 +73,14 @@ The offcore_response events are exposed as a normal events by the library. The e
 settings are exposed as regular umasks. The library takes care of encoding the
 events according to the underlying kernel interface.
 
-On Intel SapphireRapid unlike older processors, the event is treated as a regular event with a flat set of umasks to choose from.
+On Intel SapphireRapids unlike older processors, the event is treated as a regular event with a flat set of umasks to choose from.
 It is not possible to combine the various requests, supplier, snoop bits anymore. Therefore the
 library offers the list of validated combinations as per Intel's official event list.
 
+.SH Topdown via PERF_METRICS
+
+Intel SapphireRapids supports the PERF_METRICS MSR which provides support for Topdown Level 1 and 2 via a single PMU counter. This special counter provides percentages of slots for each metric. This feature must be used in conjunction with fixed counter 3 which counts SLOTS in order to work properly. The Linux kernel exposes PERF_METRICS metrics as individual pseudo events counting in slots unit however to operate correctly all events must be programmed together. The Linux kernel requires all PERF_METRICS events to be programmed as a single event group with the first event as SLOTS required. Example: '{slots,topdown-retiring,topdown-bad-spec,topdown-fe-bound,topdown-be-bound,topdown-heavy-ops,topdown-br-mispredict,topdown-fetch-lat,topdown-mem-bound}'. Libpfm4 provides acces to the PERF_METRICS pseudo events via a dedicated event called \fBTOPDOWN_M\fR. This event uses the pseudo encodings assigned by the Linux kernel to PERF_METRICS pseudo events. Using these encodings ensures the kernel detects them as targeting the PERF_METRICS MSR. Note that libpfm4 only provides the encodings and that it is up the user on Linux to group them and order them properly for the perf_events interface. There exists generic counter encodings for most of the Topdown metrics and libpfm4 provides support for those via the \fBTOPDOWN\fR event. Note that all subevents of \fBTOPDOWN_M\fR use fixed counters which have, by definition, no actual event codes. The library uses the Linux pseudo event codes for them, even when compiled on non Linux operating systems.The same holds true for any fixed counters pseudo event exported by libpfm4.
+
 .SH AUTHORS
 .nf
 Stephane Eranian <[email protected]>

src/libpfm4/docs/man3/pfm_get_event_attr_info.3

@@ -46,7 +46,9 @@ typedef struct {
                 int             is_dfl:1;
                 int             is_precise:1;
                 int             is_speculative:2;
-                int             reserved:28;
+		int		support_hw_smpl:1;
+		int		support_no_mods:1;
+                int             reserved:26;
         };
         union {
                 uint64_t        dfl_val64;
@@ -136,6 +138,16 @@ information is not available. A value of \fBPFM_EVENT_INFO_SPEC_TRUE\fR indicate
 that the attribute counts during speculative execution. A value of \fBPFM_EVENT_INFO_SPEC_FALSE\fR
 indicates that the attribute does not count during speculative execution.
 .TP
+.B support_hw_smpl
+This boolean field indicates that the attribute (in this case a umask) supports hardware sampling.
+That means the hardware can sample this event+umasks without involving the kernel at each sample.
+.TP
+.B support_no_mods
+This boolean field indicates that the attribute (in this case a umask) does not support any hardware
+or software modifiers, such as privilege level filters, sampling, precise sampling, and such. This
+is necessary when select umasks of an event have more restrictions than others, e.g., the event and
+most umasks support modifiers except a few umasks.
+.TP
 .B dfl_val64, dfl_str, dfl_bool, dfl_int
 This union contains the value of an attribute. For PFM_ATTR_UMASK, the is
 the unit mask code, for all other types this is the actual value of the

src/libpfm4/examples/showevtinfo.c

@@ -403,6 +403,11 @@ print_attr_flags(pfm_event_attr_info_t *info)
 	int n = 0;
 	int spec = info->is_speculative;
 
+	if (info->support_no_mods) {
+		printf("[no modifier supported] ");
+		n++;
+	}
+
 	if (info->is_dfl) {
 		printf("[default] ");
 		n++;

src/libpfm4/include/perfmon/pfmlib.h

@@ -819,6 +819,7 @@ typedef enum {
 	PFM_PMU_ARM_V3,			/* Arm Neoverse V3 (ARMv9) */
 	PFM_PMU_ARM_CORTEX_A55,		/* ARM Cortex A55 (ARMv8) */
 	PFM_PMU_ARM_CORTEX_A76,		/* ARM Cortex A76 (ARMv8) */
+	PFM_PMU_ARM_N3,			/* Arm Neoverse N3 */
 	/* MUST ADD NEW PMU MODELS HERE */
 
 	PFM_PMU_MAX			/* end marker */
@@ -961,7 +962,8 @@ typedef struct {
 		unsigned int    is_precise:1;	  /* Intel X86: supports PEBS */
 		unsigned int	is_speculative:2; /* count correct and wrong path occurrences */
 		unsigned int	support_hw_smpl:1;/* can be recorded by hw buffer (Intel X86=EXTPEBS) */
-		unsigned int	reserved_bits:27;
+		unsigned int	support_no_mods:1;/* attribute does not support modifiers (umask only) */
+		unsigned int	reserved_bits:26;
 	} SWIG_NAME(flags);
 	union {
 		uint64_t	dfl_val64;	/* default 64-bit value */