Skip to content

Commit 4b0a7e6

Browse files
committed
[InstCombine] Add an extra test for udiv_shl_pair_const with vscale
1 parent 7c60725 commit 4b0a7e6

File tree

2 files changed

+37
-0
lines changed

2 files changed

+37
-0
lines changed

llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-opts-counting-elems.ll

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -240,6 +240,23 @@ define i64 @cntd_all() {
240240
}
241241

242242

243+
define i64 @udiv() vscale_range(1, 16) {
244+
; CHECK-LABEL: @udiv(
245+
; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
246+
; CHECK-NEXT: [[B:%.*]] = shl nuw nsw i64 [[TMP2]], 4
247+
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
248+
; CHECK-NEXT: [[B1:%.*]] = shl nuw nsw i64 [[TMP3]], 2
249+
; CHECK-NEXT: [[TMP4:%.*]] = call range(i64 2, 65) i64 @llvm.cttz.i64(i64 [[B1]], i1 true)
250+
; CHECK-NEXT: [[C:%.*]] = lshr i64 [[B]], [[TMP4]]
251+
; CHECK-NEXT: ret i64 [[C]]
252+
;
253+
%a = call i64 @llvm.aarch64.sve.cntb(i32 31)
254+
%b = call i64 @llvm.aarch64.sve.cntw(i32 31)
255+
%c = udiv i64 %a, %b
256+
ret i64 %c
257+
}
258+
259+
243260
declare i64 @llvm.aarch64.sve.cntb(i32 %pattern)
244261
declare i64 @llvm.aarch64.sve.cnth(i32 %pattern)
245262
declare i64 @llvm.aarch64.sve.cntw(i32 %pattern)

llvm/test/Transforms/InstCombine/div-shift.ll

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1399,3 +1399,23 @@ start:
13991399
%div = udiv i8 %x, %y
14001400
ret i8 %div
14011401
}
1402+
1403+
define i32 @udiv_shl_pair_const_vscale() vscale_range(1, 16) {
1404+
; CHECK-LABEL: @udiv_shl_pair_const_vscale(
1405+
; CHECK-NEXT: entry:
1406+
; CHECK-NEXT: [[A:%.*]] = call i32 @llvm.vscale.i32()
1407+
; CHECK-NEXT: [[B:%.*]] = call i32 @llvm.vscale.i32()
1408+
; CHECK-NEXT: [[LHS:%.*]] = shl nuw nsw i32 [[A]], 2
1409+
; CHECK-NEXT: [[RHS:%.*]] = shl nuw nsw i32 [[B]], 1
1410+
; CHECK-NEXT: [[TMP0:%.*]] = call range(i32 1, 33) i32 @llvm.cttz.i32(i32 [[RHS]], i1 true)
1411+
; CHECK-NEXT: [[DIV:%.*]] = lshr i32 [[LHS]], [[TMP0]]
1412+
; CHECK-NEXT: ret i32 [[DIV]]
1413+
;
1414+
entry:
1415+
%a = call i32 @llvm.vscale()
1416+
%b = call i32 @llvm.vscale()
1417+
%lhs = shl nuw i32 %a, 2
1418+
%rhs = shl nuw i32 %b, 1
1419+
%div = udiv i32 %lhs, %rhs
1420+
ret i32 %div
1421+
}

0 commit comments

Comments
 (0)