Expanding the DarkRISCV Family!

[samsoniuk]

Hello Colleagues!

I think It is the moment to expand the DarkRISCV family in order to keep it simple, clear and at same time introduce new features. The proposal is split the core and the upper layers in a way that the complexity of new features does not affect the existing features, resulting in three lines of development:

• the 2-stage pipeline core w/ MAC and on-chip DPRAM, to provide ~40MIPS@50MHz
• the 3-stage pipeline core w/ MT, MAC and on-chip DPRAM support, to provide ~70MIPS@100MHz
• the new configurable and modular pipeline core w/ MT, MAC designed in a more modular way, with support for on-chip DPRAM, on-chip caches, external SDRAM/DDR and other new features.

Basically, the first two cores will focus the stability and simplicity, while the third core will be used to introduce and test new features, as well optimize them in order that the updates can be released in the first two cores or new intermediary cores to be introduced. In some sense, the first two cores will work as a kind of "design freeze", in a way that there will be some guarantee that new features will not create incompatibilities in the already deployed cores.

Finally, In order to keep the chronology, the proposal is call the cores as:

• DarkRISCV V1 or DarkRISCV "Classic" in the case of 2-stage pipeline core
• DarkRISCV V2 or DarkRISCV "Advanced" in the case of 3-stage pipeline core
• DarkRISCV V3 or DarkRISCV "Research" in the case of the new modular core

The names "Advanced" and "Research" are really, really bad choices and I probably need think in something better... anyway, feel free to comment and make suggestions.

Best regards,
Marcelo