Add ci job for simd models tests, with logging of rng seed.

Author: maximebuyse

.github/workflows/testable-simd-models.yml

@@ -0,0 +1,30 @@
+# This workflow runs the tests for testable simd models.
+
+name: Testable simd models
+
+on:
+  workflow_dispatch:
+  merge_group:
+  pull_request:
+    branches: [ main ]
+  push:
+    paths:
+      - '.github/workflows/testable-simd-models.yml'
+      - 'testable-simd-models/**'
+
+defaults:
+  run:
+    shell: bash
+
+jobs:
+  testable-simd-models:
+    name: Test testable simd models
+    runs-on: ubuntu-latest
+    
+    steps:
+      - name: Checkout Repository
+        uses: actions/checkout@v4
+      
+      - name: Run tests
+        run: cargo test -- --test-threads=1 --nocapture
+        

testable-simd-models/Cargo.toml

@@ -11,6 +11,7 @@ readme = "README.md"
 [dependencies]
 rand = "0.9"
 pastey = "0.1.0"
+lazy_static = "1.5.0"
 
 [lints.rust]
 unexpected_cfgs = { level = "warn" }

testable-simd-models/src/abstractions/bitvec.rs

@@ -106,16 +106,6 @@ impl<const N: u32> BitVec<N> {
             .map(int_from_bit_slice)
             .collect()
     }
-
-    /// Generate a random BitVec.
-    pub fn rand() -> Self {
-        use rand::prelude::*;
-        let random_source: Vec<_> = {
-            let mut rng = rand::rng();
-            (0..N).map(|_| rng.random::<bool>()).collect()
-        };
-        Self::from_fn(|i| random_source[i as usize].into())
-    }
 }
 
 impl<const N: u32> BitVec<N> {

testable-simd-models/src/core_arch/x86/models/avx2_handwritten.rs

@@ -419,7 +419,6 @@ pub fn psravd(a: i32x4, count: i32x4) -> i32x4 {
 }
 
 pub fn psravd256(a: i32x8, count: i32x8) -> i32x8 {
-    dbg!(a, count);
     i32x8::from_fn(|i| {
         if count[i] > 31 || count[i] < 0 {
             if a[i] < 0 {

testable-simd-models/src/core_arch/x86/tests/avx.rs

@@ -49,7 +49,9 @@ fn _mm256_movemask_ps() {
         let a: BitVec<256> = BitVec::random();
         assert_eq!(
             super::super::models::avx::_mm256_movemask_ps(a.into()),
-            unsafe { upstream::_mm256_movemask_ps(a.into()) }
+            unsafe { upstream::_mm256_movemask_ps(a.into()) },
+            "Failed with input value: {:?}",
+            a
         );
     }
 }
@@ -62,7 +64,9 @@ fn _mm256_movemask_pd() {
         let a: BitVec<256> = BitVec::random();
         assert_eq!(
             super::super::models::avx::_mm256_movemask_pd(a.into()),
-            unsafe { upstream::_mm256_movemask_pd(a.into()) }
+            unsafe { upstream::_mm256_movemask_pd(a.into()) },
+            "Failed with input value: {:?}",
+            a
         );
     }
 }
@@ -76,7 +80,10 @@ fn _mm256_testz_si256() {
         let b: BitVec<256> = BitVec::random();
         assert_eq!(
             super::super::models::avx::_mm256_testz_si256(a.into(), b.into()),
-            unsafe { upstream::_mm256_testz_si256(a.into(), b.into()) }
+            unsafe { upstream::_mm256_testz_si256(a.into(), b.into()) },
+            "Failed with input values: {:?}, {:?}",
+            a,
+            b
         );
     }
 }
@@ -90,7 +97,10 @@ fn _mm256_testc_si256() {
         let b: BitVec<256> = BitVec::random();
         assert_eq!(
             super::super::models::avx::_mm256_testc_si256(a.into(), b.into()),
-            unsafe { upstream::_mm256_testc_si256(a.into(), b.into()) }
+            unsafe { upstream::_mm256_testc_si256(a.into(), b.into()) },
+            "Failed with input values: {:?}, {:?}",
+            a,
+            b
         );
     }
 }
@@ -116,7 +126,9 @@ fn _mm256_cvtsi256_si32() {
         let a: BitVec<256> = BitVec::random();
         assert_eq!(
             super::super::models::avx::_mm256_cvtsi256_si32(a.into()),
-            unsafe { upstream::_mm256_cvtsi256_si32(a.into()) }
+            unsafe { upstream::_mm256_cvtsi256_si32(a.into()) },
+            "Failed with input value: {:?}",
+            a
         );
     }
 }