Periodically calibrate OSC16M during sleep

[smaeul]

Type of issue

Enhancement

Description

Wakeup sources like CEC and CIR need an accurate clock to do protocol decoding. Boards without external OSC32K get OSC32K divided from OSC16M. Since OSC16M's frequency drifts over time, and with temperature, the divider for OSC32K should periodically be recalculated to keep it as accurate as possible. Otherwise these wakeup sources do not work.

We have similar problems on some H6 boards where the OSC16M frequency shifts enough during CCU/PRCM suspend that the UART baud goes out of spec while the system is in sleep.

This involves two parts:

1. Turning on OSC24M long enough to run the calibration procedure. On some SoCs, the hardware calibration function can be used.
2. Some way of notifying drivers that they need to recalculate their clock dividers. This includes the CCU itself for OSC32K, but also the CIR, UART, and possibly I2C/RSB drivers, which have their own internal dividers.

[masterblaster79]

I just wanted to say that I am hit by this limitation and am interested in the workaround getting implemented.
My usecase:
I am using an Allwinner H6 based tvbox (Tanix TX6) as an all-in-one dvr solution with tvheadend. Unfortunately I cannot make it wake up in time for scheduled recordings because the RTC is running too slow in my case.
(Impressive low-lewel stuff you are coding here btw..)