diff --git a/x86/x86.md b/x86/x86.md
index bd39608..ba47de2 100644
--- a/x86/x86.md
+++ b/x86/x86.md
@@ -340,13 +340,13 @@ no other word is changed.
 `bsf/r` are undefined when its source is 0. In practice, the target register is not modified.
 
 ## lzcnt
-`lzcnt` (Leading Zero CouNT) is an opcode created in 2007, only supported by AMD in their Barcelona architecture and later (it's planned in Intel Haswell for 2013, along with its counterpart `tzcnt`).
+`lzcnt` (Leading Zero CouNT) is an opcode created in 2007, only supported by AMD in their Barcelona architecture. In 2013 added to Intel Haswell, along with its counterpart `tzcnt` (Trailing Zero CouNT).
 
 Recent opcodes would usually trigger an exception when executed on a CPU not supporting them.
 
 However, this one is mapped on `0fbd: bsr` (Bit Scan Reverse) with an `f3` prefix, so it will not trigger any exception on a CPU that doesn't support it:
  1. it will just execute `bsr` and ignore the prefix.
- 1. `bsr` and `lzcnt` work on the same register, and have the same instruction length, so the same target register will be modified, and the next instruction will be the same. Thus, only the target register and flags might be different.
+ 1. `bsr` and `lzcnt` work on the same register, and have the same instruction length, so the same target register will be modified, and the next instruction will be the same. Thus, only the target register and flags might be different. Besides, with a null source, `lzcnt` will return a null value, while `bsr` will leave the target unmodified.
 
 if you execute:
 
@@ -376,8 +376,6 @@ f3         <== ignored prefix
 ```
 
 
-It makes `lzcnt` an odd exception-less AMD detector (for now): besides, with a null source, `lzcnt` will return a null value, while `bsr` will leave the target unmodified.
-
 ## sal
 ![](pics/x86_sal.gif)
 
@@ -605,7 +603,7 @@ prefetch [eax]
 ![](pics/x86_oldpath.gif)
 
 ## future opcodes
-Intel Haswell will introduce very useful opcodes (on general registers) such as:
+Intel Haswell introduced very useful opcodes (on general registers) such as:
  * `andn`: