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microkernels.bzl
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microkernels.bzl
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"""
Microkernel filenames lists.
Auto-generated file. Do not edit!
Generator: tools/update-microkernels.py
"""
ALL_ARMSIMD32_MICROKERNEL_SRCS = [
"src/qc8-gemm/gen/qc8-gemm-1x1c4-minmax-fp32-armsimd32.c",
"src/qc8-gemm/gen/qc8-gemm-1x2c4-minmax-fp32-armsimd32.c",
"src/qc8-gemm/gen/qc8-gemm-2x1c4-minmax-fp32-armsimd32.c",
"src/qc8-gemm/gen/qc8-gemm-2x2c4-minmax-fp32-armsimd32.c",
"src/qc8-igemm/gen/qc8-igemm-1x1c4-minmax-fp32-armsimd32.c",
"src/qc8-igemm/gen/qc8-igemm-1x2c4-minmax-fp32-armsimd32.c",
"src/qc8-igemm/gen/qc8-igemm-2x1c4-minmax-fp32-armsimd32.c",
"src/qc8-igemm/gen/qc8-igemm-2x2c4-minmax-fp32-armsimd32.c",
"src/qs8-gemm/gen/qs8-gemm-1x1c4-minmax-fp32-armsimd32.c",
"src/qs8-gemm/gen/qs8-gemm-1x2c4-minmax-fp32-armsimd32.c",
"src/qs8-gemm/gen/qs8-gemm-2x1c4-minmax-fp32-armsimd32.c",
"src/qs8-gemm/gen/qs8-gemm-2x2c4-minmax-fp32-armsimd32.c",
"src/qs8-igemm/gen/qs8-igemm-1x1c4-minmax-fp32-armsimd32.c",
"src/qs8-igemm/gen/qs8-igemm-1x2c4-minmax-fp32-armsimd32.c",
"src/qs8-igemm/gen/qs8-igemm-2x1c4-minmax-fp32-armsimd32.c",
"src/qs8-igemm/gen/qs8-igemm-2x2c4-minmax-fp32-armsimd32.c",
"src/qs8-vcvt/gen/qs8-vcvt-armsimd32-x4.c",
"src/qs8-vcvt/gen/qs8-vcvt-armsimd32-x8.c",
"src/qs8-vlrelu/gen/qs8-vlrelu-armsimd32-x4.c",
"src/qs8-vlrelu/gen/qs8-vlrelu-armsimd32-x8.c",
"src/qu8-gemm/gen/qu8-gemm-1x1c4-minmax-fp32-armsimd32.c",
"src/qu8-gemm/gen/qu8-gemm-1x2c4-minmax-fp32-armsimd32.c",
"src/qu8-gemm/gen/qu8-gemm-2x1c4-minmax-fp32-armsimd32.c",
"src/qu8-gemm/gen/qu8-gemm-2x2c4-minmax-fp32-armsimd32.c",
"src/qu8-igemm/gen/qu8-igemm-1x1c4-minmax-fp32-armsimd32.c",
"src/qu8-igemm/gen/qu8-igemm-1x2c4-minmax-fp32-armsimd32.c",
"src/qu8-igemm/gen/qu8-igemm-2x1c4-minmax-fp32-armsimd32.c",
"src/qu8-igemm/gen/qu8-igemm-2x2c4-minmax-fp32-armsimd32.c",
"src/qu8-vcvt/gen/qu8-vcvt-armsimd32-x4.c",
"src/qu8-vcvt/gen/qu8-vcvt-armsimd32-x8.c",
"src/qu8-vlrelu/gen/qu8-vlrelu-armsimd32-x4.c",
"src/qu8-vlrelu/gen/qu8-vlrelu-armsimd32-x8.c",
]
ALL_AVX_MICROKERNEL_SRCS = [
"src/f16-f32-vcvt/gen/f16-f32-vcvt-avx-int16-x8.c",
"src/f16-f32-vcvt/gen/f16-f32-vcvt-avx-int16-x16.c",
"src/f16-f32-vcvt/gen/f16-f32-vcvt-avx-int16-x24.c",
"src/f16-f32-vcvt/gen/f16-f32-vcvt-avx-int16-x32.c",
"src/f16-f32-vcvt/gen/f16-f32-vcvt-avx-int32-x8.c",
"src/f16-f32-vcvt/gen/f16-f32-vcvt-avx-int32-x16.c",
"src/f16-f32-vcvt/gen/f16-f32-vcvt-avx-int32-x24.c",
"src/f16-f32-vcvt/gen/f16-f32-vcvt-avx-int32-x32.c",
"src/f32-dwconv/gen/f32-dwconv-3p8c-minmax-avx-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-3p8c-minmax-avx.c",
"src/f32-dwconv/gen/f32-dwconv-3p16c-minmax-avx-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-3p16c-minmax-avx.c",
"src/f32-dwconv/gen/f32-dwconv-4p8c-minmax-avx-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-4p8c-minmax-avx.c",
"src/f32-dwconv/gen/f32-dwconv-4p16c-minmax-avx-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-4p16c-minmax-avx.c",
"src/f32-dwconv/gen/f32-dwconv-5f5m5l8c8s4r-minmax-avx-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-5f5m5l8c8s4r-minmax-avx.c",
"src/f32-dwconv/gen/f32-dwconv-5f5m5l16c8s4r-minmax-avx-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-5f5m5l16c8s4r-minmax-avx.c",
"src/f32-dwconv/gen/f32-dwconv-6f6m7l8c8s4r-minmax-avx-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-6f6m7l8c8s4r-minmax-avx.c",
"src/f32-dwconv/gen/f32-dwconv-6f6m7l16c8s4r-minmax-avx-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-6f6m7l16c8s4r-minmax-avx.c",
"src/f32-dwconv/gen/f32-dwconv-8f8m9l8c8s4r-minmax-avx-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-8f8m9l8c8s4r-minmax-avx.c",
"src/f32-dwconv/gen/f32-dwconv-8f8m9l16c8s4r-minmax-avx-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-8f8m9l16c8s4r-minmax-avx.c",
"src/f32-dwconv/gen/f32-dwconv-9p8c-minmax-avx-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-9p8c-minmax-avx.c",
"src/f32-dwconv/gen/f32-dwconv-9p16c-minmax-avx-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-9p16c-minmax-avx.c",
"src/f32-dwconv/gen/f32-dwconv-25p8c-minmax-avx-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-25p8c-minmax-avx.c",
"src/f32-dwconv/gen/f32-dwconv-25p16c-minmax-avx-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-25p16c-minmax-avx.c",
"src/f32-f16-vcvt/gen/f32-f16-vcvt-avx-x8.c",
"src/f32-f16-vcvt/gen/f32-f16-vcvt-avx-x16.c",
"src/f32-f16-vcvt/gen/f32-f16-vcvt-avx-x24.c",
"src/f32-f16-vcvt/gen/f32-f16-vcvt-avx-x32.c",
"src/f32-gemm/gen/f32-gemm-1x8-minmax-avx-broadcast.c",
"src/f32-gemm/gen/f32-gemm-1x16-minmax-avx-broadcast.c",
"src/f32-gemm/gen/f32-gemm-3x16-minmax-avx-broadcast.c",
"src/f32-gemm/gen/f32-gemm-4x8-minmax-avx-broadcast.c",
"src/f32-gemm/gen/f32-gemm-4x16-minmax-avx-broadcast.c",
"src/f32-gemm/gen/f32-gemm-5x8-minmax-avx-broadcast.c",
"src/f32-gemm/gen/f32-gemm-5x16-minmax-avx-broadcast.c",
"src/f32-gemm/gen/f32-gemm-6x8-minmax-avx-broadcast.c",
"src/f32-gemm/gen/f32-gemm-7x8-minmax-avx-broadcast.c",
"src/f32-gemm/gen/f32-gemminc-1x8-minmax-avx-broadcast.c",
"src/f32-gemm/gen/f32-gemminc-1x16-minmax-avx-broadcast.c",
"src/f32-gemm/gen/f32-gemminc-3x16-minmax-avx-broadcast.c",
"src/f32-gemm/gen/f32-gemminc-4x8-minmax-avx-broadcast.c",
"src/f32-gemm/gen/f32-gemminc-4x16-minmax-avx-broadcast.c",
"src/f32-gemm/gen/f32-gemminc-5x8-minmax-avx-broadcast.c",
"src/f32-gemm/gen/f32-gemminc-5x16-minmax-avx-broadcast.c",
"src/f32-gemm/gen/f32-gemminc-6x8-minmax-avx-broadcast.c",
"src/f32-gemm/gen/f32-gemminc-7x8-minmax-avx-broadcast.c",
"src/f32-igemm/gen/f32-igemm-1x8-minmax-avx-broadcast.c",
"src/f32-igemm/gen/f32-igemm-1x16-minmax-avx-broadcast.c",
"src/f32-igemm/gen/f32-igemm-3x16-minmax-avx-broadcast.c",
"src/f32-igemm/gen/f32-igemm-4x8-minmax-avx-broadcast.c",
"src/f32-igemm/gen/f32-igemm-4x16-minmax-avx-broadcast.c",
"src/f32-igemm/gen/f32-igemm-5x8-minmax-avx-broadcast.c",
"src/f32-igemm/gen/f32-igemm-5x16-minmax-avx-broadcast.c",
"src/f32-igemm/gen/f32-igemm-6x8-minmax-avx-broadcast.c",
"src/f32-igemm/gen/f32-igemm-7x8-minmax-avx-broadcast.c",
"src/f32-prelu/gen/f32-prelu-avx-2x8.c",
"src/f32-prelu/gen/f32-prelu-avx-2x16.c",
"src/f32-qs8-vcvt/gen/f32-qs8-vcvt-avx-x8.c",
"src/f32-qs8-vcvt/gen/f32-qs8-vcvt-avx-x16.c",
"src/f32-qs8-vcvt/gen/f32-qs8-vcvt-avx-x24.c",
"src/f32-qs8-vcvt/gen/f32-qs8-vcvt-avx-x32.c",
"src/f32-qu8-vcvt/gen/f32-qu8-vcvt-avx-x8.c",
"src/f32-qu8-vcvt/gen/f32-qu8-vcvt-avx-x16.c",
"src/f32-qu8-vcvt/gen/f32-qu8-vcvt-avx-x24.c",
"src/f32-qu8-vcvt/gen/f32-qu8-vcvt-avx-x32.c",
"src/f32-rmax/f32-rmax-avx.c",
"src/f32-vbinary/gen/f32-vadd-minmax-avx-x8.c",
"src/f32-vbinary/gen/f32-vadd-minmax-avx-x16.c",
"src/f32-vbinary/gen/f32-vaddc-minmax-avx-x8.c",
"src/f32-vbinary/gen/f32-vaddc-minmax-avx-x16.c",
"src/f32-vbinary/gen/f32-vdiv-minmax-avx-x8.c",
"src/f32-vbinary/gen/f32-vdiv-minmax-avx-x16.c",
"src/f32-vbinary/gen/f32-vdivc-minmax-avx-x8.c",
"src/f32-vbinary/gen/f32-vdivc-minmax-avx-x16.c",
"src/f32-vbinary/gen/f32-vmax-avx-x8.c",
"src/f32-vbinary/gen/f32-vmax-avx-x16.c",
"src/f32-vbinary/gen/f32-vmaxc-avx-x8.c",
"src/f32-vbinary/gen/f32-vmaxc-avx-x16.c",
"src/f32-vbinary/gen/f32-vmin-avx-x8.c",
"src/f32-vbinary/gen/f32-vmin-avx-x16.c",
"src/f32-vbinary/gen/f32-vminc-avx-x8.c",
"src/f32-vbinary/gen/f32-vminc-avx-x16.c",
"src/f32-vbinary/gen/f32-vmul-minmax-avx-x8.c",
"src/f32-vbinary/gen/f32-vmul-minmax-avx-x16.c",
"src/f32-vbinary/gen/f32-vmulc-minmax-avx-x8.c",
"src/f32-vbinary/gen/f32-vmulc-minmax-avx-x16.c",
"src/f32-vbinary/gen/f32-vrdivc-minmax-avx-x8.c",
"src/f32-vbinary/gen/f32-vrdivc-minmax-avx-x16.c",
"src/f32-vbinary/gen/f32-vrsubc-minmax-avx-x8.c",
"src/f32-vbinary/gen/f32-vrsubc-minmax-avx-x16.c",
"src/f32-vbinary/gen/f32-vsqrdiff-avx-x8.c",
"src/f32-vbinary/gen/f32-vsqrdiff-avx-x16.c",
"src/f32-vbinary/gen/f32-vsqrdiffc-avx-x8.c",
"src/f32-vbinary/gen/f32-vsqrdiffc-avx-x16.c",
"src/f32-vbinary/gen/f32-vsub-minmax-avx-x8.c",
"src/f32-vbinary/gen/f32-vsub-minmax-avx-x16.c",
"src/f32-vbinary/gen/f32-vsubc-minmax-avx-x8.c",
"src/f32-vbinary/gen/f32-vsubc-minmax-avx-x16.c",
"src/f32-vclamp/gen/f32-vclamp-avx-x8.c",
"src/f32-vclamp/gen/f32-vclamp-avx-x16.c",
"src/f32-velu/gen/f32-velu-avx-rr2-lut4-p4-perm-x8.c",
"src/f32-velu/gen/f32-velu-avx-rr2-lut4-p4-perm-x16.c",
"src/f32-velu/gen/f32-velu-avx-rr2-lut4-p4-perm-x24.c",
"src/f32-velu/gen/f32-velu-avx-rr2-lut4-p4-perm-x32.c",
"src/f32-velu/gen/f32-velu-avx-rr2-lut4-p4-perm-x40.c",
"src/f32-velu/gen/f32-velu-avx-rr2-lut4-p4-perm-x48.c",
"src/f32-velu/gen/f32-velu-avx-rr2-lut16-p3-x8.c",
"src/f32-velu/gen/f32-velu-avx-rr2-lut16-p3-x16.c",
"src/f32-velu/gen/f32-velu-avx-rr2-lut16-p3-x24.c",
"src/f32-velu/gen/f32-velu-avx-rr2-lut16-p3-x32.c",
"src/f32-velu/gen/f32-velu-avx-rr2-lut16-p3-x40.c",
"src/f32-velu/gen/f32-velu-avx-rr2-lut16-p3-x48.c",
"src/f32-velu/gen/f32-velu-avx-rr2-p6-x8.c",
"src/f32-velu/gen/f32-velu-avx-rr2-p6-x16.c",
"src/f32-velu/gen/f32-velu-avx-rr2-p6-x24.c",
"src/f32-velu/gen/f32-velu-avx-rr2-p6-x32.c",
"src/f32-velu/gen/f32-velu-avx-rr2-p6-x40.c",
"src/f32-velu/gen/f32-velu-avx-rr2-p6-x48.c",
"src/f32-vhswish/gen/f32-vhswish-avx-x8.c",
"src/f32-vhswish/gen/f32-vhswish-avx-x16.c",
"src/f32-vlrelu/gen/f32-vlrelu-avx-x8.c",
"src/f32-vlrelu/gen/f32-vlrelu-avx-x16.c",
"src/f32-vrelu/gen/f32-vrelu-avx-x8.c",
"src/f32-vrelu/gen/f32-vrelu-avx-x16.c",
"src/f32-vrnd/gen/f32-vrndd-avx-x8.c",
"src/f32-vrnd/gen/f32-vrndd-avx-x16.c",
"src/f32-vrnd/gen/f32-vrndne-avx-x8.c",
"src/f32-vrnd/gen/f32-vrndne-avx-x16.c",
"src/f32-vrnd/gen/f32-vrndu-avx-x8.c",
"src/f32-vrnd/gen/f32-vrndu-avx-x16.c",
"src/f32-vrnd/gen/f32-vrndz-avx-x8.c",
"src/f32-vrnd/gen/f32-vrndz-avx-x16.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-x8.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-x16.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-x24.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-x32.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-x40.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-x48.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-x56.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-x64.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-x72.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-x80.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-nr2-x8.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-nr2-x16.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-nr2-x24.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-nr2-x32.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-nr2-x40.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-nr2-x48.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-nr2-x56.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-nr2-x64.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-nr2-x72.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-nr2-x80.c",
"src/f32-vsqrt/gen/f32-vsqrt-avx-sqrt-x8.c",
"src/f32-vsqrt/gen/f32-vsqrt-avx-sqrt-x16.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2-div-x8.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2-div-x16.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2-div-x24.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2-div-x32.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2-div-x40.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2-div-x48.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2-div-x56.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2-div-x64.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2-div-x72.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2-div-x80.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut8-p4h3-div-x8.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut8-p4h3-div-x16.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut8-p4h3-div-x24.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut8-p4h3-div-x32.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5-div-x8.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5-div-x16.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5-div-x24.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5-div-x32.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5-div-x40.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5-div-x48.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5-div-x56.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5-div-x64.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5-div-x72.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5-div-x80.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5-nr1-x8.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5-nr1-x16.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5-nr1-x24.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5-nr1-x32.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5-nr1-x40.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5-nr1-x48.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5-nr1-x56.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5-nr1-x64.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5-nr1-x72.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5-nr1-x80.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5-nr2-x8.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5-nr2-x16.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5-nr2-x24.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5-nr2-x32.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5-nr2-x40.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5-nr2-x48.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5-nr2-x56.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5-nr2-x64.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5-nr2-x72.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5-nr2-x80.c",
"src/f32-vunary/gen/f32-vabs-avx-x8.c",
"src/f32-vunary/gen/f32-vabs-avx-x16.c",
"src/f32-vunary/gen/f32-vneg-avx-x8.c",
"src/f32-vunary/gen/f32-vneg-avx-x16.c",
"src/f32-vunary/gen/f32-vsqr-avx-x8.c",
"src/f32-vunary/gen/f32-vsqr-avx-x16.c",
"src/math/f32-exp-avx-rr2-p5.c",
"src/math/f32-expm1minus-avx-rr2-lut4-p4-perm.c",
"src/math/f32-expm1minus-avx-rr2-lut16-p3.c",
"src/math/f32-expm1minus-avx-rr2-p6.c",
"src/math/f32-sigmoid-avx-rr2-lut64-p2-div.c",
"src/math/f32-sigmoid-avx-rr2-p5-div.c",
"src/math/f32-sigmoid-avx-rr2-p5-nr1.c",
"src/math/f32-sigmoid-avx-rr2-p5-nr2.c",
"src/math/gen/f32-tanh-avx-expm1minus-rr1-lut4-p4h2ts-perm-div.c",
"src/math/gen/f32-tanh-avx-expm1minus-rr1-lut8-p4h3ts-div.c",
"src/math/gen/f32-tanh-avx-expm1minus-rr1-p6h5ts-div.c",
"src/math/gen/f32-tanh-avx-expm1minus-rr1-p6h5ts-nr1.c",
"src/math/gen/f32-tanh-avx-expm1minus-rr1-p6h5ts-nr2.c",
"src/qc8-dwconv/gen/qc8-dwconv-3p16c-minmax-fp32-avx-mul16-add16.c",
"src/qc8-dwconv/gen/qc8-dwconv-5f5m5l8c4s4r-minmax-fp32-avx-mul32.c",
"src/qc8-dwconv/gen/qc8-dwconv-5f5m5l16c4s4r-minmax-fp32-avx-mul32.c",
"src/qc8-dwconv/gen/qc8-dwconv-6f6m7l8c4s4r-minmax-fp32-avx-mul32.c",
"src/qc8-dwconv/gen/qc8-dwconv-6f6m7l16c4s4r-minmax-fp32-avx-mul32.c",
"src/qc8-dwconv/gen/qc8-dwconv-8f8m9l8c4s4r-minmax-fp32-avx-mul32.c",
"src/qc8-dwconv/gen/qc8-dwconv-8f8m9l16c4s4r-minmax-fp32-avx-mul32.c",
"src/qc8-dwconv/gen/qc8-dwconv-9p8c-minmax-fp32-avx-mul16-add16.c",
"src/qc8-dwconv/gen/qc8-dwconv-9p8c-minmax-fp32-avx-mul16.c",
"src/qc8-dwconv/gen/qc8-dwconv-9p8c-minmax-fp32-avx-mul32.c",
"src/qc8-dwconv/gen/qc8-dwconv-9p16c-minmax-fp32-avx-mul16-add16.c",
"src/qc8-dwconv/gen/qc8-dwconv-9p16c-minmax-fp32-avx-mul16.c",
"src/qc8-dwconv/gen/qc8-dwconv-9p16c-minmax-fp32-avx-mul32.c",
"src/qc8-dwconv/gen/qc8-dwconv-25p8c-minmax-fp32-avx-mul16-add16.c",
"src/qc8-dwconv/gen/qc8-dwconv-25p8c-minmax-fp32-avx-mul16.c",
"src/qc8-dwconv/gen/qc8-dwconv-25p8c-minmax-fp32-avx-mul32.c",
"src/qc8-dwconv/gen/qc8-dwconv-25p16c-minmax-fp32-avx-mul16-add16.c",
"src/qc8-dwconv/gen/qc8-dwconv-25p16c-minmax-fp32-avx-mul16.c",
"src/qc8-dwconv/gen/qc8-dwconv-25p16c-minmax-fp32-avx-mul32.c",
"src/qc8-gemm/gen/qc8-gemm-1x4c2-minmax-fp32-avx-ld64.c",
"src/qc8-gemm/gen/qc8-gemm-1x4c2-minmax-fp32-avx-ld128.c",
"src/qc8-gemm/gen/qc8-gemm-1x4c2s4-minmax-fp32-avx-ld64.c",
"src/qc8-gemm/gen/qc8-gemm-1x4c2s4-minmax-fp32-avx-ld128.c",
"src/qc8-gemm/gen/qc8-gemm-1x4c8-minmax-fp32-avx-ld64.c",
"src/qc8-gemm/gen/qc8-gemm-1x4c8-minmax-fp32-avx-ld128.c",
"src/qc8-gemm/gen/qc8-gemm-2x4c2-minmax-fp32-avx-ld64.c",
"src/qc8-gemm/gen/qc8-gemm-2x4c2-minmax-fp32-avx-ld128.c",
"src/qc8-gemm/gen/qc8-gemm-2x4c2s4-minmax-fp32-avx-ld64.c",
"src/qc8-gemm/gen/qc8-gemm-2x4c2s4-minmax-fp32-avx-ld128.c",
"src/qc8-gemm/gen/qc8-gemm-2x4c8-minmax-fp32-avx-ld64.c",
"src/qc8-gemm/gen/qc8-gemm-2x4c8-minmax-fp32-avx-ld128.c",
"src/qc8-gemm/gen/qc8-gemm-3x4c2-minmax-fp32-avx-ld64.c",
"src/qc8-gemm/gen/qc8-gemm-3x4c2-minmax-fp32-avx-ld128.c",
"src/qc8-gemm/gen/qc8-gemm-3x4c2s4-minmax-fp32-avx-ld64.c",
"src/qc8-gemm/gen/qc8-gemm-3x4c2s4-minmax-fp32-avx-ld128.c",
"src/qc8-gemm/gen/qc8-gemm-3x4c8-minmax-fp32-avx-ld64.c",
"src/qc8-gemm/gen/qc8-gemm-3x4c8-minmax-fp32-avx-ld128.c",
"src/qc8-gemm/gen/qc8-gemm-4x4c2-minmax-fp32-avx-ld64.c",
"src/qc8-gemm/gen/qc8-gemm-4x4c2-minmax-fp32-avx-ld128.c",
"src/qc8-gemm/gen/qc8-gemm-4x4c2s4-minmax-fp32-avx-ld64.c",
"src/qc8-gemm/gen/qc8-gemm-4x4c2s4-minmax-fp32-avx-ld128.c",
"src/qc8-igemm/gen/qc8-igemm-1x4c2-minmax-fp32-avx-ld64.c",
"src/qc8-igemm/gen/qc8-igemm-1x4c2-minmax-fp32-avx-ld128.c",
"src/qc8-igemm/gen/qc8-igemm-1x4c2s4-minmax-fp32-avx-ld64.c",
"src/qc8-igemm/gen/qc8-igemm-1x4c2s4-minmax-fp32-avx-ld128.c",
"src/qc8-igemm/gen/qc8-igemm-1x4c8-minmax-fp32-avx-ld64.c",
"src/qc8-igemm/gen/qc8-igemm-1x4c8-minmax-fp32-avx-ld128.c",
"src/qc8-igemm/gen/qc8-igemm-2x4c2-minmax-fp32-avx-ld64.c",
"src/qc8-igemm/gen/qc8-igemm-2x4c2-minmax-fp32-avx-ld128.c",
"src/qc8-igemm/gen/qc8-igemm-2x4c2s4-minmax-fp32-avx-ld64.c",
"src/qc8-igemm/gen/qc8-igemm-2x4c2s4-minmax-fp32-avx-ld128.c",
"src/qc8-igemm/gen/qc8-igemm-2x4c8-minmax-fp32-avx-ld64.c",
"src/qc8-igemm/gen/qc8-igemm-2x4c8-minmax-fp32-avx-ld128.c",
"src/qc8-igemm/gen/qc8-igemm-3x4c2-minmax-fp32-avx-ld64.c",
"src/qc8-igemm/gen/qc8-igemm-3x4c2-minmax-fp32-avx-ld128.c",
"src/qc8-igemm/gen/qc8-igemm-3x4c2s4-minmax-fp32-avx-ld64.c",
"src/qc8-igemm/gen/qc8-igemm-3x4c2s4-minmax-fp32-avx-ld128.c",
"src/qc8-igemm/gen/qc8-igemm-3x4c8-minmax-fp32-avx-ld64.c",
"src/qc8-igemm/gen/qc8-igemm-3x4c8-minmax-fp32-avx-ld128.c",
"src/qc8-igemm/gen/qc8-igemm-4x4c2-minmax-fp32-avx-ld64.c",
"src/qc8-igemm/gen/qc8-igemm-4x4c2-minmax-fp32-avx-ld128.c",
"src/qc8-igemm/gen/qc8-igemm-4x4c2s4-minmax-fp32-avx-ld64.c",
"src/qc8-igemm/gen/qc8-igemm-4x4c2s4-minmax-fp32-avx-ld128.c",
"src/qs8-dwconv/gen/qs8-dwconv-5f5m5l8c4s4r-minmax-fp32-avx-mul32.c",
"src/qs8-dwconv/gen/qs8-dwconv-5f5m5l16c4s4r-minmax-fp32-avx-mul32.c",
"src/qs8-dwconv/gen/qs8-dwconv-6f6m7l8c4s4r-minmax-fp32-avx-mul32.c",
"src/qs8-dwconv/gen/qs8-dwconv-6f6m7l16c4s4r-minmax-fp32-avx-mul32.c",
"src/qs8-dwconv/gen/qs8-dwconv-8f8m9l8c4s4r-minmax-fp32-avx-mul32.c",
"src/qs8-dwconv/gen/qs8-dwconv-8f8m9l16c4s4r-minmax-fp32-avx-mul32.c",
"src/qs8-dwconv/gen/qs8-dwconv-9p8c-minmax-fp32-avx-mul16-add16.c",
"src/qs8-dwconv/gen/qs8-dwconv-9p8c-minmax-fp32-avx-mul16.c",
"src/qs8-dwconv/gen/qs8-dwconv-9p8c-minmax-fp32-avx-mul32.c",
"src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-fp32-avx-mul16-add16.c",
"src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-fp32-avx-mul16.c",
"src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-fp32-avx-mul32.c",
"src/qs8-dwconv/gen/qs8-dwconv-25p8c-minmax-fp32-avx-mul16-add16.c",
"src/qs8-dwconv/gen/qs8-dwconv-25p8c-minmax-fp32-avx-mul16.c",
"src/qs8-dwconv/gen/qs8-dwconv-25p8c-minmax-fp32-avx-mul32.c",
"src/qs8-dwconv/gen/qs8-dwconv-25p16c-minmax-fp32-avx-mul16-add16.c",
"src/qs8-dwconv/gen/qs8-dwconv-25p16c-minmax-fp32-avx-mul16.c",
"src/qs8-dwconv/gen/qs8-dwconv-25p16c-minmax-fp32-avx-mul32.c",
"src/qs8-f32-vcvt/gen/qs8-f32-vcvt-avx-x8.c",
"src/qs8-f32-vcvt/gen/qs8-f32-vcvt-avx-x16.c",
"src/qs8-f32-vcvt/gen/qs8-f32-vcvt-avx-x24.c",
"src/qs8-f32-vcvt/gen/qs8-f32-vcvt-avx-x32.c",
"src/qs8-gemm/gen/qs8-gemm-1x4c2-minmax-fp32-avx-ld64.c",
"src/qs8-gemm/gen/qs8-gemm-1x4c2-minmax-fp32-avx-ld128.c",
"src/qs8-gemm/gen/qs8-gemm-1x4c2-xw-minmax-fp32-avx.c",
"src/qs8-gemm/gen/qs8-gemm-1x4c2s4-minmax-fp32-avx-ld64.c",
"src/qs8-gemm/gen/qs8-gemm-1x4c2s4-minmax-fp32-avx-ld128.c",
"src/qs8-gemm/gen/qs8-gemm-1x4c2s4-xw-minmax-fp32-avx.c",
"src/qs8-gemm/gen/qs8-gemm-1x4c8-minmax-fp32-avx-ld64.c",
"src/qs8-gemm/gen/qs8-gemm-1x4c8-minmax-fp32-avx-ld128.c",
"src/qs8-gemm/gen/qs8-gemm-1x4c8-xw-minmax-fp32-avx.c",
"src/qs8-gemm/gen/qs8-gemm-2x4c2-minmax-fp32-avx-ld64.c",
"src/qs8-gemm/gen/qs8-gemm-2x4c2-minmax-fp32-avx-ld128.c",
"src/qs8-gemm/gen/qs8-gemm-2x4c2-xw-minmax-fp32-avx.c",
"src/qs8-gemm/gen/qs8-gemm-2x4c2s4-minmax-fp32-avx-ld64.c",
"src/qs8-gemm/gen/qs8-gemm-2x4c2s4-minmax-fp32-avx-ld128.c",
"src/qs8-gemm/gen/qs8-gemm-2x4c2s4-xw-minmax-fp32-avx.c",
"src/qs8-gemm/gen/qs8-gemm-2x4c8-minmax-fp32-avx-ld64.c",
"src/qs8-gemm/gen/qs8-gemm-2x4c8-minmax-fp32-avx-ld128.c",
"src/qs8-gemm/gen/qs8-gemm-2x4c8-xw-minmax-fp32-avx.c",
"src/qs8-gemm/gen/qs8-gemm-3x4c2-minmax-fp32-avx-ld64.c",
"src/qs8-gemm/gen/qs8-gemm-3x4c2-minmax-fp32-avx-ld128.c",
"src/qs8-gemm/gen/qs8-gemm-3x4c2-xw-minmax-fp32-avx.c",
"src/qs8-gemm/gen/qs8-gemm-3x4c2s4-minmax-fp32-avx-ld64.c",
"src/qs8-gemm/gen/qs8-gemm-3x4c2s4-minmax-fp32-avx-ld128.c",
"src/qs8-gemm/gen/qs8-gemm-3x4c2s4-xw-minmax-fp32-avx.c",
"src/qs8-gemm/gen/qs8-gemm-3x4c8-minmax-fp32-avx-ld64.c",
"src/qs8-gemm/gen/qs8-gemm-3x4c8-minmax-fp32-avx-ld128.c",
"src/qs8-gemm/gen/qs8-gemm-3x4c8-xw-minmax-fp32-avx.c",
"src/qs8-gemm/gen/qs8-gemm-4x4c2-minmax-fp32-avx-ld64.c",
"src/qs8-gemm/gen/qs8-gemm-4x4c2-minmax-fp32-avx-ld128.c",
"src/qs8-gemm/gen/qs8-gemm-4x4c2-xw-minmax-fp32-avx.c",
"src/qs8-gemm/gen/qs8-gemm-4x4c2s4-minmax-fp32-avx-ld64.c",
"src/qs8-gemm/gen/qs8-gemm-4x4c2s4-minmax-fp32-avx-ld128.c",
"src/qs8-gemm/gen/qs8-gemm-4x4c2s4-xw-minmax-fp32-avx.c",
"src/qs8-igemm/gen/qs8-igemm-1x4c2-minmax-fp32-avx-ld64.c",
"src/qs8-igemm/gen/qs8-igemm-1x4c2-minmax-fp32-avx-ld128.c",
"src/qs8-igemm/gen/qs8-igemm-1x4c2s4-minmax-fp32-avx-ld64.c",
"src/qs8-igemm/gen/qs8-igemm-1x4c2s4-minmax-fp32-avx-ld128.c",
"src/qs8-igemm/gen/qs8-igemm-1x4c8-minmax-fp32-avx-ld64.c",
"src/qs8-igemm/gen/qs8-igemm-1x4c8-minmax-fp32-avx-ld128.c",
"src/qs8-igemm/gen/qs8-igemm-2x4c2-minmax-fp32-avx-ld64.c",
"src/qs8-igemm/gen/qs8-igemm-2x4c2-minmax-fp32-avx-ld128.c",
"src/qs8-igemm/gen/qs8-igemm-2x4c2s4-minmax-fp32-avx-ld64.c",
"src/qs8-igemm/gen/qs8-igemm-2x4c2s4-minmax-fp32-avx-ld128.c",
"src/qs8-igemm/gen/qs8-igemm-2x4c8-minmax-fp32-avx-ld64.c",
"src/qs8-igemm/gen/qs8-igemm-2x4c8-minmax-fp32-avx-ld128.c",
"src/qs8-igemm/gen/qs8-igemm-3x4c2-minmax-fp32-avx-ld64.c",
"src/qs8-igemm/gen/qs8-igemm-3x4c2-minmax-fp32-avx-ld128.c",
"src/qs8-igemm/gen/qs8-igemm-3x4c2s4-minmax-fp32-avx-ld64.c",
"src/qs8-igemm/gen/qs8-igemm-3x4c2s4-minmax-fp32-avx-ld128.c",
"src/qs8-igemm/gen/qs8-igemm-3x4c8-minmax-fp32-avx-ld64.c",
"src/qs8-igemm/gen/qs8-igemm-3x4c8-minmax-fp32-avx-ld128.c",
"src/qs8-igemm/gen/qs8-igemm-4x4c2-minmax-fp32-avx-ld64.c",
"src/qs8-igemm/gen/qs8-igemm-4x4c2-minmax-fp32-avx-ld128.c",
"src/qs8-igemm/gen/qs8-igemm-4x4c2s4-minmax-fp32-avx-ld64.c",
"src/qs8-igemm/gen/qs8-igemm-4x4c2s4-minmax-fp32-avx-ld128.c",
"src/qs8-vadd/gen/qs8-vadd-minmax-avx-mul16-ld64-x8.c",
"src/qs8-vadd/gen/qs8-vadd-minmax-avx-mul16-ld64-x16.c",
"src/qs8-vadd/gen/qs8-vadd-minmax-avx-mul16-ld64-x24.c",
"src/qs8-vadd/gen/qs8-vadd-minmax-avx-mul16-ld64-x32.c",
"src/qs8-vadd/gen/qs8-vadd-minmax-avx-mul32-ld32-x8.c",
"src/qs8-vadd/gen/qs8-vadd-minmax-avx-mul32-ld32-x16.c",
"src/qs8-vadd/gen/qs8-vadd-minmax-avx-mul32-ld32-x24.c",
"src/qs8-vadd/gen/qs8-vadd-minmax-avx-mul32-ld32-x32.c",
"src/qs8-vaddc/gen/qs8-vaddc-minmax-avx-mul16-ld64-x8.c",
"src/qs8-vaddc/gen/qs8-vaddc-minmax-avx-mul16-ld64-x16.c",
"src/qs8-vaddc/gen/qs8-vaddc-minmax-avx-mul16-ld64-x24.c",
"src/qs8-vaddc/gen/qs8-vaddc-minmax-avx-mul16-ld64-x32.c",
"src/qs8-vaddc/gen/qs8-vaddc-minmax-avx-mul32-ld32-x8.c",
"src/qs8-vaddc/gen/qs8-vaddc-minmax-avx-mul32-ld32-x16.c",
"src/qs8-vaddc/gen/qs8-vaddc-minmax-avx-mul32-ld32-x24.c",
"src/qs8-vaddc/gen/qs8-vaddc-minmax-avx-mul32-ld32-x32.c",
"src/qs8-vcvt/gen/qs8-vcvt-avx-x8.c",
"src/qs8-vcvt/gen/qs8-vcvt-avx-x16.c",
"src/qs8-vcvt/gen/qs8-vcvt-avx-x32.c",
"src/qs8-vlrelu/gen/qs8-vlrelu-avx-x8.c",
"src/qs8-vlrelu/gen/qs8-vlrelu-avx-x16.c",
"src/qs8-vlrelu/gen/qs8-vlrelu-avx-x32.c",
"src/qs8-vmul/gen/qs8-vmul-minmax-fp32-avx-mul16-ld64-x8.c",
"src/qs8-vmul/gen/qs8-vmul-minmax-fp32-avx-mul16-ld64-x16.c",
"src/qs8-vmulc/gen/qs8-vmulc-minmax-fp32-avx-mul16-ld64-x8.c",
"src/qs8-vmulc/gen/qs8-vmulc-minmax-fp32-avx-mul16-ld64-x16.c",
"src/qs16-qs8-vcvt/gen/qs16-qs8-vcvt-avx-x4.c",
"src/qs16-qs8-vcvt/gen/qs16-qs8-vcvt-avx-x8.c",
"src/qs16-qs8-vcvt/gen/qs16-qs8-vcvt-avx-x16.c",
"src/qu8-dwconv/gen/qu8-dwconv-5f5m5l8c4s4r-minmax-fp32-avx-mul32.c",
"src/qu8-dwconv/gen/qu8-dwconv-5f5m5l16c4s4r-minmax-fp32-avx-mul32.c",
"src/qu8-dwconv/gen/qu8-dwconv-6f6m7l8c4s4r-minmax-fp32-avx-mul32.c",
"src/qu8-dwconv/gen/qu8-dwconv-6f6m7l16c4s4r-minmax-fp32-avx-mul32.c",
"src/qu8-dwconv/gen/qu8-dwconv-8f8m9l8c4s4r-minmax-fp32-avx-mul32.c",
"src/qu8-dwconv/gen/qu8-dwconv-8f8m9l16c4s4r-minmax-fp32-avx-mul32.c",
"src/qu8-dwconv/gen/qu8-dwconv-9p8c-minmax-fp32-avx-mul16.c",
"src/qu8-dwconv/gen/qu8-dwconv-9p8c-minmax-fp32-avx-mul32.c",
"src/qu8-dwconv/gen/qu8-dwconv-9p16c-minmax-fp32-avx-mul16.c",
"src/qu8-dwconv/gen/qu8-dwconv-9p16c-minmax-fp32-avx-mul32.c",
"src/qu8-dwconv/gen/qu8-dwconv-25p8c-minmax-fp32-avx-mul16.c",
"src/qu8-dwconv/gen/qu8-dwconv-25p8c-minmax-fp32-avx-mul32.c",
"src/qu8-dwconv/gen/qu8-dwconv-25p16c-minmax-fp32-avx-mul16.c",
"src/qu8-dwconv/gen/qu8-dwconv-25p16c-minmax-fp32-avx-mul32.c",
"src/qu8-f32-vcvt/gen/qu8-f32-vcvt-avx-x8.c",
"src/qu8-f32-vcvt/gen/qu8-f32-vcvt-avx-x16.c",
"src/qu8-f32-vcvt/gen/qu8-f32-vcvt-avx-x24.c",
"src/qu8-f32-vcvt/gen/qu8-f32-vcvt-avx-x32.c",
"src/qu8-gemm/gen/qu8-gemm-1x4c2-minmax-fp32-avx-ld64.c",
"src/qu8-gemm/gen/qu8-gemm-1x4c2-minmax-fp32-avx-ld128.c",
"src/qu8-gemm/gen/qu8-gemm-1x4c2s4-minmax-fp32-avx-ld64.c",
"src/qu8-gemm/gen/qu8-gemm-1x4c2s4-minmax-fp32-avx-ld128.c",
"src/qu8-gemm/gen/qu8-gemm-1x4c8-minmax-fp32-avx-ld64.c",
"src/qu8-gemm/gen/qu8-gemm-1x4c8-minmax-fp32-avx-ld128.c",
"src/qu8-gemm/gen/qu8-gemm-2x4c2-minmax-fp32-avx-ld64.c",
"src/qu8-gemm/gen/qu8-gemm-2x4c2-minmax-fp32-avx-ld128.c",
"src/qu8-gemm/gen/qu8-gemm-2x4c2s4-minmax-fp32-avx-ld64.c",
"src/qu8-gemm/gen/qu8-gemm-2x4c2s4-minmax-fp32-avx-ld128.c",
"src/qu8-gemm/gen/qu8-gemm-2x4c8-minmax-fp32-avx-ld64.c",
"src/qu8-gemm/gen/qu8-gemm-2x4c8-minmax-fp32-avx-ld128.c",
"src/qu8-gemm/gen/qu8-gemm-3x4c2-minmax-fp32-avx-ld64.c",
"src/qu8-gemm/gen/qu8-gemm-3x4c2-minmax-fp32-avx-ld128.c",
"src/qu8-gemm/gen/qu8-gemm-3x4c2s4-minmax-fp32-avx-ld64.c",
"src/qu8-gemm/gen/qu8-gemm-3x4c2s4-minmax-fp32-avx-ld128.c",
"src/qu8-gemm/gen/qu8-gemm-3x4c8-minmax-fp32-avx-ld64.c",
"src/qu8-gemm/gen/qu8-gemm-3x4c8-minmax-fp32-avx-ld128.c",
"src/qu8-gemm/gen/qu8-gemm-4x4c2-minmax-fp32-avx-ld64.c",
"src/qu8-gemm/gen/qu8-gemm-4x4c2-minmax-fp32-avx-ld128.c",
"src/qu8-gemm/gen/qu8-gemm-4x4c2s4-minmax-fp32-avx-ld64.c",
"src/qu8-gemm/gen/qu8-gemm-4x4c2s4-minmax-fp32-avx-ld128.c",
"src/qu8-igemm/gen/qu8-igemm-1x4c2-minmax-fp32-avx-ld64.c",
"src/qu8-igemm/gen/qu8-igemm-1x4c2-minmax-fp32-avx-ld128.c",
"src/qu8-igemm/gen/qu8-igemm-1x4c2s4-minmax-fp32-avx-ld64.c",
"src/qu8-igemm/gen/qu8-igemm-1x4c2s4-minmax-fp32-avx-ld128.c",
"src/qu8-igemm/gen/qu8-igemm-1x4c8-minmax-fp32-avx-ld64.c",
"src/qu8-igemm/gen/qu8-igemm-1x4c8-minmax-fp32-avx-ld128.c",
"src/qu8-igemm/gen/qu8-igemm-2x4c2-minmax-fp32-avx-ld64.c",
"src/qu8-igemm/gen/qu8-igemm-2x4c2-minmax-fp32-avx-ld128.c",
"src/qu8-igemm/gen/qu8-igemm-2x4c2s4-minmax-fp32-avx-ld64.c",
"src/qu8-igemm/gen/qu8-igemm-2x4c2s4-minmax-fp32-avx-ld128.c",
"src/qu8-igemm/gen/qu8-igemm-2x4c8-minmax-fp32-avx-ld64.c",
"src/qu8-igemm/gen/qu8-igemm-2x4c8-minmax-fp32-avx-ld128.c",
"src/qu8-igemm/gen/qu8-igemm-3x4c2-minmax-fp32-avx-ld64.c",
"src/qu8-igemm/gen/qu8-igemm-3x4c2-minmax-fp32-avx-ld128.c",
"src/qu8-igemm/gen/qu8-igemm-3x4c2s4-minmax-fp32-avx-ld64.c",
"src/qu8-igemm/gen/qu8-igemm-3x4c2s4-minmax-fp32-avx-ld128.c",
"src/qu8-igemm/gen/qu8-igemm-3x4c8-minmax-fp32-avx-ld64.c",
"src/qu8-igemm/gen/qu8-igemm-3x4c8-minmax-fp32-avx-ld128.c",
"src/qu8-igemm/gen/qu8-igemm-4x4c2-minmax-fp32-avx-ld64.c",
"src/qu8-igemm/gen/qu8-igemm-4x4c2-minmax-fp32-avx-ld128.c",
"src/qu8-igemm/gen/qu8-igemm-4x4c2s4-minmax-fp32-avx-ld64.c",
"src/qu8-igemm/gen/qu8-igemm-4x4c2s4-minmax-fp32-avx-ld128.c",
"src/qu8-vadd/gen/qu8-vadd-minmax-avx-mul16-ld64-x8.c",
"src/qu8-vadd/gen/qu8-vadd-minmax-avx-mul16-ld64-x16.c",
"src/qu8-vadd/gen/qu8-vadd-minmax-avx-mul32-ld32-x8.c",
"src/qu8-vadd/gen/qu8-vadd-minmax-avx-mul32-ld32-x16.c",
"src/qu8-vaddc/gen/qu8-vaddc-minmax-avx-mul16-ld64-x8.c",
"src/qu8-vaddc/gen/qu8-vaddc-minmax-avx-mul16-ld64-x16.c",
"src/qu8-vaddc/gen/qu8-vaddc-minmax-avx-mul32-ld32-x8.c",
"src/qu8-vaddc/gen/qu8-vaddc-minmax-avx-mul32-ld32-x16.c",
"src/qu8-vcvt/gen/qu8-vcvt-avx-x8.c",
"src/qu8-vcvt/gen/qu8-vcvt-avx-x16.c",
"src/qu8-vcvt/gen/qu8-vcvt-avx-x32.c",
"src/qu8-vlrelu/gen/qu8-vlrelu-avx-x8.c",
"src/qu8-vlrelu/gen/qu8-vlrelu-avx-x16.c",
"src/qu8-vlrelu/gen/qu8-vlrelu-avx-x32.c",
"src/qu8-vmul/gen/qu8-vmul-minmax-fp32-avx-mul16-ld64-x8.c",
"src/qu8-vmul/gen/qu8-vmul-minmax-fp32-avx-mul16-ld64-x16.c",
"src/qu8-vmulc/gen/qu8-vmulc-minmax-fp32-avx-mul16-ld64-x8.c",
"src/qu8-vmulc/gen/qu8-vmulc-minmax-fp32-avx-mul16-ld64-x16.c",
"src/x8-lut/gen/x8-lut-avx-x16.c",
"src/x8-lut/gen/x8-lut-avx-x32.c",
"src/x8-lut/gen/x8-lut-avx-x48.c",
"src/x8-lut/gen/x8-lut-avx-x64.c",
"src/x32-transposec/gen/x32-transposec-8x8-multi-mov-avx.c",
"src/x32-transposec/gen/x32-transposec-8x8-multi-switch-avx.c",
"src/x32-transposec/gen/x32-transposec-8x8-reuse-mov-avx.c",
"src/x32-transposec/gen/x32-transposec-8x8-reuse-multi-avx.c",
"src/x32-transposec/gen/x32-transposec-8x8-reuse-switch-avx.c",
"src/x64-transposec/gen/x64-transposec-4x4-multi-mov-avx.c",
"src/x64-transposec/gen/x64-transposec-4x4-multi-multi-avx.c",
"src/x64-transposec/gen/x64-transposec-4x4-multi-switch-avx.c",
"src/x64-transposec/gen/x64-transposec-4x4-reuse-mov-avx.c",
"src/x64-transposec/gen/x64-transposec-4x4-reuse-multi-avx.c",
"src/x64-transposec/gen/x64-transposec-4x4-reuse-switch-avx.c",
]
ALL_AVX2_MICROKERNEL_SRCS = [
"src/f16-f32acc-gemm/gen/f16-f32acc-gemm-1x8-minmax-avx2-broadcast.c",
"src/f16-f32acc-gemm/gen/f16-f32acc-gemm-1x16-minmax-avx2-broadcast.c",
"src/f16-f32acc-gemm/gen/f16-f32acc-gemm-3x16-minmax-avx2-broadcast.c",
"src/f16-f32acc-gemm/gen/f16-f32acc-gemm-4x8-minmax-avx2-broadcast.c",
"src/f16-f32acc-gemm/gen/f16-f32acc-gemm-4x16-minmax-avx2-broadcast.c",
"src/f16-f32acc-gemm/gen/f16-f32acc-gemm-5x8-minmax-avx2-broadcast.c",
"src/f16-f32acc-gemm/gen/f16-f32acc-gemm-5x16-minmax-avx2-broadcast.c",
"src/f16-f32acc-gemm/gen/f16-f32acc-gemm-6x8-minmax-avx2-broadcast.c",
"src/f16-f32acc-gemm/gen/f16-f32acc-gemm-7x8-minmax-avx2-broadcast.c",
"src/f16-f32acc-igemm/gen/f16-f32acc-igemm-1x8-minmax-avx2-broadcast.c",
"src/f16-f32acc-igemm/gen/f16-f32acc-igemm-1x16-minmax-avx2-broadcast.c",
"src/f16-f32acc-igemm/gen/f16-f32acc-igemm-3x16-minmax-avx2-broadcast.c",
"src/f16-f32acc-igemm/gen/f16-f32acc-igemm-4x8-minmax-avx2-broadcast.c",
"src/f16-f32acc-igemm/gen/f16-f32acc-igemm-4x16-minmax-avx2-broadcast.c",
"src/f16-f32acc-igemm/gen/f16-f32acc-igemm-5x8-minmax-avx2-broadcast.c",
"src/f16-f32acc-igemm/gen/f16-f32acc-igemm-5x16-minmax-avx2-broadcast.c",
"src/f16-f32acc-igemm/gen/f16-f32acc-igemm-6x8-minmax-avx2-broadcast.c",
"src/f16-f32acc-igemm/gen/f16-f32acc-igemm-7x8-minmax-avx2-broadcast.c",
"src/f16-gemm/gen/f16-gemm-1x8-minmax-avx2-broadcast.c",
"src/f16-gemm/gen/f16-gemm-1x16-minmax-avx2-broadcast.c",
"src/f16-gemm/gen/f16-gemm-3x16-minmax-avx2-broadcast.c",
"src/f16-gemm/gen/f16-gemm-4x8-minmax-avx2-broadcast.c",
"src/f16-gemm/gen/f16-gemm-4x16-minmax-avx2-broadcast.c",
"src/f16-gemm/gen/f16-gemm-5x8-minmax-avx2-broadcast.c",
"src/f16-gemm/gen/f16-gemm-5x16-minmax-avx2-broadcast.c",
"src/f16-gemm/gen/f16-gemm-6x8-minmax-avx2-broadcast.c",
"src/f16-gemm/gen/f16-gemm-7x8-minmax-avx2-broadcast.c",
"src/f16-igemm/gen/f16-igemm-1x8-minmax-avx2-broadcast.c",
"src/f16-igemm/gen/f16-igemm-1x16-minmax-avx2-broadcast.c",
"src/f16-igemm/gen/f16-igemm-3x16-minmax-avx2-broadcast.c",
"src/f16-igemm/gen/f16-igemm-4x8-minmax-avx2-broadcast.c",
"src/f16-igemm/gen/f16-igemm-4x16-minmax-avx2-broadcast.c",
"src/f16-igemm/gen/f16-igemm-5x8-minmax-avx2-broadcast.c",
"src/f16-igemm/gen/f16-igemm-5x16-minmax-avx2-broadcast.c",
"src/f16-igemm/gen/f16-igemm-6x8-minmax-avx2-broadcast.c",
"src/f16-igemm/gen/f16-igemm-7x8-minmax-avx2-broadcast.c",
"src/f16-pavgpool/f16-pavgpool-9p8x-minmax-avx2-c8.c",
"src/f16-pavgpool/f16-pavgpool-9x-minmax-avx2-c8.c",
"src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-x32-acc2.c",
"src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-x32-acc4.c",
"src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-x32.c",
"src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-x40-acc2.c",
"src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-x40-acc5.c",
"src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-x40.c",
"src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-x48-acc2.c",
"src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-x48-acc3.c",
"src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-x48.c",
"src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-x64-acc2.c",
"src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-x64-acc4.c",
"src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-x64.c",
"src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-x72-acc3.c",
"src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-x72.c",
"src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-x80-acc2.c",
"src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-x80-acc5.c",
"src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-x80.c",
"src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-x96-acc2.c",
"src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-x96-acc3.c",
"src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-x96-acc6.c",
"src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-x96.c",
"src/f16-velu/gen/f16-velu-avx2-rr1-p3-x8.c",
"src/f16-velu/gen/f16-velu-avx2-rr1-p3-x16.c",
"src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-div-x8.c",
"src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-div-x16.c",
"src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-div-x24.c",
"src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-div-x32.c",
"src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-div-x40.c",
"src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-div-x48.c",
"src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-div-x56.c",
"src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-div-x64.c",
"src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-rcp-x8.c",
"src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-rcp-x16.c",
"src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-rcp-x24.c",
"src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-rcp-x32.c",
"src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-rcp-x40.c",
"src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-rcp-x48.c",
"src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-rcp-x56.c",
"src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-rcp-x64.c",
"src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2-div-x8.c",
"src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2-div-x16.c",
"src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2-div-x24.c",
"src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2-div-x32.c",
"src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2-div-x40.c",
"src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2-div-x48.c",
"src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2-div-x56.c",
"src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2-div-x64.c",
"src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2-div-x72.c",
"src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2-div-x80.c",
"src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2-rcp-x8.c",
"src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2-rcp-x16.c",
"src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2-rcp-x24.c",
"src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2-rcp-x32.c",
"src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2-rcp-x40.c",
"src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2-rcp-x48.c",
"src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2-rcp-x56.c",
"src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2-rcp-x64.c",
"src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2-rcp-x72.c",
"src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2-rcp-x80.c",
"src/f32-qs8-vcvt/gen/f32-qs8-vcvt-avx2-x16.c",
"src/f32-qs8-vcvt/gen/f32-qs8-vcvt-avx2-x32.c",
"src/f32-qs8-vcvt/gen/f32-qs8-vcvt-avx2-x48.c",
"src/f32-qs8-vcvt/gen/f32-qs8-vcvt-avx2-x64.c",
"src/f32-qu8-vcvt/gen/f32-qu8-vcvt-avx2-x16.c",
"src/f32-qu8-vcvt/gen/f32-qu8-vcvt-avx2-x32.c",
"src/f32-qu8-vcvt/gen/f32-qu8-vcvt-avx2-x48.c",
"src/f32-qu8-vcvt/gen/f32-qu8-vcvt-avx2-x64.c",
"src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx2-p5-x64-acc2.c",
"src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx2-p5-x64-acc4.c",
"src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx2-p5-x64.c",
"src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx2-p5-x72-acc3.c",
"src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx2-p5-x72.c",
"src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx2-p5-x80-acc2.c",
"src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx2-p5-x80-acc5.c",
"src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx2-p5-x80.c",
"src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx2-p5-x96-acc2.c",
"src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx2-p5-x96-acc3.c",
"src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx2-p5-x96-acc6.c",
"src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx2-p5-x96.c",
"src/f32-raddextexp/gen/f32-raddextexp-avx2-p5-x64-acc2.c",
"src/f32-raddextexp/gen/f32-raddextexp-avx2-p5-x64-acc4.c",
"src/f32-raddextexp/gen/f32-raddextexp-avx2-p5-x64.c",
"src/f32-raddextexp/gen/f32-raddextexp-avx2-p5-x72-acc3.c",
"src/f32-raddextexp/gen/f32-raddextexp-avx2-p5-x72.c",
"src/f32-raddextexp/gen/f32-raddextexp-avx2-p5-x80-acc2.c",
"src/f32-raddextexp/gen/f32-raddextexp-avx2-p5-x80-acc5.c",
"src/f32-raddextexp/gen/f32-raddextexp-avx2-p5-x80.c",
"src/f32-raddextexp/gen/f32-raddextexp-avx2-p5-x96-acc2.c",
"src/f32-raddextexp/gen/f32-raddextexp-avx2-p5-x96-acc3.c",
"src/f32-raddextexp/gen/f32-raddextexp-avx2-p5-x96-acc6.c",
"src/f32-raddextexp/gen/f32-raddextexp-avx2-p5-x96.c",
"src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx2-rr1-p5-x64-acc2.c",
"src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx2-rr1-p5-x64-acc4.c",
"src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx2-rr1-p5-x64.c",
"src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx2-rr1-p5-x72-acc3.c",
"src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx2-rr1-p5-x72.c",
"src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx2-rr1-p5-x80-acc2.c",
"src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx2-rr1-p5-x80-acc5.c",
"src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx2-rr1-p5-x80.c",
"src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx2-rr1-p5-x96-acc2.c",
"src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx2-rr1-p5-x96-acc3.c",
"src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx2-rr1-p5-x96-acc6.c",
"src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx2-rr1-p5-x96.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut4-p4-perm-x8.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut4-p4-perm-x16.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut4-p4-perm-x24.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut4-p4-perm-x32.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut4-p4-perm-x40.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut4-p4-perm-x48.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut4-p4-perm-x56.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut4-p4-perm-x64.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut4-p4-perm-x72.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut4-p4-perm-x80.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut8-p4-perm-x8.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut8-p4-perm-x16.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut8-p4-perm-x24.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut8-p4-perm-x32.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut8-p4-perm-x40.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut8-p4-perm-x48.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut8-p4-perm-x56.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut8-p4-perm-x64.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut8-p4-perm-x72.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut8-p4-perm-x80.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut16-p3-gather-x8.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut16-p3-gather-x16.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut16-p3-gather-x24.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut16-p3-gather-x32.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut16-p3-gather-x40.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut16-p3-gather-x48.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut16-p3-gather-x56.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut16-p3-gather-x64.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut16-p3-gather-x72.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut16-p3-gather-x80.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-p6-x8.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-p6-x16.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-p6-x24.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-p6-x32.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-p6-x40.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-p6-x48.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-p6-x56.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-p6-x64.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-p6-x72.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-p6-x80.c",
"src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx2-p5-x8.c",
"src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx2-p5-x16.c",
"src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx2-p5-x24.c",
"src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx2-p5-x32.c",
"src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx2-p5-x40.c",
"src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx2-p5-x48.c",
"src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx2-p5-x56.c",
"src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx2-p5-x64.c",
"src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx2-p5-x72.c",
"src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx2-p5-x80.c",
"src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx2-p5-x88.c",
"src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx2-p5-x96.c",
"src/f32-vscaleextexp/gen/f32-vscaleextexp-avx2-p5-x8.c",
"src/f32-vscaleextexp/gen/f32-vscaleextexp-avx2-p5-x16.c",
"src/f32-vscaleextexp/gen/f32-vscaleextexp-avx2-p5-x24.c",
"src/f32-vscaleextexp/gen/f32-vscaleextexp-avx2-p5-x32.c",
"src/f32-vscaleextexp/gen/f32-vscaleextexp-avx2-p5-x40.c",
"src/f32-vscaleextexp/gen/f32-vscaleextexp-avx2-p5-x48.c",
"src/f32-vscaleextexp/gen/f32-vscaleextexp-avx2-p5-x56.c",
"src/f32-vscaleextexp/gen/f32-vscaleextexp-avx2-p5-x64.c",
"src/f32-vscaleextexp/gen/f32-vscaleextexp-avx2-p5-x72.c",
"src/f32-vscaleextexp/gen/f32-vscaleextexp-avx2-p5-x80.c",
"src/f32-vscaleextexp/gen/f32-vscaleextexp-avx2-p5-x88.c",
"src/f32-vscaleextexp/gen/f32-vscaleextexp-avx2-p5-x96.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-div-x8.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-div-x16.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-div-x24.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-div-x32.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-div-x40.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-div-x48.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-div-x56.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-div-x64.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-div-x72.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-div-x80.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr1fma-x8.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr1fma-x16.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr1fma-x24.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr1fma-x32.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr1fma-x40.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr1fma-x48.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr1fma-x56.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr1fma-x64.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr1fma-x72.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr1fma-x80.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr2fma-x8.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr2fma-x16.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr2fma-x24.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr2fma-x32.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr2fma-x40.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr2fma-x48.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr2fma-x56.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr2fma-x64.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr2fma-x72.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr2fma-x80.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3-perm-div-x8.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3-perm-div-x16.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3-perm-div-x24.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3-perm-div-x32.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3-perm-div-x40.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3-perm-div-x48.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3-perm-div-x56.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3-perm-div-x64.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3-perm-div-x72.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3-perm-div-x80.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3-perm-nr1adj-x8.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3-perm-nr1adj-x16.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3-perm-nr1adj-x24.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3-perm-nr1adj-x32.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3-perm-nr1adj-x40.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3-perm-nr1adj-x48.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3-perm-nr1adj-x56.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3-perm-nr1adj-x64.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3-perm-nr1adj-x72.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3-perm-nr1adj-x80.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3-gather-div-x8.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3-gather-div-x16.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3-gather-div-x24.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3-gather-div-x32.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3-gather-div-x40.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3-gather-div-x48.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3-gather-div-x56.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3-gather-div-x64.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3-gather-div-x72.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3-gather-div-x80.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3-gather-nr1adj-x8.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3-gather-nr1adj-x16.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3-gather-nr1adj-x24.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3-gather-nr1adj-x32.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3-gather-nr1adj-x40.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3-gather-nr1adj-x48.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3-gather-nr1adj-x56.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3-gather-nr1adj-x64.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3-gather-nr1adj-x72.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3-gather-nr1adj-x80.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3-perm-div-x8.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3-perm-div-x16.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3-perm-div-x24.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3-perm-div-x32.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3-perm-div-x40.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3-perm-div-x48.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3-perm-div-x56.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3-perm-div-x64.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3-perm-div-x72.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3-perm-div-x80.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3-perm-nr1adj-x8.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3-perm-nr1adj-x16.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3-perm-nr1adj-x24.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3-perm-nr1adj-x32.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3-perm-nr1adj-x40.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3-perm-nr1adj-x48.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3-perm-nr1adj-x56.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3-perm-nr1adj-x64.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3-perm-nr1adj-x72.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3-perm-nr1adj-x80.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5-div-x8.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5-div-x16.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5-div-x24.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5-div-x32.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5-div-x40.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5-div-x48.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5-div-x56.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5-div-x64.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5-div-x72.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5-div-x80.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5-nr1-x8.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5-nr1-x16.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5-nr1-x24.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5-nr1-x32.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5-nr1-x40.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5-nr1-x48.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5-nr1-x56.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5-nr1-x64.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5-nr1-x72.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5-nr1-x80.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5-nr1adj-x8.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5-nr1adj-x16.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5-nr1adj-x24.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5-nr1adj-x32.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5-nr1adj-x40.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5-nr1adj-x48.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5-nr1adj-x56.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5-nr1adj-x64.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5-nr1adj-x72.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5-nr1adj-x80.c",
"src/math/f16-expm1minus-avx2-rr1-p2.c",
"src/math/f16-expm1minus-avx2-rr1-p3.c",
"src/math/f16-expminus-avx2-rr1-p2.c",
"src/math/f16-expminus-avx2-rr1-p3.c",
"src/math/f16-sigmoid-avx2-rr1-p2-div.c",
"src/math/f16-sigmoid-avx2-rr1-p2-rcp.c",
"src/math/f16-sigmoid-avx2-rr1-p3-div.c",
"src/math/f16-sigmoid-avx2-rr1-p3-rcp.c",
"src/math/f32-exp-avx2-rr2-lut8-p3-perm.c",
"src/math/f32-exp-avx2-rr2-lut8-p4-perm.c",
"src/math/f32-exp-avx2-rr2-p5.c",
"src/math/f32-expm1minus-avx2-rr1-lut4-p4-perm.c",
"src/math/f32-expm1minus-avx2-rr1-lut8-p4-perm.c",
"src/math/f32-expm1minus-avx2-rr1-lut16-p3-gather.c",
"src/math/f32-expm1minus-avx2-rr1-p6.c",
"src/math/f32-expminus-avx2-rr1-p5.c",
"src/math/f32-expminus-avx2-rr2-p5.c",
"src/math/f32-extexp-avx2-p5.c",
"src/math/f32-sigmoid-avx2-rr1-lut64-p2-gather-div.c",
"src/math/f32-sigmoid-avx2-rr1-lut64-p2-gather-nr1fma.c",
"src/math/f32-sigmoid-avx2-rr1-lut64-p2-gather-nr2fma1adj.c",
"src/math/f32-sigmoid-avx2-rr1-lut64-p2-gather-nr2fma.c",
"src/math/f32-sigmoid-avx2-rr1-p5-div.c",
"src/math/f32-sigmoid-avx2-rr1-p5-nr1fma.c",
"src/math/f32-sigmoid-avx2-rr1-p5-nr2fma.c",
"src/math/f32-sigmoid-avx2-rr2-lut64-p2-gather-div.c",
"src/math/f32-sigmoid-avx2-rr2-lut64-p2-gather-nr1fma.c",
"src/math/f32-sigmoid-avx2-rr2-lut64-p2-gather-nr2fma1adj.c",
"src/math/f32-sigmoid-avx2-rr2-lut64-p2-gather-nr2fma.c",
"src/math/f32-sigmoid-avx2-rr2-p5-div.c",
"src/math/f32-sigmoid-avx2-rr2-p5-nr1fma.c",
"src/math/f32-sigmoid-avx2-rr2-p5-nr2fma.c",
"src/math/gen/f16-tanh-avx2-expm1minus-rr1-p3h2ts-div.c",
"src/math/gen/f16-tanh-avx2-expm1minus-rr1-p3h2ts-rcp.c",
"src/math/gen/f32-tanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-div.c",
"src/math/gen/f32-tanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj.c",
"src/math/gen/f32-tanh-avx2-expm1minus-rr1-lut8-p4h2ts-gather-nr1.c",
"src/math/gen/f32-tanh-avx2-expm1minus-rr1-lut8-p4h2ts-perm-nr1.c",
"src/math/gen/f32-tanh-avx2-expm1minus-rr1-lut8-p4h3ts-gather-div.c",
"src/math/gen/f32-tanh-avx2-expm1minus-rr1-lut8-p4h3ts-gather-nr1.c",
"src/math/gen/f32-tanh-avx2-expm1minus-rr1-lut8-p4h3ts-gather-nr1adj.c",
"src/math/gen/f32-tanh-avx2-expm1minus-rr1-lut8-p4h3ts-perm-div.c",
"src/math/gen/f32-tanh-avx2-expm1minus-rr1-lut8-p4h3ts-perm-nr1.c",
"src/math/gen/f32-tanh-avx2-expm1minus-rr1-lut8-p4h3ts-perm-nr1adj.c",
"src/math/gen/f32-tanh-avx2-expm1minus-rr1-p6h5ts-div.c",
"src/math/gen/f32-tanh-avx2-expm1minus-rr1-p6h5ts-nr1.c",
"src/math/gen/f32-tanh-avx2-expm1minus-rr1-p6h5ts-nr1adj.c",
"src/qc8-dwconv/gen/qc8-dwconv-3p16c-minmax-fp32-avx2-mul32.c",
"src/qc8-dwconv/gen/qc8-dwconv-5f5m5l8c8s8r-minmax-fp32-avx2-mul32.c",
"src/qc8-dwconv/gen/qc8-dwconv-5f5m5l16c8s8r-minmax-fp32-avx2-mul32.c",
"src/qc8-dwconv/gen/qc8-dwconv-5f5m5l16c16s16r-minmax-fp32-avx2-mul16-add16-vpunpck.c",
"src/qc8-dwconv/gen/qc8-dwconv-5f5m5l16c16s16r-minmax-fp32-avx2-mul16-vpmovsx.c",
"src/qc8-dwconv/gen/qc8-dwconv-5f5m5l16c16s16r-minmax-fp32-avx2-mul16-vpunpck.c",
"src/qc8-dwconv/gen/qc8-dwconv-5f5m5l32c8s8r-minmax-fp32-avx2-mul32.c",
"src/qc8-dwconv/gen/qc8-dwconv-5f5m5l32c16s16r-minmax-fp32-avx2-mul16-add16-vpunpck.c",
"src/qc8-dwconv/gen/qc8-dwconv-5f5m5l32c16s16r-minmax-fp32-avx2-mul16-vpmovsx.c",
"src/qc8-dwconv/gen/qc8-dwconv-5f5m5l32c16s16r-minmax-fp32-avx2-mul16-vpunpck.c",
"src/qc8-dwconv/gen/qc8-dwconv-6f6m7l8c8s8r-minmax-fp32-avx2-mul32.c",
"src/qc8-dwconv/gen/qc8-dwconv-6f6m7l16c8s8r-minmax-fp32-avx2-mul32.c",
"src/qc8-dwconv/gen/qc8-dwconv-6f6m7l16c16s16r-minmax-fp32-avx2-mul16-add16-vpunpck.c",
"src/qc8-dwconv/gen/qc8-dwconv-6f6m7l16c16s16r-minmax-fp32-avx2-mul16-vpmovsx.c",
"src/qc8-dwconv/gen/qc8-dwconv-6f6m7l16c16s16r-minmax-fp32-avx2-mul16-vpunpck.c",
"src/qc8-dwconv/gen/qc8-dwconv-6f6m7l32c8s8r-minmax-fp32-avx2-mul32.c",
"src/qc8-dwconv/gen/qc8-dwconv-6f6m7l32c16s16r-minmax-fp32-avx2-mul16-add16-vpunpck.c",
"src/qc8-dwconv/gen/qc8-dwconv-6f6m7l32c16s16r-minmax-fp32-avx2-mul16-vpmovsx.c",
"src/qc8-dwconv/gen/qc8-dwconv-6f6m7l32c16s16r-minmax-fp32-avx2-mul16-vpunpck.c",
"src/qc8-dwconv/gen/qc8-dwconv-8f8m9l8c8s8r-minmax-fp32-avx2-mul32.c",
"src/qc8-dwconv/gen/qc8-dwconv-8f8m9l16c8s8r-minmax-fp32-avx2-mul32.c",
"src/qc8-dwconv/gen/qc8-dwconv-8f8m9l16c16s16r-minmax-fp32-avx2-mul16-add16-vpunpck.c",
"src/qc8-dwconv/gen/qc8-dwconv-8f8m9l16c16s16r-minmax-fp32-avx2-mul16-vpmovsx.c",
"src/qc8-dwconv/gen/qc8-dwconv-8f8m9l16c16s16r-minmax-fp32-avx2-mul16-vpunpck.c",
"src/qc8-dwconv/gen/qc8-dwconv-8f8m9l32c8s8r-minmax-fp32-avx2-mul32.c",
"src/qc8-dwconv/gen/qc8-dwconv-8f8m9l32c16s16r-minmax-fp32-avx2-mul16-add16-vpunpck.c",
"src/qc8-dwconv/gen/qc8-dwconv-8f8m9l32c16s16r-minmax-fp32-avx2-mul16-vpmovsx.c",
"src/qc8-dwconv/gen/qc8-dwconv-8f8m9l32c16s16r-minmax-fp32-avx2-mul16-vpunpck.c",
"src/qc8-dwconv/gen/qc8-dwconv-9p8c-minmax-fp32-avx2-mul32.c",
"src/qc8-dwconv/gen/qc8-dwconv-9p16c-minmax-fp32-avx2-mul16-add16-vpunpck.c",
"src/qc8-dwconv/gen/qc8-dwconv-9p16c-minmax-fp32-avx2-mul16-vpmovsx.c",
"src/qc8-dwconv/gen/qc8-dwconv-9p16c-minmax-fp32-avx2-mul16-vpunpck.c",
"src/qc8-dwconv/gen/qc8-dwconv-9p16c-minmax-fp32-avx2-mul32.c",
"src/qc8-dwconv/gen/qc8-dwconv-9p32c-minmax-fp32-avx2-mul16-add16-vpunpck.c",
"src/qc8-dwconv/gen/qc8-dwconv-9p32c-minmax-fp32-avx2-mul16-vpmovsx.c",
"src/qc8-dwconv/gen/qc8-dwconv-9p32c-minmax-fp32-avx2-mul16-vpunpck.c",
"src/qc8-dwconv/gen/qc8-dwconv-9p32c-minmax-fp32-avx2-mul32.c",
"src/qc8-dwconv/gen/qc8-dwconv-25p8c-minmax-fp32-avx2-mul32.c",
"src/qc8-dwconv/gen/qc8-dwconv-25p16c-minmax-fp32-avx2-mul16-add16-vpunpck.c",
"src/qc8-dwconv/gen/qc8-dwconv-25p16c-minmax-fp32-avx2-mul16-vpmovsx.c",
"src/qc8-dwconv/gen/qc8-dwconv-25p16c-minmax-fp32-avx2-mul16-vpunpck.c",
"src/qc8-dwconv/gen/qc8-dwconv-25p16c-minmax-fp32-avx2-mul32.c",
"src/qc8-dwconv/gen/qc8-dwconv-25p32c-minmax-fp32-avx2-mul16-add16-vpunpck.c",
"src/qc8-dwconv/gen/qc8-dwconv-25p32c-minmax-fp32-avx2-mul16-vpmovsx.c",
"src/qc8-dwconv/gen/qc8-dwconv-25p32c-minmax-fp32-avx2-mul16-vpunpck.c",
"src/qc8-dwconv/gen/qc8-dwconv-25p32c-minmax-fp32-avx2-mul32.c",
"src/qc8-gemm/gen/qc8-gemm-1x8c8-minmax-fp32-avx2.c",
"src/qc8-gemm/gen/qc8-gemm-1x8c8-xw-minmax-fp32-avx2.c",
"src/qc8-gemm/gen/qc8-gemm-2x8c8-minmax-fp32-avx2.c",
"src/qc8-gemm/gen/qc8-gemm-2x8c8-xw-minmax-fp32-avx2.c",
"src/qc8-gemm/gen/qc8-gemm-3x8c8-minmax-fp32-avx2.c",
"src/qc8-gemm/gen/qc8-gemm-3x8c8-xw-minmax-fp32-avx2.c",
"src/qc8-igemm/gen/qc8-igemm-1x8c8-minmax-fp32-avx2.c",
"src/qc8-igemm/gen/qc8-igemm-2x8c8-minmax-fp32-avx2.c",
"src/qc8-igemm/gen/qc8-igemm-3x8c8-minmax-fp32-avx2.c",
"src/qs8-dwconv/gen/qs8-dwconv-5f5m5l8c8s8r-minmax-fp32-avx2-mul32.c",
"src/qs8-dwconv/gen/qs8-dwconv-5f5m5l16c8s8r-minmax-fp32-avx2-mul32.c",
"src/qs8-dwconv/gen/qs8-dwconv-5f5m5l16c16s16r-minmax-fp32-avx2-mul16-add16-vpunpck.c",
"src/qs8-dwconv/gen/qs8-dwconv-5f5m5l16c16s16r-minmax-fp32-avx2-mul16-vpmovsx.c",
"src/qs8-dwconv/gen/qs8-dwconv-5f5m5l16c16s16r-minmax-fp32-avx2-mul16-vpunpck.c",
"src/qs8-dwconv/gen/qs8-dwconv-5f5m5l32c8s8r-minmax-fp32-avx2-mul32.c",
"src/qs8-dwconv/gen/qs8-dwconv-5f5m5l32c16s16r-minmax-fp32-avx2-mul16-add16-vpunpck.c",
"src/qs8-dwconv/gen/qs8-dwconv-5f5m5l32c16s16r-minmax-fp32-avx2-mul16-vpmovsx.c",
"src/qs8-dwconv/gen/qs8-dwconv-5f5m5l32c16s16r-minmax-fp32-avx2-mul16-vpunpck.c",
"src/qs8-dwconv/gen/qs8-dwconv-6f6m7l8c8s8r-minmax-fp32-avx2-mul32.c",
"src/qs8-dwconv/gen/qs8-dwconv-6f6m7l16c8s8r-minmax-fp32-avx2-mul32.c",
"src/qs8-dwconv/gen/qs8-dwconv-6f6m7l16c16s16r-minmax-fp32-avx2-mul16-add16-vpunpck.c",
"src/qs8-dwconv/gen/qs8-dwconv-6f6m7l16c16s16r-minmax-fp32-avx2-mul16-vpmovsx.c",
"src/qs8-dwconv/gen/qs8-dwconv-6f6m7l16c16s16r-minmax-fp32-avx2-mul16-vpunpck.c",
"src/qs8-dwconv/gen/qs8-dwconv-6f6m7l32c8s8r-minmax-fp32-avx2-mul32.c",
"src/qs8-dwconv/gen/qs8-dwconv-6f6m7l32c16s16r-minmax-fp32-avx2-mul16-add16-vpunpck.c",
"src/qs8-dwconv/gen/qs8-dwconv-6f6m7l32c16s16r-minmax-fp32-avx2-mul16-vpmovsx.c",
"src/qs8-dwconv/gen/qs8-dwconv-6f6m7l32c16s16r-minmax-fp32-avx2-mul16-vpunpck.c",
"src/qs8-dwconv/gen/qs8-dwconv-8f8m9l8c8s8r-minmax-fp32-avx2-mul32.c",
"src/qs8-dwconv/gen/qs8-dwconv-8f8m9l16c8s8r-minmax-fp32-avx2-mul32.c",
"src/qs8-dwconv/gen/qs8-dwconv-8f8m9l16c16s16r-minmax-fp32-avx2-mul16-add16-vpunpck.c",
"src/qs8-dwconv/gen/qs8-dwconv-8f8m9l16c16s16r-minmax-fp32-avx2-mul16-vpmovsx.c",
"src/qs8-dwconv/gen/qs8-dwconv-8f8m9l16c16s16r-minmax-fp32-avx2-mul16-vpunpck.c",
"src/qs8-dwconv/gen/qs8-dwconv-8f8m9l32c8s8r-minmax-fp32-avx2-mul32.c",
"src/qs8-dwconv/gen/qs8-dwconv-8f8m9l32c16s16r-minmax-fp32-avx2-mul16-add16-vpunpck.c",
"src/qs8-dwconv/gen/qs8-dwconv-8f8m9l32c16s16r-minmax-fp32-avx2-mul16-vpmovsx.c",
"src/qs8-dwconv/gen/qs8-dwconv-8f8m9l32c16s16r-minmax-fp32-avx2-mul16-vpunpck.c",
"src/qs8-dwconv/gen/qs8-dwconv-9p8c-minmax-fp32-avx2-mul32.c",
"src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-fp32-avx2-mul16-add16-vpunpck.c",
"src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-fp32-avx2-mul16-vpmovsx.c",
"src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-fp32-avx2-mul16-vpunpck.c",
"src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-fp32-avx2-mul32.c",
"src/qs8-dwconv/gen/qs8-dwconv-9p32c-minmax-fp32-avx2-mul16-add16-vpunpck.c",
"src/qs8-dwconv/gen/qs8-dwconv-9p32c-minmax-fp32-avx2-mul16-vpmovsx.c",