cgsdfc · Jan 10, 2023
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 # mips-pipeline-cpu.verilog
 
+<img src="./docs/mips.png" zoom="40%">
+
 ## Introduction
 
+This project implements a simple five-stage pipeline MIPS CPU in Verilog. It has basic hazard-handling mechanisms like forwarding and stalling.
+
+- `test_data` contains testing data