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8 files changed

+135
-159
lines changed

8 files changed

+135
-159
lines changed

‎src/drivers/imxrt.c

Lines changed: 10 additions & 47 deletions
Original file line numberDiff line numberDiff line change
@@ -48,13 +48,6 @@ static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_64BYTE_ALIGNED;
4848
static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_64BYTE_ALIGNED;
4949
static struct mg_tcpip_if *s_ifp; // MIP interface
5050

51-
enum {
52-
MG_PHYREG_BCR = 0,
53-
MG_PHYREG_BSR = 1,
54-
MG_PHYREG_ID1 = 2,
55-
MG_PHYREG_ID2 = 3
56-
};
57-
5851
static uint16_t enet_phy_read(uint8_t addr, uint8_t reg) {
5952
ENET->EIR |= MG_BIT(23); // MII interrupt clear
6053
ENET->MMFR = (1 << 30) | (2 << 28) | (addr << 23) | (reg << 18) | (2 << 16);
@@ -104,28 +97,8 @@ static bool mg_tcpip_driver_imxrt_init(struct mg_tcpip_if *ifp) {
10497
// TODO(): Otherwise, guess (currently assuming max freq)
10598
int cr = (d == NULL || d->mdc_cr < 0) ? 24 : d->mdc_cr;
10699
ENET->MSCR = (1 << 8) | ((cr & 0x3f) << 1); // HOLDTIME 2 clks
107-
108-
enet_phy_write(d->phy_addr, MG_PHYREG_BCR, MG_BIT(15)); // Reset PHY
109-
enet_phy_write(d->phy_addr, MG_PHYREG_BCR,
110-
MG_BIT(12)); // Set autonegotiation
111-
112-
// PHY: Enable 50 MHz external ref clock at XI (preserve defaults)
113-
uint32_t id = enet_phy_id(d->phy_addr);
114-
MG_INFO(("PHY ID: %#04x %#04x", (uint16_t) (id >> 16), (uint16_t) id));
115-
// 2000 a140 - TI DP83825I
116-
// 0007 c0fx - LAN8720
117-
// 0022 1561 - KSZ8081RNB
118-
119-
if ((id & 0xffff0000) == 0x220000) { // KSZ8081RNB, like EVK-RTxxxx boards
120-
enet_phy_write(d->phy_addr, 31,
121-
MG_BIT(15) | MG_BIT(8) | MG_BIT(7)); // PC2R
122-
} else if ((id & 0xffff0000) == 0x20000000) { // DP83825I, like Teensy4.1
123-
enet_phy_write(d->phy_addr, 23, 0x81); // 50MHz clock input
124-
enet_phy_write(d->phy_addr, 24, 0x280); // LED status, active high
125-
} else { // Default to LAN8720
126-
MG_INFO(("Defaulting to LAN8720 PHY...")); // TODO()
127-
}
128-
100+
struct mg_phy phy = {eth_read_phy, eth_write_phy};
101+
mg_phy_init(&phy, d->phy_addr);
129102
// Select RMII mode, 100M, keep CRC, set max rx length, disable loop
130103
ENET->RCR = (1518 << 16) | MG_BIT(8) | MG_BIT(2);
131104
// ENET->RCR |= MG_BIT(3); // Receive all
@@ -171,30 +144,20 @@ static size_t mg_tcpip_driver_imxrt_tx(const void *buf, size_t len,
171144
}
172145

173146
static bool mg_tcpip_driver_imxrt_up(struct mg_tcpip_if *ifp) {
174-
struct mg_tcpip_driver_imxrt_data *d =
175-
(struct mg_tcpip_driver_imxrt_data *) ifp->driver_data;
176-
uint32_t bsr = enet_phy_read(d->phy_addr, MG_PHYREG_BSR);
177-
bool up = bsr & MG_BIT(2) ? 1 : 0;
147+
struct mg_tcpip_driver_stm32f_data *d =
148+
(struct mg_tcpip_driver_stm32f_data *) ifp->driver_data;
149+
uint8_t speed = MG_PHY_SPEED_10M;
150+
bool up = false, full_duplex = false;
151+
struct mg_phy phy = {eth_read_phy, eth_write_phy};
152+
up = mg_phy_up(&phy, d->phy_addr, &full_duplex, &speed);
178153
if ((ifp->state == MG_TCPIP_STATE_DOWN) && up) { // link state just went up
179154
// tmp = reg with flags set to the most likely situation: 100M full-duplex
180155
// if(link is slow or half) set flags otherwise
181156
// reg = tmp
182157
uint32_t tcr = ENET->TCR | MG_BIT(2); // Full-duplex
183158
uint32_t rcr = ENET->RCR & ~MG_BIT(9); // 100M
184-
uint32_t phy_id = enet_phy_id(d->phy_addr);
185-
if ((phy_id & 0xffff0000) == 0x220000) { // KSZ8081RNB
186-
uint16_t pc1r = enet_phy_read(d->phy_addr, 30); // Read PC1R
187-
if ((pc1r & 3) == 1) rcr |= MG_BIT(9); // 10M
188-
if ((pc1r & MG_BIT(2)) == 0) tcr &= ~MG_BIT(2); // Half-duplex
189-
} else if ((phy_id & 0xffff0000) == 0x20000000) { // DP83825I
190-
uint16_t physts = enet_phy_read(d->phy_addr, 16); // Read PHYSTS
191-
if (physts & MG_BIT(1)) rcr |= MG_BIT(9); // 10M
192-
if ((physts & MG_BIT(2)) == 0) tcr &= ~MG_BIT(2); // Half-duplex
193-
} else { // Default to LAN8720
194-
uint16_t scsr = enet_phy_read(d->phy_addr, 31); // Read CSCR
195-
if ((scsr & MG_BIT(3)) == 0) rcr |= MG_BIT(9); // 10M
196-
if ((scsr & MG_BIT(4)) == 0) tcr &= ~MG_BIT(2); // Half-duplex
197-
}
159+
if (speed == MG_PHY_SPEED_10M) rcr |= MG_BIT(9); // 10M
160+
if (full_duplex == false) tcr &= ~MG_BIT(2); // Half-duplex
198161
ENET->TCR = tcr; // IRQ handler does not fiddle with these registers
199162
ENET->RCR = rcr;
200163
MG_DEBUG(("Link is %uM %s-duplex", rcr & MG_BIT(9) ? 10 : 100,

‎src/drivers/phy.c

Lines changed: 81 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -1,52 +1,104 @@
11
#include "phy.h"
22

3-
enum {
4-
MG_PHY_KSZ8x = 0x22,
5-
MG_PHY_DP83x = 0x2000,
6-
MG_PHY_LAN87x = 0x7,
3+
enum { // ID1 ID2
4+
MG_PHY_KSZ8x = 0x22, // 0022 1561 - KSZ8081RNB
5+
MG_PHY_DP83x = 0x2000, // 2000 a140 - TI DP83825I
6+
MG_PHY_LAN87x = 0x7, // 0007 c0fx - LAN8720
7+
MG_PHY_RTL8201 = 0x1C // 001c c816 - RTL8201
78
};
89

910
enum {
1011
MG_PHY_REG_BCR = 0,
1112
MG_PHY_REG_BSR = 1,
1213
MG_PHY_REG_ID1 = 2,
1314
MG_PHY_REG_ID2 = 3,
14-
MG_PHY_REG_CSCR = 31,
15+
MG_PHY_DP83x_REG_PHYSTS = 16,
16+
MG_PHY_DP83x_REG_RCSR = 23,
17+
MG_PHY_DP83x_REG_LEDCR = 24,
18+
MG_PHY_KSZ8x_REG_PC1R = 30,
19+
MG_PHY_KSZ8x_REG_PC2R = 31,
20+
MG_PHY_LAN87x_REG_SCSR = 31,
21+
MG_PHY_RTL8201_REG_RMSR = 16, // in page 7
22+
MG_PHY_RTL8201_REG_PAGESEL = 31,
1523
};
1624

17-
static const char *mg_phy_id_to_str(uint16_t id) {
18-
switch (id) {
19-
case MG_PHY_KSZ8x: return "KSZ8x";
20-
case MG_PHY_DP83x: return "DP83x";
21-
case MG_PHY_LAN87x: return "LAN87x";
22-
default: return "unknown";
25+
static const char *mg_phy_id_to_str(uint16_t id1, uint16_t id2) {
26+
switch (id1) {
27+
case MG_PHY_DP83x:
28+
return "DP83x";
29+
case MG_PHY_KSZ8x:
30+
return "KSZ8x";
31+
case MG_PHY_LAN87x:
32+
return "LAN87x";
33+
case MG_PHY_RTL8201:
34+
return "RTL8201";
35+
default:
36+
return "unknown";
2337
}
38+
(void) id2;
2439
}
2540

26-
void mg_phy_init(struct mg_phy *phy) {
27-
uint16_t id1 = phy->read_reg(phy->addr, MG_PHY_REG_ID1);
28-
uint16_t id2 = phy->read_reg(phy->addr, MG_PHY_REG_ID2);
29-
MG_INFO(("PHY ID: %#04x %#04x (%s)", id1, id2, mg_phy_id_to_str(id1)));
41+
void mg_phy_init(struct mg_phy *phy, uint8_t phy_addr, uint8_t config) {
42+
phy->write_reg(phy_addr, MG_PHY_REG_BCR, MG_BIT(15)); // Reset PHY
43+
phy->write_reg(phy_addr, MG_PHY_REG_BCR, MG_BIT(12)); // Autonegotiation
3044

31-
phy->write_reg(phy->addr, MG_PHY_REG_BCR, MG_BIT(15)); // Reset PHY
32-
phy->write_reg(phy->addr, MG_PHY_REG_BCR, MG_BIT(12)); // Autonegotiation
45+
uint16_t id1 = phy->read_reg(phy_addr, MG_PHY_REG_ID1);
46+
uint16_t id2 = phy->read_reg(phy_addr, MG_PHY_REG_ID2);
47+
MG_INFO(("PHY ID: %#04x %#04x (%s)", id1, id2, mg_phy_id_to_str(id1, id2)));
3348

34-
if (id1 == MG_PHY_KSZ8x) {
35-
phy->write_reg(phy->addr, MG_PHY_REG_CSCR,
36-
MG_BIT(15) | MG_BIT(8) | MG_BIT(7));
37-
} else if (id1 == MG_PHY_DP83x) {
38-
phy->write_reg(phy->addr, 23, 0x81); // 50MHz clock input
39-
phy->write_reg(phy->addr, 24, 0x280); // LED status, active high
49+
bool clkconfig = config & 1;
50+
if (clkconfig == MG_PHY_CONF_CLOCKING) {
51+
// Use PHY crystal oscillator (preserve defaults)
52+
// nothing to do
53+
} else if (clkconfig == MG_PHY_CONF_CLOCKED) {
54+
// Enable 50 MHz external ref clock at XI (preserve defaults)
55+
if (id1 == MG_PHY_DP83x) {
56+
phy->write_reg(phy_addr, MG_PHY_DP83x_REG_RCSR, MG_BIT(7) | MG_BIT(0));
57+
} else if (id1 == MG_PHY_KSZ8x) {
58+
phy->write_reg(phy_addr, MG_PHY_KSZ8x_REG_PC2R,
59+
MG_BIT(15) | MG_BIT(8) | MG_BIT(7));
60+
} else if (id1 == MG_PHY_LAN87x) {
61+
// nothing to do
62+
} else if (id1 == MG_PHY_RTL8201) {
63+
phy->write_reg(phy_addr, MG_PHY_RTL8201_REG_PAGESEL, 7); // Select page 7
64+
phy->write_reg(phy_addr, MG_PHY_RTL8201_REG_RMSR, 0x7ffb);
65+
phy->write_reg(phy_addr, MG_PHY_RTL8201_REG_PAGESEL, 0); // Select page 0
66+
}
4067
}
68+
69+
bool leddrive = config & 2;
70+
if (leddrive && id1 == MG_PHY_DP83x) {
71+
phy->write_reg(phy_addr, MG_PHY_DP83x_REG_LEDCR,
72+
MG_BIT(9) | MG_BIT(7)); // LED status, active high
73+
} // Other PHYs do not support this feature
4174
}
4275

43-
bool mg_phy_up(struct mg_phy *phy, bool *full_duplex, uint8_t *speed) {
44-
uint16_t bsr = phy->read_reg(phy->addr, MG_PHY_REG_BSR);
76+
bool mg_phy_up(struct mg_phy *phy, uint8_t phy_addr, bool *full_duplex,
77+
uint8_t *speed) {
78+
uint16_t bsr = phy->read_reg(phy_addr, MG_PHY_REG_BSR);
79+
if ((bsr & MG_BIT(5)) && !(bsr & MG_BIT(2))) // some PHYs latch down events
80+
bsr = phy->read_reg(phy_addr, MG_PHY_REG_BSR); // read again
4581
bool up = bsr & MG_BIT(2);
46-
if (up) {
47-
uint16_t scsr = phy->read_reg(phy->addr, MG_PHY_REG_CSCR);
48-
*full_duplex = scsr & MG_BIT(4);
49-
*speed = scsr & MG_BIT(3) ? MG_PHY_SPEED_100M : MG_PHY_SPEED_10M;
82+
if (up && full_duplex != NULL && speed != NULL) {
83+
uint16_t id1 = phy->read_reg(phy_addr, MG_PHY_REG_ID1);
84+
if (id1 == MG_PHY_DP83x) {
85+
uint16_t physts = phy->read_reg(phy_addr, MG_PHY_DP83x_REG_PHYSTS);
86+
*full_duplex = physts & MG_BIT(2);
87+
*speed = (physts & MG_BIT(1)) ? MG_PHY_SPEED_10M : MG_PHY_SPEED_100M;
88+
} else if (id1 == MG_PHY_KSZ8x) {
89+
uint16_t pc1r = phy->read_reg(phy_addr, MG_PHY_KSZ8x_REG_PC1R);
90+
*full_duplex = pc1r & MG_BIT(2);
91+
*speed = (pc1r & 3) == 1 ? MG_PHY_SPEED_10M : MG_PHY_SPEED_100M;
92+
} else if (id1 == MG_PHY_LAN87x) {
93+
uint16_t scsr = phy->read_reg(phy_addr, MG_PHY_LAN87x_REG_SCSR);
94+
*full_duplex = scsr & MG_BIT(4);
95+
*speed = (scsr & MG_BIT(3)) ? MG_PHY_SPEED_100M : MG_PHY_SPEED_10M;
96+
} else if (id1 == MG_PHY_RTL8201) {
97+
uint16_t bcr = phy->read_reg(phy_addr, MG_PHY_REG_BCR);
98+
if (bcr & MG_BIT(15)) return 0; // still resetting
99+
*full_duplex = bcr & MG_BIT(8);
100+
*speed = (bcr & MG_BIT(13)) ? MG_PHY_SPEED_100M : MG_PHY_SPEED_10M;
101+
}
50102
}
51103
return up;
52104
}

‎src/drivers/phy.h

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3,12 +3,13 @@
33
#include "net_builtin.h"
44

55
struct mg_phy {
6-
uint8_t addr;
76
uint16_t (*read_reg)(uint8_t addr, uint8_t reg);
87
void (*write_reg)(uint8_t addr, uint8_t reg, uint16_t value);
98
};
109

10+
enum { MG_PHY_CONF_CLOCKING = 0, MG_PHY_CONF_CLOCKED = 1, MG_PHY_CONF_LEDS_AH = 2};
11+
1112
enum { MG_PHY_SPEED_10M, MG_PHY_SPEED_100M, MG_PHY_SPEED_1000M };
1213

13-
void mg_phy_init(struct mg_phy *);
14-
bool mg_phy_up(struct mg_phy *, bool *full_duplex, uint8_t *speed);
14+
void mg_phy_init(struct mg_phy *, uint8_t addr, uint8_t configtype);
15+
bool mg_phy_up(struct mg_phy *, uint8_t addr, bool *full_duplex, uint8_t *speed);

‎src/drivers/ra.c

Lines changed: 11 additions & 47 deletions
Original file line numberDiff line numberDiff line change
@@ -41,13 +41,6 @@ static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_32BYTE_ALIGNED;
4141
static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_32BYTE_ALIGNED;
4242
static struct mg_tcpip_if *s_ifp; // MIP interface
4343

44-
enum {
45-
MG_PHYREG_BCR = 0,
46-
MG_PHYREG_BSR = 1,
47-
MG_PHYREG_ID1 = 2,
48-
MG_PHYREG_ID2 = 3
49-
};
50-
5144
// fastest is 3 cycles (SUB + BNE) on a 3-stage pipeline or equivalent
5245
static inline void raspin(volatile uint32_t count) {
5346
while (count--) (void) 0;
@@ -164,28 +157,9 @@ static bool mg_tcpip_driver_ra_init(struct mg_tcpip_if *ifp) {
164157
EDMAC->EDMR = MG_BIT(6); // Initialize, little-endian (27.2.1)
165158

166159
MG_DEBUG(("PHY addr: %d, smispin: %d", d->phy_addr, s_smispin));
167-
raeth_phy_write(d->phy_addr, MG_PHYREG_BCR, MG_BIT(15)); // Reset PHY
168-
raeth_phy_write(d->phy_addr, MG_PHYREG_BCR,
169-
MG_BIT(12)); // Set autonegotiation
170-
171-
// PHY: Enable ref clock (preserve defaults)
172-
uint32_t id = raeth_phy_id(d->phy_addr);
173-
MG_INFO(("PHY ID: %#04x %#04x", (uint16_t) (id >> 16), (uint16_t) id));
174-
// 2000 a140 - TI DP83825I
175-
// 0007 c0fx - LAN8720
176-
// 0022 156x - KSZ8081RNB/KSZ8091RNB
177-
178-
if ((id & 0xffff0000) == 0x220000) { // KSZ8091RNB, like EK-RA6Mx boards
179-
// 25 MHz xtal at XI/XO (default)
180-
raeth_phy_write(d->phy_addr, 31, MG_BIT(15) | MG_BIT(8)); // PC2R
181-
} else if ((id & 0xffff0000) == 0x20000000) { // DP83825I, like ???
182-
// 50 MHz external at XI ???
183-
raeth_phy_write(d->phy_addr, 23, 0x81); // 50MHz clock input
184-
raeth_phy_write(d->phy_addr, 24, 0x280); // LED status, active high
185-
} else { // Default to LAN8720
186-
MG_INFO(("Defaulting to LAN8720 PHY...")); // TODO()
187-
}
188-
160+
struct mg_phy phy = {eth_read_phy, eth_write_phy};
161+
mg_phy_init(&phy, d->phy_addr);
162+
189163
// Select RMII mode,
190164
ETHERC->ECMR = MG_BIT(2) | MG_BIT(1); // 100M, Full-duplex, CRC
191165
// ETHERC->ECMR |= MG_BIT(0); // Receive all
@@ -231,29 +205,19 @@ static size_t mg_tcpip_driver_ra_tx(const void *buf, size_t len,
231205
}
232206

233207
static bool mg_tcpip_driver_ra_up(struct mg_tcpip_if *ifp) {
234-
struct mg_tcpip_driver_ra_data *d =
235-
(struct mg_tcpip_driver_ra_data *) ifp->driver_data;
236-
uint32_t bsr = raeth_phy_read(d->phy_addr, MG_PHYREG_BSR);
237-
bool up = bsr & MG_BIT(2) ? 1 : 0;
208+
struct mg_tcpip_driver_stm32f_data *d =
209+
(struct mg_tcpip_driver_stm32f_data *) ifp->driver_data;
210+
uint8_t speed = MG_PHY_SPEED_10M;
211+
bool up = false, full_duplex = false;
212+
struct mg_phy phy = {eth_read_phy, eth_write_phy};
213+
up = mg_phy_up(&phy, d->phy_addr, &full_duplex, &speed);
238214
if ((ifp->state == MG_TCPIP_STATE_DOWN) && up) { // link state just went up
239215
// tmp = reg with flags set to the most likely situation: 100M full-duplex
240216
// if(link is slow or half) set flags otherwise
241217
// reg = tmp
242218
uint32_t ecmr = ETHERC->ECMR | MG_BIT(2) | MG_BIT(1); // 100M Full-duplex
243-
uint32_t phy_id = raeth_phy_id(d->phy_addr);
244-
if ((phy_id & 0xffff0000) == 0x220000) { // KSZ8091RNB
245-
uint16_t pc1r = raeth_phy_read(d->phy_addr, 30); // Read PC1R
246-
if ((pc1r & 3) == 1) ecmr &= ~MG_BIT(2); // 10M
247-
if ((pc1r & MG_BIT(2)) == 0) ecmr &= ~MG_BIT(1); // Half-duplex
248-
} else if ((phy_id & 0xffff0000) == 0x20000000) { // DP83825I
249-
uint16_t physts = raeth_phy_read(d->phy_addr, 16); // Read PHYSTS
250-
if (physts & MG_BIT(1)) ecmr &= ~MG_BIT(2); // 10M
251-
if ((physts & MG_BIT(2)) == 0) ecmr &= ~MG_BIT(1); // Half-duplex
252-
} else { // Default to LAN8720
253-
uint16_t scsr = raeth_phy_read(d->phy_addr, 31); // Read CSCR
254-
if ((scsr & MG_BIT(3)) == 0) ecmr &= ~MG_BIT(2); // 10M
255-
if ((scsr & MG_BIT(4)) == 0) ecmr &= ~MG_BIT(1); // Half-duplex
256-
}
219+
if (speed == MG_PHY_SPEED_10M) ecmr &= ~MG_BIT(2); // 10M
220+
if (full_duplex == false) ecmr &= ~MG_BIT(1); // Half-duplex
257221
ETHERC->ECMR = ecmr; // IRQ handler does not fiddle with these registers
258222
MG_DEBUG(("Link is %uM %s-duplex", ecmr & MG_BIT(2) ? 100 : 10,
259223
ecmr & MG_BIT(1) ? "full" : "half"));

‎src/drivers/stm32f.c

Lines changed: 7 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -30,13 +30,6 @@ static uint8_t s_txno; // Current TX descriptor
3030
static uint8_t s_rxno; // Current RX descriptor
3131

3232
static struct mg_tcpip_if *s_ifp; // MIP interface
33-
enum {
34-
MG_PHYREG_BCR = 0,
35-
MG_PHYREG_BSR = 1,
36-
MG_PHYREG_ID1 = 2,
37-
MG_PHYREG_ID2 = 3,
38-
MG_PHYREG_CSCR = 31
39-
};
4033

4134
static uint16_t eth_read_phy(uint8_t addr, uint8_t reg) {
4235
ETH->MACMIIAR &= (7 << 2);
@@ -144,8 +137,8 @@ static bool mg_tcpip_driver_stm32f_init(struct mg_tcpip_if *ifp) {
144137
ETH->MACIMR = MG_BIT(3) | MG_BIT(9); // Mask timestamp & PMT IT
145138
ETH->MACFCR = MG_BIT(7); // Disable zero quarta pause
146139
// ETH->MACFFR = MG_BIT(31); // Receive all
147-
struct mg_phy phy = {d->phy_addr, eth_read_phy, eth_write_phy};
148-
mg_phy_init(&phy);
140+
struct mg_phy phy = {eth_read_phy, eth_write_phy};
141+
mg_phy_init(&phy, d->phy_addr);
149142
ETH->DMARDLAR = (uint32_t) (uintptr_t) s_rxdesc; // RX descriptors
150143
ETH->DMATDLAR = (uint32_t) (uintptr_t) s_txdesc; // RX descriptors
151144
ETH->DMAIER = MG_BIT(6) | MG_BIT(16); // RIE, NISE
@@ -154,9 +147,6 @@ static bool mg_tcpip_driver_stm32f_init(struct mg_tcpip_if *ifp) {
154147
ETH->DMAOMR =
155148
MG_BIT(1) | MG_BIT(13) | MG_BIT(21) | MG_BIT(25); // SR, ST, TSF, RSF
156149

157-
MG_DEBUG(("PHY ID: %#04hx %#04hx", eth_read_phy(phy_addr, MG_PHYREG_ID1),
158-
eth_read_phy(phy_addr, MG_PHYREG_ID2)));
159-
160150
// MAC address filtering
161151
ETH->MACA0HR = ((uint32_t) ifp->mac[5] << 8U) | ifp->mac[4];
162152
ETH->MACA0LR = (uint32_t) (ifp->mac[3] << 24) |
@@ -193,9 +183,12 @@ static bool mg_tcpip_driver_stm32f_up(struct mg_tcpip_if *ifp) {
193183
(struct mg_tcpip_driver_stm32f_data *) ifp->driver_data;
194184
uint8_t speed = MG_PHY_SPEED_10M;
195185
bool up = false, full_duplex = false;
196-
struct mg_phy phy = {d->phy_addr, eth_read_phy, eth_write_phy};
197-
up = mg_phy_up(&phy, &full_duplex, &speed);
186+
struct mg_phy phy = {eth_read_phy, eth_write_phy};
187+
up = mg_phy_up(&phy, d->phy_addr, &full_duplex, &speed);
198188
if ((ifp->state == MG_TCPIP_STATE_DOWN) && up) { // link state just went up
189+
// tmp = reg with flags set to the most likely situation: 100M full-duplex
190+
// if(link is slow or half) set flags otherwise
191+
// reg = tmp
199192
uint32_t maccr = ETH->MACCR | MG_BIT(14) | MG_BIT(11); // 100M, Full-duplex
200193
if (speed == MG_PHY_SPEED_10M) maccr &= ~MG_BIT(14); // 10M
201194
if (full_duplex == false) maccr &= ~MG_BIT(11); // Half-duplex

‎src/drivers/stm32f.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -34,7 +34,7 @@ struct mg_tcpip_driver_stm32f_data {
3434

3535
#define MG_TCPIP_DRIVER_DATA \
3636
static struct mg_tcpip_driver_stm32f_data driver_data = { \
37-
.mdc_cr = MG_DRIVER_MDC_CR, \
37+
.mdc_cr = MG_DRIVER_MDC_CR, \
3838
.phy_addr = MG_TCPIP_PHY_ADDR, \
3939
};
4040

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