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arch/arm64: fix create page table err
arm64 only PA_BITS=52 level 0 can be used as BlockDescriptors Signed-off-by: lipengfei28 <[email protected]>
1 parent ba05c7f commit ae58134

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2 files changed

+11
-2
lines changed

2 files changed

+11
-2
lines changed

arch/arm64/src/common/arm64_mmu.c

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -142,7 +142,9 @@
142142
#define BASE_XLAT_TABLE_ALIGN NUM_BASE_LEVEL_ENTRIES * sizeof(uint64_t)
143143
#endif
144144

145-
#if (CONFIG_ARM64_PA_BITS == 48)
145+
#if (CONFIG_ARM64_PA_BITS == 52)
146+
#define TCR_PS_BITS TCR_PS_BITS_4PB
147+
#elif (CONFIG_ARM64_PA_BITS == 48)
146148
#define TCR_PS_BITS TCR_PS_BITS_256TB
147149
#elif (CONFIG_ARM64_PA_BITS == 44)
148150
#define TCR_PS_BITS TCR_PS_BITS_16TB
@@ -267,6 +269,10 @@ static uint64_t get_tcr(int el)
267269
tcr |= TCR_TG0_4K | TCR_SHARED_INNER | TCR_ORGN_WBWA |
268270
TCR_IRGN_WBWA | TCR_TBI_FLAGS;
269271

272+
#if (CONFIG_ARM64_PA_BITS == 52)
273+
tcr |= TCR_DS;
274+
#endif
275+
270276
return tcr;
271277
}
272278

@@ -487,7 +493,8 @@ static void init_xlat_tables(const struct arm_mmu_region *region)
487493

488494
level_size = 1ULL << LEVEL_TO_VA_SIZE_SHIFT(level);
489495

490-
if (size >= level_size && !(virt & (level_size - 1)))
496+
if (size >= level_size && !(virt & (level_size - 1))
497+
&& ((level == 0 && CONFIG_ARM64_PA_BITS == 52) || level != 0))
491498
{
492499
/* Given range fits into level size,
493500
* create block/page descriptor

arch/arm64/src/common/arm64_mmu.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -156,6 +156,7 @@
156156
#define TCR_TG0_64K (1ULL << 14)
157157
#define TCR_TG0_16K (2ULL << 14)
158158
#define TCR_EPD1_DISABLE (1ULL << 23)
159+
#define TCR_DS (1ULL << 59)
159160

160161
#define TCR_AS_SHIFT 36U
161162
#define TCR_ASID_8 (0ULL << TCR_AS_SHIFT)
@@ -181,6 +182,7 @@
181182
#define TCR_PS_BITS_4TB 0x3ULL
182183
#define TCR_PS_BITS_16TB 0x4ULL
183184
#define TCR_PS_BITS_256TB 0x5ULL
185+
#define TCR_PS_BITS_4PB 0x6ULL
184186

185187
#define CTR_EL0_DMINLINE_SHIFT 16
186188
#define CTR_EL0_DMINLINE_MASK BIT_MASK(4)

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