MLP example design for RTL co-simulation

[andrewboutros]

These bugs were reported by @geotrieu. Adding them here to keep track of open issues and potentially fix them.

1. memory_block inside accum.v has Read after Write hazards

• Bug appeared when George tried to run a scenario where there is only two chunks. Since we write to the chunk 0, then write to chunk 1, then we read from chunk 0 again to accumulate, it seems the memory block can't return the data that quick. He made a quick fix so he can run his performance tests, but he is not sure if this bug persists for scenarios where there is only one chunk. Fix is on this branch: https://github.com/andrewboutros/rad-flow/tree/mlp_int8_patch
• It is super weird because in RAD-Sim, this isn't an issue. However, using the same RTL that is verilated by RAD-Sim, I can see in the waveforms that there is definitely an issue with this hazard.

2. FIFO sizes must be greater than the number of input vectors

• Say we wanted to run a test with 100 x 3 input vectors. We need a fifo size of 512 to accommodate this, otherwise it doesn't terminate.
• Issue exists in both RAD-Sim and Modelsim, both in Verilated RTL and Native SystemC.
• George didn't get a chance to look into a fix for this one.

3. It is possible that simulation using native SystemC modules written at a higher level of abstraction instead of a close-to-RTL implementation result in a significant speedup.