From a04190933376cbc1b8554881a00d1efe9347d982 Mon Sep 17 00:00:00 2001 From: George Trieu Date: Mon, 28 Aug 2023 18:54:06 -0400 Subject: [PATCH 1/4] Initial commit of the add example --- rad-sim/example-designs/add/CMakeLists.txt | 33 +++++++ rad-sim/example-designs/add/add.clks | 2 + rad-sim/example-designs/add/add.place | 2 + rad-sim/example-designs/add/add_driver.cpp | 52 +++++++++++ rad-sim/example-designs/add/add_driver.hpp | 30 ++++++ rad-sim/example-designs/add/add_system.cpp | 28 ++++++ rad-sim/example-designs/add/add_system.hpp | 24 +++++ rad-sim/example-designs/add/add_top.cpp | 33 +++++++ rad-sim/example-designs/add/add_top.hpp | 24 +++++ rad-sim/example-designs/add/config.yml | 37 ++++++++ rad-sim/example-designs/add/modules/adder.cpp | 64 +++++++++++++ rad-sim/example-designs/add/modules/adder.hpp | 30 ++++++ .../example-designs/add/modules/client.cpp | 92 +++++++++++++++++++ .../example-designs/add/modules/client.hpp | 38 ++++++++ 14 files changed, 489 insertions(+) create mode 100644 rad-sim/example-designs/add/CMakeLists.txt create mode 100644 rad-sim/example-designs/add/add.clks create mode 100644 rad-sim/example-designs/add/add.place create mode 100644 rad-sim/example-designs/add/add_driver.cpp create mode 100644 rad-sim/example-designs/add/add_driver.hpp create mode 100644 rad-sim/example-designs/add/add_system.cpp create mode 100644 rad-sim/example-designs/add/add_system.hpp create mode 100644 rad-sim/example-designs/add/add_top.cpp create mode 100644 rad-sim/example-designs/add/add_top.hpp create mode 100644 rad-sim/example-designs/add/config.yml create mode 100644 rad-sim/example-designs/add/modules/adder.cpp create mode 100644 rad-sim/example-designs/add/modules/adder.hpp create mode 100644 rad-sim/example-designs/add/modules/client.cpp create mode 100644 rad-sim/example-designs/add/modules/client.hpp diff --git a/rad-sim/example-designs/add/CMakeLists.txt b/rad-sim/example-designs/add/CMakeLists.txt new file mode 100644 index 0000000..6dceabd --- /dev/null +++ b/rad-sim/example-designs/add/CMakeLists.txt @@ -0,0 +1,33 @@ +cmake_minimum_required(VERSION 3.19) +find_package(SystemCLanguage CONFIG REQUIRED) + +include_directories( + ./ + modules + ../../sim + ../../sim/noc + ../../sim/noc/booksim + ../../sim/noc/booksim/networks + ../../sim/noc/booksim/routers +) + +set(srcfiles + modules/adder.cpp + modules/client.cpp + add_top.cpp + add_driver.cpp + add_system.cpp +) + +set(hdrfiles + modules/adder.hpp + modules/client.hpp + add_top.hpp + add_driver.hpp + add_system.hpp +) + +add_compile_options(-Wall -Wextra -pedantic) + +add_library(design STATIC ${srcfiles} ${hdrfiles}) +target_link_libraries(design PUBLIC SystemC::systemc booksim noc) \ No newline at end of file diff --git a/rad-sim/example-designs/add/add.clks b/rad-sim/example-designs/add/add.clks new file mode 100644 index 0000000..a5df186 --- /dev/null +++ b/rad-sim/example-designs/add/add.clks @@ -0,0 +1,2 @@ +adder_inst 0 0 +client_inst 0 0 \ No newline at end of file diff --git a/rad-sim/example-designs/add/add.place b/rad-sim/example-designs/add/add.place new file mode 100644 index 0000000..ca746f7 --- /dev/null +++ b/rad-sim/example-designs/add/add.place @@ -0,0 +1,2 @@ +adder_inst 0 0 axis +client_inst 0 3 axis \ No newline at end of file diff --git a/rad-sim/example-designs/add/add_driver.cpp b/rad-sim/example-designs/add/add_driver.cpp new file mode 100644 index 0000000..460a770 --- /dev/null +++ b/rad-sim/example-designs/add/add_driver.cpp @@ -0,0 +1,52 @@ +#include + +#define NUM_ADDENDS 100 + +add_driver::add_driver(const sc_module_name &name) + : sc_module(name) { + + // Random Seed + srand (time(NULL)); + + // Generate random numbers to be added together by the adder + std::cout << "Generating Random Numbers to be added ..." << std::endl; + for (unsigned int i = 0; i < NUM_ADDENDS; i++) { + unsigned int r_num = std::rand() % 10 + 1; + std::cout << r_num << " "; + numbers_to_send.push_back(r_num); + } + std::cout << std::endl << "----------------------------------------" << std::endl; + + SC_CTHREAD(source, clk.pos()); + SC_CTHREAD(sink, clk.pos()); +} + +add_driver::~add_driver() {} + +void add_driver::source() { + // Reset + rst.write(true); + client_valid.write(false); + wait(); + rst.write(false); + wait(); + + unsigned int idx = 0; + while (idx < numbers_to_send.size()) { + client_tdata.write(numbers_to_send[idx]); + client_tlast.write(idx >= (numbers_to_send.size() - 1)); + client_valid.write(true); + + wait(); + + if (client_valid.read() && client_ready.read()) { + idx++; + } + } + client_valid.write(false); + std::cout << "Finished sending all numbers to adder module!" << std::endl; + wait(); +} + +void add_driver::sink() { +} \ No newline at end of file diff --git a/rad-sim/example-designs/add/add_driver.hpp b/rad-sim/example-designs/add/add_driver.hpp new file mode 100644 index 0000000..e447560 --- /dev/null +++ b/rad-sim/example-designs/add/add_driver.hpp @@ -0,0 +1,30 @@ +#pragma once + +#include +#include +#include +#include +#include +#include +#include + +class add_driver : public sc_module { +private: + std::vector numbers_to_send; + +public: + sc_in clk; + sc_out rst; + sc_out> client_tdata; + sc_out client_tlast; + sc_out client_valid; + sc_in client_ready; + + add_driver(const sc_module_name &name); + ~add_driver(); + + void source(); + void sink(); + + SC_HAS_PROCESS(add_driver); +}; \ No newline at end of file diff --git a/rad-sim/example-designs/add/add_system.cpp b/rad-sim/example-designs/add/add_system.cpp new file mode 100644 index 0000000..26a9f10 --- /dev/null +++ b/rad-sim/example-designs/add/add_system.cpp @@ -0,0 +1,28 @@ +#include + +add_system::add_system(const sc_module_name &name, sc_clock *driver_clk_sig) + : sc_module(name) { + + // Instantiate driver + driver_inst = new add_driver("driver"); + driver_inst->clk(*driver_clk_sig); + driver_inst->rst(rst_sig); + driver_inst->client_tdata(client_tdata_sig); + driver_inst->client_tlast(client_tlast_sig); + driver_inst->client_valid(client_valid_sig); + driver_inst->client_ready(client_ready_sig); + + // Instantiate design top-level + dut_inst = new add_top("dut"); + dut_inst->rst(rst_sig); + dut_inst->client_tdata(client_tdata_sig); + dut_inst->client_tlast(client_tlast_sig); + dut_inst->client_valid(client_valid_sig); + dut_inst->client_ready(client_ready_sig); +} + +add_system::~add_system() { + delete driver_inst; + delete dut_inst; + delete sysclk; +} \ No newline at end of file diff --git a/rad-sim/example-designs/add/add_system.hpp b/rad-sim/example-designs/add/add_system.hpp new file mode 100644 index 0000000..8207d43 --- /dev/null +++ b/rad-sim/example-designs/add/add_system.hpp @@ -0,0 +1,24 @@ +#pragma once + +#include +#include +#include +#include + +class add_system : public sc_module { +private: + sc_signal> client_tdata_sig; + sc_signal client_tlast_sig; + sc_signal client_valid_sig; + sc_signal client_ready_sig; + +public: + sc_signal rst_sig; + sc_clock *sysclk; + add_driver *driver_inst; + add_top *dut_inst; + + add_system(const sc_module_name &name, + sc_clock *driver_clk_sig); + ~add_system(); +}; \ No newline at end of file diff --git a/rad-sim/example-designs/add/add_top.cpp b/rad-sim/example-designs/add/add_top.cpp new file mode 100644 index 0000000..9e5cf63 --- /dev/null +++ b/rad-sim/example-designs/add/add_top.cpp @@ -0,0 +1,33 @@ +#include + +add_top::add_top(const sc_module_name &name) + : sc_module(name) { + + std::string module_name_str; + char module_name[25]; + + module_name_str = "client_inst"; + std::strcpy(module_name, module_name_str.c_str()); + + client_inst = new client(module_name, 16); + client_inst->rst(rst); + client_inst->client_tdata(client_tdata); + client_inst->client_tlast(client_tlast); + client_inst->client_valid(client_valid); + client_inst->client_ready(client_ready); + + module_name_str = "adder_inst"; + std::strcpy(module_name, module_name_str.c_str()); + adder_inst = new adder(module_name); + adder_inst->rst(rst); + + radsim_design.BuildDesignContext("add.place", + "add.clks"); + radsim_design.CreateSystemNoCs(rst); + radsim_design.ConnectModulesToNoC(); +} + +add_top::~add_top() { + delete adder_inst; + delete client_inst; +} \ No newline at end of file diff --git a/rad-sim/example-designs/add/add_top.hpp b/rad-sim/example-designs/add/add_top.hpp new file mode 100644 index 0000000..d15e44a --- /dev/null +++ b/rad-sim/example-designs/add/add_top.hpp @@ -0,0 +1,24 @@ +#pragma once + +#include +#include +#include +#include +#include + +class add_top : public sc_module { +private: + adder *adder_inst; + client *client_inst; + +public: + sc_in rst; + // Client's interface + sc_in> client_tdata; + sc_in client_tlast; + sc_in client_valid; + sc_out client_ready; + + add_top(const sc_module_name &name); + ~add_top(); +}; \ No newline at end of file diff --git a/rad-sim/example-designs/add/config.yml b/rad-sim/example-designs/add/config.yml new file mode 100644 index 0000000..24749d8 --- /dev/null +++ b/rad-sim/example-designs/add/config.yml @@ -0,0 +1,37 @@ +noc: + type: ['2d'] + num_nocs: 1 + clk_period: [1.0] + payload_width: [166] + topology: ['mesh'] + dim_x: [4] + dim_y: [4] + routing_func: ['dim_order'] + vcs: [5] + vc_buffer_size: [8] + output_buffer_size: [8] + num_packet_types: [5] + router_uarch: ['iq'] + vc_allocator: ['islip'] + sw_allocator: ['islip'] + credit_delay: [1] + routing_delay: [1] + vc_alloc_delay: [1] + sw_alloc_delay: [1] + +noc_adapters: + clk_period: [1.25] + fifo_size: [16] + obuff_size: [2] + in_arbiter: ['fixed_rr'] + out_arbiter: ['priority_rr'] + vc_mapping: ['direct'] + +design: + name: 'add' + noc_placement: ['add.place'] + clk_periods: [5.0] + +telemetry: + log_verbosity: 2 + traces: [] \ No newline at end of file diff --git a/rad-sim/example-designs/add/modules/adder.cpp b/rad-sim/example-designs/add/modules/adder.cpp new file mode 100644 index 0000000..ff0bf44 --- /dev/null +++ b/rad-sim/example-designs/add/modules/adder.cpp @@ -0,0 +1,64 @@ +#include + +adder::adder(const sc_module_name &name) + : radsim_module(name) { + + // Combinational logic and its sensitivity list + SC_METHOD(Assign); + sensitive << rst; + // Sequential logic and its clock/reset setup + SC_CTHREAD(Tick, clk.pos()); + reset_signal_is(rst, true); // Reset is active high + + // This function must be defined & called for any RAD-Sim module to register + // its info for automatically connecting to the NoC + this->RegisterModuleInfo(); +} + +adder::~adder() {} + +void adder::Assign() { + if (rst) { + axis_adder_interface.tready.write(false); + } else { + // Always ready to accept the transaction + axis_adder_interface.tready.write(true); + } +} + +void adder::Tick() { + wait(); + + // Always @ positive edge of the clock + while (true) { + // Receiving transaction from AXI-S interface + if (axis_adder_interface.tvalid.read() && + axis_adder_interface.tready.read()) { + uint64_t current_sum = adder_rolling_sum.to_uint64(); + adder_rolling_sum = current_sum + axis_adder_interface.tdata.read().to_uint64(); + t_finished.write(axis_adder_interface.tlast.read()); + std::cout << module_name << ": Got Transaction (user = " + << axis_adder_interface.tuser.read().to_uint64() << ") (addend = " + << axis_adder_interface.tdata.read().to_uint64() << ")!" + << std::endl; + } + + // Print Sum and Exit + if (t_finished.read()) { + std::cout << "The final sum of all the addends in the transactions is: " << adder_rolling_sum.to_uint64() << std::endl; + sc_stop(); + } + wait(); + } +} + +void adder::RegisterModuleInfo() { + std::string port_name; + _num_noc_axis_slave_ports = 0; + _num_noc_axis_master_ports = 0; + _num_noc_aximm_slave_ports = 0; + _num_noc_aximm_master_ports = 0; + + port_name = module_name + ".axis_adder_interface"; + RegisterAxisSlavePort(port_name, &axis_adder_interface, DATAW, 0); +} \ No newline at end of file diff --git a/rad-sim/example-designs/add/modules/adder.hpp b/rad-sim/example-designs/add/modules/adder.hpp new file mode 100644 index 0000000..aedafa3 --- /dev/null +++ b/rad-sim/example-designs/add/modules/adder.hpp @@ -0,0 +1,30 @@ +#pragma once + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +class adder : public radsim_module { +private: + sc_bv adder_rolling_sum; // Sum to store result + sc_signal t_finished; // Signal flagging that the transaction has terminated + +public: + sc_in rst; + // Interface to the NoC + axis_slave_port axis_adder_interface; + + adder(const sc_module_name &name); + ~adder(); + + void Assign(); // Combinational logic process + void Tick(); // Sequential logic process + SC_HAS_PROCESS(adder); + void RegisterModuleInfo(); +}; \ No newline at end of file diff --git a/rad-sim/example-designs/add/modules/client.cpp b/rad-sim/example-designs/add/modules/client.cpp new file mode 100644 index 0000000..36c3d89 --- /dev/null +++ b/rad-sim/example-designs/add/modules/client.cpp @@ -0,0 +1,92 @@ +#include + +client::client(const sc_module_name &name, unsigned int fifo_depth) + : radsim_module(name) { + + client_fifo_depth = fifo_depth; + + // Combinational logic and its sensitivity list + SC_METHOD(Assign); + sensitive << rst << client_fifo_full; + // Sequential logic and its clock/reset setup + SC_CTHREAD(Tick, clk.pos()); + reset_signal_is(rst, true); // Reset is active high + + // This function must be defined & called for any RAD-Sim module to register + // its info for automatically connecting to the NoC + this->RegisterModuleInfo(); +} + +client::~client() {} + +void client::Assign() { + if (rst) { + client_ready.write(true); // ready to accept requests from driver testbench + } else { + // Ready to accept new addend from driver testbench as long as the addend + // FIFO is not full + client_ready.write(!client_fifo_full.read()); + } +} + +void client::Tick() { + // Reset logic + axis_client_interface.tvalid.write(false); + while (!client_tdata_fifo.empty()) { + client_tdata_fifo.pop(); + } + client_fifo_full.write(false); + wait(); + + std::string src_port_name = module_name + ".axis_client_interface"; + + // Always @ positive edge of the clock + while (true) { + // Interface with testbench driver + if (client_ready.read() && client_valid.read()) { + client_tdata_fifo.push(client_tdata); + testbench_tlast = client_tlast.read(); + std::cout << module_name << ": Pushed request to FIFO" << std::endl; + } + client_fifo_full.write(client_tdata_fifo.size() >= client_fifo_depth); + + // Sending transactions to AXI-S NoC + if (!client_tdata_fifo.empty()) { + sc_bv tdata = client_tdata_fifo.front(); + std::string dst_port_name = "adder_inst.axis_adder_interface"; + uint64_t dst_addr = radsim_design.GetPortDestinationID(dst_port_name); + uint64_t src_addr = radsim_design.GetPortDestinationID(src_port_name); + + axis_client_interface.tdest.write(dst_addr); + axis_client_interface.tid.write(0); + axis_client_interface.tstrb.write(0); + axis_client_interface.tkeep.write(0); + axis_client_interface.tuser.write(src_addr); + axis_client_interface.tlast.write(testbench_tlast && (client_tdata_fifo.size() == 1)); + axis_client_interface.tdata.write(tdata); + + axis_client_interface.tvalid.write(true); + } else { + axis_client_interface.tvalid.write(false); + } + + if (axis_client_interface.tvalid.read() && + axis_client_interface.tready.read()) { + axis_client_interface.tvalid.write(false); + client_tdata_fifo.pop(); + std::cout << module_name << ": Sent Transaction!" << std::endl; + } + wait(); + } +} + +void client::RegisterModuleInfo() { + std::string port_name; + _num_noc_axis_slave_ports = 0; + _num_noc_axis_master_ports = 0; + _num_noc_aximm_slave_ports = 0; + _num_noc_aximm_master_ports = 0; + + port_name = module_name + ".axis_client_interface"; + RegisterAxisMasterPort(port_name, &axis_client_interface, DATAW, 0); +} diff --git a/rad-sim/example-designs/add/modules/client.hpp b/rad-sim/example-designs/add/modules/client.hpp new file mode 100644 index 0000000..88ff58d --- /dev/null +++ b/rad-sim/example-designs/add/modules/client.hpp @@ -0,0 +1,38 @@ +#pragma once + +#include +#include +#include +#include +#include +#include +#include +#include + +#define DATAW 512 + +class client : public radsim_module { +private: + std::queue> client_tdata_fifo; // FIFO to store numbers + unsigned int client_fifo_depth; // MAXIMUM number of addends to store in FIFO + sc_signal client_fifo_full; // Signal flagging addend FIFO is full + bool testbench_tlast; + +public: + sc_in rst; + // Interface to driver logic + sc_in> client_tdata; + sc_in client_tlast; + sc_in client_valid; + sc_out client_ready; + // Interface to the NoC + axis_master_port axis_client_interface; + + client(const sc_module_name &name, unsigned int fifo_depth); + ~client(); + + void Assign(); // Combinational logic process + void Tick(); // Sequential logic process + SC_HAS_PROCESS(client); + void RegisterModuleInfo(); +}; \ No newline at end of file From f2d7454ebec96deb887a03430374c2db423aaa24 Mon Sep 17 00:00:00 2001 From: George Trieu Date: Mon, 11 Sep 2023 16:32:45 -0400 Subject: [PATCH 2/4] Minor changes to the add example design --- rad-sim/example-designs/add/add_driver.cpp | 15 +++++++-------- rad-sim/example-designs/add/add_driver.hpp | 4 ++-- rad-sim/example-designs/add/modules/adder.cpp | 3 ++- rad-sim/example-designs/add/modules/client.cpp | 1 - 4 files changed, 11 insertions(+), 12 deletions(-) diff --git a/rad-sim/example-designs/add/add_driver.cpp b/rad-sim/example-designs/add/add_driver.cpp index 460a770..911a69d 100644 --- a/rad-sim/example-designs/add/add_driver.cpp +++ b/rad-sim/example-designs/add/add_driver.cpp @@ -1,6 +1,6 @@ #include -#define NUM_ADDENDS 100 +#define NUM_ADDENDS 3 add_driver::add_driver(const sc_module_name &name) : sc_module(name) { @@ -13,7 +13,7 @@ add_driver::add_driver(const sc_module_name &name) for (unsigned int i = 0; i < NUM_ADDENDS; i++) { unsigned int r_num = std::rand() % 10 + 1; std::cout << r_num << " "; - numbers_to_send.push_back(r_num); + numbers_to_send.push(r_num); } std::cout << std::endl << "----------------------------------------" << std::endl; @@ -31,20 +31,19 @@ void add_driver::source() { rst.write(false); wait(); - unsigned int idx = 0; - while (idx < numbers_to_send.size()) { - client_tdata.write(numbers_to_send[idx]); - client_tlast.write(idx >= (numbers_to_send.size() - 1)); + while (!numbers_to_send.empty()) { + client_tdata.write(numbers_to_send.front()); + client_tlast.write(numbers_to_send.size() <= 1); client_valid.write(true); wait(); if (client_valid.read() && client_ready.read()) { - idx++; + numbers_to_send.pop(); } } client_valid.write(false); - std::cout << "Finished sending all numbers to adder module!" << std::endl; + std::cout << "Finished sending all numbers to client module!" << std::endl; wait(); } diff --git a/rad-sim/example-designs/add/add_driver.hpp b/rad-sim/example-designs/add/add_driver.hpp index e447560..53768ea 100644 --- a/rad-sim/example-designs/add/add_driver.hpp +++ b/rad-sim/example-designs/add/add_driver.hpp @@ -6,11 +6,11 @@ #include #include #include -#include +#include class add_driver : public sc_module { private: - std::vector numbers_to_send; + std::queue numbers_to_send; public: sc_in clk; diff --git a/rad-sim/example-designs/add/modules/adder.cpp b/rad-sim/example-designs/add/modules/adder.cpp index ff0bf44..48fa6ea 100644 --- a/rad-sim/example-designs/add/modules/adder.cpp +++ b/rad-sim/example-designs/add/modules/adder.cpp @@ -19,6 +19,7 @@ adder::~adder() {} void adder::Assign() { if (rst) { + adder_rolling_sum = 0; axis_adder_interface.tready.write(false); } else { // Always ready to accept the transaction @@ -45,7 +46,7 @@ void adder::Tick() { // Print Sum and Exit if (t_finished.read()) { - std::cout << "The final sum of all the addends in the transactions is: " << adder_rolling_sum.to_uint64() << std::endl; + std::cout << module_name << ": The final sum of all the addends in the transactions is: " << adder_rolling_sum.to_uint64() << std::endl; sc_stop(); } wait(); diff --git a/rad-sim/example-designs/add/modules/client.cpp b/rad-sim/example-designs/add/modules/client.cpp index 36c3d89..f07743a 100644 --- a/rad-sim/example-designs/add/modules/client.cpp +++ b/rad-sim/example-designs/add/modules/client.cpp @@ -72,7 +72,6 @@ void client::Tick() { if (axis_client_interface.tvalid.read() && axis_client_interface.tready.read()) { - axis_client_interface.tvalid.write(false); client_tdata_fifo.pop(); std::cout << module_name << ": Sent Transaction!" << std::endl; } From 3bff40a0e2b98e538d1a899d4f523a4ae4861f23 Mon Sep 17 00:00:00 2001 From: George Trieu Date: Wed, 20 Sep 2023 15:01:32 -0400 Subject: [PATCH 3/4] changed DATAW to something smaller --- rad-sim/example-designs/add/modules/client.hpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rad-sim/example-designs/add/modules/client.hpp b/rad-sim/example-designs/add/modules/client.hpp index 88ff58d..c60d88f 100644 --- a/rad-sim/example-designs/add/modules/client.hpp +++ b/rad-sim/example-designs/add/modules/client.hpp @@ -9,7 +9,7 @@ #include #include -#define DATAW 512 +#define DATAW 128 class client : public radsim_module { private: From 81c73d1165449607f9a91ee30b78ad7a40a517fc Mon Sep 17 00:00:00 2001 From: George Trieu Date: Mon, 2 Oct 2023 15:09:30 -0400 Subject: [PATCH 4/4] Changed verification of design to be performed in the sink thread - Add Example --- rad-sim/example-designs/add/add_driver.cpp | 12 ++++++++++++ rad-sim/example-designs/add/add_driver.hpp | 3 +++ rad-sim/example-designs/add/add_system.cpp | 4 ++++ rad-sim/example-designs/add/add_system.hpp | 2 ++ rad-sim/example-designs/add/add_top.cpp | 2 ++ rad-sim/example-designs/add/add_top.hpp | 2 ++ rad-sim/example-designs/add/modules/adder.cpp | 6 ++++-- rad-sim/example-designs/add/modules/adder.hpp | 2 ++ 8 files changed, 31 insertions(+), 2 deletions(-) diff --git a/rad-sim/example-designs/add/add_driver.cpp b/rad-sim/example-designs/add/add_driver.cpp index 911a69d..388f289 100644 --- a/rad-sim/example-designs/add/add_driver.cpp +++ b/rad-sim/example-designs/add/add_driver.cpp @@ -7,6 +7,7 @@ add_driver::add_driver(const sc_module_name &name) // Random Seed srand (time(NULL)); + actual_sum = 0; // Generate random numbers to be added together by the adder std::cout << "Generating Random Numbers to be added ..." << std::endl; @@ -14,6 +15,7 @@ add_driver::add_driver(const sc_module_name &name) unsigned int r_num = std::rand() % 10 + 1; std::cout << r_num << " "; numbers_to_send.push(r_num); + actual_sum += r_num; } std::cout << std::endl << "----------------------------------------" << std::endl; @@ -48,4 +50,14 @@ void add_driver::source() { } void add_driver::sink() { + while (!response_valid.read()) { + wait(); + } + std::cout << "Received " << response.read().to_uint64() << " sum from the adder!" << std::endl; + std::cout << "The actual sum is " << actual_sum << std::endl; + + if (response.read() != actual_sum) std::cout << "FAILURE - Output is not matching!" << std::endl; + else std::cout << "SUCCESS - Output is matching!" << std::endl; + + sc_stop(); } \ No newline at end of file diff --git a/rad-sim/example-designs/add/add_driver.hpp b/rad-sim/example-designs/add/add_driver.hpp index 53768ea..baae941 100644 --- a/rad-sim/example-designs/add/add_driver.hpp +++ b/rad-sim/example-designs/add/add_driver.hpp @@ -11,6 +11,7 @@ class add_driver : public sc_module { private: std::queue numbers_to_send; + int actual_sum; public: sc_in clk; @@ -19,6 +20,8 @@ class add_driver : public sc_module { sc_out client_tlast; sc_out client_valid; sc_in client_ready; + sc_in> response; + sc_in response_valid; add_driver(const sc_module_name &name); ~add_driver(); diff --git a/rad-sim/example-designs/add/add_system.cpp b/rad-sim/example-designs/add/add_system.cpp index 26a9f10..faec250 100644 --- a/rad-sim/example-designs/add/add_system.cpp +++ b/rad-sim/example-designs/add/add_system.cpp @@ -11,6 +11,8 @@ add_system::add_system(const sc_module_name &name, sc_clock *driver_clk_sig) driver_inst->client_tlast(client_tlast_sig); driver_inst->client_valid(client_valid_sig); driver_inst->client_ready(client_ready_sig); + driver_inst->response(response_sig); + driver_inst->response_valid(response_valid_sig); // Instantiate design top-level dut_inst = new add_top("dut"); @@ -19,6 +21,8 @@ add_system::add_system(const sc_module_name &name, sc_clock *driver_clk_sig) dut_inst->client_tlast(client_tlast_sig); dut_inst->client_valid(client_valid_sig); dut_inst->client_ready(client_ready_sig); + dut_inst->response(response_sig); + dut_inst->response_valid(response_valid_sig); } add_system::~add_system() { diff --git a/rad-sim/example-designs/add/add_system.hpp b/rad-sim/example-designs/add/add_system.hpp index 8207d43..6911498 100644 --- a/rad-sim/example-designs/add/add_system.hpp +++ b/rad-sim/example-designs/add/add_system.hpp @@ -11,6 +11,8 @@ class add_system : public sc_module { sc_signal client_tlast_sig; sc_signal client_valid_sig; sc_signal client_ready_sig; + sc_signal> response_sig; + sc_signal response_valid_sig; public: sc_signal rst_sig; diff --git a/rad-sim/example-designs/add/add_top.cpp b/rad-sim/example-designs/add/add_top.cpp index 9e5cf63..d20fe63 100644 --- a/rad-sim/example-designs/add/add_top.cpp +++ b/rad-sim/example-designs/add/add_top.cpp @@ -20,6 +20,8 @@ add_top::add_top(const sc_module_name &name) std::strcpy(module_name, module_name_str.c_str()); adder_inst = new adder(module_name); adder_inst->rst(rst); + adder_inst->response(response); + adder_inst->response_valid(response_valid); radsim_design.BuildDesignContext("add.place", "add.clks"); diff --git a/rad-sim/example-designs/add/add_top.hpp b/rad-sim/example-designs/add/add_top.hpp index d15e44a..23a51fb 100644 --- a/rad-sim/example-designs/add/add_top.hpp +++ b/rad-sim/example-designs/add/add_top.hpp @@ -18,6 +18,8 @@ class add_top : public sc_module { sc_in client_tlast; sc_in client_valid; sc_out client_ready; + sc_out> response; + sc_out response_valid; add_top(const sc_module_name &name); ~add_top(); diff --git a/rad-sim/example-designs/add/modules/adder.cpp b/rad-sim/example-designs/add/modules/adder.cpp index 48fa6ea..dc48ae7 100644 --- a/rad-sim/example-designs/add/modules/adder.cpp +++ b/rad-sim/example-designs/add/modules/adder.cpp @@ -28,6 +28,8 @@ void adder::Assign() { } void adder::Tick() { + response_valid.write(0); + response.write(0); wait(); // Always @ positive edge of the clock @@ -46,8 +48,8 @@ void adder::Tick() { // Print Sum and Exit if (t_finished.read()) { - std::cout << module_name << ": The final sum of all the addends in the transactions is: " << adder_rolling_sum.to_uint64() << std::endl; - sc_stop(); + response_valid.write(1); + response.write(adder_rolling_sum); } wait(); } diff --git a/rad-sim/example-designs/add/modules/adder.hpp b/rad-sim/example-designs/add/modules/adder.hpp index aedafa3..dbc2e67 100644 --- a/rad-sim/example-designs/add/modules/adder.hpp +++ b/rad-sim/example-designs/add/modules/adder.hpp @@ -17,6 +17,8 @@ class adder : public radsim_module { public: sc_in rst; + sc_out response_valid; + sc_out> response; // Interface to the NoC axis_slave_port axis_adder_interface;