diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/i3c_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/i3c_regs.h
index 04f5a56075b..02d2f94eae4 100644
--- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/i3c_regs.h
+++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/i3c_regs.h
@@ -864,9 +864,27 @@ typedef struct {
#define MXC_F_I3C_TARG_CAP1_CCCH_POS 12 /**< TARG_CAP1_CCCH Position */
#define MXC_F_I3C_TARG_CAP1_CCCH ((uint32_t)(0xFUL << MXC_F_I3C_TARG_CAP1_CCCH_POS)) /**< TARG_CAP1_CCCH Mask */
+#define MXC_V_I3C_TARG_CAP1_CCCH_BASIC ((uint32_t)0x1UL) /**< TARG_CAP1_CCCH_BASIC Value */
+#define MXC_S_I3C_TARG_CAP1_CCCH_BASIC (MXC_V_I3C_TARG_CAP1_CCCH_BASIC << MXC_F_I3C_TARG_CAP1_CCCH_POS) /**< TARG_CAP1_CCCH_BASIC Setting */
+#define MXC_V_I3C_TARG_CAP1_CCCH_LIMITS ((uint32_t)0x2UL) /**< TARG_CAP1_CCCH_LIMITS Value */
+#define MXC_S_I3C_TARG_CAP1_CCCH_LIMITS (MXC_V_I3C_TARG_CAP1_CCCH_LIMITS << MXC_F_I3C_TARG_CAP1_CCCH_POS) /**< TARG_CAP1_CCCH_LIMITS Setting */
+#define MXC_V_I3C_TARG_CAP1_CCCH_INTACT ((uint32_t)0x4UL) /**< TARG_CAP1_CCCH_INTACT Value */
+#define MXC_S_I3C_TARG_CAP1_CCCH_INTACT (MXC_V_I3C_TARG_CAP1_CCCH_INTACT << MXC_F_I3C_TARG_CAP1_CCCH_POS) /**< TARG_CAP1_CCCH_INTACT Setting */
+#define MXC_V_I3C_TARG_CAP1_CCCH_VENDOR ((uint32_t)0x8UL) /**< TARG_CAP1_CCCH_VENDOR Value */
+#define MXC_S_I3C_TARG_CAP1_CCCH_VENDOR (MXC_V_I3C_TARG_CAP1_CCCH_VENDOR << MXC_F_I3C_TARG_CAP1_CCCH_POS) /**< TARG_CAP1_CCCH_VENDOR Setting */
#define MXC_F_I3C_TARG_CAP1_IBI_EVENTS_POS 16 /**< TARG_CAP1_IBI_EVENTS Position */
#define MXC_F_I3C_TARG_CAP1_IBI_EVENTS ((uint32_t)(0x1FUL << MXC_F_I3C_TARG_CAP1_IBI_EVENTS_POS)) /**< TARG_CAP1_IBI_EVENTS Mask */
+#define MXC_V_I3C_TARG_CAP1_IBI_EVENTS_IBI ((uint32_t)0x1UL) /**< TARG_CAP1_IBI_EVENTS_IBI Value */
+#define MXC_S_I3C_TARG_CAP1_IBI_EVENTS_IBI (MXC_V_I3C_TARG_CAP1_IBI_EVENTS_IBI << MXC_F_I3C_TARG_CAP1_IBI_EVENTS_POS) /**< TARG_CAP1_IBI_EVENTS_IBI Setting */
+#define MXC_V_I3C_TARG_CAP1_IBI_EVENTS_PAYLOAD ((uint32_t)0x2UL) /**< TARG_CAP1_IBI_EVENTS_PAYLOAD Value */
+#define MXC_S_I3C_TARG_CAP1_IBI_EVENTS_PAYLOAD (MXC_V_I3C_TARG_CAP1_IBI_EVENTS_PAYLOAD << MXC_F_I3C_TARG_CAP1_IBI_EVENTS_POS) /**< TARG_CAP1_IBI_EVENTS_PAYLOAD Setting */
+#define MXC_V_I3C_TARG_CAP1_IBI_EVENTS_CONTREQ ((uint32_t)0x4UL) /**< TARG_CAP1_IBI_EVENTS_CONTREQ Value */
+#define MXC_S_I3C_TARG_CAP1_IBI_EVENTS_CONTREQ (MXC_V_I3C_TARG_CAP1_IBI_EVENTS_CONTREQ << MXC_F_I3C_TARG_CAP1_IBI_EVENTS_POS) /**< TARG_CAP1_IBI_EVENTS_CONTREQ Setting */
+#define MXC_V_I3C_TARG_CAP1_IBI_EVENTS_HJ ((uint32_t)0x8UL) /**< TARG_CAP1_IBI_EVENTS_HJ Value */
+#define MXC_S_I3C_TARG_CAP1_IBI_EVENTS_HJ (MXC_V_I3C_TARG_CAP1_IBI_EVENTS_HJ << MXC_F_I3C_TARG_CAP1_IBI_EVENTS_POS) /**< TARG_CAP1_IBI_EVENTS_HJ Setting */
+#define MXC_V_I3C_TARG_CAP1_IBI_EVENTS_BAMATCH ((uint32_t)0x10UL) /**< TARG_CAP1_IBI_EVENTS_BAMATCH Value */
+#define MXC_S_I3C_TARG_CAP1_IBI_EVENTS_BAMATCH (MXC_V_I3C_TARG_CAP1_IBI_EVENTS_BAMATCH << MXC_F_I3C_TARG_CAP1_IBI_EVENTS_POS) /**< TARG_CAP1_IBI_EVENTS_BAMATCH Setting */
#define MXC_F_I3C_TARG_CAP1_TIMECTRL_POS 21 /**< TARG_CAP1_TIMECTRL Position */
#define MXC_F_I3C_TARG_CAP1_TIMECTRL ((uint32_t)(0x1UL << MXC_F_I3C_TARG_CAP1_TIMECTRL_POS)) /**< TARG_CAP1_TIMECTRL Mask */
@@ -1066,9 +1084,9 @@ typedef struct {
#define MXC_S_I3C_CONT_STATUS_IBITYPE_NONE (MXC_V_I3C_CONT_STATUS_IBITYPE_NONE << MXC_F_I3C_CONT_STATUS_IBITYPE_POS) /**< CONT_STATUS_IBITYPE_NONE Setting */
#define MXC_V_I3C_CONT_STATUS_IBITYPE_IBI ((uint32_t)0x1UL) /**< CONT_STATUS_IBITYPE_IBI Value */
#define MXC_S_I3C_CONT_STATUS_IBITYPE_IBI (MXC_V_I3C_CONT_STATUS_IBITYPE_IBI << MXC_F_I3C_CONT_STATUS_IBITYPE_POS) /**< CONT_STATUS_IBITYPE_IBI Setting */
-#define MXC_V_I3C_CONT_STATUS_IBITYPE_CONT_REQ ((uint32_t)0x1UL) /**< CONT_STATUS_IBITYPE_CONT_REQ Value */
+#define MXC_V_I3C_CONT_STATUS_IBITYPE_CONT_REQ ((uint32_t)0x2UL) /**< CONT_STATUS_IBITYPE_CONT_REQ Value */
#define MXC_S_I3C_CONT_STATUS_IBITYPE_CONT_REQ (MXC_V_I3C_CONT_STATUS_IBITYPE_CONT_REQ << MXC_F_I3C_CONT_STATUS_IBITYPE_POS) /**< CONT_STATUS_IBITYPE_CONT_REQ Setting */
-#define MXC_V_I3C_CONT_STATUS_IBITYPE_HOTJOIN_REQ ((uint32_t)0x1UL) /**< CONT_STATUS_IBITYPE_HOTJOIN_REQ Value */
+#define MXC_V_I3C_CONT_STATUS_IBITYPE_HOTJOIN_REQ ((uint32_t)0x3UL) /**< CONT_STATUS_IBITYPE_HOTJOIN_REQ Value */
#define MXC_S_I3C_CONT_STATUS_IBITYPE_HOTJOIN_REQ (MXC_V_I3C_CONT_STATUS_IBITYPE_HOTJOIN_REQ << MXC_F_I3C_CONT_STATUS_IBITYPE_POS) /**< CONT_STATUS_IBITYPE_HOTJOIN_REQ Setting */
#define MXC_F_I3C_CONT_STATUS_TARG_START_POS 8 /**< CONT_STATUS_TARG_START Position */
diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h
index d387642d9e3..dd3a4ed134e 100644
--- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h
+++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h
@@ -629,6 +629,7 @@ We may want to handle GET_IRQ better...
/******************************************************************************/
/* I3C */
+#define MXC_CFG_I3C_INSTANCES (1)
#define MXC_I3C_FIFO_DEPTH (8)
/* Non-secure Mapping */
@@ -647,6 +648,11 @@ We may want to handle GET_IRQ better...
#define MXC_I3C MXC_I3C_NS
#endif
+#define MXC_I3C_GET_BASE(i) ((i) == 0 ? MXC_BASE_I3C : 0)
+#define MXC_I3C_GET_I3C(i) ((i) == 0 ? MXC_I3C : 0)
+#define MXC_I3C_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I3C_IRQn : 0)
+#define MXC_I3C_GET_IDX(p) ((p) == MXC_I3C_NS ? 0 : (p) == MXC_I3C_S ? 0 : -1)
+
/******************************************************************************/
/* DMA */
#define MXC_DMA_CHANNELS (4)
diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd
index 78400b6907e..818e55ed644 100644
--- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd
+++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd
@@ -4865,11 +4865,60 @@
CCCH
CCC Handled by IP.
[15:12]
+
+
+ BASIC
+ Basic CCCs.
+ 1
+
+
+ LIMITS
+ CCCs related to maximum transfer lengths and speed.
+ 2
+
+
+ INTACT
+ Pending Interrupt and Activity Mode fields of GETSTATUS CCC.
+ 4
+
+
+ VENDOR
+ Vendor Reserved field of GETSTATUS CCC.
+ 8
+
+
IBI_EVENTS
Supported IBI events.
[20:16]
+
+
+ IBI
+ IBI support.
+ 1
+
+
+ PAYLOAD
+ IBI has payload.
+ 2
+
+
+ CONTREQ
+ Controller request support.
+ 4
+
+
+ HJ
+ Hot-Join support.
+ 8
+
+
+ BAMATCH
+ Use BAMATCH field of CONFIG register to measure 1us Bus Available timing.
+ 16
+
+
TIMECTRL
@@ -5234,12 +5283,12 @@
CONT_REQ
Controller request.
- 1
+ 2
HOTJOIN_REQ
Hot-Join request.
- 1
+ 3
@@ -12060,4 +12109,4 @@
-
\ No newline at end of file
+
diff --git a/Libraries/PeriphDrivers/Include/MAX32657/i3c.h b/Libraries/PeriphDrivers/Include/MAX32657/i3c.h
new file mode 100644
index 00000000000..95a592f4693
--- /dev/null
+++ b/Libraries/PeriphDrivers/Include/MAX32657/i3c.h
@@ -0,0 +1,646 @@
+/**
+* @file i3c.h
+* @brief Improved Inter Integrated Circuit (I3C) communications interface driver.
+*/
+
+/******************************************************************************
+ *
+ * Copyright (C) 2024 Analog Devices, Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************/
+
+/* Define to prevent redundant inclusion */
+#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_I3C_H_
+#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_I3C_H_
+
+#include
+#include
+#include "mxc_sys.h"
+#include "i3c_regs.h"
+#include "dma_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup i3c I3C
+ * @ingroup periphlibs
+ * @{
+ */
+
+/***** Definitions *****/
+
+/**
+ * @brief Maximum supported IBI bytes.
+ *
+ */
+#define MXC_I3C_MAX_IBI_BYTES 7U
+
+/**
+ * @brief Invalid I2C/I3C address.
+ *
+ */
+#define MXC_I3C_ADDR_INVALID 0U
+
+typedef struct _i3c_ccc_req_t mxc_i3c_ccc_req_t;
+typedef struct _i3c_req_t mxc_i3c_req_t;
+
+/**
+ * @brief The list of high-keeper options.
+ *
+ * This setting should match the high-keeper implementation of the device.
+ */
+typedef enum {
+ MXC_I3C_HIGH_KEEPER_OFF = MXC_S_I3C_CONT_CTRL0_HKEEP_OFF, ///< No high-keeper support
+ MXC_I3C_HIGH_KEEPER_ON_CHIP = MXC_S_I3C_CONT_CTRL0_HKEEP_ON_CHIP, ///< SCL and SDA pads
+ ///< have weak pull-ups
+ MXC_I3C_HIGH_KEEPER_EXT_SDA = MXC_S_I3C_CONT_CTRL0_HKEEP_EXT_SDA, ///< External high-keeper
+ ///< support for SDA signal
+ MXC_I3C_HIGH_KEEPER_EXT_SCL_SDA = MXC_S_I3C_CONT_CTRL0_HKEEP_EXT_SCL_SDA,
+ ///< External high-keeper support for SCL and SDA signals
+} mxc_i3c_high_keeper_t;
+
+/**
+ * @brief The list of receive FIFO trigger levels.
+ */
+typedef enum {
+ MXC_I3C_RX_TH_NOT_EMPTY = MXC_V_I3C_CONT_FIFOCTRL_RX_THD_LVL_NOT_EMPTY, ///<
+ MXC_I3C_RX_TH_QUARTER_FULL = MXC_V_I3C_CONT_FIFOCTRL_RX_THD_LVL_QUARTER_FULL, ///<
+ MXC_I3C_RX_TH_HALF_FULL = MXC_V_I3C_CONT_FIFOCTRL_RX_THD_LVL_HALF_FULL, ///<
+ MXC_I3C_RX_TH_3_4_FULL = MXC_V_I3C_CONT_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL, ///<
+} mxc_i3c_rx_threshold_t;
+
+/**
+ * @brief The list of transmit FIFO trigger levels.
+ */
+typedef enum {
+ MXC_I3C_TX_TH_EMPTY = MXC_V_I3C_CONT_FIFOCTRL_TX_THD_LVL_EMPTY, ///<
+ MXC_I3C_TX_TH_QUARTER_FULL = MXC_V_I3C_CONT_FIFOCTRL_TX_THD_LVL_QUARTER_FULL, ///<
+ MXC_I3C_TX_TH_HALF_FULL = MXC_V_I3C_CONT_FIFOCTRL_TX_THD_LVL_HALF_FULL, ///<
+ MXC_I3C_TX_TH_ALMOST_FULL = MXC_V_I3C_CONT_FIFOCTRL_TX_THD_LVL_ALMOST_FULL, ///<
+} mxc_i3c_tx_threshold_t;
+
+/**
+ * @brief Transfer type enumeration.
+ *
+ */
+typedef enum {
+ MXC_I3C_TRANSFER_TYPE_READ = 0,
+ MXC_I3C_TRANSFER_TYPE_WRITE = 1
+} mxc_i3c_transfer_type_t;
+
+/**
+ * @brief IBI types.
+ *
+ */
+typedef enum {
+ MXC_I3C_IBI_TYPE_NONE = MXC_V_I3C_CONT_STATUS_IBITYPE_NONE, ///<
+ MXC_I3C_IBI_TYPE_IBI = MXC_V_I3C_CONT_STATUS_IBITYPE_IBI, ///<
+ MXC_I3C_IBI_TYPE_CONTROLLER_REQ = MXC_V_I3C_CONT_STATUS_IBITYPE_CONT_REQ, ///<
+ MXC_I3C_IBI_TYPE_HOTJOIN_REQ = MXC_V_I3C_CONT_STATUS_IBITYPE_HOTJOIN_REQ, ///<
+} mxc_i3c_ibi_type_t;
+
+/* CCC request flags */
+#define MXC_I3C_CCC_HAS_DEFINING_BYTE (1U << 0)
+#define MXC_I3C_CCC_HAS_SUB_COMMAND (1U << 1)
+#define MXC_I3C_CCC_HAS_DATA (1U << 2)
+
+/**
+ * @brief I3C configuration options used during initialization.
+ *
+ */
+typedef struct {
+ bool target_mode; ///< If the driver should be initialized in target mode.
+ uint8_t static_addr; ///< Static address to use if target mode is used.
+ uint32_t pp_hz; ///< SCL frequency to be used in push-pull operation.
+ uint32_t od_hz; ///< SCL frequency to be used in open-drain operation.
+ uint32_t i2c_hz; ///< SCL frequency to be used in I2C operation.
+} mxc_i3c_config_t;
+
+/**
+ * @brief Common Command Code request structure.
+ *
+ * Broadcast and direct commands are distinguished by MSB, i.e. if MSB being set
+ * implies a direct CCC while MSB being 0 implies a broadcast CCC.
+ *
+ */
+struct _i3c_ccc_req_t {
+ uint8_t ccc; ///< CCC command to send.
+ uint8_t target_addr; ///< Target address if CCC is a direct command. Ignored
+ ///< if CCC is a broadcast command.
+ mxc_i3c_transfer_type_t xfer_type; ///< Transfer type. Ignored for broadcast CCCs.
+ uint8_t flags; ///< See request flags above.
+ uint8_t def_byte; ///< Optional defining byte. Defined by CCC.
+ uint8_t sub_cmd; ///< Optional sub-command. Defined by CCC. Only used by direct
+ ///< CCCs.
+ unsigned char *tx_buf; ///< Optional data bytes to send.
+ uint8_t tx_len; ///< Length of optional data.
+ unsigned char *rx_buf; ///< Optional data bytes to read.
+ uint8_t rx_len; ///< Length of optional data.
+};
+
+/**
+ * @brief Private SDR request structure.
+ *
+ * SDR read and write to an I3C target.
+ *
+ */
+struct _i3c_req_t {
+ uint8_t target_addr; ///< Target address.
+ bool is_i2c; ///< If this is a legacy I2C transfer.
+ bool stop; ///< Send a STOP after the transaction.
+ unsigned char *tx_buf; ///< Optional data bytes to send.
+ uint16_t tx_len; ///< Length of optional data.
+ unsigned char *rx_buf; ///< Optional data bytes to read.
+ uint16_t rx_len; ///< Length of optional data.
+};
+
+/**
+ * @brief IBI payload request callback. Write additional byte to \a byte.
+ *
+ * This function will be called as long as non-zero is returned.
+ *
+ * @return Non-zero if a byte is written to \a byte, 0 to indicate no more additional
+ * bytes left to send.
+ */
+typedef int (*mxc_i3c_ibi_getbyte_t)(mxc_i3c_regs_t *i3c, unsigned char *byte);
+
+/***** Function Prototypes *****/
+
+/* ************************************************************************* */
+/* Control/Configuration functions */
+/* ************************************************************************* */
+
+/**
+ * @brief Initialize and enable I3C peripheral.
+ *
+ * @note On default this function enables I3C peripheral clock and I3C gpio pins.
+ * If you wish to skip clock and gpio initialization, define MSDK_NO_GPIO_CLK_INIT
+ * flag in project.mk file.
+ *
+ * @param i3c Pointer to I3C registers (selects the I3C block used).
+ * @param config Config options. See \ref mxc_i3c_config_t for details.
+ *
+ * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_I3C_Init(mxc_i3c_regs_t *i3c, mxc_i3c_config_t *config);
+
+/**
+ * @brief Recover I3C bus if necessary. Should only be used in controller mode.
+ *
+ * @param i3c Pointer to I3C registers.
+ * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_I3C_Recover(mxc_i3c_regs_t *i3c);
+
+/**
+ * @brief Disable and shutdown I3C peripheral.
+ *
+ * @param i3c Pointer to I3C registers.
+ *
+ * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_I3C_Shutdown(mxc_i3c_regs_t *i3c);
+
+/**
+ * @brief Sets the SCL frequency for I3C push-pull operation.
+ *
+ * Recommended value for push-pull frequency is fclk / 2, where fclk is the I3C
+ * peripheral clock. Note that I3C supports a maximum frequency of 12.5MHz.
+ * Should only be used in controller mode.
+ *
+ * @param i3c Pointer to I3C registers (selects the I3C block used).
+ * @param frequency Frequency in hertz.
+ *
+ * @return Negative if error, otherwise actual speed set. See \ref
+ * MXC_Error_Codes for the list of error return codes.
+ */
+int MXC_I3C_SetPPFrequency(mxc_i3c_regs_t *i3c, unsigned int frequency);
+
+/**
+ * @brief Get the frequency of the I3C push-pull mode. Should only be used in
+ * controller mode.
+ *
+ * @param i3c Pointer to I3C registers.
+ *
+ * @return The I3C push-pull frequency in hertz.
+ */
+unsigned int MXC_I3C_GetPPFrequency(mxc_i3c_regs_t *i3c);
+
+/**
+ * @brief Sets the SCL frequency for I3C open-drain operation.
+ *
+ * Note that open-drain SCL also depends on push-pull SCL settings. See
+ * MXC_I3C_SetPPFrequency(). Should only be used in controller mode.
+ *
+ * @param i3c Pointer to I3C registers (selects the I3C block used).
+ * @param frequency Frequency in hertz.
+ * @param highPP Set SCL high period to high period in push-pull mode.
+ * This is used to prevent legacy I2C devices from detecting
+ * I3C messages.
+ * @return Negative if error, otherwise actual speed set. See \ref
+ * MXC_Error_Codes for the list of error return codes.
+ */
+int MXC_I3C_SetODFrequency(mxc_i3c_regs_t *i3c, unsigned int frequency, bool highPP);
+
+/**
+ * @brief Get the frequency of the I3C open-drain mode. Should only be used in
+ * controller mode.
+ *
+ * @param i3c Pointer to I3C registers.
+ *
+ * @return The I3C open-drain frequency in hertz.
+ */
+unsigned int MXC_I3C_GetODFrequency(mxc_i3c_regs_t *i3c);
+
+/**
+ * @brief Sets the SCL frequency for I2C mode. Should only be used in controller mode.
+ *
+ * @param i3c Pointer to I3C registers (selects the I3C block used).
+ * @param frequency Frequency in hertz.
+ *
+ * @return Negative if error, otherwise actual speed set. See \ref
+ * MXC_Error_Codes for the list of error return codes.
+ */
+int MXC_I3C_SetI2CFrequency(mxc_i3c_regs_t *i3c, unsigned int frequency);
+
+/**
+ * @brief Get the frequency of the I3C in I2C mode. Should only be used in controller
+ * mode.
+ *
+ * @param i3c Pointer to I3C registers.
+ *
+ * @return The frequency of I2C mode in hertz.
+ */
+unsigned int MXC_I3C_GetI2CFrequency(mxc_i3c_regs_t *i3c);
+
+/**
+ * @brief Sets the skew value for I3C push-pull operation.
+ *
+ * Note that this setting requires peripheral clock (fclk) to SCL ratio to be at
+ * least 4. See MXC_I3C_SetPPFrequency(). Should only be used in controller mode.
+ *
+ * @param i3c Pointer to I3C registers (selects the I3C block used).
+ * @param skew Skew value in units of peripheral clock cycles. Cannot
+ * be greater than 7.
+ *
+ * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_I3C_SetSkew(mxc_i3c_regs_t *i3c, uint8_t skew);
+
+/**
+ * @brief Sets the high-keeper implementation for the device. Should only be used
+ * in controller mode.
+ *
+ * See \ref mxc_i3c_high_keeper_t.
+ *
+ * @param i3c Pointer to I3C registers (selects the I3C block used).
+ * @param hkeep High-keeper option.
+ *
+ * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_I3C_SetHighKeeperMode(mxc_i3c_regs_t *i3c, mxc_i3c_high_keeper_t hkeep);
+
+/**
+ * @brief Emit an I2C or I3C start in controller mode.
+ *
+ * @param i3c Pointer to I3C registers.
+ * @param isI2C True if I2C, false if I3C.
+ * @param xferType Transfer type. See \ref mxc_i3c_transfer_type_t.
+ * @param addr Target address.
+ * @param readCount Number of bytes to read if this is a read message.
+ *
+ * @return Success/Fail. E_SUCCESS if request is successful, E_BUSY if an IBI occurrs,
+ * one of \ref MXC_Error_Codes otherwise.
+ */
+int MXC_I3C_EmitStart(mxc_i3c_regs_t *i3c, bool isI2C, mxc_i3c_transfer_type_t xferType,
+ uint8_t addr, uint8_t readCount);
+
+/**
+ * @brief Emit an I3C target reset pattern in controller mode.
+ *
+ * @param i3c Pointer to I3C registers.
+ *
+ * @return Success/Fail. See \ref MXC_Error_Codes for possible return codes.
+ */
+int MXC_I3C_ResetTarget(mxc_i3c_regs_t *i3c);
+
+/**
+ * @brief Emit an I2C STOP in controller mode.
+ *
+ * @param i3c Pointer to I3C registers.
+ */
+void MXC_I3C_EmitI2CStop(mxc_i3c_regs_t *i3c);
+
+/**
+ * @brief Emit an I3C STOP in controller mode.
+ *
+ * @param i3c Pointer to I3C registers.
+ */
+void MXC_I3C_EmitStop(mxc_i3c_regs_t *i3c);
+
+/**
+ * @brief Send or broadcast a Common Command Code (CCC).
+ *
+ * @param i3c Pointer to I3C registers.
+ * @param req CCC request data.
+ *
+ * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_I3C_Controller_CCC(mxc_i3c_regs_t *i3c, const mxc_i3c_ccc_req_t *req);
+
+/**
+ * @brief Perform a private SDR or a legacy I2C transfer.
+ *
+ * @param i3c Pointer to I3C registers.
+ * @param req Request data.
+ *
+ * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_I3C_Controller_Transaction(mxc_i3c_regs_t *i3c, const mxc_i3c_req_t *req);
+
+/**
+ * @brief Start dynamic address assignment.
+ *
+ * If E_SUCCESS is returned, PID, BCR and DCR are read into their corresponding buffers.
+ * Call MXC_I3C_ControllerDAA again with a valid \a addr to assign a dynamic address to
+ * the target and read PID, BCR and DCR of the next target. If E_SHUTDOWN is returned,
+ * DAA process is complete
+ *
+ * @param i3c Pointer to I3C registers.
+ * @param pid Buffer to store provisioned ID of a target.
+ * @param bcr Buffer to store Bus Characteristics Register of a target.
+ * @param dcr Buffer to store Device Characteristics Register of a target.
+ *
+ * @return Success/Fail, E_SUCCESS if request is successful, E_SHUTDOWN if DAA is
+ * finished, E_FAIL if an error occurs during DAA, one of \ref MXC_Error_Codes
+ * otherwise.
+ */
+int MXC_I3C_Controller_DAA(mxc_i3c_regs_t *i3c, uint8_t addr, uint8_t *pid, uint8_t *bcr,
+ uint8_t *dcr);
+
+/**
+ * @brief Generate a hot-join request in target mode.
+ *
+ * Hot-Join will only be generated if the target is powered on after the bus is
+ * configured or physically connected to an already configured bus. If the active
+ * controller disables the Hot-Join events through DISEC CCCs, it will not be
+ * generated either.
+ *
+ * @param i3c Pointer to I3C registers.
+ *
+ * @return E_SUCCESS if request is submitted. E_BAD_STATE if operation is not allowed in
+ * the current state. E_NOT_SUPPORTED is returned in case HotJoin generation is not
+ * supported. Note that return value of E_SUCCESS does not guarantee a successful
+ * Hot-Join since the decision is up to the controller.
+ */
+int MXC_I3C_HotJoin(mxc_i3c_regs_t *i3c);
+
+/**
+ * @brief Generate an In-Band Interrupt in target mode.
+ *
+ * @param i3c Pointer to I3C registers.
+ * @param mdb Mandatory data byte to be sent if IBI is acknowledged.
+ * @param getByteCb Callback to get additional databytes from the application. Pass NULL
+ * if no additional data bytes except \a mdb will be sent with the IBI
+ * request.
+ *
+ * @return E_SUCCESS if request is submitted. E_BAD_STATE if operation is not allowed in
+ * the current state. E_NOT_SUPPORTED is returned in case IBI generation is not
+ * supported. Note that return value of E_SUCCESS does not guarantee that the
+ * request has been acknowledged.
+ */
+int MXC_I3C_RequestIBI(mxc_i3c_regs_t *i3c, unsigned char mdb, mxc_i3c_ibi_getbyte_t getByteCb);
+
+/**
+ * @brief Enter offline mode and stop participating on the bus. Valid only in target mode.
+ *
+ * Offline mode is only allowed if the target has already been assigned a dynamic address.
+ *
+ * @param i3c Pointer to I3C registers.
+ *
+ * @return E_SUCCESS if device switches to offline mode, E_BAD_STATE otherwise.
+ */
+int MXC_I3C_Standby(mxc_i3c_regs_t *i3c);
+
+/**
+ * @brief Exit offline mode using previously assigned dynamic address. Valid only in
+ * target mode.
+ *
+ * @param i3c Pointer to I3C registers.
+ *
+ * @return E_SUCCESS if device comes out of offline mode, E_BAD_STATE otherwise.
+ */
+int MXC_I3C_Wakeup(mxc_i3c_regs_t *i3c);
+
+/**
+ * @brief Unloads bytes from the receive FIFO. Both controller and target mode can
+ * use this function to read the receive FIFO.
+ *
+ * @param i3c Pointer to I3C registers.
+ * @param bytes The buffer to read the data into.
+ * @param len The number of bytes to read.
+ * @param timeout Timeout in microseconds to wait. Use -1 to wait indefinitely.
+ *
+ * @return The number of bytes actually read.
+ */
+int MXC_I3C_ReadRXFIFO(mxc_i3c_regs_t *i3c, volatile unsigned char *bytes, unsigned int len,
+ int timeout);
+
+/**
+ * @brief Loads bytes into the transmit FIFO. Both controller and target mode can
+ * use this function to write into the transmit FIFO.
+ *
+ * @param i2c Pointer to I3C registers.
+ * @param bytes The buffer containing the bytes to write.
+ * @param len The number of bytes to write.
+ * @param end If set to true, last byte in \a bytes is marked as end-of-data.
+ * @param timeout Timeout in microseconds to wait. Use -1 to wait indefinitely.
+ *
+ * @return The number of bytes actually written.
+ */
+int MXC_I3C_WriteTXFIFO(mxc_i3c_regs_t *i3c, const unsigned char *bytes, unsigned int len, bool end,
+ int timeout);
+
+/**
+ * @brief Return the current error code if any.
+ *
+ * @param i3c Pointer to I3C registers.
+ * @return E_NO_ERROR if no error found.
+ * E_NO_RESPONSE if request NACKed.
+ * E_ABORT if write aborted.
+ * E_BAD_STATE if request is invalid or a message mode error occurs.
+ * E_TIME_OUT if a timeout error occurred.
+ * E_OVERFLOW in case of read data underrun or write data overflow.
+ * E_FAIL otherwise.
+ */
+int MXC_I3C_Controller_GetError(mxc_i3c_regs_t *i3c);
+
+/**
+ * @brief Clear the error register.
+ *
+ * @param i3c Pointer to I3c registers.
+ */
+void MXC_I3C_Controller_ClearError(mxc_i3c_regs_t *i3c);
+
+/**
+ * @brief Set the transmit threshold level.
+ *
+ * When operating as a controller, the function sets the transmit threshold level
+ * for when the master should add additional bytes to the transmit FIFO. Can be used in
+ * both controller and target mode.
+ *
+ * @param i3c Pointer to I3C registers.
+ * @param rxth Receive threshold level to set. See \ref mxc_i3c_rx_threshold_t
+ * for available options.
+ * @param txth Transmit threshold level to set. See \ref mxc_i3c_tx_threshold_t
+ * for available options.
+ *
+ * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.
+ */
+int MXC_I3C_SetRXTXThreshold(mxc_i3c_regs_t *i3c, mxc_i3c_rx_threshold_t rxth,
+ mxc_i3c_tx_threshold_t txth);
+
+/**
+ * @brief Returns the dynamic address in target mode.
+ *
+ * @param i3c Pointer to I3C registers.
+ *
+ * @return Dynamic address set by bus controller. If the address is invalid or
+ * device is not running in target mode, then 0 is returned.
+ */
+uint8_t MXC_I3C_GetDynamicAddress(mxc_i3c_regs_t *i3c);
+
+/**
+ * @brief Interrupt handler.
+ *
+ * @param i3c Pointer to I3C registers.
+ */
+void MXC_I3C_IRQHandler(mxc_i3c_regs_t *i3c);
+
+/**
+ * @brief Removes and discards all bytes currently in the receive FIFO. Valid in
+ * both controller and target mode.
+ *
+ * @param i3c Pointer to I3C registers.
+ */
+void MXC_I3C_ClearRXFIFO(mxc_i3c_regs_t *i3c);
+
+/**
+ * @brief Removes and discards all bytes currently in the transmit FIFO. Valid in
+ * both controller and target mode.
+ *
+ * @param i3c Pointer to I3C registers.
+ */
+void MXC_I3C_ClearTXFIFO(mxc_i3c_regs_t *i3c);
+
+/**
+ * @brief Return the number of bytes in receive buffer or FIFO.
+ *
+ * @param i3c Pointer to I3C registers.
+ *
+ * @return Number of bytes in receive buffer or FIFO.
+ */
+unsigned int MXC_I3C_Controller_GetRXCount(mxc_i3c_regs_t *i3c);
+
+/**
+ * @brief Return the number of bytes in transmit buffer or FIFO.
+ *
+ * @param i3c Pointer to I3C registers.
+ *
+ * @return Number of bytes in transmit buffer or FIFO.
+ */
+unsigned int MXC_I3C_Controller_GetTXCount(mxc_i3c_regs_t *i3c);
+
+/**
+ * @brief Enable controller interrupts.
+ *
+ * @param i3c Pointer to I3C registers.
+ * @param mask Interrupt mask to set.
+ */
+void MXC_I3C_Controller_EnableInt(mxc_i3c_regs_t *i3c, uint32_t mask);
+
+/**
+ * @brief Disable controller interrupts.
+ *
+ * @param i3c Pointer to I3C registers.
+ * @param mask Interrupt mask to set.
+ */
+void MXC_I3C_Controller_DisableInt(mxc_i3c_regs_t *i3c, uint32_t mask);
+
+/**
+ * @brief Get the presently set interrupt flags.
+ *
+ * @param i3c Pointer to I3C registers.
+ *
+ * @return See \ref MXC_Error_Codes for a list of return values.
+ */
+unsigned int MXC_I3C_Controller_GetFlags(mxc_i3c_regs_t *i3c);
+
+/**
+ * @brief Clear controller interrupts.
+ *
+ * Note that some bits cannot be cleared manually and self-clear only when their
+ * respective conditions occur.
+ *
+ * @param i3c Pointer to I3C registers.
+ * @param mask Interrupt mask to clear.
+ */
+void MXC_I3C_Controller_ClearFlags(mxc_i3c_regs_t *i3c, uint32_t mask);
+
+/**
+ * @brief Enable target interrupts.
+ *
+ * @param i3c Pointer to I3C registers.
+ * @param mask Interrupt mask to set.
+ */
+void MXC_I3C_Target_EnableInt(mxc_i3c_regs_t *i3c, uint32_t mask);
+
+/**
+ * @brief Disable target interrupts.
+ *
+ * @param i3c Pointer to I3C registers.
+ * @param mask Interrupt mask to set.
+ */
+void MXC_I3C_Target_DisableInt(mxc_i3c_regs_t *i3c, uint32_t mask);
+
+/**
+ * @brief Get the presently set target mode interrupt flags.
+ *
+ * @param i3c Pointer to I3C registers.
+ *
+ * @return See \ref MXC_Error_Codes for a list of return values.
+ */
+int MXC_I3C_Target_GetFlags(mxc_i3c_regs_t *i3c);
+
+/**
+ * @brief Clear target interrupts.
+ *
+ * Note that some bits cannot be cleared manually and self-clear only when their
+ * respective conditions occur.
+ *
+ * @param i3c Pointer to I3C registers.
+ * @param mask Interrupt mask to clear.
+ */
+void MXC_I3C_Target_ClearFlags(mxc_i3c_regs_t *i3c, uint32_t mask);
+
+/**@} end of group i3c */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_I3C_H_
diff --git a/Libraries/PeriphDrivers/Source/I3C/i3c_ccc.h b/Libraries/PeriphDrivers/Source/I3C/i3c_ccc.h
new file mode 100644
index 00000000000..6bc3ba139a8
--- /dev/null
+++ b/Libraries/PeriphDrivers/Source/I3C/i3c_ccc.h
@@ -0,0 +1,88 @@
+/**
+* @file i3c_ccc.h
+* @brief Improved Inter Integrated Circuit (I3C) Common Command Codes (CCC).
+*/
+
+/******************************************************************************
+ *
+ * Copyright (C) 2024 Analog Devices, Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************/
+
+#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_I3C_I3C_CCC_H_
+#define LIBRARIES_PERIPHDRIVERS_SOURCE_I3C_I3C_CCC_H_
+
+/* Broadcast CCCs */
+#define MXC_I3C_CCC_B_ENEC 0x00 /* Enable Events Command */
+#define MXC_I3C_CCC_B_DISEC 0x01 /* Disable Events Command */
+#define MXC_I3C_CCC_B_ENTAS0 0x02 /* Enter Activity State 0 */
+#define MXC_I3C_CCC_B_ENTAS1 0x03 /* Enter Activity State 1 */
+#define MXC_I3C_CCC_B_ENTAS2 0x04 /* Enter Activity State 2 */
+#define MXC_I3C_CCC_B_ENTAS3 0x05 /* Enter Activity State 3 */
+#define MXC_I3C_CCC_B_RSTDAA 0x06 /* Reset Dynamic Address Assignment */
+#define MXC_I3C_CCC_B_ENTDAA 0x07 /* Enter Dynamic Address Assignment */
+#define MXC_I3C_CCC_B_DEFTGTS 0x08 /* Define List of Targets */
+#define MXC_I3C_CCC_B_SETMWL 0x09 /* Set Max Write Length */
+#define MXC_I3C_CCC_B_SETMRL 0x0A /* Set Max Read Length */
+#define MXC_I3C_CCC_B_ENTTM 0x0B /* Enter Test Mode */
+#define MXC_I3C_CCC_B_SETBUSCON 0x0C /* Set Bus Context */
+#define MXC_I3C_CCC_B_ENDXFR 0x12 /* Data Transfer Ending Procedure Control */
+#define MXC_I3C_CCC_B_ENTHDR0 0x20 /* Enter HDR Mode 0 */
+#define MXC_I3C_CCC_B_ENTHDR1 0x21 /* Enter HDR Mode 1 */
+#define MXC_I3C_CCC_B_ENTHDR2 0x22 /* Enter HDR Mode 2 */
+#define MXC_I3C_CCC_B_ENTHDR3 0x23 /* Enter HDR Mode 3 */
+#define MXC_I3C_CCC_B_ENTHDR4 0x24 /* Enter HDR Mode 4 */
+#define MXC_I3C_CCC_B_ENTHDR5 0x25 /* Enter HDR Mode 5 */
+#define MXC_I3C_CCC_B_ENTHDR6 0x26 /* Enter HDR Mode 6 */
+#define MXC_I3C_CCC_B_ENTHDR7 0x27 /* Enter HDR Mode 7 */
+#define MXC_I3C_CCC_B_SETXTIME 0x28 /* Exchange Timing Information */
+#define MXC_I3C_CCC_B_SETAASA 0x29 /* Set Dynamic Address as Static Address */
+#define MXC_I3C_CCC_B_RSTACT 0x2A /* Target Reset Action */
+#define MXC_I3C_CCC_B_DEFGRPA 0x2B /* Define List of Group Addresses */
+#define MXC_I3C_CCC_B_RSTGRPA 0x2C /* Reset Group Address */
+#define MXC_I3C_CCC_B_MLANE 0x2D /* Multi-Land Data Transfer Control */
+
+/* Direct CCCs */
+#define MXC_I3C_CCC_D_ENEC 0x80 /* Enable Events Command */
+#define MXC_I3C_CCC_D_DISEC 0x81 /* Disable Events Command */
+#define MXC_I3C_CCC_D_ENTAS0 0x82 /* Enter Activity State 0 */
+#define MXC_I3C_CCC_D_ENTAS1 0x83 /* Enter Activity State 1 */
+#define MXC_I3C_CCC_D_ENTAS2 0x84 /* Enter Activity State 2 */
+#define MXC_I3C_CCC_D_ENTAS3 0x85 /* Enter Activity State 3 */
+#define MXC_I3C_CCC_D_RSTDAA 0x86 /* Reset Dynamic Address Assignment NACKed */
+#define MXC_I3C_CCC_D_SETDASA 0x87 /* Set Dynamic Address from Static Address */
+#define MXC_I3C_CCC_D_SETNEWDA 0x88 /* Set New Dynamic Address */
+#define MXC_I3C_CCC_D_SETMWL 0x89 /* Set Max Write Length */
+#define MXC_I3C_CCC_D_SETMRL 0x8A /* Set Max Read Length */
+#define MXC_I3C_CCC_D_GETMWL 0x8B /* Get Max Write Length */
+#define MXC_I3C_CCC_D_GETMRL 0x8C /* Get Max Read Length */
+#define MXC_I3C_CCC_D_GETPID 0x8D /* Get Provisioned ID */
+#define MXC_I3C_CCC_D_GETBCR 0x8E /* Get Bus Characteristics Register */
+#define MXC_I3C_CCC_D_GETDCR 0x8F /* Get Device Characteristics Register */
+#define MXC_I3C_CCC_D_GETSTATUS 0x90 /* Get Device Status */
+#define MXC_I3C_CCC_D_GETACCCR 0x91 /* Get Accept Controller Role */
+#define MXC_I3C_CCC_D_ENDXFR 0x92 /* Data Transfer Ending Procedure Control */
+#define MXC_I3C_CCC_D_SETBRGTGT 0x93 /* Set Bridge Targets */
+#define MXC_I3C_CCC_D_GETMXDS 0x94 /* Get Max Data Speed */
+#define MXC_I3C_CCC_D_GETCAPS 0x95 /* Get Optional Feature Capabilities */
+#define MXC_I3C_CCC_D_D2DXFER 0x97 /* Device to Device(s) Tunneling Control */
+#define MXC_I3C_CCC_D_SETXTIME 0x98 /* Set Exchange Timing Information */
+#define MXC_I3C_CCC_D_GETXTIME 0x99 /* Get Exchange Timing Information */
+#define MXC_I3C_CCC_D_RSTACT 0x9A /* Target Reset Action */
+#define MXC_I3C_CCC_D_SETGRPA 0x9B /* Set Group Address */
+#define MXC_I3C_CCC_D_RSTGRPA 0x9C /* Reset Group Address */
+#define MXC_I3C_CCC_D_MLANE 0x9D /* Multi-Lane Data Transfer Control */
+
+#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_I3C_I3C_CCC_H_
diff --git a/Libraries/PeriphDrivers/Source/I3C/i3c_me30.c b/Libraries/PeriphDrivers/Source/I3C/i3c_me30.c
new file mode 100644
index 00000000000..7a0a9dfcf79
--- /dev/null
+++ b/Libraries/PeriphDrivers/Source/I3C/i3c_me30.c
@@ -0,0 +1,281 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2024 Analog Devices, Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************/
+
+/* **** Includes **** */
+#include
+#include "mxc_errors.h"
+#include "mxc_sys.h"
+#include "i3c.h"
+#include "i3c_reva.h"
+#include "i3c_ccc.h"
+
+/* **** Definitions **** */
+
+/* **** Functions **** */
+int MXC_I3C_Init(mxc_i3c_regs_t *i3c, mxc_i3c_config_t *config)
+{
+ int ret;
+
+#ifndef MSDK_NO_GPIO_CLK_INIT
+ MXC_SYS_Reset_Periph(MXC_SYS_RESET0_I3C);
+ MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I3C);
+ MXC_GPIO_Config(&gpio_cfg_i3c);
+#endif
+
+ if (!config->target_mode) {
+ /* Controller mode initialization */
+ /* 1. SCL frequency and duty cycle */
+ ret = MXC_I3C_SetPPFrequency(i3c, config->pp_hz);
+ if (ret < 0) {
+ return ret;
+ }
+
+ ret = MXC_I3C_SetODFrequency(i3c, config->od_hz, false);
+ if (ret < 0) {
+ return ret;
+ }
+
+ ret = MXC_I3C_SetI2CFrequency(i3c, config->i2c_hz);
+ if (ret < 0) {
+ return ret;
+ }
+ }
+
+ return MXC_I3C_RevA_Init((mxc_i3c_reva_regs_t *)i3c, config->target_mode, config->static_addr);
+}
+
+int MXC_I3C_Recover(mxc_i3c_regs_t *i3c)
+{
+ return MXC_I3C_RevA_Recover((mxc_i3c_reva_regs_t *)i3c);
+}
+
+int MXC_I3C_Shutdown(mxc_i3c_regs_t *i3c)
+{
+ int ret;
+
+ ret = MXC_I3C_RevA_Shutdown((mxc_i3c_reva_regs_t *)i3c);
+ if (ret < 0) {
+ return ret;
+ }
+
+#ifndef MSDK_NO_GPIO_CLK_INIT
+ MXC_SYS_Reset_Periph(MXC_SYS_RESET0_I3C);
+ MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I3C);
+#endif
+
+ return E_SUCCESS;
+}
+
+int MXC_I3C_SetPPFrequency(mxc_i3c_regs_t *i3c, unsigned int frequency)
+{
+ return MXC_I3C_RevA_SetPPFrequency((mxc_i3c_reva_regs_t *)i3c, frequency);
+}
+
+unsigned int MXC_I3C_GetPPFrequency(mxc_i3c_regs_t *i3c)
+{
+ return MXC_I3C_RevA_GetPPFrequency((mxc_i3c_reva_regs_t *)i3c);
+}
+
+int MXC_I3C_SetODFrequency(mxc_i3c_regs_t *i3c, unsigned int frequency, bool highPP)
+{
+ return MXC_I3C_RevA_SetODFrequency((mxc_i3c_reva_regs_t *)i3c, frequency, highPP);
+}
+
+unsigned int MXC_I3C_GetODFrequency(mxc_i3c_regs_t *i3c)
+{
+ return MXC_I3C_RevA_GetODFrequency((mxc_i3c_reva_regs_t *)i3c);
+}
+
+int MXC_I3C_SetI2CFrequency(mxc_i3c_regs_t *i3c, unsigned int frequency)
+{
+ return MXC_I3C_RevA_SetI2CFrequency((mxc_i3c_reva_regs_t *)i3c, frequency);
+}
+
+unsigned int MXC_I3C_GetI2CFrequency(mxc_i3c_regs_t *i3c)
+{
+ return MXC_I3C_RevA_GetI2CFrequency((mxc_i3c_reva_regs_t *)i3c);
+}
+
+int MXC_I3C_SetSkew(mxc_i3c_regs_t *i3c, uint8_t skew)
+{
+ return MXC_I3C_RevA_SetSkew((mxc_i3c_reva_regs_t *)i3c, skew);
+}
+
+int MXC_I3C_SetHighKeeperMode(mxc_i3c_regs_t *i3c, mxc_i3c_high_keeper_t hkeep)
+{
+ return MXC_I3C_RevA_SetHighKeeperMode((mxc_i3c_reva_regs_t *)i3c, hkeep);
+}
+
+int MXC_I3C_EmitStart(mxc_i3c_regs_t *i3c, bool isI2C, mxc_i3c_transfer_type_t xferType,
+ uint8_t addr, uint8_t readCount)
+{
+ return MXC_I3C_RevA_EmitStart((mxc_i3c_reva_regs_t *)i3c, isI2C, xferType, addr, readCount);
+}
+
+int MXC_I3C_ResetTarget(mxc_i3c_regs_t *i3c)
+{
+ return MXC_I3C_RevA_ResetTarget((mxc_i3c_reva_regs_t *)i3c);
+}
+
+void MXC_I3C_EmitStop(mxc_i3c_regs_t *i3c)
+{
+ return MXC_I3C_RevA_EmitStop((mxc_i3c_reva_regs_t *)i3c);
+}
+
+void MXC_I3C_EmitI2CStop(mxc_i3c_regs_t *i3c)
+{
+ return MXC_I3C_RevA_EmitI2CStop((mxc_i3c_reva_regs_t *)i3c);
+}
+
+int MXC_I3C_Controller_CCC(mxc_i3c_regs_t *i3c, const mxc_i3c_ccc_req_t *req)
+{
+ return MXC_I3C_RevA_Controller_CCC((mxc_i3c_reva_regs_t *)i3c, (mxc_i3c_reva_ccc_req_t *)req);
+}
+
+int MXC_I3C_Controller_Transaction(mxc_i3c_regs_t *i3c, const mxc_i3c_req_t *req)
+{
+ return MXC_I3C_RevA_Controller_Transaction((mxc_i3c_reva_regs_t *)i3c,
+ (mxc_i3c_reva_req_t *)req);
+}
+
+int MXC_I3C_Controller_DAA(mxc_i3c_regs_t *i3c, uint8_t addr, uint8_t *pid, uint8_t *bcr,
+ uint8_t *dcr)
+{
+ return MXC_I3C_RevA_Controller_DAA((mxc_i3c_reva_regs_t *)i3c, addr, pid, bcr, dcr);
+}
+
+int MXC_I3C_HotJoin(mxc_i3c_regs_t *i3c)
+{
+ return MXC_I3C_RevA_HotJoin((mxc_i3c_reva_regs_t *)i3c);
+}
+
+int MXC_I3C_RequestIBI(mxc_i3c_regs_t *i3c, unsigned char mdb, mxc_i3c_ibi_getbyte_t getByteCb)
+{
+ return MXC_I3C_RevA_RequestIBI((mxc_i3c_reva_regs_t *)i3c, mdb,
+ (mxc_i3c_reva_ibi_getbyte_t)getByteCb);
+}
+
+int MXC_I3C_Standby(mxc_i3c_regs_t *i3c)
+{
+ return MXC_I3C_RevA_Standby((mxc_i3c_reva_regs_t *)i3c);
+}
+
+int MXC_I3C_Wakeup(mxc_i3c_regs_t *i3c)
+{
+ return MXC_I3C_RevA_Wakeup((mxc_i3c_reva_regs_t *)i3c);
+}
+
+int MXC_I3C_ReadRXFIFO(mxc_i3c_regs_t *i3c, volatile unsigned char *bytes, unsigned int len,
+ int timeout)
+{
+ return MXC_I3C_RevA_ReadRXFIFO((mxc_i3c_reva_regs_t *)i3c, bytes, len, timeout);
+}
+
+int MXC_I3C_WriteTXFIFO(mxc_i3c_regs_t *i3c, const unsigned char *bytes, unsigned int len, bool end,
+ int timeout)
+{
+ return MXC_I3C_RevA_WriteTXFIFO((mxc_i3c_reva_regs_t *)i3c, bytes, len, end, timeout);
+}
+
+int MXC_I3C_Controller_GetError(mxc_i3c_regs_t *i3c)
+{
+ return MXC_I3C_RevA_Controller_GetError((mxc_i3c_reva_regs_t *)i3c);
+}
+
+void MXC_I3C_Controller_ClearError(mxc_i3c_regs_t *i3c)
+{
+ MXC_I3C_RevA_Controller_ClearError((mxc_i3c_reva_regs_t *)i3c);
+}
+
+int MXC_I3C_SetRXTXThreshold(mxc_i3c_regs_t *i3c, mxc_i3c_rx_threshold_t rxth,
+ mxc_i3c_tx_threshold_t txth)
+{
+ return MXC_I3C_RevA_SetRXTXThreshold((mxc_i3c_reva_regs_t *)i3c,
+ (mxc_i3c_reva_rx_threshold_t)rxth,
+ (mxc_i3c_reva_tx_threshold_t)txth);
+}
+
+uint8_t MXC_I3C_GetDynamicAddress(mxc_i3c_regs_t *i3c)
+{
+ return MXC_I3C_RevA_GetDynamicAddress((mxc_i3c_reva_regs_t *)i3c);
+}
+
+void MXC_I3C_IRQHandler(mxc_i3c_regs_t *i3c)
+{
+ MXC_I3C_RevA_IRQHandler((mxc_i3c_reva_regs_t *)i3c);
+}
+
+void MXC_I3C_ClearRXFIFO(mxc_i3c_regs_t *i3c)
+{
+ MXC_I3C_RevA_ClearRXFIFO((mxc_i3c_reva_regs_t *)i3c);
+}
+
+void MXC_I3C_ClearTXFIFO(mxc_i3c_regs_t *i3c)
+{
+ MXC_I3C_RevA_ClearTXFIFO((mxc_i3c_reva_regs_t *)i3c);
+}
+
+unsigned int MXC_I3C_Controller_GetRXCount(mxc_i3c_regs_t *i3c)
+{
+ return MXC_I3C_RevA_Controller_GetRXCount((mxc_i3c_reva_regs_t *)i3c);
+}
+
+unsigned int MXC_I3C_Controller_GetTXCount(mxc_i3c_regs_t *i3c)
+{
+ return MXC_I3C_RevA_Controller_GetTXCount((mxc_i3c_reva_regs_t *)i3c);
+}
+
+void MXC_I3C_Controller_EnableInt(mxc_i3c_regs_t *i3c, uint32_t mask)
+{
+ MXC_I3C_RevA_Controller_EnableInt((mxc_i3c_reva_regs_t *)i3c, mask);
+}
+
+void MXC_I3C_Controller_DisableInt(mxc_i3c_regs_t *i3c, uint32_t mask)
+{
+ MXC_I3C_RevA_Controller_DisableInt((mxc_i3c_reva_regs_t *)i3c, mask);
+}
+
+unsigned int MXC_I3C_Controller_GetFlags(mxc_i3c_regs_t *i3c)
+{
+ return MXC_I3C_RevA_Controller_GetFlags((mxc_i3c_reva_regs_t *)i3c);
+}
+
+void MXC_I3C_Controller_ClearFlags(mxc_i3c_regs_t *i3c, uint32_t mask)
+{
+ MXC_I3C_RevA_Controller_ClearFlags((mxc_i3c_reva_regs_t *)i3c, mask);
+}
+
+void MXC_I3C_Target_EnableInt(mxc_i3c_regs_t *i3c, uint32_t mask)
+{
+ MXC_I3C_RevA_Target_EnableInt((mxc_i3c_reva_regs_t *)i3c, mask);
+}
+
+void MXC_I3C_Target_DisableInt(mxc_i3c_regs_t *i3c, uint32_t mask)
+{
+ MXC_I3C_RevA_Target_DisableInt((mxc_i3c_reva_regs_t *)i3c, mask);
+}
+
+int MXC_I3C_Target_GetFlags(mxc_i3c_regs_t *i3c)
+{
+ return MXC_I3C_RevA_Target_GetFlags((mxc_i3c_reva_regs_t *)i3c);
+}
+
+void MXC_I3C_Target_ClearFlags(mxc_i3c_regs_t *i3c, uint32_t mask)
+{
+ MXC_I3C_RevA_Target_ClearFlags((mxc_i3c_reva_regs_t *)i3c, mask);
+}
diff --git a/Libraries/PeriphDrivers/Source/I3C/i3c_reva.c b/Libraries/PeriphDrivers/Source/I3C/i3c_reva.c
new file mode 100644
index 00000000000..86562738f75
--- /dev/null
+++ b/Libraries/PeriphDrivers/Source/I3C/i3c_reva.c
@@ -0,0 +1,969 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2024 Analog Devices, Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************/
+
+/* **** Includes **** */
+#include
+#include "mxc_errors.h"
+#include "mxc_sys.h"
+#include "i3c_regs.h"
+#include "i3c.h"
+#include "i3c_reva.h"
+#include "i3c_ccc.h"
+
+/* **** Definitions **** */
+#ifndef ARRAY_SIZE
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x)[0])
+#endif
+
+#define MXC_I3C_REVA_MAX_FIFO_TRANSACTION 255U
+
+#define GET_FIELD(reg, field) ((i3c->reg & MXC_F_I3C_REVA_##field) >> MXC_F_I3C_REVA_##field##_POS)
+#define SET_FIELD(reg, field, value) \
+ do { \
+ i3c->reg &= ~MXC_F_I3C_REVA_##field; \
+ i3c->reg |= value << MXC_F_I3C_##field##_POS; \
+ } while (0);
+
+#define MXC_F_I3C_REVA_CONT_ERRWARN_MASK \
+ (MXC_F_I3C_REVA_CONT_ERRWARN_NACK | MXC_F_I3C_REVA_CONT_ERRWARN_TX_ABT | \
+ MXC_F_I3C_REVA_CONT_ERRWARN_RX_TERM | MXC_F_I3C_REVA_CONT_ERRWARN_HDR_PAR | \
+ MXC_F_I3C_REVA_CONT_ERRWARN_HDR_CRC | MXC_F_I3C_REVA_CONT_ERRWARN_TX_OVR | \
+ MXC_F_I3C_REVA_CONT_ERRWARN_MSG | MXC_F_I3C_REVA_CONT_ERRWARN_INV_REQ | \
+ MXC_F_I3C_REVA_CONT_ERRWARN_TO)
+
+#define MXC_F_I3C_REVA_CONT_STATUS_MASK \
+ (MXC_F_I3C_REVA_CONT_STATUS_IBI_WON | MXC_F_I3C_REVA_CONT_STATUS_CONT_TRANS | \
+ MXC_F_I3C_REVA_CONT_STATUS_DONE | MXC_F_I3C_REVA_CONT_STATUS_NACK | \
+ MXC_F_I3C_REVA_CONT_STATUS_REQ_DONE | MXC_F_I3C_REVA_CONT_STATUS_TARG_START)
+
+/* MCTRL_TYPE values if request is EmitStartAddr */
+typedef enum {
+ MXC_I3C_REVA_START_TYPE_SDR = 0,
+ MXC_I3C_REVA_START_TYPE_I2C = 1
+} mxc_i3c_reva_start_type_t;
+
+/* MCTRL_IBIRESP values if request is EmitStartAddr and AutoIBI */
+#define MXC_I3C_REVA_CONT_CTRL1_IBIRESP_ACK 0x00U
+#define MXC_I3C_REVA_CONT_CTRL1_IBIRESP_NACK 0x01U
+#define MXC_I3C_REVA_CONT_CTRL1_IBIRESP_ACK_WITH_MB 0x02U
+#define MXC_I3C_REVA_CONT_CTRL1_IBIRESP_MANUAL 0x03U
+
+/* Provisioned ID length */
+#define MXC_I3C_PROVISIONED_ID_LEN 6U
+
+/* Broadcast address */
+#define MXC_I3C_BROADCAST_ADDR 0x7EU
+
+typedef struct {
+ mxc_i3c_reva_regs_t *regs; ///< Pointer to regs of this I3C instance.
+ mxc_i3c_reva_ibi_getbyte_t ibiGetByteCB; ///< IBI additional data callback.
+} mxc_i3c_reva_controller_t;
+
+typedef enum {
+ MXC_I3C_REVA_IBIRESP_ACK = 0,
+ MXC_I3C_REVA_IBIRESP_NACK = 1,
+ MXC_I3C_REVA_IBIRESP_ACK_WITH_MB = 2,
+ MXC_I3C_REVA_IBIRESP_MANUAL = 3
+} mxc_i3c_reva_ibiresp_t;
+
+#define MXC_I3C_REVA_ADDR_INVALID 0x00U
+
+/* **** Globals **** */
+/**
+ * @brief I3C controller instances.
+ *
+ */
+mxc_i3c_reva_controller_t controller[MXC_CFG_I3C_INSTANCES];
+
+/* **** Functions **** */
+int MXC_I3C_RevA_Init(mxc_i3c_reva_regs_t *i3c, bool targetMode, uint8_t staticAddr)
+{
+ int ret = E_NO_ERROR;
+ int idx;
+ uint8_t val;
+
+ idx = MXC_I3C_GET_IDX((mxc_i3c_regs_t *)i3c);
+ if (idx < 0) {
+ return E_BAD_PARAM;
+ }
+
+ if (!targetMode) {
+ /* Controller mode initialization */
+
+ /* SCL-to-SDA skew */
+ ret = MXC_I3C_RevA_SetSkew(i3c, 0);
+ if (ret < 0) {
+ return ret;
+ }
+
+ /* High-Keeper implementation selection */
+ ret = MXC_I3C_RevA_SetHighKeeperMode(i3c, MXC_I3C_HIGH_KEEPER_OFF);
+ if (ret < 0) {
+ return ret;
+ }
+
+ /* 2. If using fifos, set tx rx fifo trigger levels */
+ if (i3c->targ_cap1 & MXC_F_I3C_REVA_TARG_CAP1_RXFIFO_CFG) {
+ MXC_I3C_RevA_SetRXTXThreshold(i3c, MXC_I3C_REVA_RX_TH_NOT_EMPTY,
+ MXC_I3C_REVA_TX_TH_ALMOST_FULL);
+ }
+
+ /* 3. Optionally write IBIRULES reg to optimize response to incoming IBIs */
+
+ /* 4. Enable controller mode */
+ SET_FIELD(cont_ctrl0, CONT_CTRL0_EN, MXC_V_I3C_REVA_CONT_CTRL0_EN_ON);
+ } else {
+ /* Target mode initialization */
+ /* 1. After reset, write setup registers needed for optional features */
+
+ if (i3c->targ_cap1 & MXC_F_I3C_REVA_TARG_CAP1_RXFIFO_CFG) {
+ MXC_I3C_RevA_SetRXTXThreshold(i3c, MXC_I3C_REVA_RX_TH_NOT_EMPTY,
+ MXC_I3C_REVA_TX_TH_ALMOST_FULL);
+ }
+
+ /* Set BCR, DCR */
+ val = 0 << 6; /* Device role: target */
+ if (i3c->targ_cap1 & MXC_S_I3C_REVA_TARG_CAP1_CCCH_LIMITS) {
+ val |= 1 << 0; /* Max data speed limitation */
+ }
+ if (i3c->targ_cap1 & MXC_S_I3C_REVA_TARG_CAP1_CCCH_BASIC) {
+ val |= 1 << 5; /* Supports advanced capabiliries */
+ }
+ if (i3c->targ_cap1 & MXC_S_I3C_REVA_TARG_CAP1_IBI_EVENTS_IBI) {
+ val |= 1 << 1; /* Supports IBI generation */
+ }
+ if (i3c->targ_cap1 & MXC_S_I3C_REVA_TARG_CAP1_IBI_EVENTS_PAYLOAD) {
+ val |= 1 << 2; /* MDB and additional data bytes may follow the IBI */
+ }
+ val |= 1 << 3; /* Offline capable */
+ SET_FIELD(targ_idext, TARG_IDEXT_BUSCHAR, val);
+
+ /* Set DCR to generic device */
+ SET_FIELD(targ_idext, TARG_IDEXT_DEVCHAR, 0);
+
+ /* Enable CCC handling */
+ MXC_I3C_RevA_Target_EnableInt(i3c, MXC_F_I3C_REVA_TARG_INTEN_CCC);
+
+ /* 2. Write 1 to CONFIG.TGTENA */
+ SET_FIELD(targ_ctrl0, TARG_CTRL0_EN, 1);
+
+ /* Clear STOP bit */
+ SET_FIELD(targ_status, TARG_STATUS_STOP, 0);
+ }
+
+ controller[idx].regs = i3c;
+
+ return E_NO_ERROR;
+}
+
+static inline uint8_t MXC_I3C_RevA_Controller_GetState(mxc_i3c_reva_regs_t *i3c)
+{
+ return (uint8_t)GET_FIELD(cont_status, CONT_STATUS_STATE);
+}
+
+static inline int MXC_I3C_RevA_Controller_WaitForDone(mxc_i3c_reva_regs_t *i3c, int timeout)
+{
+ while (!(i3c->cont_status & MXC_F_I3C_REVA_CONT_STATUS_DONE)) {
+ if (timeout == 0) {
+ return E_TIME_OUT;
+ }
+ if (timeout > 0) {
+ timeout--;
+ }
+ }
+
+ return E_SUCCESS;
+}
+
+static inline int MXC_I3C_RevA_Controller_WaitForReqDone(mxc_i3c_reva_regs_t *i3c, int timeout)
+{
+ while (!(i3c->cont_status & MXC_F_I3C_REVA_CONT_STATUS_REQ_DONE)) {
+ if (timeout == 0) {
+ return E_TIME_OUT;
+ }
+ if (timeout > 0) {
+ timeout--;
+ }
+ }
+
+ return E_SUCCESS;
+}
+
+int MXC_I3C_RevA_Recover(mxc_i3c_reva_regs_t *i3c)
+{
+ int retries = 3;
+
+ while (retries &&
+ MXC_I3C_RevA_Controller_GetState(i3c) == MXC_V_I3C_REVA_CONT_STATUS_STATE_SDR_NORM) {
+ MXC_I3C_RevA_EmitStop(i3c);
+ retries--;
+ }
+
+ while (GET_FIELD(cont_status, CONT_STATUS_TARG_START)) {
+ SET_FIELD(cont_status, CONT_STATUS_TARG_START, 1);
+ MXC_I3C_RevA_AutoIBI(i3c);
+ MXC_I3C_RevA_Controller_WaitForDone(i3c, 1000);
+ MXC_I3C_RevA_ClearRXFIFO(i3c);
+ }
+
+ retries = 1000;
+ while (retries &&
+ MXC_I3C_RevA_Controller_GetState(i3c) != MXC_V_I3C_REVA_CONT_STATUS_STATE_IDLE) {
+ retries--;
+ }
+
+ if (retries == 0) {
+ return E_TIME_OUT;
+ }
+
+ return 0;
+}
+
+int MXC_I3C_RevA_Shutdown(mxc_i3c_reva_regs_t *i3c)
+{
+ int idx;
+
+ idx = MXC_I3C_GET_IDX((mxc_i3c_regs_t *)i3c);
+ if (idx < 0) {
+ return E_BAD_PARAM;
+ }
+
+ if (GET_FIELD(cont_ctrl0, CONT_CTRL0_EN)) {
+ SET_FIELD(cont_ctrl0, CONT_CTRL0_EN, MXC_V_I3C_REVA_CONT_CTRL0_EN_OFF);
+ MXC_I3C_RevA_Controller_DisableInt(i3c, i3c->cont_inten);
+ MXC_I3C_RevA_Controller_ClearFlags(i3c, i3c->cont_intfl);
+ } else if (GET_FIELD(targ_ctrl0, TARG_CTRL0_EN)) {
+ SET_FIELD(targ_ctrl0, TARG_CTRL0_EN, 0);
+ MXC_I3C_RevA_Target_DisableInt(i3c, i3c->targ_inten);
+ MXC_I3C_RevA_Target_ClearFlags(i3c, i3c->targ_intfl);
+ }
+
+ MXC_I3C_RevA_ClearRXFIFO(i3c);
+ MXC_I3C_RevA_ClearTXFIFO(i3c);
+ controller[idx].ibiGetByteCB = NULL;
+
+ return E_SUCCESS;
+}
+
+int MXC_I3C_RevA_SetPPFrequency(mxc_i3c_reva_regs_t *i3c, unsigned int frequency)
+{
+ uint32_t ticks, highPeriod, lowPeriod;
+
+ ticks = PeripheralClock / frequency;
+ /* Frequency must be less than or equal to half of peripheral clock */
+ if (ticks < 2 || ticks > 32) {
+ return E_BAD_PARAM;
+ }
+
+ highPeriod = ticks / 2;
+ lowPeriod = ticks / 2;
+ if (ticks % 2) {
+ lowPeriod++;
+ }
+
+ i3c->cont_ctrl0 &= ~MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD;
+ i3c->cont_ctrl0 &= ~MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD;
+ i3c->cont_ctrl0 |= (highPeriod - 1) << MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS;
+ i3c->cont_ctrl0 |= (lowPeriod - highPeriod) << MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_POS;
+
+ return (int)MXC_I3C_RevA_GetPPFrequency(i3c);
+}
+
+unsigned int MXC_I3C_RevA_GetPPFrequency(mxc_i3c_reva_regs_t *i3c)
+{
+ uint8_t highPeriod, lowPeriod;
+
+ highPeriod = 1 + ((i3c->cont_ctrl0 & MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD) >>
+ MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS);
+ lowPeriod = highPeriod + ((i3c->cont_ctrl0 & MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD) >>
+ MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_POS);
+
+ return PeripheralClock / (highPeriod + lowPeriod);
+}
+
+int MXC_I3C_RevA_SetODFrequency(mxc_i3c_reva_regs_t *i3c, unsigned int frequency, bool highPP)
+{
+ uint32_t lowPeriod;
+ uint8_t ppBaud;
+
+ /*
+ * Minimum low period = 200ns
+ * Minimum high period = 200ns for first broadcast address
+ * Maximum high period = 41ns
+ */
+ if ((!highPP && frequency > 2500000U) || frequency > 5000000U) {
+ return E_BAD_PARAM;
+ }
+
+ ppBaud = (i3c->cont_ctrl0 & MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD) >>
+ MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS;
+ lowPeriod = PeripheralClock / frequency;
+ if (highPP) {
+ lowPeriod = (lowPeriod / (ppBaud + 1)) - 2;
+ } else {
+ lowPeriod = (lowPeriod / (2 * (ppBaud + 1))) - 1;
+ }
+
+ i3c->cont_ctrl0 &= ~(MXC_F_I3C_REVA_CONT_CTRL0_OD_LBAUD | MXC_F_I3C_REVA_CONT_CTRL0_OD_HP);
+ i3c->cont_ctrl0 |= lowPeriod << MXC_F_I3C_REVA_CONT_CTRL0_OD_LBAUD_POS;
+ i3c->cont_ctrl0 |= (highPP ? 1 : 0) << MXC_F_I3C_REVA_CONT_CTRL0_OD_HP_POS;
+
+ return (int)MXC_I3C_RevA_GetODFrequency(i3c);
+}
+
+unsigned int MXC_I3C_RevA_GetODFrequency(mxc_i3c_reva_regs_t *i3c)
+{
+ uint8_t highPeriod, lowPeriod, odBaud, ppBaud;
+
+ ppBaud = (i3c->cont_ctrl0 & MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD) >>
+ MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS;
+ odBaud = (i3c->cont_ctrl0 & MXC_F_I3C_REVA_CONT_CTRL0_OD_LBAUD) >>
+ MXC_F_I3C_REVA_CONT_CTRL0_OD_LBAUD_POS;
+ lowPeriod = (odBaud + 1) * (ppBaud + 1);
+ if (i3c->cont_ctrl0 & MXC_F_I3C_REVA_CONT_CTRL0_OD_HP) {
+ highPeriod = ppBaud + 1;
+ } else {
+ highPeriod = lowPeriod;
+ }
+
+ return PeripheralClock / (highPeriod + lowPeriod);
+}
+
+int MXC_I3C_RevA_SetI2CFrequency(mxc_i3c_reva_regs_t *i3c, unsigned int frequency)
+{
+ uint8_t odBaud, ppBaud;
+ uint32_t lowPeriod;
+
+ ppBaud = (i3c->cont_ctrl0 & MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD) >>
+ MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS;
+ odBaud = (i3c->cont_ctrl0 & MXC_F_I3C_REVA_CONT_CTRL0_OD_LBAUD) >>
+ MXC_F_I3C_REVA_CONT_CTRL0_OD_LBAUD_POS;
+
+ lowPeriod = PeripheralClock / frequency;
+ lowPeriod /= (odBaud + 1) * (ppBaud + 1);
+ lowPeriod = (lowPeriod >> 1) - 1;
+ lowPeriod = lowPeriod << 1;
+
+ if (lowPeriod > 0xF) {
+ lowPeriod = 0xF;
+ }
+ i3c->cont_ctrl0 &= ~MXC_F_I3C_REVA_CONT_CTRL0_I2C_BAUD;
+ i3c->cont_ctrl0 |= lowPeriod << MXC_F_I3C_REVA_CONT_CTRL0_I2C_BAUD_POS;
+
+ return (int)MXC_I3C_RevA_GetI2CFrequency(i3c);
+}
+
+unsigned int MXC_I3C_RevA_GetI2CFrequency(mxc_i3c_reva_regs_t *i3c)
+{
+ uint8_t i2cBaud, odBaud, ppBaud;
+ uint32_t lowPeriod, highPeriod;
+
+ i2cBaud = (i3c->cont_ctrl0 & MXC_F_I3C_REVA_CONT_CTRL0_I2C_BAUD) >>
+ MXC_F_I3C_REVA_CONT_CTRL0_I2C_BAUD_POS;
+ ppBaud = (i3c->cont_ctrl0 & MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD) >>
+ MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS;
+ odBaud = (i3c->cont_ctrl0 & MXC_F_I3C_REVA_CONT_CTRL0_OD_LBAUD) >>
+ MXC_F_I3C_REVA_CONT_CTRL0_OD_LBAUD_POS;
+
+ lowPeriod = (odBaud + 1) * (ppBaud + 1) * ((i2cBaud >> 1) + 1);
+ highPeriod = lowPeriod;
+ if ((i2cBaud % 2) != 0) {
+ highPeriod++;
+ }
+
+ return PeripheralClock / (lowPeriod + highPeriod);
+}
+
+uint8_t MXC_I3C_RevA_GetDynamicAddress(mxc_i3c_reva_regs_t *i3c)
+{
+ if (GET_FIELD(targ_ctrl0, TARG_CTRL0_EN) && GET_FIELD(targ_dynaddr, TARG_DYNADDR_VALID)) {
+ return GET_FIELD(targ_dynaddr, TARG_DYNADDR_ADDR);
+ }
+
+ return MXC_I3C_ADDR_INVALID;
+}
+
+int MXC_I3C_RevA_SetSkew(mxc_i3c_reva_regs_t *i3c, uint8_t skew)
+{
+ unsigned int ppFreq;
+
+ if (skew > 7) {
+ return E_BAD_PARAM;
+ }
+
+ if (skew > 0) {
+ ppFreq = MXC_I3C_RevA_GetPPFrequency(i3c);
+ if ((PeripheralClock / ppFreq) < 4) {
+ return E_BAD_STATE;
+ }
+ }
+
+ i3c->cont_ctrl0 &= ~MXC_F_I3C_REVA_CONT_CTRL0_PP_SKEW;
+ i3c->cont_ctrl0 |= (uint32_t)skew << MXC_F_I3C_REVA_CONT_CTRL0_PP_SKEW_POS;
+
+ return E_SUCCESS;
+}
+
+int MXC_I3C_RevA_SetHighKeeperMode(mxc_i3c_reva_regs_t *i3c, mxc_i3c_reva_high_keeper_t hkeep)
+{
+ if (hkeep > MXC_I3C_REVA_HIGH_KEEPER_EXT_SCL_SDA) {
+ return E_BAD_PARAM;
+ }
+
+ i3c->cont_ctrl0 &= ~MXC_F_I3C_REVA_CONT_CTRL0_HKEEP;
+ i3c->cont_ctrl0 |= hkeep;
+
+ return E_SUCCESS;
+}
+
+/**
+ * @brief Request an I3C or I2C bus operation.
+ *
+ * @param i3c Pointer to I3C registers.
+ * @param request Request type. e.g. MXC_V_I3C_REVA_CONT_CTRL1_REQUEST_EMIT_START_ADDR.
+ * @param type Request type if EmitStartAddr is requested. For other requests, pass 0.
+ * @param xferType 1 if this is a read request, 0 if write.
+ * @param addr Target address. This is usually 7'h7E for I3C broadcast messages,
+ * target's static address for I2C messages and target's dynamic
+ * address for I3C SDR messages.
+ * @param readCount Maximum bytes allowed to be read from the target. Set to 0 if you wish
+ * to allow the read until the target stops sending.
+ *
+ * @return Success/Fail. E_SUCCESS if request is successful, E_BUSY if an IBI occurrs during a START,
+ * one of \ref MXC_Error_Codes otherwise.
+ */
+static int MXC_I3C_RevA_ControllerRequest(mxc_i3c_reva_regs_t *i3c, uint8_t request,
+ mxc_i3c_reva_start_type_t type,
+ mxc_i3c_transfer_type_t xferType, uint8_t addr,
+ uint8_t readCount)
+{
+ uint32_t cont1;
+ int timeout = 1000;
+
+ cont1 = (request << MXC_F_I3C_CONT_CTRL1_REQ_POS) | (addr << MXC_F_I3C_CONT_CTRL1_ADDR_POS) |
+ (type << MXC_F_I3C_CONT_CTRL1_TYPE_POS) |
+ (MXC_I3C_REVA_CONT_CTRL1_IBIRESP_NACK << MXC_F_I3C_CONT_CTRL1_IBIRESP_POS);
+ if (xferType == MXC_I3C_TRANSFER_TYPE_READ) {
+ cont1 |= 1U << MXC_F_I3C_CONT_CTRL1_RDWR_DIR_POS;
+ cont1 |= readCount << MXC_F_I3C_CONT_CTRL1_TERM_RD_POS;
+ }
+
+ i3c->cont_errwarn = MXC_F_I3C_REVA_CONT_ERRWARN_MASK;
+ MXC_I3C_RevA_Controller_ClearFlags(i3c, MXC_F_I3C_REVA_CONT_STATUS_MASK);
+ i3c->cont_ctrl1 = cont1;
+
+ if (request == MXC_V_I3C_REVA_CONT_CTRL1_REQ_EMIT_START ||
+ request == MXC_V_I3C_REVA_CONT_CTRL1_REQ_PROCESS_DAA) {
+ while (!(i3c->cont_status & MXC_F_I3C_REVA_CONT_STATUS_REQ_DONE)) {
+ if (--timeout == 0) {
+ return E_TIME_OUT;
+ }
+ }
+ }
+
+ /* Check for ACK/NACK */
+ if (i3c->cont_status & MXC_F_I3C_REVA_CONT_STATUS_NACK) {
+ /* Address NACKed, exit */
+ return E_NO_RESPONSE;
+ } else if (i3c->cont_status & MXC_F_I3C_REVA_CONT_STATUS_ERRWARN) {
+ /* Error occurred, check MERRWARN register for details */
+ return MXC_I3C_RevA_Controller_GetError(i3c);
+ } else if (i3c->cont_status & MXC_F_I3C_REVA_CONT_STATUS_IBI_WON) {
+ return E_BUSY;
+ }
+
+ return E_SUCCESS;
+}
+
+int MXC_I3C_RevA_EmitStart(mxc_i3c_reva_regs_t *i3c, bool isI2C, mxc_i3c_transfer_type_t xferType,
+ uint8_t addr, uint8_t readCount)
+{
+ return MXC_I3C_RevA_ControllerRequest(i3c, MXC_V_I3C_REVA_CONT_CTRL1_REQ_EMIT_START,
+ isI2C ? MXC_I3C_REVA_START_TYPE_I2C :
+ MXC_I3C_REVA_START_TYPE_SDR,
+ xferType, addr, readCount);
+}
+
+int MXC_I3C_RevA_ResetTarget(mxc_i3c_reva_regs_t *i3c)
+{
+ return MXC_I3C_RevA_ControllerRequest(i3c, MXC_V_I3C_REVA_CONT_CTRL1_REQ_EXIT_RST,
+ MXC_I3C_REVA_START_TYPE_SDR, 0, 0, 0);
+}
+
+void MXC_I3C_RevA_EmitStop(mxc_i3c_reva_regs_t *i3c)
+{
+ /* Configure MCTRL register for STOP */
+ i3c->cont_ctrl1 &= ~(MXC_F_I3C_REVA_CONT_CTRL1_REQ | MXC_F_I3C_REVA_CONT_CTRL1_RDWR_DIR |
+ MXC_F_I3C_REVA_CONT_CTRL1_TERM_RD);
+ i3c->cont_ctrl1 |= MXC_S_I3C_REVA_CONT_CTRL1_REQ_EMIT_STOP;
+ /* Wait for REQ_DONE */
+ MXC_I3C_RevA_Controller_WaitForReqDone(i3c, 1000);
+}
+
+void MXC_I3C_RevA_EmitI2CStop(mxc_i3c_reva_regs_t *i3c)
+{
+ /* Configure MCTRL register for STOP */
+ i3c->cont_ctrl1 = MXC_S_I3C_REVA_CONT_CTRL1_REQ_EMIT_STOP |
+ (1 << MXC_F_I3C_REVA_CONT_CTRL1_TYPE_POS);
+ /* Wait for REQ_DONE */
+ MXC_I3C_RevA_Controller_WaitForReqDone(i3c, 1000);
+}
+
+int MXC_I3C_RevA_Controller_CCC(mxc_i3c_reva_regs_t *i3c, const mxc_i3c_reva_ccc_req_t *req)
+{
+ int ret;
+
+ MXC_I3C_RevA_ClearTXFIFO(i3c);
+ MXC_I3C_RevA_ClearRXFIFO(i3c);
+ MXC_I3C_RevA_EmitStart(i3c, false, MXC_I3C_TRANSFER_TYPE_WRITE, MXC_I3C_BROADCAST_ADDR, 0);
+
+ MXC_I3C_RevA_WriteTXFIFO(i3c, &req->ccc, 1, req->flags == 0, 100);
+ if (req->flags & MXC_I3C_CCC_HAS_DEFINING_BYTE) {
+ MXC_I3C_RevA_WriteTXFIFO(i3c, &req->def_byte, 1, req->tx_len == 0, 100);
+ }
+ MXC_I3C_RevA_Controller_WaitForDone(i3c, 1000);
+
+ if (req->ccc & 0x80) {
+ /* Direct CCC */
+ ret = MXC_I3C_RevA_EmitStart(i3c, false, req->xfer_type, req->target_addr, req->rx_len);
+ if (ret < 0) {
+ goto err;
+ }
+ if (req->xfer_type == MXC_I3C_TRANSFER_TYPE_WRITE) {
+ /* Write message */
+ if (req->flags & MXC_I3C_CCC_HAS_SUB_COMMAND) {
+ i3c->cont_txfifo8 = req->sub_cmd & (req->tx_len ? 0 : (1 << 8));
+ }
+ if (req->tx_len) {
+ MXC_I3C_RevA_WriteTXFIFO(i3c, req->tx_buf, req->tx_len, true, 100);
+ }
+ } else {
+ /* Read message */
+ MXC_I3C_RevA_ReadRXFIFO(i3c, req->rx_buf, req->rx_len, -1);
+ }
+ } else {
+ /* Broadcast CCC */
+ if (req->tx_len) {
+ MXC_I3C_RevA_WriteTXFIFO(i3c, req->tx_buf, req->tx_len, true, 100);
+ }
+ }
+ MXC_I3C_RevA_Controller_WaitForDone(i3c, 1000);
+
+ /* Check for errors */
+ ret = MXC_I3C_RevA_Controller_GetError(i3c);
+err:
+ MXC_I3C_RevA_EmitStop(i3c);
+
+ return ret;
+}
+
+static int MXC_I3C_RevA_Controller_SDR(mxc_i3c_reva_regs_t *i3c, const mxc_i3c_reva_req_t *req)
+{
+ int ret;
+
+ ret =
+ MXC_I3C_RevA_EmitStart(i3c, false, MXC_I3C_TRANSFER_TYPE_WRITE, MXC_I3C_BROADCAST_ADDR, 0);
+
+ if (ret < 0) {
+ goto err;
+ }
+
+ /* Restart with write */
+ if (req->tx_len) {
+ ret = MXC_I3C_RevA_EmitStart(i3c, false, MXC_I3C_TRANSFER_TYPE_WRITE, req->target_addr, 0);
+ if (ret < 0) {
+ goto err;
+ }
+
+ ret = MXC_I3C_RevA_WriteTXFIFO(i3c, req->tx_buf, req->tx_len, true, 100);
+ if (ret < 0) {
+ goto err;
+ }
+
+ MXC_I3C_RevA_Controller_WaitForDone(i3c, 1000);
+ }
+
+ if (req->rx_len) {
+ ret = MXC_I3C_RevA_EmitStart(i3c, false, MXC_I3C_TRANSFER_TYPE_READ, req->target_addr,
+ req->rx_len);
+ if (ret < 0) {
+ goto err;
+ }
+
+ ret = MXC_I3C_RevA_ReadRXFIFO(i3c, req->rx_buf, req->rx_len, 100);
+ if (ret < 0) {
+ goto err;
+ }
+
+ MXC_I3C_RevA_Controller_WaitForDone(i3c, 1000);
+ }
+
+ /* Check for errors */
+ ret = MXC_I3C_RevA_Controller_GetError(i3c);
+err:
+ if (req->stop || ret != E_SUCCESS) {
+ MXC_I3C_RevA_EmitStop(i3c);
+ }
+
+ return ret;
+}
+
+static int MXC_I3C_RevA_Controller_I2C(mxc_i3c_reva_regs_t *i3c, const mxc_i3c_reva_req_t *req)
+{
+ int ret = E_SUCCESS;
+ uint8_t readCount;
+ uint16_t remaining;
+
+ if (req->tx_len) {
+ ret = MXC_I3C_RevA_EmitStart(i3c, true, MXC_I3C_TRANSFER_TYPE_WRITE, req->target_addr, 0);
+ if (ret < 0) {
+ return ret;
+ }
+
+ ret = MXC_I3C_RevA_WriteTXFIFO(i3c, req->tx_buf, req->tx_len, true, 1000);
+ if (ret != req->tx_len) {
+ ret = MXC_I3C_RevA_Controller_GetError(i3c);
+ goto err;
+ }
+ MXC_I3C_RevA_Controller_WaitForDone(i3c, 1000);
+
+ ret = E_SUCCESS;
+ }
+
+ if (req->rx_len) {
+ remaining = req->rx_len;
+ while (remaining > 0) {
+ readCount = (remaining < MXC_I3C_REVA_MAX_FIFO_TRANSACTION) ?
+ remaining :
+ MXC_I3C_REVA_MAX_FIFO_TRANSACTION;
+
+ ret = MXC_I3C_RevA_EmitStart(i3c, true, MXC_I3C_TRANSFER_TYPE_READ, req->target_addr,
+ readCount);
+ if (ret < 0) {
+ goto err;
+ }
+
+ ret = MXC_I3C_RevA_ReadRXFIFO(i3c, req->rx_buf + (req->rx_len - remaining), readCount,
+ 1000);
+ if (ret == readCount) {
+ remaining -= readCount;
+ } else {
+ ret = MXC_I3C_RevA_Controller_GetError(i3c);
+ goto err;
+ }
+ }
+
+ ret = E_SUCCESS;
+ }
+
+err:
+ if (req->stop || ret != E_SUCCESS) {
+ MXC_I3C_RevA_EmitI2CStop(i3c);
+ }
+
+ return ret;
+}
+
+int MXC_I3C_RevA_Controller_Transaction(mxc_i3c_reva_regs_t *i3c, const mxc_i3c_reva_req_t *req)
+{
+ if (MXC_I3C_RevA_Controller_GetState(i3c) != MXC_V_I3C_REVA_CONT_STATUS_STATE_IDLE &&
+ MXC_I3C_RevA_Controller_GetState(i3c) != MXC_V_I3C_REVA_CONT_STATUS_STATE_SDR_NORM) {
+ return E_BUSY;
+ }
+
+ if (req->tx_len == 0 && req->rx_len == 0) {
+ return E_BAD_PARAM;
+ }
+
+ MXC_I3C_RevA_ClearTXFIFO(i3c);
+ MXC_I3C_RevA_ClearRXFIFO(i3c);
+
+ if (!req->is_i2c) {
+ return MXC_I3C_RevA_Controller_SDR(i3c, req);
+ }
+
+ return MXC_I3C_RevA_Controller_I2C(i3c, req);
+}
+
+int MXC_I3C_RevA_Controller_DAA(mxc_i3c_reva_regs_t *i3c, uint8_t addr, uint8_t *pid, uint8_t *bcr,
+ uint8_t *dcr)
+{
+ int ret;
+
+ MXC_I3C_RevA_ClearTXFIFO(i3c);
+ MXC_I3C_RevA_ClearRXFIFO(i3c);
+
+ if (MXC_I3C_RevA_Controller_GetState(i3c) == MXC_V_I3C_REVA_CONT_STATUS_STATE_DAA &&
+ GET_FIELD(cont_status, CONT_STATUS_WAIT)) {
+ MXC_I3C_RevA_WriteTXFIFO(i3c, &addr, 1, true, 10);
+ MXC_I3C_RevA_Controller_WaitForDone(i3c, 1000);
+ }
+
+ ret = MXC_I3C_RevA_ControllerRequest(i3c, MXC_V_I3C_REVA_CONT_CTRL1_REQ_PROCESS_DAA,
+ MXC_I3C_REVA_START_TYPE_SDR, 0, 0, 0);
+ if (ret == E_SUCCESS) {
+ if (MXC_I3C_RevA_Controller_GetState(i3c) == MXC_V_I3C_REVA_CONT_STATUS_STATE_DAA &&
+ GET_FIELD(cont_status, CONT_STATUS_WAIT)) {
+ MXC_I3C_RevA_ReadRXFIFO(i3c, pid, MXC_I3C_PROVISIONED_ID_LEN, 10);
+ MXC_I3C_RevA_ReadRXFIFO(i3c, bcr, 1, 1);
+ MXC_I3C_RevA_ReadRXFIFO(i3c, dcr, 1, 1);
+ } else if (MXC_I3C_RevA_Controller_GetState(i3c) == MXC_V_I3C_REVA_CONT_STATUS_STATE_IDLE &&
+ GET_FIELD(cont_status, CONT_STATUS_DONE)) {
+ ret = E_SHUTDOWN;
+ } else {
+ ret = E_FAIL;
+ }
+ }
+
+ return ret;
+}
+
+int MXC_I3C_RevA_AutoIBI(mxc_i3c_reva_regs_t *i3c)
+{
+ int timeout = 500;
+ i3c->cont_ctrl1 &= ~(MXC_F_I3C_CONT_CTRL1_REQ | MXC_F_I3C_CONT_CTRL1_IBIRESP);
+ i3c->cont_ctrl1 |= MXC_S_I3C_REVA_CONT_CTRL1_REQ_AUTO_IBI |
+ (MXC_I3C_REVA_IBIRESP_ACK << MXC_F_I3C_REVA_CONT_CTRL1_IBIRESP_POS);
+
+ while (!GET_FIELD(cont_status, CONT_STATUS_IBI_WON)) {
+ if (--timeout == 0) {
+ return E_TIME_OUT;
+ }
+ }
+ SET_FIELD(cont_status, CONT_STATUS_IBI_WON, 0);
+
+ return 0;
+}
+
+int MXC_I3C_RevA_HotJoin(mxc_i3c_reva_regs_t *i3c)
+{
+ if (!(i3c->targ_cap1 & MXC_S_I3C_REVA_TARG_CAP1_IBI_EVENTS_HJ)) {
+ return E_NOT_SUPPORTED;
+ }
+
+ if ((MXC_I3C_RevA_GetDynamicAddress(i3c) != MXC_I3C_ADDR_INVALID) ||
+ (i3c->targ_status & MXC_F_I3C_REVA_TARG_STATUS_HJ_DIS)) {
+ return E_BAD_STATE;
+ }
+
+ SET_FIELD(targ_ctrl0, TARG_CTRL0_EN, 0);
+ SET_FIELD(targ_ctrl1, TARG_CTRL1_EVENT, MXC_V_I3C_REVA_TARG_CTRL1_EVENT_HJ);
+ SET_FIELD(targ_ctrl0, TARG_CTRL0_EN, 1);
+
+ return E_SUCCESS;
+}
+
+int MXC_I3C_RevA_RequestIBI(mxc_i3c_reva_regs_t *i3c, unsigned char mdb,
+ mxc_i3c_reva_ibi_getbyte_t getByteCb)
+{
+ int ret, idx;
+ unsigned char byte;
+
+ idx = MXC_I3C_GET_IDX((mxc_i3c_regs_t *)i3c);
+ if (idx < 0) {
+ return E_BAD_PARAM;
+ }
+
+ if (!(i3c->targ_cap1 & MXC_S_I3C_REVA_TARG_CAP1_IBI_EVENTS_HJ)) {
+ return E_NOT_SUPPORTED;
+ }
+
+ if ((MXC_I3C_RevA_GetDynamicAddress(i3c) == MXC_I3C_ADDR_INVALID) ||
+ (i3c->targ_status & MXC_F_I3C_REVA_TARG_STATUS_IBI_DIS)) {
+ return E_BAD_STATE;
+ }
+
+ if (i3c->targ_status & MXC_F_I3C_REVA_TARG_STATUS_EVENT) {
+ return E_BUSY;
+ }
+
+ /* Write MDB and additional data bytes to TX FIFO */
+ controller[idx].ibiGetByteCB = getByteCb;
+ if (i3c->targ_cap1 & MXC_S_I3C_REVA_TARG_CAP1_IBI_EVENTS_PAYLOAD) {
+ if (getByteCb) {
+ while ((i3c->targ_status & MXC_F_I3C_REVA_TARG_STATUS_TX_NFULL)) {
+ ret = getByteCb(i3c, &byte);
+ if (ret) {
+ i3c->targ_txfifo8 = byte;
+ } else {
+ break;
+ }
+ }
+ }
+ SET_FIELD(targ_ctrl1, TARG_CTRL1_IBIDATA, mdb);
+ SET_FIELD(targ_ctrl1, TARG_CTRL1_EXTIBI,
+ !!(i3c->targ_fifoctrl & MXC_F_I3C_REVA_TARG_FIFOCTRL_TX_LVL));
+ }
+
+ MXC_I3C_RevA_Target_EnableInt(i3c, MXC_F_I3C_REVA_TARG_INTEN_EVENT_REQ |
+ MXC_F_I3C_REVA_TARG_INTEN_TX_NFULL |
+ MXC_F_I3C_REVA_TARG_INTEN_STOP);
+
+ SET_FIELD(targ_ctrl1, TARG_CTRL1_EVENT, MXC_V_I3C_REVA_TARG_CTRL1_EVENT_IBI);
+
+ return E_SUCCESS;
+}
+
+int MXC_I3C_RevA_Standby(mxc_i3c_reva_regs_t *i3c)
+{
+ if (MXC_I3C_RevA_GetDynamicAddress(i3c) == MXC_I3C_ADDR_INVALID) {
+ return E_BAD_STATE;
+ }
+
+ SET_FIELD(targ_ctrl0, TARG_CTRL0_EN, 0);
+
+ return E_SUCCESS;
+}
+
+int MXC_I3C_RevA_Wakeup(mxc_i3c_reva_regs_t *i3c)
+{
+ if ((MXC_I3C_RevA_GetDynamicAddress(i3c) == MXC_I3C_ADDR_INVALID) ||
+ (GET_FIELD(targ_ctrl0, TARG_CTRL0_EN))) {
+ return E_BAD_STATE;
+ }
+
+ i3c->targ_ctrl0 |= (MXC_F_I3C_REVA_TARG_CTRL0_EN | MXC_F_I3C_REVA_TARG_CTRL0_OFFLINE);
+
+ return E_SUCCESS;
+}
+
+void MXC_I3C_RevA_SetIBIPayloadCallback(mxc_i3c_reva_regs_t *i3c,
+ mxc_i3c_reva_ibi_getbyte_t payloadCb)
+{
+ int idx;
+
+ idx = MXC_I3C_GET_IDX((mxc_i3c_regs_t *)i3c);
+ if (idx >= 0) {
+ controller[idx].ibiGetByteCB = payloadCb;
+ }
+}
+
+int MXC_I3C_RevA_Controller_GetError(mxc_i3c_reva_regs_t *i3c)
+{
+ uint32_t errFlags = i3c->cont_errwarn & MXC_F_I3C_REVA_CONT_ERRWARN_MASK;
+
+ if (errFlags & MXC_F_I3C_REVA_CONT_ERRWARN_NACK) {
+ return E_NO_RESPONSE;
+ } else if (errFlags & MXC_F_I3C_REVA_CONT_ERRWARN_TX_ABT) {
+ return E_ABORT;
+ } else if (errFlags & (MXC_F_I3C_REVA_CONT_ERRWARN_INV_REQ | MXC_F_I3C_REVA_CONT_ERRWARN_MSG)) {
+ return E_BAD_STATE;
+ } else if (errFlags & MXC_F_I3C_REVA_CONT_ERRWARN_TO) {
+ return E_TIME_OUT;
+ } else if (errFlags &
+ (MXC_F_I3C_REVA_CONT_ERRWARN_RX_UNR | MXC_F_I3C_REVA_CONT_ERRWARN_TX_OVR)) {
+ return E_OVERFLOW;
+ }
+
+ return E_NO_ERROR;
+}
+
+void MXC_I3C_RevA_Controller_ClearError(mxc_i3c_reva_regs_t *i3c)
+{
+ i3c->cont_errwarn = MXC_F_I3C_REVA_CONT_ERRWARN_MASK;
+}
+
+int MXC_I3C_RevA_SetRXTXThreshold(mxc_i3c_reva_regs_t *i3c, mxc_i3c_reva_rx_threshold_t rxth,
+ mxc_i3c_reva_tx_threshold_t txth)
+{
+ if (rxth > MXC_V_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL ||
+ txth > MXC_V_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_ALMOST_FULL) {
+ return E_BAD_PARAM;
+ }
+
+ i3c->cont_fifoctrl &=
+ ~(MXC_F_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL | MXC_F_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL);
+ i3c->cont_fifoctrl = (rxth << MXC_F_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_POS) |
+ (txth << MXC_F_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_POS) |
+ MXC_F_I3C_REVA_CONT_FIFOCTRL_UNLOCK;
+
+ return E_SUCCESS;
+}
+
+int MXC_I3C_RevA_ReadRXFIFO(mxc_i3c_reva_regs_t *i3c, volatile unsigned char *bytes,
+ unsigned int len, int timeout)
+{
+ unsigned int readb = 0;
+
+ if (timeout == 0) {
+ timeout = 1;
+ } else if ((timeout > 0) && (timeout < (len + 1))) {
+ timeout = len + 1;
+ }
+
+ while ((len > readb) && (timeout != 0)) {
+ if (i3c->cont_status & MXC_F_I3C_REVA_CONT_STATUS_RX_RDY) {
+ bytes[readb++] = i3c->cont_rxfifo8;
+ }
+ if (timeout > 0) {
+ timeout--;
+ }
+ }
+
+ return readb;
+}
+
+int MXC_I3C_RevA_WriteTXFIFO(mxc_i3c_reva_regs_t *i3c, const unsigned char *bytes, unsigned int len,
+ bool end, int timeout)
+{
+ unsigned int written = 0;
+
+ if (len == 0) {
+ return 0;
+ }
+
+ if (timeout == 0) {
+ timeout = 1;
+ } else if ((timeout > 0) && (timeout < (len + 1))) {
+ timeout = len + 1;
+ }
+
+ while ((len - 1 > written) && (timeout != 0)) {
+ if (i3c->cont_status & MXC_F_I3C_REVA_CONT_STATUS_TX_NFULL) {
+ i3c->cont_txfifo8o = bytes[written++];
+ }
+ if (timeout > 0) {
+ timeout--;
+ }
+ }
+
+ while ((len == written + 1) && (timeout != 0)) {
+ if (i3c->cont_status & MXC_F_I3C_REVA_CONT_STATUS_TX_NFULL) {
+ if (end) {
+ i3c->cont_txfifo8e = bytes[written++];
+ } else {
+ i3c->cont_txfifo8o = bytes[written++];
+ }
+ }
+ if (timeout > 0) {
+ timeout--;
+ }
+ }
+
+ return written;
+}
+
+void MXC_I3C_RevA_IRQHandler(mxc_i3c_reva_regs_t *i3c)
+{
+ int idx;
+
+ idx = MXC_I3C_GET_IDX((mxc_i3c_regs_t *)i3c);
+ if (idx < 0) {
+ return;
+ }
+}
diff --git a/Libraries/PeriphDrivers/Source/I3C/i3c_reva.h b/Libraries/PeriphDrivers/Source/I3C/i3c_reva.h
new file mode 100644
index 00000000000..5540a194579
--- /dev/null
+++ b/Libraries/PeriphDrivers/Source/I3C/i3c_reva.h
@@ -0,0 +1,255 @@
+/**
+* @file i3c.h
+* @brief Improved Inter Integrated Circuit (I3C) communications interface driver.
+*/
+
+/******************************************************************************
+ *
+ * Copyright (C) 2024 Analog Devices, Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************/
+
+#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_I3C_I3C_REVA_H_
+#define LIBRARIES_PERIPHDRIVERS_SOURCE_I3C_I3C_REVA_H_
+
+/* **** Includes **** */
+#include
+#include "i3c.h"
+#include "i3c_reva.h"
+#include "i3c_reva_regs.h"
+#include "mxc_sys.h"
+
+/****** Definitions *****/
+
+/**
+ * @brief Maximum supported IBI bytes.
+ *
+ */
+#define MXC_I3C_REVA_MAX_IBI_BYTES 7U
+
+typedef struct _i3c_reva_ccc_req_t mxc_i3c_reva_ccc_req_t;
+typedef struct _i3c_reva_req_t mxc_i3c_reva_req_t;
+
+/**
+ * @brief The list of high-keeper options.
+ *
+ * This setting should match the high-keeper implementation of the device.
+ */
+typedef enum {
+ MXC_I3C_REVA_HIGH_KEEPER_OFF = MXC_S_I3C_REVA_CONT_CTRL0_HKEEP_OFF, ///< No high-keeper support
+ MXC_I3C_REVA_HIGH_KEEPER_ON_CHIP =
+ MXC_S_I3C_REVA_CONT_CTRL0_HKEEP_ON_CHIP, ///< SCL and SDA pads
+ ///< have weak pull-ups
+ MXC_I3C_REVA_HIGH_KEEPER_EXT_SDA =
+ MXC_S_I3C_REVA_CONT_CTRL0_HKEEP_EXT_SDA, ///< External high-keeper
+ ///< support for SDA signal
+ MXC_I3C_REVA_HIGH_KEEPER_EXT_SCL_SDA = MXC_S_I3C_REVA_CONT_CTRL0_HKEEP_EXT_SCL_SDA,
+ ///< External high-keeper support for SCL and SDA signals
+} mxc_i3c_reva_high_keeper_t;
+
+/**
+ * @brief The list of receive FIFO trigger levels.
+ */
+typedef enum {
+ MXC_I3C_REVA_RX_TH_NOT_EMPTY = MXC_V_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_NOT_EMPTY, ///<
+ MXC_I3C_REVA_RX_TH_QUARTER_FULL = MXC_V_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_QUARTER_FULL, ///<
+ MXC_I3C_REVA_RX_TH_HALF_FULL = MXC_V_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_HALF_FULL, ///<
+ MXC_I3C_REVA_RX_TH_3_QUARTER_FULL = MXC_V_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL, ///<
+} mxc_i3c_reva_rx_threshold_t;
+
+/**
+ * @brief The list of transmit FIFO trigger levels.
+ */
+typedef enum {
+ MXC_I3C_REVA_TX_TH_EMPTY = MXC_V_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_EMPTY, ///<
+ MXC_I3C_REVA_TX_TH_QUARTER_FULL = MXC_V_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_QUARTER_FULL, ///<
+ MXC_I3C_REVA_TX_TH_HALF_FULL = MXC_V_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_HALF_FULL, ///<
+ MXC_I3C_REVA_TX_TH_ALMOST_FULL = MXC_V_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_ALMOST_FULL, ///<
+} mxc_i3c_reva_tx_threshold_t;
+
+/**
+ * @brief IBI types.
+ *
+ */
+typedef enum {
+ MXC_I3C_REVA_IBI_TYPE_NONE = MXC_V_I3C_REVA_CONT_STATUS_IBITYPE_NONE, ///<
+ MXC_I3C_REVA_IBI_TYPE_IBI = MXC_V_I3C_REVA_CONT_STATUS_IBITYPE_IBI, ///<
+ MXC_I3C_REVA_IBI_TYPE_CONTROLLER_REQ = MXC_V_I3C_REVA_CONT_STATUS_IBITYPE_CONT_REQ, ///<
+ MXC_I3C_REVA_IBI_TYPE_HOTJOIN_REQ = MXC_V_I3C_REVA_CONT_STATUS_IBITYPE_HOTJOIN_REQ, ///<
+} mxc_i3c_reva_ibi_type_t;
+
+/**
+ * @brief Common Command Code request structure.
+ *
+ * Broadcast and direct commands are distinguished by MSB, i.e. if MSB being set
+ * implies a direct CCC while MSB being 0 implies a broadcast CCC.
+ *
+ */
+struct _i3c_reva_ccc_req_t {
+ uint8_t ccc; ///< CCC command to send.
+ uint8_t target_addr; ///< Target address if CCC is a direct command. Ignored
+ ///< if CCC is a broadcast command.
+ mxc_i3c_transfer_type_t xfer_type; ///< Transfer type. Ignored for broadcast CCCs.
+ uint8_t flags; ///< See request flags above.
+ uint8_t def_byte; ///< Optional defining byte. Defined by CCC.
+ uint8_t sub_cmd; ///< Optional sub-command. Defined by CCC. Only used by direct
+ ///< CCCs.
+ unsigned char *tx_buf; ///< Optional data bytes to send.
+ uint8_t tx_len; ///< Length of optional data.
+ unsigned char *rx_buf; ///< Optional data bytes to read.
+ uint8_t rx_len; ///< Length of optional data.
+};
+
+/**
+ * @brief Private SDR request structure.
+ *
+ * SDR read and write to an I3C target.
+ *
+ */
+struct _i3c_reva_req_t {
+ uint8_t target_addr; ///< Target address.
+ bool is_i2c; ///< If this is a legacy I2C transfer.
+ bool stop; ///< Send a STOP after the transaction.
+ unsigned char *tx_buf; ///< Optional data bytes to send.
+ uint16_t tx_len; ///< Length of optional data.
+ unsigned char *rx_buf; ///< Optional data bytes to read.
+ uint16_t rx_len; ///< Length of optional data.
+};
+
+/**
+ * @brief IBI payload request callback. Write additional byte to \a byte.
+ *
+ * This function will be called as long as non-zero is returned.
+ *
+ * @return Non-zero if a byte is written to \a byte, 0 to indicate no more additional
+ * bytes left to send.
+ */
+typedef int (*mxc_i3c_reva_ibi_getbyte_t)(mxc_i3c_reva_regs_t *i3c, unsigned char *byte);
+
+/* **** Function Prototypes **** */
+
+/* ************************************************************************* */
+/* Control/Configuration functions */
+/* ************************************************************************* */
+
+int MXC_I3C_RevA_Init(mxc_i3c_reva_regs_t *i3c, bool targetMode, uint8_t staticAddr);
+int MXC_I3C_RevA_Recover(mxc_i3c_reva_regs_t *i3c);
+int MXC_I3C_RevA_Shutdown(mxc_i3c_reva_regs_t *i3c);
+int MXC_I3C_RevA_SetPPFrequency(mxc_i3c_reva_regs_t *i3c, unsigned int frequency);
+unsigned int MXC_I3C_RevA_GetPPFrequency(mxc_i3c_reva_regs_t *i3c);
+int MXC_I3C_RevA_SetODFrequency(mxc_i3c_reva_regs_t *i3c, unsigned int frequency, bool highPP);
+unsigned int MXC_I3C_RevA_GetODFrequency(mxc_i3c_reva_regs_t *i3c);
+int MXC_I3C_RevA_SetI2CFrequency(mxc_i3c_reva_regs_t *i3c, unsigned int frequency);
+unsigned int MXC_I3C_RevA_GetI2CFrequency(mxc_i3c_reva_regs_t *i3c);
+uint8_t MXC_I3C_RevA_GetDynamicAddress(mxc_i3c_reva_regs_t *i3c);
+int MXC_I3C_RevA_SetSkew(mxc_i3c_reva_regs_t *i3c, uint8_t skew);
+int MXC_I3C_RevA_SetHighKeeperMode(mxc_i3c_reva_regs_t *i3c, mxc_i3c_reva_high_keeper_t hkeep);
+
+/* ************************************************************************* */
+/* Protocol functions */
+/* ************************************************************************* */
+int MXC_I3C_RevA_EmitStart(mxc_i3c_reva_regs_t *i3c, bool isI2C, mxc_i3c_transfer_type_t xferType,
+ uint8_t addr, uint8_t readCount);
+int MXC_I3C_RevA_ResetTarget(mxc_i3c_reva_regs_t *i3c);
+void MXC_I3C_RevA_EmitStop(mxc_i3c_reva_regs_t *i3c);
+void MXC_I3C_RevA_EmitI2CStop(mxc_i3c_reva_regs_t *i3c);
+int MXC_I3C_RevA_Controller_CCC(mxc_i3c_reva_regs_t *i3c, const mxc_i3c_reva_ccc_req_t *req);
+int MXC_I3C_RevA_Controller_Transaction(mxc_i3c_reva_regs_t *i3c, const mxc_i3c_reva_req_t *req);
+int MXC_I3C_RevA_Controller_DAA(mxc_i3c_reva_regs_t *i3c, uint8_t addr, uint8_t *pid, uint8_t *bcr,
+ uint8_t *dcr);
+int MXC_I3C_RevA_AutoIBI(mxc_i3c_reva_regs_t *i3c);
+int MXC_I3C_RevA_HotJoin(mxc_i3c_reva_regs_t *i3c);
+int MXC_I3C_RevA_RequestIBI(mxc_i3c_reva_regs_t *i3c, unsigned char mdb,
+ mxc_i3c_reva_ibi_getbyte_t getByteCb);
+int MXC_I3C_RevA_Standby(mxc_i3c_reva_regs_t *i3c);
+int MXC_I3C_RevA_Wakeup(mxc_i3c_reva_regs_t *i3c);
+
+/* ************************************************************************* */
+/* Low-level functions */
+/* ************************************************************************* */
+int MXC_I3C_RevA_Controller_GetError(mxc_i3c_reva_regs_t *i3c);
+void MXC_I3C_RevA_Controller_ClearError(mxc_i3c_reva_regs_t *i3c);
+
+int MXC_I3C_RevA_SetRXTXThreshold(mxc_i3c_reva_regs_t *i3c, mxc_i3c_reva_rx_threshold_t rxth,
+ mxc_i3c_reva_tx_threshold_t txth);
+int MXC_I3C_RevA_ReadRXFIFO(mxc_i3c_reva_regs_t *i3c, volatile unsigned char *bytes,
+ unsigned int len, int timeout);
+int MXC_I3C_RevA_WriteTXFIFO(mxc_i3c_reva_regs_t *i3c, const unsigned char *bytes, unsigned int len,
+ bool end, int timeout);
+void MXC_I3C_RevA_IRQHandler(mxc_i3c_reva_regs_t *i3c);
+
+static inline void MXC_I3C_RevA_ClearRXFIFO(mxc_i3c_reva_regs_t *i3c)
+{
+ i3c->cont_fifoctrl |= MXC_F_I3C_REVA_CONT_FIFOCTRL_RX_FLUSH;
+}
+
+static inline void MXC_I3C_RevA_ClearTXFIFO(mxc_i3c_reva_regs_t *i3c)
+{
+ i3c->cont_fifoctrl |= MXC_F_I3C_REVA_CONT_FIFOCTRL_TX_FLUSH;
+}
+
+static inline unsigned int MXC_I3C_RevA_Controller_GetRXCount(mxc_i3c_reva_regs_t *i3c)
+{
+ return ((i3c->cont_fifoctrl & MXC_F_I3C_REVA_CONT_FIFOCTRL_RX_LVL) >>
+ MXC_F_I3C_REVA_CONT_FIFOCTRL_RX_LVL_POS);
+}
+
+static inline unsigned int MXC_I3C_RevA_Controller_GetTXCount(mxc_i3c_reva_regs_t *i3c)
+{
+ return ((i3c->cont_fifoctrl & MXC_F_I3C_REVA_CONT_FIFOCTRL_TX_LVL) >>
+ MXC_F_I3C_REVA_CONT_FIFOCTRL_TX_LVL_POS);
+}
+
+static inline void MXC_I3C_RevA_Controller_EnableInt(mxc_i3c_reva_regs_t *i3c, uint32_t mask)
+{
+ i3c->cont_inten |= mask;
+}
+
+static inline void MXC_I3C_RevA_Controller_DisableInt(mxc_i3c_reva_regs_t *i3c, uint32_t mask)
+{
+ i3c->cont_intclr |= mask;
+}
+
+static inline unsigned int MXC_I3C_RevA_Controller_GetFlags(mxc_i3c_reva_regs_t *i3c)
+{
+ return i3c->cont_intfl;
+}
+
+static inline void MXC_I3C_RevA_Controller_ClearFlags(mxc_i3c_reva_regs_t *i3c, uint32_t mask)
+{
+ i3c->cont_status |= mask;
+}
+
+static inline void MXC_I3C_RevA_Target_EnableInt(mxc_i3c_reva_regs_t *i3c, uint32_t mask)
+{
+ i3c->targ_inten |= mask;
+}
+
+static inline void MXC_I3C_RevA_Target_DisableInt(mxc_i3c_reva_regs_t *i3c, uint32_t mask)
+{
+ i3c->targ_intclr |= mask;
+}
+
+static inline int MXC_I3C_RevA_Target_GetFlags(mxc_i3c_reva_regs_t *i3c)
+{
+ return i3c->targ_intfl;
+}
+
+static inline void MXC_I3C_RevA_Target_ClearFlags(mxc_i3c_reva_regs_t *i3c, uint32_t mask)
+{
+ i3c->targ_status |= mask;
+}
+
+#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_I3C_I3C_REVA_H_
diff --git a/Libraries/PeriphDrivers/Source/I3C/i3c_reva.svd b/Libraries/PeriphDrivers/Source/I3C/i3c_reva.svd
index 0135661cb41..a177eab96ae 100644
--- a/Libraries/PeriphDrivers/Source/I3C/i3c_reva.svd
+++ b/Libraries/PeriphDrivers/Source/I3C/i3c_reva.svd
@@ -1221,11 +1221,60 @@
CCCH
CCC Handled by IP.
[15:12]
+
+
+ BASIC
+ Basic CCCs.
+ 1
+
+
+ LIMITS
+ CCCs related to maximum transfer lengths and speed.
+ 2
+
+
+ INTACT
+ Pending Interrupt and Activity Mode fields of GETSTATUS CCC.
+ 4
+
+
+ VENDOR
+ Vendor Reserved field of GETSTATUS CCC.
+ 8
+
+
IBI_EVENTS
Supported IBI events.
[20:16]
+
+
+ IBI
+ IBI support.
+ 1
+
+
+ PAYLOAD
+ IBI has payload.
+ 2
+
+
+ CONTREQ
+ Controller request support.
+ 4
+
+
+ HJ
+ Hot-Join support.
+ 8
+
+
+ BAMATCH
+ Use BAMATCH field of CONFIG register to measure 1us Bus Available timing.
+ 16
+
+
TIMECTRL
@@ -1590,12 +1639,12 @@
CONT_REQ
Controller request.
- 1
+ 2
HOTJOIN_REQ
Hot-Join request.
- 1
+ 3
@@ -2403,4 +2452,4 @@
-
\ No newline at end of file
+
diff --git a/Libraries/PeriphDrivers/Source/I3C/i3c_reva_regs.h b/Libraries/PeriphDrivers/Source/I3C/i3c_reva_regs.h
new file mode 100644
index 00000000000..d26b87101ad
--- /dev/null
+++ b/Libraries/PeriphDrivers/Source/I3C/i3c_reva_regs.h
@@ -0,0 +1,1619 @@
+/**
+ * @file i3c_reva_regs.h
+ * @brief Registers, Bit Masks and Bit Positions for the I3C_REVA Peripheral Module.
+ * @note This file is @generated.
+ * @ingroup i3c_reva_registers
+ */
+
+/******************************************************************************
+ *
+ * Copyright (C) 2024 Analog Devices, Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************/
+
+#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_I3C_I3C_REVA_REGS_H_
+#define LIBRARIES_PERIPHDRIVERS_SOURCE_I3C_I3C_REVA_REGS_H_
+
+/* **** Includes **** */
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined (__ICCARM__)
+ #pragma system_include
+#endif
+
+#if defined (__CC_ARM)
+ #pragma anon_unions
+#endif
+/// @cond
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __R
+#define __R volatile const
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup i3c_reva
+ * @defgroup i3c_reva_registers I3C_REVA_Registers
+ * @brief Registers, Bit Masks and Bit Positions for the I3C_REVA Peripheral Module.
+ * @details Improved Inter-Integrated Circuit.
+ */
+
+/**
+ * @ingroup i3c_reva_registers
+ * Structure type to access the I3C_REVA Registers.
+ */
+typedef struct {
+ __IO uint32_t cont_ctrl0; /**< \b 0x000: I3C_REVA CONT_CTRL0 Register */
+ __IO uint32_t targ_ctrl0; /**< \b 0x004: I3C_REVA TARG_CTRL0 Register */
+ __IO uint32_t targ_status; /**< \b 0x008: I3C_REVA TARG_STATUS Register */
+ __IO uint32_t targ_ctrl1; /**< \b 0x00C: I3C_REVA TARG_CTRL1 Register */
+ __IO uint32_t targ_inten; /**< \b 0x010: I3C_REVA TARG_INTEN Register */
+ __O uint32_t targ_intclr; /**< \b 0x014: I3C_REVA TARG_INTCLR Register */
+ __I uint32_t targ_intfl; /**< \b 0x018: I3C_REVA TARG_INTFL Register */
+ __IO uint32_t targ_errwarn; /**< \b 0x01C: I3C_REVA TARG_ERRWARN Register */
+ __IO uint32_t targ_dmactrl; /**< \b 0x020: I3C_REVA TARG_DMACTRL Register */
+ __R uint32_t rsv_0x24_0x2b[2];
+ __IO uint32_t targ_fifoctrl; /**< \b 0x02C: I3C_REVA TARG_FIFOCTRL Register */
+ __O uint32_t targ_txfifo8; /**< \b 0x030: I3C_REVA TARG_TXFIFO8 Register */
+ __O uint32_t targ_txfifo8e; /**< \b 0x034: I3C_REVA TARG_TXFIFO8E Register */
+ __O uint32_t targ_txfifo16; /**< \b 0x038: I3C_REVA TARG_TXFIFO16 Register */
+ __O uint32_t targ_txfifo16e; /**< \b 0x03C: I3C_REVA TARG_TXFIFO16E Register */
+ __I uint32_t targ_rxfifo8; /**< \b 0x040: I3C_REVA TARG_RXFIFO8 Register */
+ __R uint32_t rsv_0x44;
+ __I uint32_t targ_rxfifo16; /**< \b 0x048: I3C_REVA TARG_RXFIFO16 Register */
+ __R uint32_t rsv_0x4c_0x53[2];
+ __O uint32_t targ_txfifo8o; /**< \b 0x054: I3C_REVA TARG_TXFIFO8O Register */
+ __R uint32_t rsv_0x58;
+ __I uint32_t targ_cap0; /**< \b 0x05C: I3C_REVA TARG_CAP0 Register */
+ __I uint32_t targ_cap1; /**< \b 0x060: I3C_REVA TARG_CAP1 Register */
+ __IO uint32_t targ_dynaddr; /**< \b 0x064: I3C_REVA TARG_DYNADDR Register */
+ __IO uint32_t targ_maxlimits; /**< \b 0x068: I3C_REVA TARG_MAXLIMITS Register */
+ __R uint32_t rsv_0x6c;
+ __IO uint32_t targ_idext; /**< \b 0x070: I3C_REVA TARG_IDEXT Register */
+ __R uint32_t rsv_0x74_0x7b[2];
+ __I uint32_t targ_msglast; /**< \b 0x07C: I3C_REVA TARG_MSGLAST Register */
+ __R uint32_t rsv_0x80;
+ __IO uint32_t cont_ctrl1; /**< \b 0x084: I3C_REVA CONT_CTRL1 Register */
+ __IO uint32_t cont_status; /**< \b 0x088: I3C_REVA CONT_STATUS Register */
+ __IO uint32_t cont_ibirules; /**< \b 0x08C: I3C_REVA CONT_IBIRULES Register */
+ __IO uint32_t cont_inten; /**< \b 0x090: I3C_REVA CONT_INTEN Register */
+ __O uint32_t cont_intclr; /**< \b 0x094: I3C_REVA CONT_INTCLR Register */
+ __I uint32_t cont_intfl; /**< \b 0x098: I3C_REVA CONT_INTFL Register */
+ __IO uint32_t cont_errwarn; /**< \b 0x09C: I3C_REVA CONT_ERRWARN Register */
+ __IO uint32_t cont_dmactrl; /**< \b 0x0A0: I3C_REVA CONT_DMACTRL Register */
+ __R uint32_t rsv_0xa4_0xab[2];
+ __IO uint32_t cont_fifoctrl; /**< \b 0x0AC: I3C_REVA CONT_FIFOCTRL Register */
+ __O uint32_t cont_txfifo8; /**< \b 0x0B0: I3C_REVA CONT_TXFIFO8 Register */
+ __O uint32_t cont_txfifo8e; /**< \b 0x0B4: I3C_REVA CONT_TXFIFO8E Register */
+ __O uint32_t cont_txfifo16; /**< \b 0x0B8: I3C_REVA CONT_TXFIFO16 Register */
+ __O uint32_t cont_txfifo16e; /**< \b 0x0BC: I3C_REVA CONT_TXFIFO16E Register */
+ __I uint32_t cont_rxfifo8; /**< \b 0x0C0: I3C_REVA CONT_RXFIFO8 Register */
+ __R uint32_t rsv_0xc4;
+ __I uint32_t cont_rxfifo16; /**< \b 0x0C8: I3C_REVA CONT_RXFIFO16 Register */
+ __O uint32_t cont_txfifo8o; /**< \b 0x0CC: I3C_REVA CONT_TXFIFO8O Register */
+ union {
+ __IO uint32_t cont_txsdrmsg_ctrl; /**< \b 0x0D0: I3C_REVA CONT_TXSDRMSG_CTRL Register */
+ __O uint32_t cont_txsdrmsg_fifo; /**< \b 0x0D0: I3C_REVA CONT_TXSDRMSG_FIFO Register */
+ };
+ __I uint32_t cont_rxsdrmsg; /**< \b 0x0D4: I3C_REVA CONT_RXSDRMSG Register */
+ __O uint32_t cont_txddrmsg; /**< \b 0x0D8: I3C_REVA CONT_TXDDRMSG Register */
+ __I uint32_t cont_rxddr16; /**< \b 0x0DC: I3C_REVA CONT_RXDDR16 Register */
+ __R uint32_t rsv_0xe0;
+ __IO uint32_t cont_dynaddr; /**< \b 0x0E4: I3C_REVA CONT_DYNADDR Register */
+ __R uint32_t rsv_0xe8_0x113[11];
+ __I uint32_t targ_groupdef; /**< \b 0x114: I3C_REVA TARG_GROUPDEF Register */
+ __R uint32_t rsv_0x118;
+ __IO uint32_t targ_mapctrl0; /**< \b 0x11C: I3C_REVA TARG_MAPCTRL0 Register */
+ __IO uint32_t targ_mapctrl1; /**< \b 0x120: I3C_REVA TARG_MAPCTRL1 Register */
+ __IO uint32_t targ_mapctrl2; /**< \b 0x124: I3C_REVA TARG_MAPCTRL2 Register */
+} mxc_i3c_reva_regs_t;
+
+/* Register offsets for module I3C_REVA */
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_Register_Offsets Register Offsets
+ * @brief I3C_REVA Peripheral Register Offsets from the I3C_REVA Base Peripheral Address.
+ * @{
+ */
+#define MXC_R_I3C_REVA_CONT_CTRL0 ((uint32_t)0x00000000UL) /**< Offset from I3C_REVA Base Address: 0x0000 */
+#define MXC_R_I3C_REVA_TARG_CTRL0 ((uint32_t)0x00000004UL) /**< Offset from I3C_REVA Base Address: 0x0004 */
+#define MXC_R_I3C_REVA_TARG_STATUS ((uint32_t)0x00000008UL) /**< Offset from I3C_REVA Base Address: 0x0008 */
+#define MXC_R_I3C_REVA_TARG_CTRL1 ((uint32_t)0x0000000CUL) /**< Offset from I3C_REVA Base Address: 0x000C */
+#define MXC_R_I3C_REVA_TARG_INTEN ((uint32_t)0x00000010UL) /**< Offset from I3C_REVA Base Address: 0x0010 */
+#define MXC_R_I3C_REVA_TARG_INTCLR ((uint32_t)0x00000014UL) /**< Offset from I3C_REVA Base Address: 0x0014 */
+#define MXC_R_I3C_REVA_TARG_INTFL ((uint32_t)0x00000018UL) /**< Offset from I3C_REVA Base Address: 0x0018 */
+#define MXC_R_I3C_REVA_TARG_ERRWARN ((uint32_t)0x0000001CUL) /**< Offset from I3C_REVA Base Address: 0x001C */
+#define MXC_R_I3C_REVA_TARG_DMACTRL ((uint32_t)0x00000020UL) /**< Offset from I3C_REVA Base Address: 0x0020 */
+#define MXC_R_I3C_REVA_TARG_FIFOCTRL ((uint32_t)0x0000002CUL) /**< Offset from I3C_REVA Base Address: 0x002C */
+#define MXC_R_I3C_REVA_TARG_TXFIFO8 ((uint32_t)0x00000030UL) /**< Offset from I3C_REVA Base Address: 0x0030 */
+#define MXC_R_I3C_REVA_TARG_TXFIFO8E ((uint32_t)0x00000034UL) /**< Offset from I3C_REVA Base Address: 0x0034 */
+#define MXC_R_I3C_REVA_TARG_TXFIFO16 ((uint32_t)0x00000038UL) /**< Offset from I3C_REVA Base Address: 0x0038 */
+#define MXC_R_I3C_REVA_TARG_TXFIFO16E ((uint32_t)0x0000003CUL) /**< Offset from I3C_REVA Base Address: 0x003C */
+#define MXC_R_I3C_REVA_TARG_RXFIFO8 ((uint32_t)0x00000040UL) /**< Offset from I3C_REVA Base Address: 0x0040 */
+#define MXC_R_I3C_REVA_TARG_RXFIFO16 ((uint32_t)0x00000048UL) /**< Offset from I3C_REVA Base Address: 0x0048 */
+#define MXC_R_I3C_REVA_TARG_TXFIFO8O ((uint32_t)0x00000054UL) /**< Offset from I3C_REVA Base Address: 0x0054 */
+#define MXC_R_I3C_REVA_TARG_CAP0 ((uint32_t)0x0000005CUL) /**< Offset from I3C_REVA Base Address: 0x005C */
+#define MXC_R_I3C_REVA_TARG_CAP1 ((uint32_t)0x00000060UL) /**< Offset from I3C_REVA Base Address: 0x0060 */
+#define MXC_R_I3C_REVA_TARG_DYNADDR ((uint32_t)0x00000064UL) /**< Offset from I3C_REVA Base Address: 0x0064 */
+#define MXC_R_I3C_REVA_TARG_MAXLIMITS ((uint32_t)0x00000068UL) /**< Offset from I3C_REVA Base Address: 0x0068 */
+#define MXC_R_I3C_REVA_TARG_IDEXT ((uint32_t)0x00000070UL) /**< Offset from I3C_REVA Base Address: 0x0070 */
+#define MXC_R_I3C_REVA_TARG_MSGLAST ((uint32_t)0x0000007CUL) /**< Offset from I3C_REVA Base Address: 0x007C */
+#define MXC_R_I3C_REVA_CONT_CTRL1 ((uint32_t)0x00000084UL) /**< Offset from I3C_REVA Base Address: 0x0084 */
+#define MXC_R_I3C_REVA_CONT_STATUS ((uint32_t)0x00000088UL) /**< Offset from I3C_REVA Base Address: 0x0088 */
+#define MXC_R_I3C_REVA_CONT_IBIRULES ((uint32_t)0x0000008CUL) /**< Offset from I3C_REVA Base Address: 0x008C */
+#define MXC_R_I3C_REVA_CONT_INTEN ((uint32_t)0x00000090UL) /**< Offset from I3C_REVA Base Address: 0x0090 */
+#define MXC_R_I3C_REVA_CONT_INTCLR ((uint32_t)0x00000094UL) /**< Offset from I3C_REVA Base Address: 0x0094 */
+#define MXC_R_I3C_REVA_CONT_INTFL ((uint32_t)0x00000098UL) /**< Offset from I3C_REVA Base Address: 0x0098 */
+#define MXC_R_I3C_REVA_CONT_ERRWARN ((uint32_t)0x0000009CUL) /**< Offset from I3C_REVA Base Address: 0x009C */
+#define MXC_R_I3C_REVA_CONT_DMACTRL ((uint32_t)0x000000A0UL) /**< Offset from I3C_REVA Base Address: 0x00A0 */
+#define MXC_R_I3C_REVA_CONT_FIFOCTRL ((uint32_t)0x000000ACUL) /**< Offset from I3C_REVA Base Address: 0x00AC */
+#define MXC_R_I3C_REVA_CONT_TXFIFO8 ((uint32_t)0x000000B0UL) /**< Offset from I3C_REVA Base Address: 0x00B0 */
+#define MXC_R_I3C_REVA_CONT_TXFIFO8E ((uint32_t)0x000000B4UL) /**< Offset from I3C_REVA Base Address: 0x00B4 */
+#define MXC_R_I3C_REVA_CONT_TXFIFO16 ((uint32_t)0x000000B8UL) /**< Offset from I3C_REVA Base Address: 0x00B8 */
+#define MXC_R_I3C_REVA_CONT_TXFIFO16E ((uint32_t)0x000000BCUL) /**< Offset from I3C_REVA Base Address: 0x00BC */
+#define MXC_R_I3C_REVA_CONT_RXFIFO8 ((uint32_t)0x000000C0UL) /**< Offset from I3C_REVA Base Address: 0x00C0 */
+#define MXC_R_I3C_REVA_CONT_RXFIFO16 ((uint32_t)0x000000C8UL) /**< Offset from I3C_REVA Base Address: 0x00C8 */
+#define MXC_R_I3C_REVA_CONT_TXFIFO8O ((uint32_t)0x000000CCUL) /**< Offset from I3C_REVA Base Address: 0x00CC */
+#define MXC_R_I3C_REVA_CONT_TXSDRMSG_CTRL ((uint32_t)0x000000D0UL) /**< Offset from I3C_REVA Base Address: 0x00D0 */
+#define MXC_R_I3C_REVA_CONT_TXSDRMSG_FIFO ((uint32_t)0x000000D0UL) /**< Offset from I3C_REVA Base Address: 0x00D0 */
+#define MXC_R_I3C_REVA_CONT_RXSDRMSG ((uint32_t)0x000000D4UL) /**< Offset from I3C_REVA Base Address: 0x00D4 */
+#define MXC_R_I3C_REVA_CONT_TXDDRMSG ((uint32_t)0x000000D8UL) /**< Offset from I3C_REVA Base Address: 0x00D8 */
+#define MXC_R_I3C_REVA_CONT_RXDDR16 ((uint32_t)0x000000DCUL) /**< Offset from I3C_REVA Base Address: 0x00DC */
+#define MXC_R_I3C_REVA_CONT_DYNADDR ((uint32_t)0x000000E4UL) /**< Offset from I3C_REVA Base Address: 0x00E4 */
+#define MXC_R_I3C_REVA_TARG_GROUPDEF ((uint32_t)0x00000114UL) /**< Offset from I3C_REVA Base Address: 0x0114 */
+#define MXC_R_I3C_REVA_TARG_MAPCTRL0 ((uint32_t)0x0000011CUL) /**< Offset from I3C_REVA Base Address: 0x011C */
+#define MXC_R_I3C_REVA_TARG_MAPCTRL1 ((uint32_t)0x00000120UL) /**< Offset from I3C_REVA Base Address: 0x0120 */
+#define MXC_R_I3C_REVA_TARG_MAPCTRL2 ((uint32_t)0x00000124UL) /**< Offset from I3C_REVA Base Address: 0x0124 */
+/**@} end of group i3c_reva_registers */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_CONT_CTRL0 I3C_REVA_CONT_CTRL0
+ * @brief Controller Control 0 (Configuration) Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_CONT_CTRL0_EN_POS 0 /**< CONT_CTRL0_EN Position */
+#define MXC_F_I3C_REVA_CONT_CTRL0_EN ((uint32_t)(0x3UL << MXC_F_I3C_REVA_CONT_CTRL0_EN_POS)) /**< CONT_CTRL0_EN Mask */
+#define MXC_V_I3C_REVA_CONT_CTRL0_EN_OFF ((uint32_t)0x0UL) /**< CONT_CTRL0_EN_OFF Value */
+#define MXC_S_I3C_REVA_CONT_CTRL0_EN_OFF (MXC_V_I3C_REVA_CONT_CTRL0_EN_OFF << MXC_F_I3C_REVA_CONT_CTRL0_EN_POS) /**< CONT_CTRL0_EN_OFF Setting */
+#define MXC_V_I3C_REVA_CONT_CTRL0_EN_ON ((uint32_t)0x1UL) /**< CONT_CTRL0_EN_ON Value */
+#define MXC_S_I3C_REVA_CONT_CTRL0_EN_ON (MXC_V_I3C_REVA_CONT_CTRL0_EN_ON << MXC_F_I3C_REVA_CONT_CTRL0_EN_POS) /**< CONT_CTRL0_EN_ON Setting */
+#define MXC_V_I3C_REVA_CONT_CTRL0_EN_CAP ((uint32_t)0x2UL) /**< CONT_CTRL0_EN_CAP Value */
+#define MXC_S_I3C_REVA_CONT_CTRL0_EN_CAP (MXC_V_I3C_REVA_CONT_CTRL0_EN_CAP << MXC_F_I3C_REVA_CONT_CTRL0_EN_POS) /**< CONT_CTRL0_EN_CAP Setting */
+
+#define MXC_F_I3C_REVA_CONT_CTRL0_TO_DIS_POS 3 /**< CONT_CTRL0_TO_DIS Position */
+#define MXC_F_I3C_REVA_CONT_CTRL0_TO_DIS ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_CTRL0_TO_DIS_POS)) /**< CONT_CTRL0_TO_DIS Mask */
+
+#define MXC_F_I3C_REVA_CONT_CTRL0_HKEEP_POS 4 /**< CONT_CTRL0_HKEEP Position */
+#define MXC_F_I3C_REVA_CONT_CTRL0_HKEEP ((uint32_t)(0x3UL << MXC_F_I3C_REVA_CONT_CTRL0_HKEEP_POS)) /**< CONT_CTRL0_HKEEP Mask */
+#define MXC_V_I3C_REVA_CONT_CTRL0_HKEEP_OFF ((uint32_t)0x0UL) /**< CONT_CTRL0_HKEEP_OFF Value */
+#define MXC_S_I3C_REVA_CONT_CTRL0_HKEEP_OFF (MXC_V_I3C_REVA_CONT_CTRL0_HKEEP_OFF << MXC_F_I3C_REVA_CONT_CTRL0_HKEEP_POS) /**< CONT_CTRL0_HKEEP_OFF Setting */
+#define MXC_V_I3C_REVA_CONT_CTRL0_HKEEP_ON_CHIP ((uint32_t)0x1UL) /**< CONT_CTRL0_HKEEP_ON_CHIP Value */
+#define MXC_S_I3C_REVA_CONT_CTRL0_HKEEP_ON_CHIP (MXC_V_I3C_REVA_CONT_CTRL0_HKEEP_ON_CHIP << MXC_F_I3C_REVA_CONT_CTRL0_HKEEP_POS) /**< CONT_CTRL0_HKEEP_ON_CHIP Setting */
+#define MXC_V_I3C_REVA_CONT_CTRL0_HKEEP_EXT_SDA ((uint32_t)0x2UL) /**< CONT_CTRL0_HKEEP_EXT_SDA Value */
+#define MXC_S_I3C_REVA_CONT_CTRL0_HKEEP_EXT_SDA (MXC_V_I3C_REVA_CONT_CTRL0_HKEEP_EXT_SDA << MXC_F_I3C_REVA_CONT_CTRL0_HKEEP_POS) /**< CONT_CTRL0_HKEEP_EXT_SDA Setting */
+#define MXC_V_I3C_REVA_CONT_CTRL0_HKEEP_EXT_SCL_SDA ((uint32_t)0x3UL) /**< CONT_CTRL0_HKEEP_EXT_SCL_SDA Value */
+#define MXC_S_I3C_REVA_CONT_CTRL0_HKEEP_EXT_SCL_SDA (MXC_V_I3C_REVA_CONT_CTRL0_HKEEP_EXT_SCL_SDA << MXC_F_I3C_REVA_CONT_CTRL0_HKEEP_POS) /**< CONT_CTRL0_HKEEP_EXT_SCL_SDA Setting */
+
+#define MXC_F_I3C_REVA_CONT_CTRL0_OD_STOP_POS 6 /**< CONT_CTRL0_OD_STOP Position */
+#define MXC_F_I3C_REVA_CONT_CTRL0_OD_STOP ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_CTRL0_OD_STOP_POS)) /**< CONT_CTRL0_OD_STOP Mask */
+
+#define MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS 8 /**< CONT_CTRL0_PP_BAUD Position */
+#define MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD ((uint32_t)(0xFUL << MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS)) /**< CONT_CTRL0_PP_BAUD Mask */
+#define MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_1_FCLK ((uint32_t)0x0UL) /**< CONT_CTRL0_PP_BAUD_1_FCLK Value */
+#define MXC_S_I3C_REVA_CONT_CTRL0_PP_BAUD_1_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_1_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_1_FCLK Setting */
+#define MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_2_FCLK ((uint32_t)0x1UL) /**< CONT_CTRL0_PP_BAUD_2_FCLK Value */
+#define MXC_S_I3C_REVA_CONT_CTRL0_PP_BAUD_2_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_2_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_2_FCLK Setting */
+#define MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_3_FCLK ((uint32_t)0x2UL) /**< CONT_CTRL0_PP_BAUD_3_FCLK Value */
+#define MXC_S_I3C_REVA_CONT_CTRL0_PP_BAUD_3_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_3_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_3_FCLK Setting */
+#define MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_4_FCLK ((uint32_t)0x3UL) /**< CONT_CTRL0_PP_BAUD_4_FCLK Value */
+#define MXC_S_I3C_REVA_CONT_CTRL0_PP_BAUD_4_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_4_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_4_FCLK Setting */
+#define MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_5_FCLK ((uint32_t)0x4UL) /**< CONT_CTRL0_PP_BAUD_5_FCLK Value */
+#define MXC_S_I3C_REVA_CONT_CTRL0_PP_BAUD_5_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_5_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_5_FCLK Setting */
+#define MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_6_FCLK ((uint32_t)0x5UL) /**< CONT_CTRL0_PP_BAUD_6_FCLK Value */
+#define MXC_S_I3C_REVA_CONT_CTRL0_PP_BAUD_6_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_6_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_6_FCLK Setting */
+#define MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_7_FCLK ((uint32_t)0x6UL) /**< CONT_CTRL0_PP_BAUD_7_FCLK Value */
+#define MXC_S_I3C_REVA_CONT_CTRL0_PP_BAUD_7_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_7_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_7_FCLK Setting */
+#define MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_8_FCLK ((uint32_t)0x7UL) /**< CONT_CTRL0_PP_BAUD_8_FCLK Value */
+#define MXC_S_I3C_REVA_CONT_CTRL0_PP_BAUD_8_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_8_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_8_FCLK Setting */
+#define MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_9_FCLK ((uint32_t)0x8UL) /**< CONT_CTRL0_PP_BAUD_9_FCLK Value */
+#define MXC_S_I3C_REVA_CONT_CTRL0_PP_BAUD_9_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_9_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_9_FCLK Setting */
+#define MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_10_FCLK ((uint32_t)0x9UL) /**< CONT_CTRL0_PP_BAUD_10_FCLK Value */
+#define MXC_S_I3C_REVA_CONT_CTRL0_PP_BAUD_10_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_10_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_10_FCLK Setting */
+#define MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_11_FCLK ((uint32_t)0xAUL) /**< CONT_CTRL0_PP_BAUD_11_FCLK Value */
+#define MXC_S_I3C_REVA_CONT_CTRL0_PP_BAUD_11_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_11_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_11_FCLK Setting */
+#define MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_12_FCLK ((uint32_t)0xBUL) /**< CONT_CTRL0_PP_BAUD_12_FCLK Value */
+#define MXC_S_I3C_REVA_CONT_CTRL0_PP_BAUD_12_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_12_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_12_FCLK Setting */
+#define MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_13_FCLK ((uint32_t)0xCUL) /**< CONT_CTRL0_PP_BAUD_13_FCLK Value */
+#define MXC_S_I3C_REVA_CONT_CTRL0_PP_BAUD_13_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_13_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_13_FCLK Setting */
+#define MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_14_FCLK ((uint32_t)0xDUL) /**< CONT_CTRL0_PP_BAUD_14_FCLK Value */
+#define MXC_S_I3C_REVA_CONT_CTRL0_PP_BAUD_14_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_14_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_14_FCLK Setting */
+#define MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_15_FCLK ((uint32_t)0xEUL) /**< CONT_CTRL0_PP_BAUD_15_FCLK Value */
+#define MXC_S_I3C_REVA_CONT_CTRL0_PP_BAUD_15_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_15_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_15_FCLK Setting */
+#define MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_16_FCLK ((uint32_t)0xFUL) /**< CONT_CTRL0_PP_BAUD_16_FCLK Value */
+#define MXC_S_I3C_REVA_CONT_CTRL0_PP_BAUD_16_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_16_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_16_FCLK Setting */
+
+#define MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_POS 12 /**< CONT_CTRL0_PP_ADD_LBAUD Position */
+#define MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD ((uint32_t)(0xFUL << MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_POS)) /**< CONT_CTRL0_PP_ADD_LBAUD Mask */
+#define MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_0_FCLK ((uint32_t)0x0UL) /**< CONT_CTRL0_PP_ADD_LBAUD_0_FCLK Value */
+#define MXC_S_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_0_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_0_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_0_FCLK Setting */
+#define MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_1_FCLK ((uint32_t)0x1UL) /**< CONT_CTRL0_PP_ADD_LBAUD_1_FCLK Value */
+#define MXC_S_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_1_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_1_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_1_FCLK Setting */
+#define MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_2_FCLK ((uint32_t)0x2UL) /**< CONT_CTRL0_PP_ADD_LBAUD_2_FCLK Value */
+#define MXC_S_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_2_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_2_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_2_FCLK Setting */
+#define MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_3_FCLK ((uint32_t)0x3UL) /**< CONT_CTRL0_PP_ADD_LBAUD_3_FCLK Value */
+#define MXC_S_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_3_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_3_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_3_FCLK Setting */
+#define MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_4_FCLK ((uint32_t)0x4UL) /**< CONT_CTRL0_PP_ADD_LBAUD_4_FCLK Value */
+#define MXC_S_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_4_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_4_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_4_FCLK Setting */
+#define MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_5_FCLK ((uint32_t)0x5UL) /**< CONT_CTRL0_PP_ADD_LBAUD_5_FCLK Value */
+#define MXC_S_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_5_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_5_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_5_FCLK Setting */
+#define MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_6_FCLK ((uint32_t)0x6UL) /**< CONT_CTRL0_PP_ADD_LBAUD_6_FCLK Value */
+#define MXC_S_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_6_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_6_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_6_FCLK Setting */
+#define MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_7_FCLK ((uint32_t)0x7UL) /**< CONT_CTRL0_PP_ADD_LBAUD_7_FCLK Value */
+#define MXC_S_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_7_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_7_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_7_FCLK Setting */
+#define MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_8_FCLK ((uint32_t)0x8UL) /**< CONT_CTRL0_PP_ADD_LBAUD_8_FCLK Value */
+#define MXC_S_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_8_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_8_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_8_FCLK Setting */
+#define MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_9_FCLK ((uint32_t)0x9UL) /**< CONT_CTRL0_PP_ADD_LBAUD_9_FCLK Value */
+#define MXC_S_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_9_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_9_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_9_FCLK Setting */
+#define MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_10_FCLK ((uint32_t)0xAUL) /**< CONT_CTRL0_PP_ADD_LBAUD_10_FCLK Value */
+#define MXC_S_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_10_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_10_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_10_FCLK Setting */
+#define MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_11_FCLK ((uint32_t)0xBUL) /**< CONT_CTRL0_PP_ADD_LBAUD_11_FCLK Value */
+#define MXC_S_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_11_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_11_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_11_FCLK Setting */
+#define MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_12_FCLK ((uint32_t)0xCUL) /**< CONT_CTRL0_PP_ADD_LBAUD_12_FCLK Value */
+#define MXC_S_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_12_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_12_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_12_FCLK Setting */
+#define MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_13_FCLK ((uint32_t)0xDUL) /**< CONT_CTRL0_PP_ADD_LBAUD_13_FCLK Value */
+#define MXC_S_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_13_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_13_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_13_FCLK Setting */
+#define MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_14_FCLK ((uint32_t)0xEUL) /**< CONT_CTRL0_PP_ADD_LBAUD_14_FCLK Value */
+#define MXC_S_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_14_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_14_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_14_FCLK Setting */
+#define MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_15_FCLK ((uint32_t)0xFUL) /**< CONT_CTRL0_PP_ADD_LBAUD_15_FCLK Value */
+#define MXC_S_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_15_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_15_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_15_FCLK Setting */
+
+#define MXC_F_I3C_REVA_CONT_CTRL0_OD_LBAUD_POS 16 /**< CONT_CTRL0_OD_LBAUD Position */
+#define MXC_F_I3C_REVA_CONT_CTRL0_OD_LBAUD ((uint32_t)(0xFFUL << MXC_F_I3C_REVA_CONT_CTRL0_OD_LBAUD_POS)) /**< CONT_CTRL0_OD_LBAUD Mask */
+
+#define MXC_F_I3C_REVA_CONT_CTRL0_OD_HP_POS 24 /**< CONT_CTRL0_OD_HP Position */
+#define MXC_F_I3C_REVA_CONT_CTRL0_OD_HP ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_CTRL0_OD_HP_POS)) /**< CONT_CTRL0_OD_HP Mask */
+
+#define MXC_F_I3C_REVA_CONT_CTRL0_PP_SKEW_POS 25 /**< CONT_CTRL0_PP_SKEW Position */
+#define MXC_F_I3C_REVA_CONT_CTRL0_PP_SKEW ((uint32_t)(0x7UL << MXC_F_I3C_REVA_CONT_CTRL0_PP_SKEW_POS)) /**< CONT_CTRL0_PP_SKEW Mask */
+
+#define MXC_F_I3C_REVA_CONT_CTRL0_I2C_BAUD_POS 28 /**< CONT_CTRL0_I2C_BAUD Position */
+#define MXC_F_I3C_REVA_CONT_CTRL0_I2C_BAUD ((uint32_t)(0xFUL << MXC_F_I3C_REVA_CONT_CTRL0_I2C_BAUD_POS)) /**< CONT_CTRL0_I2C_BAUD Mask */
+
+/**@} end of group I3C_REVA_CONT_CTRL0_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_TARG_CTRL0 I3C_REVA_TARG_CTRL0
+ * @brief Target Control 0 (Configuration) Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_TARG_CTRL0_EN_POS 0 /**< TARG_CTRL0_EN Position */
+#define MXC_F_I3C_REVA_TARG_CTRL0_EN ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_CTRL0_EN_POS)) /**< TARG_CTRL0_EN Mask */
+
+#define MXC_F_I3C_REVA_TARG_CTRL0_MATCHSS_POS 2 /**< TARG_CTRL0_MATCHSS Position */
+#define MXC_F_I3C_REVA_TARG_CTRL0_MATCHSS ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_CTRL0_MATCHSS_POS)) /**< TARG_CTRL0_MATCHSS Mask */
+
+#define MXC_F_I3C_REVA_TARG_CTRL0_TO_IGN_POS 3 /**< TARG_CTRL0_TO_IGN Position */
+#define MXC_F_I3C_REVA_TARG_CTRL0_TO_IGN ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_CTRL0_TO_IGN_POS)) /**< TARG_CTRL0_TO_IGN Mask */
+
+#define MXC_F_I3C_REVA_TARG_CTRL0_OFFLINE_POS 9 /**< TARG_CTRL0_OFFLINE Position */
+#define MXC_F_I3C_REVA_TARG_CTRL0_OFFLINE ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_CTRL0_OFFLINE_POS)) /**< TARG_CTRL0_OFFLINE Mask */
+
+/**@} end of group I3C_REVA_TARG_CTRL0_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_TARG_STATUS I3C_REVA_TARG_STATUS
+ * @brief Target Status Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_TARG_STATUS_BUSY_POS 0 /**< TARG_STATUS_BUSY Position */
+#define MXC_F_I3C_REVA_TARG_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_STATUS_BUSY_POS)) /**< TARG_STATUS_BUSY Mask */
+
+#define MXC_F_I3C_REVA_TARG_STATUS_LIST_RESP_POS 1 /**< TARG_STATUS_LIST_RESP Position */
+#define MXC_F_I3C_REVA_TARG_STATUS_LIST_RESP ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_STATUS_LIST_RESP_POS)) /**< TARG_STATUS_LIST_RESP Mask */
+
+#define MXC_F_I3C_REVA_TARG_STATUS_CCCH_POS 2 /**< TARG_STATUS_CCCH Position */
+#define MXC_F_I3C_REVA_TARG_STATUS_CCCH ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_STATUS_CCCH_POS)) /**< TARG_STATUS_CCCH Mask */
+
+#define MXC_F_I3C_REVA_TARG_STATUS_RX_SDR_POS 3 /**< TARG_STATUS_RX_SDR Position */
+#define MXC_F_I3C_REVA_TARG_STATUS_RX_SDR ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_STATUS_RX_SDR_POS)) /**< TARG_STATUS_RX_SDR Mask */
+
+#define MXC_F_I3C_REVA_TARG_STATUS_TX_SDR_POS 4 /**< TARG_STATUS_TX_SDR Position */
+#define MXC_F_I3C_REVA_TARG_STATUS_TX_SDR ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_STATUS_TX_SDR_POS)) /**< TARG_STATUS_TX_SDR Mask */
+
+#define MXC_F_I3C_REVA_TARG_STATUS_DAA_POS 5 /**< TARG_STATUS_DAA Position */
+#define MXC_F_I3C_REVA_TARG_STATUS_DAA ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_STATUS_DAA_POS)) /**< TARG_STATUS_DAA Mask */
+
+#define MXC_F_I3C_REVA_TARG_STATUS_HDR_POS 6 /**< TARG_STATUS_HDR Position */
+#define MXC_F_I3C_REVA_TARG_STATUS_HDR ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_STATUS_HDR_POS)) /**< TARG_STATUS_HDR Mask */
+
+#define MXC_F_I3C_REVA_TARG_STATUS_START_POS 8 /**< TARG_STATUS_START Position */
+#define MXC_F_I3C_REVA_TARG_STATUS_START ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_STATUS_START_POS)) /**< TARG_STATUS_START Mask */
+
+#define MXC_F_I3C_REVA_TARG_STATUS_ADDRMATCH_POS 9 /**< TARG_STATUS_ADDRMATCH Position */
+#define MXC_F_I3C_REVA_TARG_STATUS_ADDRMATCH ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_STATUS_ADDRMATCH_POS)) /**< TARG_STATUS_ADDRMATCH Mask */
+
+#define MXC_F_I3C_REVA_TARG_STATUS_STOP_POS 10 /**< TARG_STATUS_STOP Position */
+#define MXC_F_I3C_REVA_TARG_STATUS_STOP ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_STATUS_STOP_POS)) /**< TARG_STATUS_STOP Mask */
+
+#define MXC_F_I3C_REVA_TARG_STATUS_RX_RDY_POS 11 /**< TARG_STATUS_RX_RDY Position */
+#define MXC_F_I3C_REVA_TARG_STATUS_RX_RDY ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_STATUS_RX_RDY_POS)) /**< TARG_STATUS_RX_RDY Mask */
+
+#define MXC_F_I3C_REVA_TARG_STATUS_TX_NFULL_POS 12 /**< TARG_STATUS_TX_NFULL Position */
+#define MXC_F_I3C_REVA_TARG_STATUS_TX_NFULL ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_STATUS_TX_NFULL_POS)) /**< TARG_STATUS_TX_NFULL Mask */
+
+#define MXC_F_I3C_REVA_TARG_STATUS_DYNADDR_CHG_POS 13 /**< TARG_STATUS_DYNADDR_CHG Position */
+#define MXC_F_I3C_REVA_TARG_STATUS_DYNADDR_CHG ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_STATUS_DYNADDR_CHG_POS)) /**< TARG_STATUS_DYNADDR_CHG Mask */
+
+#define MXC_F_I3C_REVA_TARG_STATUS_CCC_POS 14 /**< TARG_STATUS_CCC Position */
+#define MXC_F_I3C_REVA_TARG_STATUS_CCC ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_STATUS_CCC_POS)) /**< TARG_STATUS_CCC Mask */
+
+#define MXC_F_I3C_REVA_TARG_STATUS_ERRWARN_POS 15 /**< TARG_STATUS_ERRWARN Position */
+#define MXC_F_I3C_REVA_TARG_STATUS_ERRWARN ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_STATUS_ERRWARN_POS)) /**< TARG_STATUS_ERRWARN Mask */
+
+#define MXC_F_I3C_REVA_TARG_STATUS_CCCH_DONE_POS 17 /**< TARG_STATUS_CCCH_DONE Position */
+#define MXC_F_I3C_REVA_TARG_STATUS_CCCH_DONE ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_STATUS_CCCH_DONE_POS)) /**< TARG_STATUS_CCCH_DONE Mask */
+
+#define MXC_F_I3C_REVA_TARG_STATUS_EVENT_REQ_POS 18 /**< TARG_STATUS_EVENT_REQ Position */
+#define MXC_F_I3C_REVA_TARG_STATUS_EVENT_REQ ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_STATUS_EVENT_REQ_POS)) /**< TARG_STATUS_EVENT_REQ Mask */
+
+#define MXC_F_I3C_REVA_TARG_STATUS_TARG_RST_POS 19 /**< TARG_STATUS_TARG_RST Position */
+#define MXC_F_I3C_REVA_TARG_STATUS_TARG_RST ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_STATUS_TARG_RST_POS)) /**< TARG_STATUS_TARG_RST Mask */
+
+#define MXC_F_I3C_REVA_TARG_STATUS_EVENT_POS 20 /**< TARG_STATUS_EVENT Position */
+#define MXC_F_I3C_REVA_TARG_STATUS_EVENT ((uint32_t)(0x3UL << MXC_F_I3C_REVA_TARG_STATUS_EVENT_POS)) /**< TARG_STATUS_EVENT Mask */
+#define MXC_V_I3C_REVA_TARG_STATUS_EVENT_NONE ((uint32_t)0x0UL) /**< TARG_STATUS_EVENT_NONE Value */
+#define MXC_S_I3C_REVA_TARG_STATUS_EVENT_NONE (MXC_V_I3C_REVA_TARG_STATUS_EVENT_NONE << MXC_F_I3C_REVA_TARG_STATUS_EVENT_POS) /**< TARG_STATUS_EVENT_NONE Setting */
+#define MXC_V_I3C_REVA_TARG_STATUS_EVENT_REQ_PEND ((uint32_t)0x1UL) /**< TARG_STATUS_EVENT_REQ_PEND Value */
+#define MXC_S_I3C_REVA_TARG_STATUS_EVENT_REQ_PEND (MXC_V_I3C_REVA_TARG_STATUS_EVENT_REQ_PEND << MXC_F_I3C_REVA_TARG_STATUS_EVENT_POS) /**< TARG_STATUS_EVENT_REQ_PEND Setting */
+#define MXC_V_I3C_REVA_TARG_STATUS_EVENT_REQ_NACK ((uint32_t)0x2UL) /**< TARG_STATUS_EVENT_REQ_NACK Value */
+#define MXC_S_I3C_REVA_TARG_STATUS_EVENT_REQ_NACK (MXC_V_I3C_REVA_TARG_STATUS_EVENT_REQ_NACK << MXC_F_I3C_REVA_TARG_STATUS_EVENT_POS) /**< TARG_STATUS_EVENT_REQ_NACK Setting */
+#define MXC_V_I3C_REVA_TARG_STATUS_EVENT_REQ_ACK ((uint32_t)0x3UL) /**< TARG_STATUS_EVENT_REQ_ACK Value */
+#define MXC_S_I3C_REVA_TARG_STATUS_EVENT_REQ_ACK (MXC_V_I3C_REVA_TARG_STATUS_EVENT_REQ_ACK << MXC_F_I3C_REVA_TARG_STATUS_EVENT_POS) /**< TARG_STATUS_EVENT_REQ_ACK Setting */
+
+#define MXC_F_I3C_REVA_TARG_STATUS_IBI_DIS_POS 24 /**< TARG_STATUS_IBI_DIS Position */
+#define MXC_F_I3C_REVA_TARG_STATUS_IBI_DIS ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_STATUS_IBI_DIS_POS)) /**< TARG_STATUS_IBI_DIS Mask */
+
+#define MXC_F_I3C_REVA_TARG_STATUS_CONTREQ_DIS_POS 25 /**< TARG_STATUS_CONTREQ_DIS Position */
+#define MXC_F_I3C_REVA_TARG_STATUS_CONTREQ_DIS ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_STATUS_CONTREQ_DIS_POS)) /**< TARG_STATUS_CONTREQ_DIS Mask */
+
+#define MXC_F_I3C_REVA_TARG_STATUS_HJ_DIS_POS 27 /**< TARG_STATUS_HJ_DIS Position */
+#define MXC_F_I3C_REVA_TARG_STATUS_HJ_DIS ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_STATUS_HJ_DIS_POS)) /**< TARG_STATUS_HJ_DIS Mask */
+
+#define MXC_F_I3C_REVA_TARG_STATUS_ACTSTATE_POS 28 /**< TARG_STATUS_ACTSTATE Position */
+#define MXC_F_I3C_REVA_TARG_STATUS_ACTSTATE ((uint32_t)(0x3UL << MXC_F_I3C_REVA_TARG_STATUS_ACTSTATE_POS)) /**< TARG_STATUS_ACTSTATE Mask */
+#define MXC_V_I3C_REVA_TARG_STATUS_ACTSTATE_NORMAL ((uint32_t)0x0UL) /**< TARG_STATUS_ACTSTATE_NORMAL Value */
+#define MXC_S_I3C_REVA_TARG_STATUS_ACTSTATE_NORMAL (MXC_V_I3C_REVA_TARG_STATUS_ACTSTATE_NORMAL << MXC_F_I3C_REVA_TARG_STATUS_ACTSTATE_POS) /**< TARG_STATUS_ACTSTATE_NORMAL Setting */
+#define MXC_V_I3C_REVA_TARG_STATUS_ACTSTATE_1MS_LAT ((uint32_t)0x1UL) /**< TARG_STATUS_ACTSTATE_1MS_LAT Value */
+#define MXC_S_I3C_REVA_TARG_STATUS_ACTSTATE_1MS_LAT (MXC_V_I3C_REVA_TARG_STATUS_ACTSTATE_1MS_LAT << MXC_F_I3C_REVA_TARG_STATUS_ACTSTATE_POS) /**< TARG_STATUS_ACTSTATE_1MS_LAT Setting */
+#define MXC_V_I3C_REVA_TARG_STATUS_ACTSTATE_100MS_LAT ((uint32_t)0x2UL) /**< TARG_STATUS_ACTSTATE_100MS_LAT Value */
+#define MXC_S_I3C_REVA_TARG_STATUS_ACTSTATE_100MS_LAT (MXC_V_I3C_REVA_TARG_STATUS_ACTSTATE_100MS_LAT << MXC_F_I3C_REVA_TARG_STATUS_ACTSTATE_POS) /**< TARG_STATUS_ACTSTATE_100MS_LAT Setting */
+#define MXC_V_I3C_REVA_TARG_STATUS_ACTSTATE_10S_LAT ((uint32_t)0x3UL) /**< TARG_STATUS_ACTSTATE_10S_LAT Value */
+#define MXC_S_I3C_REVA_TARG_STATUS_ACTSTATE_10S_LAT (MXC_V_I3C_REVA_TARG_STATUS_ACTSTATE_10S_LAT << MXC_F_I3C_REVA_TARG_STATUS_ACTSTATE_POS) /**< TARG_STATUS_ACTSTATE_10S_LAT Setting */
+
+#define MXC_F_I3C_REVA_TARG_STATUS_TIMECTRL_POS 30 /**< TARG_STATUS_TIMECTRL Position */
+#define MXC_F_I3C_REVA_TARG_STATUS_TIMECTRL ((uint32_t)(0x3UL << MXC_F_I3C_REVA_TARG_STATUS_TIMECTRL_POS)) /**< TARG_STATUS_TIMECTRL Mask */
+#define MXC_V_I3C_REVA_TARG_STATUS_TIMECTRL_DIS ((uint32_t)0x0UL) /**< TARG_STATUS_TIMECTRL_DIS Value */
+#define MXC_S_I3C_REVA_TARG_STATUS_TIMECTRL_DIS (MXC_V_I3C_REVA_TARG_STATUS_TIMECTRL_DIS << MXC_F_I3C_REVA_TARG_STATUS_TIMECTRL_POS) /**< TARG_STATUS_TIMECTRL_DIS Setting */
+#define MXC_V_I3C_REVA_TARG_STATUS_TIMECTRL_SYNC ((uint32_t)0x1UL) /**< TARG_STATUS_TIMECTRL_SYNC Value */
+#define MXC_S_I3C_REVA_TARG_STATUS_TIMECTRL_SYNC (MXC_V_I3C_REVA_TARG_STATUS_TIMECTRL_SYNC << MXC_F_I3C_REVA_TARG_STATUS_TIMECTRL_POS) /**< TARG_STATUS_TIMECTRL_SYNC Setting */
+#define MXC_V_I3C_REVA_TARG_STATUS_TIMECTRL_ASYNC ((uint32_t)0x2UL) /**< TARG_STATUS_TIMECTRL_ASYNC Value */
+#define MXC_S_I3C_REVA_TARG_STATUS_TIMECTRL_ASYNC (MXC_V_I3C_REVA_TARG_STATUS_TIMECTRL_ASYNC << MXC_F_I3C_REVA_TARG_STATUS_TIMECTRL_POS) /**< TARG_STATUS_TIMECTRL_ASYNC Setting */
+#define MXC_V_I3C_REVA_TARG_STATUS_TIMECTRL_BOTH ((uint32_t)0x3UL) /**< TARG_STATUS_TIMECTRL_BOTH Value */
+#define MXC_S_I3C_REVA_TARG_STATUS_TIMECTRL_BOTH (MXC_V_I3C_REVA_TARG_STATUS_TIMECTRL_BOTH << MXC_F_I3C_REVA_TARG_STATUS_TIMECTRL_POS) /**< TARG_STATUS_TIMECTRL_BOTH Setting */
+
+/**@} end of group I3C_REVA_TARG_STATUS_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_TARG_CTRL1 I3C_REVA_TARG_CTRL1
+ * @brief Target Control 1 Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_TARG_CTRL1_EVENT_POS 0 /**< TARG_CTRL1_EVENT Position */
+#define MXC_F_I3C_REVA_TARG_CTRL1_EVENT ((uint32_t)(0x3UL << MXC_F_I3C_REVA_TARG_CTRL1_EVENT_POS)) /**< TARG_CTRL1_EVENT Mask */
+#define MXC_V_I3C_REVA_TARG_CTRL1_EVENT_NORMAL ((uint32_t)0x0UL) /**< TARG_CTRL1_EVENT_NORMAL Value */
+#define MXC_S_I3C_REVA_TARG_CTRL1_EVENT_NORMAL (MXC_V_I3C_REVA_TARG_CTRL1_EVENT_NORMAL << MXC_F_I3C_REVA_TARG_CTRL1_EVENT_POS) /**< TARG_CTRL1_EVENT_NORMAL Setting */
+#define MXC_V_I3C_REVA_TARG_CTRL1_EVENT_IBI ((uint32_t)0x1UL) /**< TARG_CTRL1_EVENT_IBI Value */
+#define MXC_S_I3C_REVA_TARG_CTRL1_EVENT_IBI (MXC_V_I3C_REVA_TARG_CTRL1_EVENT_IBI << MXC_F_I3C_REVA_TARG_CTRL1_EVENT_POS) /**< TARG_CTRL1_EVENT_IBI Setting */
+#define MXC_V_I3C_REVA_TARG_CTRL1_EVENT_CONTREQ ((uint32_t)0x2UL) /**< TARG_CTRL1_EVENT_CONTREQ Value */
+#define MXC_S_I3C_REVA_TARG_CTRL1_EVENT_CONTREQ (MXC_V_I3C_REVA_TARG_CTRL1_EVENT_CONTREQ << MXC_F_I3C_REVA_TARG_CTRL1_EVENT_POS) /**< TARG_CTRL1_EVENT_CONTREQ Setting */
+#define MXC_V_I3C_REVA_TARG_CTRL1_EVENT_HJ ((uint32_t)0x3UL) /**< TARG_CTRL1_EVENT_HJ Value */
+#define MXC_S_I3C_REVA_TARG_CTRL1_EVENT_HJ (MXC_V_I3C_REVA_TARG_CTRL1_EVENT_HJ << MXC_F_I3C_REVA_TARG_CTRL1_EVENT_POS) /**< TARG_CTRL1_EVENT_HJ Setting */
+
+#define MXC_F_I3C_REVA_TARG_CTRL1_EXTIBI_POS 3 /**< TARG_CTRL1_EXTIBI Position */
+#define MXC_F_I3C_REVA_TARG_CTRL1_EXTIBI ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_CTRL1_EXTIBI_POS)) /**< TARG_CTRL1_EXTIBI Mask */
+
+#define MXC_F_I3C_REVA_TARG_CTRL1_DYNADDR_IDX_POS 4 /**< TARG_CTRL1_DYNADDR_IDX Position */
+#define MXC_F_I3C_REVA_TARG_CTRL1_DYNADDR_IDX ((uint32_t)(0xFUL << MXC_F_I3C_REVA_TARG_CTRL1_DYNADDR_IDX_POS)) /**< TARG_CTRL1_DYNADDR_IDX Mask */
+
+#define MXC_F_I3C_REVA_TARG_CTRL1_IBIDATA_POS 8 /**< TARG_CTRL1_IBIDATA Position */
+#define MXC_F_I3C_REVA_TARG_CTRL1_IBIDATA ((uint32_t)(0xFFUL << MXC_F_I3C_REVA_TARG_CTRL1_IBIDATA_POS)) /**< TARG_CTRL1_IBIDATA Mask */
+
+/**@} end of group I3C_REVA_TARG_CTRL1_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_TARG_INTEN I3C_REVA_TARG_INTEN
+ * @brief Target Interrupt Enable Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_TARG_INTEN_START_POS 8 /**< TARG_INTEN_START Position */
+#define MXC_F_I3C_REVA_TARG_INTEN_START ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTEN_START_POS)) /**< TARG_INTEN_START Mask */
+
+#define MXC_F_I3C_REVA_TARG_INTEN_ADDRMATCH_POS 9 /**< TARG_INTEN_ADDRMATCH Position */
+#define MXC_F_I3C_REVA_TARG_INTEN_ADDRMATCH ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTEN_ADDRMATCH_POS)) /**< TARG_INTEN_ADDRMATCH Mask */
+
+#define MXC_F_I3C_REVA_TARG_INTEN_STOP_POS 10 /**< TARG_INTEN_STOP Position */
+#define MXC_F_I3C_REVA_TARG_INTEN_STOP ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTEN_STOP_POS)) /**< TARG_INTEN_STOP Mask */
+
+#define MXC_F_I3C_REVA_TARG_INTEN_RX_RDY_POS 11 /**< TARG_INTEN_RX_RDY Position */
+#define MXC_F_I3C_REVA_TARG_INTEN_RX_RDY ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTEN_RX_RDY_POS)) /**< TARG_INTEN_RX_RDY Mask */
+
+#define MXC_F_I3C_REVA_TARG_INTEN_TX_NFULL_POS 12 /**< TARG_INTEN_TX_NFULL Position */
+#define MXC_F_I3C_REVA_TARG_INTEN_TX_NFULL ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTEN_TX_NFULL_POS)) /**< TARG_INTEN_TX_NFULL Mask */
+
+#define MXC_F_I3C_REVA_TARG_INTEN_DYNADDR_CHG_POS 13 /**< TARG_INTEN_DYNADDR_CHG Position */
+#define MXC_F_I3C_REVA_TARG_INTEN_DYNADDR_CHG ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTEN_DYNADDR_CHG_POS)) /**< TARG_INTEN_DYNADDR_CHG Mask */
+
+#define MXC_F_I3C_REVA_TARG_INTEN_CCC_POS 14 /**< TARG_INTEN_CCC Position */
+#define MXC_F_I3C_REVA_TARG_INTEN_CCC ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTEN_CCC_POS)) /**< TARG_INTEN_CCC Mask */
+
+#define MXC_F_I3C_REVA_TARG_INTEN_ERRWARN_POS 15 /**< TARG_INTEN_ERRWARN Position */
+#define MXC_F_I3C_REVA_TARG_INTEN_ERRWARN ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTEN_ERRWARN_POS)) /**< TARG_INTEN_ERRWARN Mask */
+
+#define MXC_F_I3C_REVA_TARG_INTEN_CCCH_DONE_POS 17 /**< TARG_INTEN_CCCH_DONE Position */
+#define MXC_F_I3C_REVA_TARG_INTEN_CCCH_DONE ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTEN_CCCH_DONE_POS)) /**< TARG_INTEN_CCCH_DONE Mask */
+
+#define MXC_F_I3C_REVA_TARG_INTEN_EVENT_REQ_POS 18 /**< TARG_INTEN_EVENT_REQ Position */
+#define MXC_F_I3C_REVA_TARG_INTEN_EVENT_REQ ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTEN_EVENT_REQ_POS)) /**< TARG_INTEN_EVENT_REQ Mask */
+
+#define MXC_F_I3C_REVA_TARG_INTEN_TARG_RST_POS 19 /**< TARG_INTEN_TARG_RST Position */
+#define MXC_F_I3C_REVA_TARG_INTEN_TARG_RST ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTEN_TARG_RST_POS)) /**< TARG_INTEN_TARG_RST Mask */
+
+/**@} end of group I3C_REVA_TARG_INTEN_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_TARG_INTCLR I3C_REVA_TARG_INTCLR
+ * @brief Target Interrupt Clear Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_TARG_INTCLR_START_POS 8 /**< TARG_INTCLR_START Position */
+#define MXC_F_I3C_REVA_TARG_INTCLR_START ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTCLR_START_POS)) /**< TARG_INTCLR_START Mask */
+
+#define MXC_F_I3C_REVA_TARG_INTCLR_ADDRMATCH_POS 9 /**< TARG_INTCLR_ADDRMATCH Position */
+#define MXC_F_I3C_REVA_TARG_INTCLR_ADDRMATCH ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTCLR_ADDRMATCH_POS)) /**< TARG_INTCLR_ADDRMATCH Mask */
+
+#define MXC_F_I3C_REVA_TARG_INTCLR_STOP_POS 10 /**< TARG_INTCLR_STOP Position */
+#define MXC_F_I3C_REVA_TARG_INTCLR_STOP ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTCLR_STOP_POS)) /**< TARG_INTCLR_STOP Mask */
+
+#define MXC_F_I3C_REVA_TARG_INTCLR_RX_RDY_POS 11 /**< TARG_INTCLR_RX_RDY Position */
+#define MXC_F_I3C_REVA_TARG_INTCLR_RX_RDY ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTCLR_RX_RDY_POS)) /**< TARG_INTCLR_RX_RDY Mask */
+
+#define MXC_F_I3C_REVA_TARG_INTCLR_TX_NFULL_POS 12 /**< TARG_INTCLR_TX_NFULL Position */
+#define MXC_F_I3C_REVA_TARG_INTCLR_TX_NFULL ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTCLR_TX_NFULL_POS)) /**< TARG_INTCLR_TX_NFULL Mask */
+
+#define MXC_F_I3C_REVA_TARG_INTCLR_DYNADDR_CHG_POS 13 /**< TARG_INTCLR_DYNADDR_CHG Position */
+#define MXC_F_I3C_REVA_TARG_INTCLR_DYNADDR_CHG ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTCLR_DYNADDR_CHG_POS)) /**< TARG_INTCLR_DYNADDR_CHG Mask */
+
+#define MXC_F_I3C_REVA_TARG_INTCLR_CCC_POS 14 /**< TARG_INTCLR_CCC Position */
+#define MXC_F_I3C_REVA_TARG_INTCLR_CCC ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTCLR_CCC_POS)) /**< TARG_INTCLR_CCC Mask */
+
+#define MXC_F_I3C_REVA_TARG_INTCLR_ERRWARN_POS 15 /**< TARG_INTCLR_ERRWARN Position */
+#define MXC_F_I3C_REVA_TARG_INTCLR_ERRWARN ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTCLR_ERRWARN_POS)) /**< TARG_INTCLR_ERRWARN Mask */
+
+#define MXC_F_I3C_REVA_TARG_INTCLR_CCCH_DONE_POS 17 /**< TARG_INTCLR_CCCH_DONE Position */
+#define MXC_F_I3C_REVA_TARG_INTCLR_CCCH_DONE ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTCLR_CCCH_DONE_POS)) /**< TARG_INTCLR_CCCH_DONE Mask */
+
+#define MXC_F_I3C_REVA_TARG_INTCLR_EVENT_REQ_POS 18 /**< TARG_INTCLR_EVENT_REQ Position */
+#define MXC_F_I3C_REVA_TARG_INTCLR_EVENT_REQ ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTCLR_EVENT_REQ_POS)) /**< TARG_INTCLR_EVENT_REQ Mask */
+
+#define MXC_F_I3C_REVA_TARG_INTCLR_TARG_RST_POS 19 /**< TARG_INTCLR_TARG_RST Position */
+#define MXC_F_I3C_REVA_TARG_INTCLR_TARG_RST ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTCLR_TARG_RST_POS)) /**< TARG_INTCLR_TARG_RST Mask */
+
+/**@} end of group I3C_REVA_TARG_INTCLR_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_TARG_INTFL I3C_REVA_TARG_INTFL
+ * @brief Target Interrupt Flag Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_TARG_INTFL_START_POS 8 /**< TARG_INTFL_START Position */
+#define MXC_F_I3C_REVA_TARG_INTFL_START ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTFL_START_POS)) /**< TARG_INTFL_START Mask */
+
+#define MXC_F_I3C_REVA_TARG_INTFL_ADDRMATCH_POS 9 /**< TARG_INTFL_ADDRMATCH Position */
+#define MXC_F_I3C_REVA_TARG_INTFL_ADDRMATCH ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTFL_ADDRMATCH_POS)) /**< TARG_INTFL_ADDRMATCH Mask */
+
+#define MXC_F_I3C_REVA_TARG_INTFL_STOP_POS 10 /**< TARG_INTFL_STOP Position */
+#define MXC_F_I3C_REVA_TARG_INTFL_STOP ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTFL_STOP_POS)) /**< TARG_INTFL_STOP Mask */
+
+#define MXC_F_I3C_REVA_TARG_INTFL_RX_RDY_POS 11 /**< TARG_INTFL_RX_RDY Position */
+#define MXC_F_I3C_REVA_TARG_INTFL_RX_RDY ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTFL_RX_RDY_POS)) /**< TARG_INTFL_RX_RDY Mask */
+
+#define MXC_F_I3C_REVA_TARG_INTFL_TX_NFULL_POS 12 /**< TARG_INTFL_TX_NFULL Position */
+#define MXC_F_I3C_REVA_TARG_INTFL_TX_NFULL ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTFL_TX_NFULL_POS)) /**< TARG_INTFL_TX_NFULL Mask */
+
+#define MXC_F_I3C_REVA_TARG_INTFL_DYNADDR_CHG_POS 13 /**< TARG_INTFL_DYNADDR_CHG Position */
+#define MXC_F_I3C_REVA_TARG_INTFL_DYNADDR_CHG ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTFL_DYNADDR_CHG_POS)) /**< TARG_INTFL_DYNADDR_CHG Mask */
+
+#define MXC_F_I3C_REVA_TARG_INTFL_CCC_POS 14 /**< TARG_INTFL_CCC Position */
+#define MXC_F_I3C_REVA_TARG_INTFL_CCC ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTFL_CCC_POS)) /**< TARG_INTFL_CCC Mask */
+
+#define MXC_F_I3C_REVA_TARG_INTFL_ERRWARN_POS 15 /**< TARG_INTFL_ERRWARN Position */
+#define MXC_F_I3C_REVA_TARG_INTFL_ERRWARN ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTFL_ERRWARN_POS)) /**< TARG_INTFL_ERRWARN Mask */
+
+#define MXC_F_I3C_REVA_TARG_INTFL_CCCH_DONE_POS 17 /**< TARG_INTFL_CCCH_DONE Position */
+#define MXC_F_I3C_REVA_TARG_INTFL_CCCH_DONE ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTFL_CCCH_DONE_POS)) /**< TARG_INTFL_CCCH_DONE Mask */
+
+#define MXC_F_I3C_REVA_TARG_INTFL_EVENT_REQ_POS 18 /**< TARG_INTFL_EVENT_REQ Position */
+#define MXC_F_I3C_REVA_TARG_INTFL_EVENT_REQ ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTFL_EVENT_REQ_POS)) /**< TARG_INTFL_EVENT_REQ Mask */
+
+#define MXC_F_I3C_REVA_TARG_INTFL_TARG_RST_POS 19 /**< TARG_INTFL_TARG_RST Position */
+#define MXC_F_I3C_REVA_TARG_INTFL_TARG_RST ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTFL_TARG_RST_POS)) /**< TARG_INTFL_TARG_RST Mask */
+
+/**@} end of group I3C_REVA_TARG_INTFL_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_TARG_ERRWARN I3C_REVA_TARG_ERRWARN
+ * @brief Target Error and Warning Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_TARG_ERRWARN_OVR_POS 0 /**< TARG_ERRWARN_OVR Position */
+#define MXC_F_I3C_REVA_TARG_ERRWARN_OVR ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_ERRWARN_OVR_POS)) /**< TARG_ERRWARN_OVR Mask */
+
+#define MXC_F_I3C_REVA_TARG_ERRWARN_UNR_POS 1 /**< TARG_ERRWARN_UNR Position */
+#define MXC_F_I3C_REVA_TARG_ERRWARN_UNR ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_ERRWARN_UNR_POS)) /**< TARG_ERRWARN_UNR Mask */
+
+#define MXC_F_I3C_REVA_TARG_ERRWARN_UNR_NACK_POS 2 /**< TARG_ERRWARN_UNR_NACK Position */
+#define MXC_F_I3C_REVA_TARG_ERRWARN_UNR_NACK ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_ERRWARN_UNR_NACK_POS)) /**< TARG_ERRWARN_UNR_NACK Mask */
+
+#define MXC_F_I3C_REVA_TARG_ERRWARN_CONT_RX_TERM_POS 3 /**< TARG_ERRWARN_CONT_RX_TERM Position */
+#define MXC_F_I3C_REVA_TARG_ERRWARN_CONT_RX_TERM ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_ERRWARN_CONT_RX_TERM_POS)) /**< TARG_ERRWARN_CONT_RX_TERM Mask */
+
+#define MXC_F_I3C_REVA_TARG_ERRWARN_INVSTART_POS 4 /**< TARG_ERRWARN_INVSTART Position */
+#define MXC_F_I3C_REVA_TARG_ERRWARN_INVSTART ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_ERRWARN_INVSTART_POS)) /**< TARG_ERRWARN_INVSTART Mask */
+
+#define MXC_F_I3C_REVA_TARG_ERRWARN_SDR_PAR_POS 8 /**< TARG_ERRWARN_SDR_PAR Position */
+#define MXC_F_I3C_REVA_TARG_ERRWARN_SDR_PAR ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_ERRWARN_SDR_PAR_POS)) /**< TARG_ERRWARN_SDR_PAR Mask */
+
+#define MXC_F_I3C_REVA_TARG_ERRWARN_TO_POS 11 /**< TARG_ERRWARN_TO Position */
+#define MXC_F_I3C_REVA_TARG_ERRWARN_TO ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_ERRWARN_TO_POS)) /**< TARG_ERRWARN_TO Mask */
+
+#define MXC_F_I3C_REVA_TARG_ERRWARN_RX_UNR_POS 16 /**< TARG_ERRWARN_RX_UNR Position */
+#define MXC_F_I3C_REVA_TARG_ERRWARN_RX_UNR ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_ERRWARN_RX_UNR_POS)) /**< TARG_ERRWARN_RX_UNR Mask */
+
+#define MXC_F_I3C_REVA_TARG_ERRWARN_TX_OVR_POS 17 /**< TARG_ERRWARN_TX_OVR Position */
+#define MXC_F_I3C_REVA_TARG_ERRWARN_TX_OVR ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_ERRWARN_TX_OVR_POS)) /**< TARG_ERRWARN_TX_OVR Mask */
+
+/**@} end of group I3C_REVA_TARG_ERRWARN_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_TARG_DMACTRL I3C_REVA_TARG_DMACTRL
+ * @brief Target DMA Control Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_TARG_DMACTRL_RX_EN_POS 0 /**< TARG_DMACTRL_RX_EN Position */
+#define MXC_F_I3C_REVA_TARG_DMACTRL_RX_EN ((uint32_t)(0x3UL << MXC_F_I3C_REVA_TARG_DMACTRL_RX_EN_POS)) /**< TARG_DMACTRL_RX_EN Mask */
+#define MXC_V_I3C_REVA_TARG_DMACTRL_RX_EN_DIS ((uint32_t)0x0UL) /**< TARG_DMACTRL_RX_EN_DIS Value */
+#define MXC_S_I3C_REVA_TARG_DMACTRL_RX_EN_DIS (MXC_V_I3C_REVA_TARG_DMACTRL_RX_EN_DIS << MXC_F_I3C_REVA_TARG_DMACTRL_RX_EN_POS) /**< TARG_DMACTRL_RX_EN_DIS Setting */
+#define MXC_V_I3C_REVA_TARG_DMACTRL_RX_EN_ONE_FR ((uint32_t)0x1UL) /**< TARG_DMACTRL_RX_EN_ONE_FR Value */
+#define MXC_S_I3C_REVA_TARG_DMACTRL_RX_EN_ONE_FR (MXC_V_I3C_REVA_TARG_DMACTRL_RX_EN_ONE_FR << MXC_F_I3C_REVA_TARG_DMACTRL_RX_EN_POS) /**< TARG_DMACTRL_RX_EN_ONE_FR Setting */
+#define MXC_V_I3C_REVA_TARG_DMACTRL_RX_EN_EN ((uint32_t)0x2UL) /**< TARG_DMACTRL_RX_EN_EN Value */
+#define MXC_S_I3C_REVA_TARG_DMACTRL_RX_EN_EN (MXC_V_I3C_REVA_TARG_DMACTRL_RX_EN_EN << MXC_F_I3C_REVA_TARG_DMACTRL_RX_EN_POS) /**< TARG_DMACTRL_RX_EN_EN Setting */
+
+#define MXC_F_I3C_REVA_TARG_DMACTRL_TX_EN_POS 2 /**< TARG_DMACTRL_TX_EN Position */
+#define MXC_F_I3C_REVA_TARG_DMACTRL_TX_EN ((uint32_t)(0x3UL << MXC_F_I3C_REVA_TARG_DMACTRL_TX_EN_POS)) /**< TARG_DMACTRL_TX_EN Mask */
+#define MXC_V_I3C_REVA_TARG_DMACTRL_TX_EN_DIS ((uint32_t)0x0UL) /**< TARG_DMACTRL_TX_EN_DIS Value */
+#define MXC_S_I3C_REVA_TARG_DMACTRL_TX_EN_DIS (MXC_V_I3C_REVA_TARG_DMACTRL_TX_EN_DIS << MXC_F_I3C_REVA_TARG_DMACTRL_TX_EN_POS) /**< TARG_DMACTRL_TX_EN_DIS Setting */
+#define MXC_V_I3C_REVA_TARG_DMACTRL_TX_EN_ONE_FR ((uint32_t)0x1UL) /**< TARG_DMACTRL_TX_EN_ONE_FR Value */
+#define MXC_S_I3C_REVA_TARG_DMACTRL_TX_EN_ONE_FR (MXC_V_I3C_REVA_TARG_DMACTRL_TX_EN_ONE_FR << MXC_F_I3C_REVA_TARG_DMACTRL_TX_EN_POS) /**< TARG_DMACTRL_TX_EN_ONE_FR Setting */
+#define MXC_V_I3C_REVA_TARG_DMACTRL_TX_EN_EN ((uint32_t)0x2UL) /**< TARG_DMACTRL_TX_EN_EN Value */
+#define MXC_S_I3C_REVA_TARG_DMACTRL_TX_EN_EN (MXC_V_I3C_REVA_TARG_DMACTRL_TX_EN_EN << MXC_F_I3C_REVA_TARG_DMACTRL_TX_EN_POS) /**< TARG_DMACTRL_TX_EN_EN Setting */
+
+#define MXC_F_I3C_REVA_TARG_DMACTRL_WIDTH_POS 4 /**< TARG_DMACTRL_WIDTH Position */
+#define MXC_F_I3C_REVA_TARG_DMACTRL_WIDTH ((uint32_t)(0x3UL << MXC_F_I3C_REVA_TARG_DMACTRL_WIDTH_POS)) /**< TARG_DMACTRL_WIDTH Mask */
+#define MXC_V_I3C_REVA_TARG_DMACTRL_WIDTH_BYTE ((uint32_t)0x0UL) /**< TARG_DMACTRL_WIDTH_BYTE Value */
+#define MXC_S_I3C_REVA_TARG_DMACTRL_WIDTH_BYTE (MXC_V_I3C_REVA_TARG_DMACTRL_WIDTH_BYTE << MXC_F_I3C_REVA_TARG_DMACTRL_WIDTH_POS) /**< TARG_DMACTRL_WIDTH_BYTE Setting */
+#define MXC_V_I3C_REVA_TARG_DMACTRL_WIDTH_HALFWORD ((uint32_t)0x2UL) /**< TARG_DMACTRL_WIDTH_HALFWORD Value */
+#define MXC_S_I3C_REVA_TARG_DMACTRL_WIDTH_HALFWORD (MXC_V_I3C_REVA_TARG_DMACTRL_WIDTH_HALFWORD << MXC_F_I3C_REVA_TARG_DMACTRL_WIDTH_POS) /**< TARG_DMACTRL_WIDTH_HALFWORD Setting */
+
+/**@} end of group I3C_REVA_TARG_DMACTRL_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_TARG_FIFOCTRL I3C_REVA_TARG_FIFOCTRL
+ * @brief Target FIFO Control Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_TARG_FIFOCTRL_TX_FLUSH_POS 0 /**< TARG_FIFOCTRL_TX_FLUSH Position */
+#define MXC_F_I3C_REVA_TARG_FIFOCTRL_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_FIFOCTRL_TX_FLUSH_POS)) /**< TARG_FIFOCTRL_TX_FLUSH Mask */
+
+#define MXC_F_I3C_REVA_TARG_FIFOCTRL_RX_FLUSH_POS 1 /**< TARG_FIFOCTRL_RX_FLUSH Position */
+#define MXC_F_I3C_REVA_TARG_FIFOCTRL_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_FIFOCTRL_RX_FLUSH_POS)) /**< TARG_FIFOCTRL_RX_FLUSH Mask */
+
+#define MXC_F_I3C_REVA_TARG_FIFOCTRL_UNLOCK_POS 3 /**< TARG_FIFOCTRL_UNLOCK Position */
+#define MXC_F_I3C_REVA_TARG_FIFOCTRL_UNLOCK ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_FIFOCTRL_UNLOCK_POS)) /**< TARG_FIFOCTRL_UNLOCK Mask */
+
+#define MXC_F_I3C_REVA_TARG_FIFOCTRL_TX_THD_LVL_POS 4 /**< TARG_FIFOCTRL_TX_THD_LVL Position */
+#define MXC_F_I3C_REVA_TARG_FIFOCTRL_TX_THD_LVL ((uint32_t)(0x3UL << MXC_F_I3C_REVA_TARG_FIFOCTRL_TX_THD_LVL_POS)) /**< TARG_FIFOCTRL_TX_THD_LVL Mask */
+#define MXC_V_I3C_REVA_TARG_FIFOCTRL_TX_THD_LVL_EMPTY ((uint32_t)0x0UL) /**< TARG_FIFOCTRL_TX_THD_LVL_EMPTY Value */
+#define MXC_S_I3C_REVA_TARG_FIFOCTRL_TX_THD_LVL_EMPTY (MXC_V_I3C_REVA_TARG_FIFOCTRL_TX_THD_LVL_EMPTY << MXC_F_I3C_REVA_TARG_FIFOCTRL_TX_THD_LVL_POS) /**< TARG_FIFOCTRL_TX_THD_LVL_EMPTY Setting */
+#define MXC_V_I3C_REVA_TARG_FIFOCTRL_TX_THD_LVL_QUARTER_FULL ((uint32_t)0x1UL) /**< TARG_FIFOCTRL_TX_THD_LVL_QUARTER_FULL Value */
+#define MXC_S_I3C_REVA_TARG_FIFOCTRL_TX_THD_LVL_QUARTER_FULL (MXC_V_I3C_REVA_TARG_FIFOCTRL_TX_THD_LVL_QUARTER_FULL << MXC_F_I3C_REVA_TARG_FIFOCTRL_TX_THD_LVL_POS) /**< TARG_FIFOCTRL_TX_THD_LVL_QUARTER_FULL Setting */
+#define MXC_V_I3C_REVA_TARG_FIFOCTRL_TX_THD_LVL_HALF_FULL ((uint32_t)0x2UL) /**< TARG_FIFOCTRL_TX_THD_LVL_HALF_FULL Value */
+#define MXC_S_I3C_REVA_TARG_FIFOCTRL_TX_THD_LVL_HALF_FULL (MXC_V_I3C_REVA_TARG_FIFOCTRL_TX_THD_LVL_HALF_FULL << MXC_F_I3C_REVA_TARG_FIFOCTRL_TX_THD_LVL_POS) /**< TARG_FIFOCTRL_TX_THD_LVL_HALF_FULL Setting */
+#define MXC_V_I3C_REVA_TARG_FIFOCTRL_TX_THD_LVL_ALMOST_FULL ((uint32_t)0x3UL) /**< TARG_FIFOCTRL_TX_THD_LVL_ALMOST_FULL Value */
+#define MXC_S_I3C_REVA_TARG_FIFOCTRL_TX_THD_LVL_ALMOST_FULL (MXC_V_I3C_REVA_TARG_FIFOCTRL_TX_THD_LVL_ALMOST_FULL << MXC_F_I3C_REVA_TARG_FIFOCTRL_TX_THD_LVL_POS) /**< TARG_FIFOCTRL_TX_THD_LVL_ALMOST_FULL Setting */
+
+#define MXC_F_I3C_REVA_TARG_FIFOCTRL_RX_THD_LVL_POS 6 /**< TARG_FIFOCTRL_RX_THD_LVL Position */
+#define MXC_F_I3C_REVA_TARG_FIFOCTRL_RX_THD_LVL ((uint32_t)(0x3UL << MXC_F_I3C_REVA_TARG_FIFOCTRL_RX_THD_LVL_POS)) /**< TARG_FIFOCTRL_RX_THD_LVL Mask */
+#define MXC_V_I3C_REVA_TARG_FIFOCTRL_RX_THD_LVL_NOT_EMPTY ((uint32_t)0x0UL) /**< TARG_FIFOCTRL_RX_THD_LVL_NOT_EMPTY Value */
+#define MXC_S_I3C_REVA_TARG_FIFOCTRL_RX_THD_LVL_NOT_EMPTY (MXC_V_I3C_REVA_TARG_FIFOCTRL_RX_THD_LVL_NOT_EMPTY << MXC_F_I3C_REVA_TARG_FIFOCTRL_RX_THD_LVL_POS) /**< TARG_FIFOCTRL_RX_THD_LVL_NOT_EMPTY Setting */
+#define MXC_V_I3C_REVA_TARG_FIFOCTRL_RX_THD_LVL_QUARTER_FULL ((uint32_t)0x1UL) /**< TARG_FIFOCTRL_RX_THD_LVL_QUARTER_FULL Value */
+#define MXC_S_I3C_REVA_TARG_FIFOCTRL_RX_THD_LVL_QUARTER_FULL (MXC_V_I3C_REVA_TARG_FIFOCTRL_RX_THD_LVL_QUARTER_FULL << MXC_F_I3C_REVA_TARG_FIFOCTRL_RX_THD_LVL_POS) /**< TARG_FIFOCTRL_RX_THD_LVL_QUARTER_FULL Setting */
+#define MXC_V_I3C_REVA_TARG_FIFOCTRL_RX_THD_LVL_HALF_FULL ((uint32_t)0x2UL) /**< TARG_FIFOCTRL_RX_THD_LVL_HALF_FULL Value */
+#define MXC_S_I3C_REVA_TARG_FIFOCTRL_RX_THD_LVL_HALF_FULL (MXC_V_I3C_REVA_TARG_FIFOCTRL_RX_THD_LVL_HALF_FULL << MXC_F_I3C_REVA_TARG_FIFOCTRL_RX_THD_LVL_POS) /**< TARG_FIFOCTRL_RX_THD_LVL_HALF_FULL Setting */
+#define MXC_V_I3C_REVA_TARG_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL ((uint32_t)0x3UL) /**< TARG_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL Value */
+#define MXC_S_I3C_REVA_TARG_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL (MXC_V_I3C_REVA_TARG_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL << MXC_F_I3C_REVA_TARG_FIFOCTRL_RX_THD_LVL_POS) /**< TARG_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL Setting */
+
+#define MXC_F_I3C_REVA_TARG_FIFOCTRL_TX_LVL_POS 16 /**< TARG_FIFOCTRL_TX_LVL Position */
+#define MXC_F_I3C_REVA_TARG_FIFOCTRL_TX_LVL ((uint32_t)(0x3FUL << MXC_F_I3C_REVA_TARG_FIFOCTRL_TX_LVL_POS)) /**< TARG_FIFOCTRL_TX_LVL Mask */
+
+#define MXC_F_I3C_REVA_TARG_FIFOCTRL_RX_LVL_POS 24 /**< TARG_FIFOCTRL_RX_LVL Position */
+#define MXC_F_I3C_REVA_TARG_FIFOCTRL_RX_LVL ((uint32_t)(0x3FUL << MXC_F_I3C_REVA_TARG_FIFOCTRL_RX_LVL_POS)) /**< TARG_FIFOCTRL_RX_LVL Mask */
+
+#define MXC_F_I3C_REVA_TARG_FIFOCTRL_TX_FULL_POS 30 /**< TARG_FIFOCTRL_TX_FULL Position */
+#define MXC_F_I3C_REVA_TARG_FIFOCTRL_TX_FULL ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_FIFOCTRL_TX_FULL_POS)) /**< TARG_FIFOCTRL_TX_FULL Mask */
+
+#define MXC_F_I3C_REVA_TARG_FIFOCTRL_RX_EM_POS 31 /**< TARG_FIFOCTRL_RX_EM Position */
+#define MXC_F_I3C_REVA_TARG_FIFOCTRL_RX_EM ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_FIFOCTRL_RX_EM_POS)) /**< TARG_FIFOCTRL_RX_EM Mask */
+
+/**@} end of group I3C_REVA_TARG_FIFOCTRL_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_TARG_TXFIFO8 I3C_REVA_TARG_TXFIFO8
+ * @brief Target Write Byte Data Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_TARG_TXFIFO8_DATA_POS 0 /**< TARG_TXFIFO8_DATA Position */
+#define MXC_F_I3C_REVA_TARG_TXFIFO8_DATA ((uint32_t)(0xFFUL << MXC_F_I3C_REVA_TARG_TXFIFO8_DATA_POS)) /**< TARG_TXFIFO8_DATA Mask */
+
+#define MXC_F_I3C_REVA_TARG_TXFIFO8_END_POS 8 /**< TARG_TXFIFO8_END Position */
+#define MXC_F_I3C_REVA_TARG_TXFIFO8_END ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_TXFIFO8_END_POS)) /**< TARG_TXFIFO8_END Mask */
+
+#define MXC_F_I3C_REVA_TARG_TXFIFO8_END2_POS 16 /**< TARG_TXFIFO8_END2 Position */
+#define MXC_F_I3C_REVA_TARG_TXFIFO8_END2 ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_TXFIFO8_END2_POS)) /**< TARG_TXFIFO8_END2 Mask */
+
+/**@} end of group I3C_REVA_TARG_TXFIFO8_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_TARG_TXFIFO8E I3C_REVA_TARG_TXFIFO8E
+ * @brief Target Write Byte Data as End Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_TARG_TXFIFO8E_DATA_POS 0 /**< TARG_TXFIFO8E_DATA Position */
+#define MXC_F_I3C_REVA_TARG_TXFIFO8E_DATA ((uint32_t)(0xFFUL << MXC_F_I3C_REVA_TARG_TXFIFO8E_DATA_POS)) /**< TARG_TXFIFO8E_DATA Mask */
+
+/**@} end of group I3C_REVA_TARG_TXFIFO8E_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_TARG_TXFIFO16 I3C_REVA_TARG_TXFIFO16
+ * @brief Target Write Half-Word Data Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_TARG_TXFIFO16_DATA_POS 0 /**< TARG_TXFIFO16_DATA Position */
+#define MXC_F_I3C_REVA_TARG_TXFIFO16_DATA ((uint32_t)(0xFFFFUL << MXC_F_I3C_REVA_TARG_TXFIFO16_DATA_POS)) /**< TARG_TXFIFO16_DATA Mask */
+
+#define MXC_F_I3C_REVA_TARG_TXFIFO16_END_POS 16 /**< TARG_TXFIFO16_END Position */
+#define MXC_F_I3C_REVA_TARG_TXFIFO16_END ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_TXFIFO16_END_POS)) /**< TARG_TXFIFO16_END Mask */
+
+/**@} end of group I3C_REVA_TARG_TXFIFO16_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_TARG_TXFIFO16E I3C_REVA_TARG_TXFIFO16E
+ * @brief Target Write Half-Word Data as End Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_TARG_TXFIFO16E_DATA_POS 0 /**< TARG_TXFIFO16E_DATA Position */
+#define MXC_F_I3C_REVA_TARG_TXFIFO16E_DATA ((uint32_t)(0xFFFFUL << MXC_F_I3C_REVA_TARG_TXFIFO16E_DATA_POS)) /**< TARG_TXFIFO16E_DATA Mask */
+
+/**@} end of group I3C_REVA_TARG_TXFIFO16E_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_TARG_RXFIFO8 I3C_REVA_TARG_RXFIFO8
+ * @brief Target Read Byte Data Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_TARG_RXFIFO8_DATA_POS 0 /**< TARG_RXFIFO8_DATA Position */
+#define MXC_F_I3C_REVA_TARG_RXFIFO8_DATA ((uint32_t)(0xFFUL << MXC_F_I3C_REVA_TARG_RXFIFO8_DATA_POS)) /**< TARG_RXFIFO8_DATA Mask */
+
+/**@} end of group I3C_REVA_TARG_RXFIFO8_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_TARG_RXFIFO16 I3C_REVA_TARG_RXFIFO16
+ * @brief Target Read Half-Word Data Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_TARG_RXFIFO16_DATA_POS 0 /**< TARG_RXFIFO16_DATA Position */
+#define MXC_F_I3C_REVA_TARG_RXFIFO16_DATA ((uint32_t)(0xFFFFUL << MXC_F_I3C_REVA_TARG_RXFIFO16_DATA_POS)) /**< TARG_RXFIFO16_DATA Mask */
+
+/**@} end of group I3C_REVA_TARG_RXFIFO16_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_TARG_TXFIFO8O I3C_REVA_TARG_TXFIFO8O
+ * @brief Target Byte-Only Write Byte Data Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_TARG_TXFIFO8O_DATA_POS 0 /**< TARG_TXFIFO8O_DATA Position */
+#define MXC_F_I3C_REVA_TARG_TXFIFO8O_DATA ((uint32_t)(0xFFUL << MXC_F_I3C_REVA_TARG_TXFIFO8O_DATA_POS)) /**< TARG_TXFIFO8O_DATA Mask */
+
+/**@} end of group I3C_REVA_TARG_TXFIFO8O_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_TARG_CAP0 I3C_REVA_TARG_CAP0
+ * @brief Target Capabilities 0 Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_TARG_CAP0_MAPCNT_POS 0 /**< TARG_CAP0_MAPCNT Position */
+#define MXC_F_I3C_REVA_TARG_CAP0_MAPCNT ((uint32_t)(0xFUL << MXC_F_I3C_REVA_TARG_CAP0_MAPCNT_POS)) /**< TARG_CAP0_MAPCNT Mask */
+
+#define MXC_F_I3C_REVA_TARG_CAP0_I2C_10BADDR_POS 4 /**< TARG_CAP0_I2C_10BADDR Position */
+#define MXC_F_I3C_REVA_TARG_CAP0_I2C_10BADDR ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_CAP0_I2C_10BADDR_POS)) /**< TARG_CAP0_I2C_10BADDR Mask */
+
+#define MXC_F_I3C_REVA_TARG_CAP0_I2C_SWRST_POS 5 /**< TARG_CAP0_I2C_SWRST Position */
+#define MXC_F_I3C_REVA_TARG_CAP0_I2C_SWRST ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_CAP0_I2C_SWRST_POS)) /**< TARG_CAP0_I2C_SWRST Mask */
+
+#define MXC_F_I3C_REVA_TARG_CAP0_I2C_DEVID_POS 6 /**< TARG_CAP0_I2C_DEVID Position */
+#define MXC_F_I3C_REVA_TARG_CAP0_I2C_DEVID ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_CAP0_I2C_DEVID_POS)) /**< TARG_CAP0_I2C_DEVID Mask */
+
+#define MXC_F_I3C_REVA_TARG_CAP0_FIFO32_REG_POS 7 /**< TARG_CAP0_FIFO32_REG Position */
+#define MXC_F_I3C_REVA_TARG_CAP0_FIFO32_REG ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_CAP0_FIFO32_REG_POS)) /**< TARG_CAP0_FIFO32_REG Mask */
+
+#define MXC_F_I3C_REVA_TARG_CAP0_EXTIBI_POS 8 /**< TARG_CAP0_EXTIBI Position */
+#define MXC_F_I3C_REVA_TARG_CAP0_EXTIBI ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_CAP0_EXTIBI_POS)) /**< TARG_CAP0_EXTIBI Mask */
+
+#define MXC_F_I3C_REVA_TARG_CAP0_EXTIBI_REG_POS 9 /**< TARG_CAP0_EXTIBI_REG Position */
+#define MXC_F_I3C_REVA_TARG_CAP0_EXTIBI_REG ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_CAP0_EXTIBI_REG_POS)) /**< TARG_CAP0_EXTIBI_REG Mask */
+
+#define MXC_F_I3C_REVA_TARG_CAP0_HDRBT_LANES_POS 12 /**< TARG_CAP0_HDRBT_LANES Position */
+#define MXC_F_I3C_REVA_TARG_CAP0_HDRBT_LANES ((uint32_t)(0x3UL << MXC_F_I3C_REVA_TARG_CAP0_HDRBT_LANES_POS)) /**< TARG_CAP0_HDRBT_LANES Mask */
+
+#define MXC_F_I3C_REVA_TARG_CAP0_CCC_V1_1_POS 16 /**< TARG_CAP0_CCC_V1_1 Position */
+#define MXC_F_I3C_REVA_TARG_CAP0_CCC_V1_1 ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_CAP0_CCC_V1_1_POS)) /**< TARG_CAP0_CCC_V1_1 Mask */
+
+#define MXC_F_I3C_REVA_TARG_CAP0_TARG_RST_POS 17 /**< TARG_CAP0_TARG_RST Position */
+#define MXC_F_I3C_REVA_TARG_CAP0_TARG_RST ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_CAP0_TARG_RST_POS)) /**< TARG_CAP0_TARG_RST Mask */
+
+#define MXC_F_I3C_REVA_TARG_CAP0_GROUPADDR_POS 18 /**< TARG_CAP0_GROUPADDR Position */
+#define MXC_F_I3C_REVA_TARG_CAP0_GROUPADDR ((uint32_t)(0x3UL << MXC_F_I3C_REVA_TARG_CAP0_GROUPADDR_POS)) /**< TARG_CAP0_GROUPADDR Mask */
+
+#define MXC_F_I3C_REVA_TARG_CAP0_AASA_CCC_POS 21 /**< TARG_CAP0_AASA_CCC Position */
+#define MXC_F_I3C_REVA_TARG_CAP0_AASA_CCC ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_CAP0_AASA_CCC_POS)) /**< TARG_CAP0_AASA_CCC Mask */
+
+#define MXC_F_I3C_REVA_TARG_CAP0_T2T_SUBSC_POS 22 /**< TARG_CAP0_T2T_SUBSC Position */
+#define MXC_F_I3C_REVA_TARG_CAP0_T2T_SUBSC ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_CAP0_T2T_SUBSC_POS)) /**< TARG_CAP0_T2T_SUBSC Mask */
+
+#define MXC_F_I3C_REVA_TARG_CAP0_T2T_WR_POS 23 /**< TARG_CAP0_T2T_WR Position */
+#define MXC_F_I3C_REVA_TARG_CAP0_T2T_WR ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_CAP0_T2T_WR_POS)) /**< TARG_CAP0_T2T_WR Mask */
+
+/**@} end of group I3C_REVA_TARG_CAP0_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_TARG_CAP1 I3C_REVA_TARG_CAP1
+ * @brief TARG_Capabilities 1 Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_TARG_CAP1_PROVID_POS 0 /**< TARG_CAP1_PROVID Position */
+#define MXC_F_I3C_REVA_TARG_CAP1_PROVID ((uint32_t)(0x3UL << MXC_F_I3C_REVA_TARG_CAP1_PROVID_POS)) /**< TARG_CAP1_PROVID Mask */
+
+#define MXC_F_I3C_REVA_TARG_CAP1_PROVID_REG_POS 2 /**< TARG_CAP1_PROVID_REG Position */
+#define MXC_F_I3C_REVA_TARG_CAP1_PROVID_REG ((uint32_t)(0xFUL << MXC_F_I3C_REVA_TARG_CAP1_PROVID_REG_POS)) /**< TARG_CAP1_PROVID_REG Mask */
+
+#define MXC_F_I3C_REVA_TARG_CAP1_HDR_MODES_POS 6 /**< TARG_CAP1_HDR_MODES Position */
+#define MXC_F_I3C_REVA_TARG_CAP1_HDR_MODES ((uint32_t)(0x7UL << MXC_F_I3C_REVA_TARG_CAP1_HDR_MODES_POS)) /**< TARG_CAP1_HDR_MODES Mask */
+
+#define MXC_F_I3C_REVA_TARG_CAP1_CONT_POS 9 /**< TARG_CAP1_CONT Position */
+#define MXC_F_I3C_REVA_TARG_CAP1_CONT ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_CAP1_CONT_POS)) /**< TARG_CAP1_CONT Mask */
+
+#define MXC_F_I3C_REVA_TARG_CAP1_STATADDR_POS 10 /**< TARG_CAP1_STATADDR Position */
+#define MXC_F_I3C_REVA_TARG_CAP1_STATADDR ((uint32_t)(0x3UL << MXC_F_I3C_REVA_TARG_CAP1_STATADDR_POS)) /**< TARG_CAP1_STATADDR Mask */
+
+#define MXC_F_I3C_REVA_TARG_CAP1_CCCH_POS 12 /**< TARG_CAP1_CCCH Position */
+#define MXC_F_I3C_REVA_TARG_CAP1_CCCH ((uint32_t)(0xFUL << MXC_F_I3C_REVA_TARG_CAP1_CCCH_POS)) /**< TARG_CAP1_CCCH Mask */
+#define MXC_V_I3C_REVA_TARG_CAP1_CCCH_BASIC ((uint32_t)0x1UL) /**< TARG_CAP1_CCCH_BASIC Value */
+#define MXC_S_I3C_REVA_TARG_CAP1_CCCH_BASIC (MXC_V_I3C_REVA_TARG_CAP1_CCCH_BASIC << MXC_F_I3C_REVA_TARG_CAP1_CCCH_POS) /**< TARG_CAP1_CCCH_BASIC Setting */
+#define MXC_V_I3C_REVA_TARG_CAP1_CCCH_LIMITS ((uint32_t)0x2UL) /**< TARG_CAP1_CCCH_LIMITS Value */
+#define MXC_S_I3C_REVA_TARG_CAP1_CCCH_LIMITS (MXC_V_I3C_REVA_TARG_CAP1_CCCH_LIMITS << MXC_F_I3C_REVA_TARG_CAP1_CCCH_POS) /**< TARG_CAP1_CCCH_LIMITS Setting */
+#define MXC_V_I3C_REVA_TARG_CAP1_CCCH_INTACT ((uint32_t)0x4UL) /**< TARG_CAP1_CCCH_INTACT Value */
+#define MXC_S_I3C_REVA_TARG_CAP1_CCCH_INTACT (MXC_V_I3C_REVA_TARG_CAP1_CCCH_INTACT << MXC_F_I3C_REVA_TARG_CAP1_CCCH_POS) /**< TARG_CAP1_CCCH_INTACT Setting */
+#define MXC_V_I3C_REVA_TARG_CAP1_CCCH_VENDOR ((uint32_t)0x8UL) /**< TARG_CAP1_CCCH_VENDOR Value */
+#define MXC_S_I3C_REVA_TARG_CAP1_CCCH_VENDOR (MXC_V_I3C_REVA_TARG_CAP1_CCCH_VENDOR << MXC_F_I3C_REVA_TARG_CAP1_CCCH_POS) /**< TARG_CAP1_CCCH_VENDOR Setting */
+
+#define MXC_F_I3C_REVA_TARG_CAP1_IBI_EVENTS_POS 16 /**< TARG_CAP1_IBI_EVENTS Position */
+#define MXC_F_I3C_REVA_TARG_CAP1_IBI_EVENTS ((uint32_t)(0x1FUL << MXC_F_I3C_REVA_TARG_CAP1_IBI_EVENTS_POS)) /**< TARG_CAP1_IBI_EVENTS Mask */
+#define MXC_V_I3C_REVA_TARG_CAP1_IBI_EVENTS_IBI ((uint32_t)0x1UL) /**< TARG_CAP1_IBI_EVENTS_IBI Value */
+#define MXC_S_I3C_REVA_TARG_CAP1_IBI_EVENTS_IBI (MXC_V_I3C_REVA_TARG_CAP1_IBI_EVENTS_IBI << MXC_F_I3C_REVA_TARG_CAP1_IBI_EVENTS_POS) /**< TARG_CAP1_IBI_EVENTS_IBI Setting */
+#define MXC_V_I3C_REVA_TARG_CAP1_IBI_EVENTS_PAYLOAD ((uint32_t)0x2UL) /**< TARG_CAP1_IBI_EVENTS_PAYLOAD Value */
+#define MXC_S_I3C_REVA_TARG_CAP1_IBI_EVENTS_PAYLOAD (MXC_V_I3C_REVA_TARG_CAP1_IBI_EVENTS_PAYLOAD << MXC_F_I3C_REVA_TARG_CAP1_IBI_EVENTS_POS) /**< TARG_CAP1_IBI_EVENTS_PAYLOAD Setting */
+#define MXC_V_I3C_REVA_TARG_CAP1_IBI_EVENTS_CONTREQ ((uint32_t)0x4UL) /**< TARG_CAP1_IBI_EVENTS_CONTREQ Value */
+#define MXC_S_I3C_REVA_TARG_CAP1_IBI_EVENTS_CONTREQ (MXC_V_I3C_REVA_TARG_CAP1_IBI_EVENTS_CONTREQ << MXC_F_I3C_REVA_TARG_CAP1_IBI_EVENTS_POS) /**< TARG_CAP1_IBI_EVENTS_CONTREQ Setting */
+#define MXC_V_I3C_REVA_TARG_CAP1_IBI_EVENTS_HJ ((uint32_t)0x8UL) /**< TARG_CAP1_IBI_EVENTS_HJ Value */
+#define MXC_S_I3C_REVA_TARG_CAP1_IBI_EVENTS_HJ (MXC_V_I3C_REVA_TARG_CAP1_IBI_EVENTS_HJ << MXC_F_I3C_REVA_TARG_CAP1_IBI_EVENTS_POS) /**< TARG_CAP1_IBI_EVENTS_HJ Setting */
+#define MXC_V_I3C_REVA_TARG_CAP1_IBI_EVENTS_BAMATCH ((uint32_t)0x10UL) /**< TARG_CAP1_IBI_EVENTS_BAMATCH Value */
+#define MXC_S_I3C_REVA_TARG_CAP1_IBI_EVENTS_BAMATCH (MXC_V_I3C_REVA_TARG_CAP1_IBI_EVENTS_BAMATCH << MXC_F_I3C_REVA_TARG_CAP1_IBI_EVENTS_POS) /**< TARG_CAP1_IBI_EVENTS_BAMATCH Setting */
+
+#define MXC_F_I3C_REVA_TARG_CAP1_TIMECTRL_POS 21 /**< TARG_CAP1_TIMECTRL Position */
+#define MXC_F_I3C_REVA_TARG_CAP1_TIMECTRL ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_CAP1_TIMECTRL_POS)) /**< TARG_CAP1_TIMECTRL Mask */
+
+#define MXC_F_I3C_REVA_TARG_CAP1_EXTFIFO_POS 23 /**< TARG_CAP1_EXTFIFO Position */
+#define MXC_F_I3C_REVA_TARG_CAP1_EXTFIFO ((uint32_t)(0x7UL << MXC_F_I3C_REVA_TARG_CAP1_EXTFIFO_POS)) /**< TARG_CAP1_EXTFIFO Mask */
+
+#define MXC_F_I3C_REVA_TARG_CAP1_TXFIFO_CFG_POS 26 /**< TARG_CAP1_TXFIFO_CFG Position */
+#define MXC_F_I3C_REVA_TARG_CAP1_TXFIFO_CFG ((uint32_t)(0x3UL << MXC_F_I3C_REVA_TARG_CAP1_TXFIFO_CFG_POS)) /**< TARG_CAP1_TXFIFO_CFG Mask */
+
+#define MXC_F_I3C_REVA_TARG_CAP1_RXFIFO_CFG_POS 28 /**< TARG_CAP1_RXFIFO_CFG Position */
+#define MXC_F_I3C_REVA_TARG_CAP1_RXFIFO_CFG ((uint32_t)(0x3UL << MXC_F_I3C_REVA_TARG_CAP1_RXFIFO_CFG_POS)) /**< TARG_CAP1_RXFIFO_CFG Mask */
+
+#define MXC_F_I3C_REVA_TARG_CAP1_INTR_POS 30 /**< TARG_CAP1_INTR Position */
+#define MXC_F_I3C_REVA_TARG_CAP1_INTR ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_CAP1_INTR_POS)) /**< TARG_CAP1_INTR Mask */
+
+#define MXC_F_I3C_REVA_TARG_CAP1_DMA_POS 31 /**< TARG_CAP1_DMA Position */
+#define MXC_F_I3C_REVA_TARG_CAP1_DMA ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_CAP1_DMA_POS)) /**< TARG_CAP1_DMA Mask */
+
+/**@} end of group I3C_REVA_TARG_CAP1_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_TARG_DYNADDR I3C_REVA_TARG_DYNADDR
+ * @brief Target Dynamic Address Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_TARG_DYNADDR_VALID_POS 0 /**< TARG_DYNADDR_VALID Position */
+#define MXC_F_I3C_REVA_TARG_DYNADDR_VALID ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_DYNADDR_VALID_POS)) /**< TARG_DYNADDR_VALID Mask */
+
+#define MXC_F_I3C_REVA_TARG_DYNADDR_ADDR_POS 1 /**< TARG_DYNADDR_ADDR Position */
+#define MXC_F_I3C_REVA_TARG_DYNADDR_ADDR ((uint32_t)(0x7FUL << MXC_F_I3C_REVA_TARG_DYNADDR_ADDR_POS)) /**< TARG_DYNADDR_ADDR Mask */
+
+#define MXC_F_I3C_REVA_TARG_DYNADDR_CAUSE_POS 8 /**< TARG_DYNADDR_CAUSE Position */
+#define MXC_F_I3C_REVA_TARG_DYNADDR_CAUSE ((uint32_t)(0x7UL << MXC_F_I3C_REVA_TARG_DYNADDR_CAUSE_POS)) /**< TARG_DYNADDR_CAUSE Mask */
+
+/**@} end of group I3C_REVA_TARG_DYNADDR_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_TARG_MAXLIMITS I3C_REVA_TARG_MAXLIMITS
+ * @brief Maximum Limits Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_TARG_MAXLIMITS_RX_POS 0 /**< TARG_MAXLIMITS_RX Position */
+#define MXC_F_I3C_REVA_TARG_MAXLIMITS_RX ((uint32_t)(0xFFFUL << MXC_F_I3C_REVA_TARG_MAXLIMITS_RX_POS)) /**< TARG_MAXLIMITS_RX Mask */
+
+#define MXC_F_I3C_REVA_TARG_MAXLIMITS_TX_POS 16 /**< TARG_MAXLIMITS_TX Position */
+#define MXC_F_I3C_REVA_TARG_MAXLIMITS_TX ((uint32_t)(0xFFFUL << MXC_F_I3C_REVA_TARG_MAXLIMITS_TX_POS)) /**< TARG_MAXLIMITS_TX Mask */
+
+/**@} end of group I3C_REVA_TARG_MAXLIMITS_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_TARG_IDEXT I3C_REVA_TARG_IDEXT
+ * @brief ID Extension Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_TARG_IDEXT_DEVCHAR_POS 8 /**< TARG_IDEXT_DEVCHAR Position */
+#define MXC_F_I3C_REVA_TARG_IDEXT_DEVCHAR ((uint32_t)(0xFFUL << MXC_F_I3C_REVA_TARG_IDEXT_DEVCHAR_POS)) /**< TARG_IDEXT_DEVCHAR Mask */
+
+#define MXC_F_I3C_REVA_TARG_IDEXT_BUSCHAR_POS 16 /**< TARG_IDEXT_BUSCHAR Position */
+#define MXC_F_I3C_REVA_TARG_IDEXT_BUSCHAR ((uint32_t)(0xFFUL << MXC_F_I3C_REVA_TARG_IDEXT_BUSCHAR_POS)) /**< TARG_IDEXT_BUSCHAR Mask */
+
+/**@} end of group I3C_REVA_TARG_IDEXT_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_TARG_MSGLAST I3C_REVA_TARG_MSGLAST
+ * @brief Target Matching Address Index Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_TARG_MSGLAST_IDX_POS 0 /**< TARG_MSGLAST_IDX Position */
+#define MXC_F_I3C_REVA_TARG_MSGLAST_IDX ((uint32_t)(0xFUL << MXC_F_I3C_REVA_TARG_MSGLAST_IDX_POS)) /**< TARG_MSGLAST_IDX Mask */
+
+#define MXC_F_I3C_REVA_TARG_MSGLAST_STATADDR_POS 4 /**< TARG_MSGLAST_STATADDR Position */
+#define MXC_F_I3C_REVA_TARG_MSGLAST_STATADDR ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_MSGLAST_STATADDR_POS)) /**< TARG_MSGLAST_STATADDR Mask */
+
+#define MXC_F_I3C_REVA_TARG_MSGLAST_GROUP_POS 5 /**< TARG_MSGLAST_GROUP Position */
+#define MXC_F_I3C_REVA_TARG_MSGLAST_GROUP ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_MSGLAST_GROUP_POS)) /**< TARG_MSGLAST_GROUP Mask */
+
+#define MXC_F_I3C_REVA_TARG_MSGLAST_MODE_POS 6 /**< TARG_MSGLAST_MODE Position */
+#define MXC_F_I3C_REVA_TARG_MSGLAST_MODE ((uint32_t)(0x3UL << MXC_F_I3C_REVA_TARG_MSGLAST_MODE_POS)) /**< TARG_MSGLAST_MODE Mask */
+#define MXC_V_I3C_REVA_TARG_MSGLAST_MODE_DYN_STAT_ADDR ((uint32_t)0x0UL) /**< TARG_MSGLAST_MODE_DYN_STAT_ADDR Value */
+#define MXC_S_I3C_REVA_TARG_MSGLAST_MODE_DYN_STAT_ADDR (MXC_V_I3C_REVA_TARG_MSGLAST_MODE_DYN_STAT_ADDR << MXC_F_I3C_REVA_TARG_MSGLAST_MODE_POS) /**< TARG_MSGLAST_MODE_DYN_STAT_ADDR Setting */
+#define MXC_V_I3C_REVA_TARG_MSGLAST_MODE_HDR_DDR ((uint32_t)0x1UL) /**< TARG_MSGLAST_MODE_HDR_DDR Value */
+#define MXC_S_I3C_REVA_TARG_MSGLAST_MODE_HDR_DDR (MXC_V_I3C_REVA_TARG_MSGLAST_MODE_HDR_DDR << MXC_F_I3C_REVA_TARG_MSGLAST_MODE_POS) /**< TARG_MSGLAST_MODE_HDR_DDR Setting */
+#define MXC_V_I3C_REVA_TARG_MSGLAST_MODE_HDR_BT ((uint32_t)0x2UL) /**< TARG_MSGLAST_MODE_HDR_BT Value */
+#define MXC_S_I3C_REVA_TARG_MSGLAST_MODE_HDR_BT (MXC_V_I3C_REVA_TARG_MSGLAST_MODE_HDR_BT << MXC_F_I3C_REVA_TARG_MSGLAST_MODE_POS) /**< TARG_MSGLAST_MODE_HDR_BT Setting */
+
+#define MXC_F_I3C_REVA_TARG_MSGLAST_PREV_IDX_POS 8 /**< TARG_MSGLAST_PREV_IDX Position */
+#define MXC_F_I3C_REVA_TARG_MSGLAST_PREV_IDX ((uint32_t)(0xFUL << MXC_F_I3C_REVA_TARG_MSGLAST_PREV_IDX_POS)) /**< TARG_MSGLAST_PREV_IDX Mask */
+
+#define MXC_F_I3C_REVA_TARG_MSGLAST_PREV_GROUP_POS 13 /**< TARG_MSGLAST_PREV_GROUP Position */
+#define MXC_F_I3C_REVA_TARG_MSGLAST_PREV_GROUP ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_MSGLAST_PREV_GROUP_POS)) /**< TARG_MSGLAST_PREV_GROUP Mask */
+
+#define MXC_F_I3C_REVA_TARG_MSGLAST_PREV_MODE_POS 14 /**< TARG_MSGLAST_PREV_MODE Position */
+#define MXC_F_I3C_REVA_TARG_MSGLAST_PREV_MODE ((uint32_t)(0x3UL << MXC_F_I3C_REVA_TARG_MSGLAST_PREV_MODE_POS)) /**< TARG_MSGLAST_PREV_MODE Mask */
+#define MXC_V_I3C_REVA_TARG_MSGLAST_PREV_MODE_DYN_STAT_ADDR ((uint32_t)0x0UL) /**< TARG_MSGLAST_PREV_MODE_DYN_STAT_ADDR Value */
+#define MXC_S_I3C_REVA_TARG_MSGLAST_PREV_MODE_DYN_STAT_ADDR (MXC_V_I3C_REVA_TARG_MSGLAST_PREV_MODE_DYN_STAT_ADDR << MXC_F_I3C_REVA_TARG_MSGLAST_PREV_MODE_POS) /**< TARG_MSGLAST_PREV_MODE_DYN_STAT_ADDR Setting */
+#define MXC_V_I3C_REVA_TARG_MSGLAST_PREV_MODE_HDR_DDR ((uint32_t)0x1UL) /**< TARG_MSGLAST_PREV_MODE_HDR_DDR Value */
+#define MXC_S_I3C_REVA_TARG_MSGLAST_PREV_MODE_HDR_DDR (MXC_V_I3C_REVA_TARG_MSGLAST_PREV_MODE_HDR_DDR << MXC_F_I3C_REVA_TARG_MSGLAST_PREV_MODE_POS) /**< TARG_MSGLAST_PREV_MODE_HDR_DDR Setting */
+#define MXC_V_I3C_REVA_TARG_MSGLAST_PREV_MODE_HDR_BT ((uint32_t)0x2UL) /**< TARG_MSGLAST_PREV_MODE_HDR_BT Value */
+#define MXC_S_I3C_REVA_TARG_MSGLAST_PREV_MODE_HDR_BT (MXC_V_I3C_REVA_TARG_MSGLAST_PREV_MODE_HDR_BT << MXC_F_I3C_REVA_TARG_MSGLAST_PREV_MODE_POS) /**< TARG_MSGLAST_PREV_MODE_HDR_BT Setting */
+
+#define MXC_F_I3C_REVA_TARG_MSGLAST_SECPREV_IDX_POS 16 /**< TARG_MSGLAST_SECPREV_IDX Position */
+#define MXC_F_I3C_REVA_TARG_MSGLAST_SECPREV_IDX ((uint32_t)(0xFUL << MXC_F_I3C_REVA_TARG_MSGLAST_SECPREV_IDX_POS)) /**< TARG_MSGLAST_SECPREV_IDX Mask */
+
+#define MXC_F_I3C_REVA_TARG_MSGLAST_SECPREV_GROUP_POS 21 /**< TARG_MSGLAST_SECPREV_GROUP Position */
+#define MXC_F_I3C_REVA_TARG_MSGLAST_SECPREV_GROUP ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_MSGLAST_SECPREV_GROUP_POS)) /**< TARG_MSGLAST_SECPREV_GROUP Mask */
+
+#define MXC_F_I3C_REVA_TARG_MSGLAST_SECPREV_MODE_POS 22 /**< TARG_MSGLAST_SECPREV_MODE Position */
+#define MXC_F_I3C_REVA_TARG_MSGLAST_SECPREV_MODE ((uint32_t)(0x3UL << MXC_F_I3C_REVA_TARG_MSGLAST_SECPREV_MODE_POS)) /**< TARG_MSGLAST_SECPREV_MODE Mask */
+#define MXC_V_I3C_REVA_TARG_MSGLAST_SECPREV_MODE_DYN_STAT_ADDR ((uint32_t)0x0UL) /**< TARG_MSGLAST_SECPREV_MODE_DYN_STAT_ADDR Value */
+#define MXC_S_I3C_REVA_TARG_MSGLAST_SECPREV_MODE_DYN_STAT_ADDR (MXC_V_I3C_REVA_TARG_MSGLAST_SECPREV_MODE_DYN_STAT_ADDR << MXC_F_I3C_REVA_TARG_MSGLAST_SECPREV_MODE_POS) /**< TARG_MSGLAST_SECPREV_MODE_DYN_STAT_ADDR Setting */
+#define MXC_V_I3C_REVA_TARG_MSGLAST_SECPREV_MODE_HDR_DDR ((uint32_t)0x1UL) /**< TARG_MSGLAST_SECPREV_MODE_HDR_DDR Value */
+#define MXC_S_I3C_REVA_TARG_MSGLAST_SECPREV_MODE_HDR_DDR (MXC_V_I3C_REVA_TARG_MSGLAST_SECPREV_MODE_HDR_DDR << MXC_F_I3C_REVA_TARG_MSGLAST_SECPREV_MODE_POS) /**< TARG_MSGLAST_SECPREV_MODE_HDR_DDR Setting */
+#define MXC_V_I3C_REVA_TARG_MSGLAST_SECPREV_MODE_HDR_BT ((uint32_t)0x2UL) /**< TARG_MSGLAST_SECPREV_MODE_HDR_BT Value */
+#define MXC_S_I3C_REVA_TARG_MSGLAST_SECPREV_MODE_HDR_BT (MXC_V_I3C_REVA_TARG_MSGLAST_SECPREV_MODE_HDR_BT << MXC_F_I3C_REVA_TARG_MSGLAST_SECPREV_MODE_POS) /**< TARG_MSGLAST_SECPREV_MODE_HDR_BT Setting */
+
+/**@} end of group I3C_REVA_TARG_MSGLAST_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_CONT_CTRL1 I3C_REVA_CONT_CTRL1
+ * @brief Controller Control 1 Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_CONT_CTRL1_REQ_POS 0 /**< CONT_CTRL1_REQ Position */
+#define MXC_F_I3C_REVA_CONT_CTRL1_REQ ((uint32_t)(0x7UL << MXC_F_I3C_REVA_CONT_CTRL1_REQ_POS)) /**< CONT_CTRL1_REQ Mask */
+#define MXC_V_I3C_REVA_CONT_CTRL1_REQ_NONE ((uint32_t)0x0UL) /**< CONT_CTRL1_REQ_NONE Value */
+#define MXC_S_I3C_REVA_CONT_CTRL1_REQ_NONE (MXC_V_I3C_REVA_CONT_CTRL1_REQ_NONE << MXC_F_I3C_REVA_CONT_CTRL1_REQ_POS) /**< CONT_CTRL1_REQ_NONE Setting */
+#define MXC_V_I3C_REVA_CONT_CTRL1_REQ_EMIT_START ((uint32_t)0x1UL) /**< CONT_CTRL1_REQ_EMIT_START Value */
+#define MXC_S_I3C_REVA_CONT_CTRL1_REQ_EMIT_START (MXC_V_I3C_REVA_CONT_CTRL1_REQ_EMIT_START << MXC_F_I3C_REVA_CONT_CTRL1_REQ_POS) /**< CONT_CTRL1_REQ_EMIT_START Setting */
+#define MXC_V_I3C_REVA_CONT_CTRL1_REQ_EMIT_STOP ((uint32_t)0x2UL) /**< CONT_CTRL1_REQ_EMIT_STOP Value */
+#define MXC_S_I3C_REVA_CONT_CTRL1_REQ_EMIT_STOP (MXC_V_I3C_REVA_CONT_CTRL1_REQ_EMIT_STOP << MXC_F_I3C_REVA_CONT_CTRL1_REQ_POS) /**< CONT_CTRL1_REQ_EMIT_STOP Setting */
+#define MXC_V_I3C_REVA_CONT_CTRL1_REQ_IBI_ACKNACK ((uint32_t)0x3UL) /**< CONT_CTRL1_REQ_IBI_ACKNACK Value */
+#define MXC_S_I3C_REVA_CONT_CTRL1_REQ_IBI_ACKNACK (MXC_V_I3C_REVA_CONT_CTRL1_REQ_IBI_ACKNACK << MXC_F_I3C_REVA_CONT_CTRL1_REQ_POS) /**< CONT_CTRL1_REQ_IBI_ACKNACK Setting */
+#define MXC_V_I3C_REVA_CONT_CTRL1_REQ_PROCESS_DAA ((uint32_t)0x4UL) /**< CONT_CTRL1_REQ_PROCESS_DAA Value */
+#define MXC_S_I3C_REVA_CONT_CTRL1_REQ_PROCESS_DAA (MXC_V_I3C_REVA_CONT_CTRL1_REQ_PROCESS_DAA << MXC_F_I3C_REVA_CONT_CTRL1_REQ_POS) /**< CONT_CTRL1_REQ_PROCESS_DAA Setting */
+#define MXC_V_I3C_REVA_CONT_CTRL1_REQ_EXIT_RST ((uint32_t)0x6UL) /**< CONT_CTRL1_REQ_EXIT_RST Value */
+#define MXC_S_I3C_REVA_CONT_CTRL1_REQ_EXIT_RST (MXC_V_I3C_REVA_CONT_CTRL1_REQ_EXIT_RST << MXC_F_I3C_REVA_CONT_CTRL1_REQ_POS) /**< CONT_CTRL1_REQ_EXIT_RST Setting */
+#define MXC_V_I3C_REVA_CONT_CTRL1_REQ_AUTO_IBI ((uint32_t)0x7UL) /**< CONT_CTRL1_REQ_AUTO_IBI Value */
+#define MXC_S_I3C_REVA_CONT_CTRL1_REQ_AUTO_IBI (MXC_V_I3C_REVA_CONT_CTRL1_REQ_AUTO_IBI << MXC_F_I3C_REVA_CONT_CTRL1_REQ_POS) /**< CONT_CTRL1_REQ_AUTO_IBI Setting */
+
+#define MXC_F_I3C_REVA_CONT_CTRL1_TYPE_POS 4 /**< CONT_CTRL1_TYPE Position */
+#define MXC_F_I3C_REVA_CONT_CTRL1_TYPE ((uint32_t)(0x3UL << MXC_F_I3C_REVA_CONT_CTRL1_TYPE_POS)) /**< CONT_CTRL1_TYPE Mask */
+
+#define MXC_F_I3C_REVA_CONT_CTRL1_IBIRESP_POS 6 /**< CONT_CTRL1_IBIRESP Position */
+#define MXC_F_I3C_REVA_CONT_CTRL1_IBIRESP ((uint32_t)(0x3UL << MXC_F_I3C_REVA_CONT_CTRL1_IBIRESP_POS)) /**< CONT_CTRL1_IBIRESP Mask */
+
+#define MXC_F_I3C_REVA_CONT_CTRL1_RDWR_DIR_POS 8 /**< CONT_CTRL1_RDWR_DIR Position */
+#define MXC_F_I3C_REVA_CONT_CTRL1_RDWR_DIR ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_CTRL1_RDWR_DIR_POS)) /**< CONT_CTRL1_RDWR_DIR Mask */
+
+#define MXC_F_I3C_REVA_CONT_CTRL1_ADDR_POS 9 /**< CONT_CTRL1_ADDR Position */
+#define MXC_F_I3C_REVA_CONT_CTRL1_ADDR ((uint32_t)(0x7FUL << MXC_F_I3C_REVA_CONT_CTRL1_ADDR_POS)) /**< CONT_CTRL1_ADDR Mask */
+
+#define MXC_F_I3C_REVA_CONT_CTRL1_TERM_RD_POS 16 /**< CONT_CTRL1_TERM_RD Position */
+#define MXC_F_I3C_REVA_CONT_CTRL1_TERM_RD ((uint32_t)(0xFFUL << MXC_F_I3C_REVA_CONT_CTRL1_TERM_RD_POS)) /**< CONT_CTRL1_TERM_RD Mask */
+
+/**@} end of group I3C_REVA_CONT_CTRL1_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_CONT_STATUS I3C_REVA_CONT_STATUS
+ * @brief Controller Status Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_CONT_STATUS_STATE_POS 0 /**< CONT_STATUS_STATE Position */
+#define MXC_F_I3C_REVA_CONT_STATUS_STATE ((uint32_t)(0x7UL << MXC_F_I3C_REVA_CONT_STATUS_STATE_POS)) /**< CONT_STATUS_STATE Mask */
+#define MXC_V_I3C_REVA_CONT_STATUS_STATE_IDLE ((uint32_t)0x0UL) /**< CONT_STATUS_STATE_IDLE Value */
+#define MXC_S_I3C_REVA_CONT_STATUS_STATE_IDLE (MXC_V_I3C_REVA_CONT_STATUS_STATE_IDLE << MXC_F_I3C_REVA_CONT_STATUS_STATE_POS) /**< CONT_STATUS_STATE_IDLE Setting */
+#define MXC_V_I3C_REVA_CONT_STATUS_STATE_TARG_REQ ((uint32_t)0x1UL) /**< CONT_STATUS_STATE_TARG_REQ Value */
+#define MXC_S_I3C_REVA_CONT_STATUS_STATE_TARG_REQ (MXC_V_I3C_REVA_CONT_STATUS_STATE_TARG_REQ << MXC_F_I3C_REVA_CONT_STATUS_STATE_POS) /**< CONT_STATUS_STATE_TARG_REQ Setting */
+#define MXC_V_I3C_REVA_CONT_STATUS_STATE_SDR_TXSDRMSG ((uint32_t)0x2UL) /**< CONT_STATUS_STATE_SDR_TXSDRMSG Value */
+#define MXC_S_I3C_REVA_CONT_STATUS_STATE_SDR_TXSDRMSG (MXC_V_I3C_REVA_CONT_STATUS_STATE_SDR_TXSDRMSG << MXC_F_I3C_REVA_CONT_STATUS_STATE_POS) /**< CONT_STATUS_STATE_SDR_TXSDRMSG Setting */
+#define MXC_V_I3C_REVA_CONT_STATUS_STATE_SDR_NORM ((uint32_t)0x3UL) /**< CONT_STATUS_STATE_SDR_NORM Value */
+#define MXC_S_I3C_REVA_CONT_STATUS_STATE_SDR_NORM (MXC_V_I3C_REVA_CONT_STATUS_STATE_SDR_NORM << MXC_F_I3C_REVA_CONT_STATUS_STATE_POS) /**< CONT_STATUS_STATE_SDR_NORM Setting */
+#define MXC_V_I3C_REVA_CONT_STATUS_STATE_DDR ((uint32_t)0x4UL) /**< CONT_STATUS_STATE_DDR Value */
+#define MXC_S_I3C_REVA_CONT_STATUS_STATE_DDR (MXC_V_I3C_REVA_CONT_STATUS_STATE_DDR << MXC_F_I3C_REVA_CONT_STATUS_STATE_POS) /**< CONT_STATUS_STATE_DDR Setting */
+#define MXC_V_I3C_REVA_CONT_STATUS_STATE_DAA ((uint32_t)0x5UL) /**< CONT_STATUS_STATE_DAA Value */
+#define MXC_S_I3C_REVA_CONT_STATUS_STATE_DAA (MXC_V_I3C_REVA_CONT_STATUS_STATE_DAA << MXC_F_I3C_REVA_CONT_STATUS_STATE_POS) /**< CONT_STATUS_STATE_DAA Setting */
+#define MXC_V_I3C_REVA_CONT_STATUS_STATE_IBI_ACKNACK ((uint32_t)0x6UL) /**< CONT_STATUS_STATE_IBI_ACKNACK Value */
+#define MXC_S_I3C_REVA_CONT_STATUS_STATE_IBI_ACKNACK (MXC_V_I3C_REVA_CONT_STATUS_STATE_IBI_ACKNACK << MXC_F_I3C_REVA_CONT_STATUS_STATE_POS) /**< CONT_STATUS_STATE_IBI_ACKNACK Setting */
+#define MXC_V_I3C_REVA_CONT_STATUS_STATE_IBI_RX ((uint32_t)0x7UL) /**< CONT_STATUS_STATE_IBI_RX Value */
+#define MXC_S_I3C_REVA_CONT_STATUS_STATE_IBI_RX (MXC_V_I3C_REVA_CONT_STATUS_STATE_IBI_RX << MXC_F_I3C_REVA_CONT_STATUS_STATE_POS) /**< CONT_STATUS_STATE_IBI_RX Setting */
+
+#define MXC_F_I3C_REVA_CONT_STATUS_WAIT_POS 4 /**< CONT_STATUS_WAIT Position */
+#define MXC_F_I3C_REVA_CONT_STATUS_WAIT ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_STATUS_WAIT_POS)) /**< CONT_STATUS_WAIT Mask */
+
+#define MXC_F_I3C_REVA_CONT_STATUS_NACK_POS 5 /**< CONT_STATUS_NACK Position */
+#define MXC_F_I3C_REVA_CONT_STATUS_NACK ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_STATUS_NACK_POS)) /**< CONT_STATUS_NACK Mask */
+
+#define MXC_F_I3C_REVA_CONT_STATUS_IBITYPE_POS 6 /**< CONT_STATUS_IBITYPE Position */
+#define MXC_F_I3C_REVA_CONT_STATUS_IBITYPE ((uint32_t)(0x3UL << MXC_F_I3C_REVA_CONT_STATUS_IBITYPE_POS)) /**< CONT_STATUS_IBITYPE Mask */
+#define MXC_V_I3C_REVA_CONT_STATUS_IBITYPE_NONE ((uint32_t)0x0UL) /**< CONT_STATUS_IBITYPE_NONE Value */
+#define MXC_S_I3C_REVA_CONT_STATUS_IBITYPE_NONE (MXC_V_I3C_REVA_CONT_STATUS_IBITYPE_NONE << MXC_F_I3C_REVA_CONT_STATUS_IBITYPE_POS) /**< CONT_STATUS_IBITYPE_NONE Setting */
+#define MXC_V_I3C_REVA_CONT_STATUS_IBITYPE_IBI ((uint32_t)0x1UL) /**< CONT_STATUS_IBITYPE_IBI Value */
+#define MXC_S_I3C_REVA_CONT_STATUS_IBITYPE_IBI (MXC_V_I3C_REVA_CONT_STATUS_IBITYPE_IBI << MXC_F_I3C_REVA_CONT_STATUS_IBITYPE_POS) /**< CONT_STATUS_IBITYPE_IBI Setting */
+#define MXC_V_I3C_REVA_CONT_STATUS_IBITYPE_CONT_REQ ((uint32_t)0x2UL) /**< CONT_STATUS_IBITYPE_CONT_REQ Value */
+#define MXC_S_I3C_REVA_CONT_STATUS_IBITYPE_CONT_REQ (MXC_V_I3C_REVA_CONT_STATUS_IBITYPE_CONT_REQ << MXC_F_I3C_REVA_CONT_STATUS_IBITYPE_POS) /**< CONT_STATUS_IBITYPE_CONT_REQ Setting */
+#define MXC_V_I3C_REVA_CONT_STATUS_IBITYPE_HOTJOIN_REQ ((uint32_t)0x3UL) /**< CONT_STATUS_IBITYPE_HOTJOIN_REQ Value */
+#define MXC_S_I3C_REVA_CONT_STATUS_IBITYPE_HOTJOIN_REQ (MXC_V_I3C_REVA_CONT_STATUS_IBITYPE_HOTJOIN_REQ << MXC_F_I3C_REVA_CONT_STATUS_IBITYPE_POS) /**< CONT_STATUS_IBITYPE_HOTJOIN_REQ Setting */
+
+#define MXC_F_I3C_REVA_CONT_STATUS_TARG_START_POS 8 /**< CONT_STATUS_TARG_START Position */
+#define MXC_F_I3C_REVA_CONT_STATUS_TARG_START ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_STATUS_TARG_START_POS)) /**< CONT_STATUS_TARG_START Mask */
+
+#define MXC_F_I3C_REVA_CONT_STATUS_REQ_DONE_POS 9 /**< CONT_STATUS_REQ_DONE Position */
+#define MXC_F_I3C_REVA_CONT_STATUS_REQ_DONE ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_STATUS_REQ_DONE_POS)) /**< CONT_STATUS_REQ_DONE Mask */
+
+#define MXC_F_I3C_REVA_CONT_STATUS_DONE_POS 10 /**< CONT_STATUS_DONE Position */
+#define MXC_F_I3C_REVA_CONT_STATUS_DONE ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_STATUS_DONE_POS)) /**< CONT_STATUS_DONE Mask */
+
+#define MXC_F_I3C_REVA_CONT_STATUS_RX_RDY_POS 11 /**< CONT_STATUS_RX_RDY Position */
+#define MXC_F_I3C_REVA_CONT_STATUS_RX_RDY ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_STATUS_RX_RDY_POS)) /**< CONT_STATUS_RX_RDY Mask */
+
+#define MXC_F_I3C_REVA_CONT_STATUS_TX_NFULL_POS 12 /**< CONT_STATUS_TX_NFULL Position */
+#define MXC_F_I3C_REVA_CONT_STATUS_TX_NFULL ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_STATUS_TX_NFULL_POS)) /**< CONT_STATUS_TX_NFULL Mask */
+
+#define MXC_F_I3C_REVA_CONT_STATUS_IBI_WON_POS 13 /**< CONT_STATUS_IBI_WON Position */
+#define MXC_F_I3C_REVA_CONT_STATUS_IBI_WON ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_STATUS_IBI_WON_POS)) /**< CONT_STATUS_IBI_WON Mask */
+
+#define MXC_F_I3C_REVA_CONT_STATUS_ERRWARN_POS 15 /**< CONT_STATUS_ERRWARN Position */
+#define MXC_F_I3C_REVA_CONT_STATUS_ERRWARN ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_STATUS_ERRWARN_POS)) /**< CONT_STATUS_ERRWARN Mask */
+
+#define MXC_F_I3C_REVA_CONT_STATUS_CONT_TRANS_POS 19 /**< CONT_STATUS_CONT_TRANS Position */
+#define MXC_F_I3C_REVA_CONT_STATUS_CONT_TRANS ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_STATUS_CONT_TRANS_POS)) /**< CONT_STATUS_CONT_TRANS Mask */
+
+#define MXC_F_I3C_REVA_CONT_STATUS_IBI_ADDR_POS 24 /**< CONT_STATUS_IBI_ADDR Position */
+#define MXC_F_I3C_REVA_CONT_STATUS_IBI_ADDR ((uint32_t)(0x7FUL << MXC_F_I3C_REVA_CONT_STATUS_IBI_ADDR_POS)) /**< CONT_STATUS_IBI_ADDR Mask */
+
+/**@} end of group I3C_REVA_CONT_STATUS_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_CONT_IBIRULES I3C_REVA_CONT_IBIRULES
+ * @brief Controller IBI Registry and Rules Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_CONT_IBIRULES_ADDR0_POS 0 /**< CONT_IBIRULES_ADDR0 Position */
+#define MXC_F_I3C_REVA_CONT_IBIRULES_ADDR0 ((uint32_t)(0x3FUL << MXC_F_I3C_REVA_CONT_IBIRULES_ADDR0_POS)) /**< CONT_IBIRULES_ADDR0 Mask */
+
+#define MXC_F_I3C_REVA_CONT_IBIRULES_ADDR1_POS 6 /**< CONT_IBIRULES_ADDR1 Position */
+#define MXC_F_I3C_REVA_CONT_IBIRULES_ADDR1 ((uint32_t)(0x3FUL << MXC_F_I3C_REVA_CONT_IBIRULES_ADDR1_POS)) /**< CONT_IBIRULES_ADDR1 Mask */
+
+#define MXC_F_I3C_REVA_CONT_IBIRULES_ADDR2_POS 12 /**< CONT_IBIRULES_ADDR2 Position */
+#define MXC_F_I3C_REVA_CONT_IBIRULES_ADDR2 ((uint32_t)(0x3FUL << MXC_F_I3C_REVA_CONT_IBIRULES_ADDR2_POS)) /**< CONT_IBIRULES_ADDR2 Mask */
+
+#define MXC_F_I3C_REVA_CONT_IBIRULES_ADDR3_POS 18 /**< CONT_IBIRULES_ADDR3 Position */
+#define MXC_F_I3C_REVA_CONT_IBIRULES_ADDR3 ((uint32_t)(0x3FUL << MXC_F_I3C_REVA_CONT_IBIRULES_ADDR3_POS)) /**< CONT_IBIRULES_ADDR3 Mask */
+
+#define MXC_F_I3C_REVA_CONT_IBIRULES_ADDR4_POS 24 /**< CONT_IBIRULES_ADDR4 Position */
+#define MXC_F_I3C_REVA_CONT_IBIRULES_ADDR4 ((uint32_t)(0x3FUL << MXC_F_I3C_REVA_CONT_IBIRULES_ADDR4_POS)) /**< CONT_IBIRULES_ADDR4 Mask */
+
+#define MXC_F_I3C_REVA_CONT_IBIRULES_MSB0_POS 30 /**< CONT_IBIRULES_MSB0 Position */
+#define MXC_F_I3C_REVA_CONT_IBIRULES_MSB0 ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_IBIRULES_MSB0_POS)) /**< CONT_IBIRULES_MSB0 Mask */
+
+#define MXC_F_I3C_REVA_CONT_IBIRULES_NOBYTE_POS 31 /**< CONT_IBIRULES_NOBYTE Position */
+#define MXC_F_I3C_REVA_CONT_IBIRULES_NOBYTE ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_IBIRULES_NOBYTE_POS)) /**< CONT_IBIRULES_NOBYTE Mask */
+
+/**@} end of group I3C_REVA_CONT_IBIRULES_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_CONT_INTEN I3C_REVA_CONT_INTEN
+ * @brief Controller Interrupt Enable Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_CONT_INTEN_TARG_START_POS 8 /**< CONT_INTEN_TARG_START Position */
+#define MXC_F_I3C_REVA_CONT_INTEN_TARG_START ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTEN_TARG_START_POS)) /**< CONT_INTEN_TARG_START Mask */
+
+#define MXC_F_I3C_REVA_CONT_INTEN_REQ_DONE_POS 9 /**< CONT_INTEN_REQ_DONE Position */
+#define MXC_F_I3C_REVA_CONT_INTEN_REQ_DONE ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTEN_REQ_DONE_POS)) /**< CONT_INTEN_REQ_DONE Mask */
+
+#define MXC_F_I3C_REVA_CONT_INTEN_DONE_POS 10 /**< CONT_INTEN_DONE Position */
+#define MXC_F_I3C_REVA_CONT_INTEN_DONE ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTEN_DONE_POS)) /**< CONT_INTEN_DONE Mask */
+
+#define MXC_F_I3C_REVA_CONT_INTEN_RX_RDY_POS 11 /**< CONT_INTEN_RX_RDY Position */
+#define MXC_F_I3C_REVA_CONT_INTEN_RX_RDY ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTEN_RX_RDY_POS)) /**< CONT_INTEN_RX_RDY Mask */
+
+#define MXC_F_I3C_REVA_CONT_INTEN_TX_NFULL_POS 12 /**< CONT_INTEN_TX_NFULL Position */
+#define MXC_F_I3C_REVA_CONT_INTEN_TX_NFULL ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTEN_TX_NFULL_POS)) /**< CONT_INTEN_TX_NFULL Mask */
+
+#define MXC_F_I3C_REVA_CONT_INTEN_IBI_WON_POS 13 /**< CONT_INTEN_IBI_WON Position */
+#define MXC_F_I3C_REVA_CONT_INTEN_IBI_WON ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTEN_IBI_WON_POS)) /**< CONT_INTEN_IBI_WON Mask */
+
+#define MXC_F_I3C_REVA_CONT_INTEN_ERRWARN_POS 15 /**< CONT_INTEN_ERRWARN Position */
+#define MXC_F_I3C_REVA_CONT_INTEN_ERRWARN ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTEN_ERRWARN_POS)) /**< CONT_INTEN_ERRWARN Mask */
+
+#define MXC_F_I3C_REVA_CONT_INTEN_NOW_CONT_POS 19 /**< CONT_INTEN_NOW_CONT Position */
+#define MXC_F_I3C_REVA_CONT_INTEN_NOW_CONT ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTEN_NOW_CONT_POS)) /**< CONT_INTEN_NOW_CONT Mask */
+
+/**@} end of group I3C_REVA_CONT_INTEN_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_CONT_INTCLR I3C_REVA_CONT_INTCLR
+ * @brief Controller Interrupt Clear Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_CONT_INTCLR_TARG_START_POS 8 /**< CONT_INTCLR_TARG_START Position */
+#define MXC_F_I3C_REVA_CONT_INTCLR_TARG_START ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTCLR_TARG_START_POS)) /**< CONT_INTCLR_TARG_START Mask */
+
+#define MXC_F_I3C_REVA_CONT_INTCLR_REQ_DONE_POS 9 /**< CONT_INTCLR_REQ_DONE Position */
+#define MXC_F_I3C_REVA_CONT_INTCLR_REQ_DONE ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTCLR_REQ_DONE_POS)) /**< CONT_INTCLR_REQ_DONE Mask */
+
+#define MXC_F_I3C_REVA_CONT_INTCLR_DONE_POS 10 /**< CONT_INTCLR_DONE Position */
+#define MXC_F_I3C_REVA_CONT_INTCLR_DONE ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTCLR_DONE_POS)) /**< CONT_INTCLR_DONE Mask */
+
+#define MXC_F_I3C_REVA_CONT_INTCLR_RX_RDY_POS 11 /**< CONT_INTCLR_RX_RDY Position */
+#define MXC_F_I3C_REVA_CONT_INTCLR_RX_RDY ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTCLR_RX_RDY_POS)) /**< CONT_INTCLR_RX_RDY Mask */
+
+#define MXC_F_I3C_REVA_CONT_INTCLR_TX_NFULL_POS 12 /**< CONT_INTCLR_TX_NFULL Position */
+#define MXC_F_I3C_REVA_CONT_INTCLR_TX_NFULL ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTCLR_TX_NFULL_POS)) /**< CONT_INTCLR_TX_NFULL Mask */
+
+#define MXC_F_I3C_REVA_CONT_INTCLR_IBI_WON_POS 13 /**< CONT_INTCLR_IBI_WON Position */
+#define MXC_F_I3C_REVA_CONT_INTCLR_IBI_WON ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTCLR_IBI_WON_POS)) /**< CONT_INTCLR_IBI_WON Mask */
+
+#define MXC_F_I3C_REVA_CONT_INTCLR_ERRWARN_POS 15 /**< CONT_INTCLR_ERRWARN Position */
+#define MXC_F_I3C_REVA_CONT_INTCLR_ERRWARN ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTCLR_ERRWARN_POS)) /**< CONT_INTCLR_ERRWARN Mask */
+
+#define MXC_F_I3C_REVA_CONT_INTCLR_NOW_CONT_POS 19 /**< CONT_INTCLR_NOW_CONT Position */
+#define MXC_F_I3C_REVA_CONT_INTCLR_NOW_CONT ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTCLR_NOW_CONT_POS)) /**< CONT_INTCLR_NOW_CONT Mask */
+
+/**@} end of group I3C_REVA_CONT_INTCLR_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_CONT_INTFL I3C_REVA_CONT_INTFL
+ * @brief Controller Interrupt Flag Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_CONT_INTFL_TARG_START_POS 8 /**< CONT_INTFL_TARG_START Position */
+#define MXC_F_I3C_REVA_CONT_INTFL_TARG_START ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTFL_TARG_START_POS)) /**< CONT_INTFL_TARG_START Mask */
+
+#define MXC_F_I3C_REVA_CONT_INTFL_REQ_DONE_POS 9 /**< CONT_INTFL_REQ_DONE Position */
+#define MXC_F_I3C_REVA_CONT_INTFL_REQ_DONE ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTFL_REQ_DONE_POS)) /**< CONT_INTFL_REQ_DONE Mask */
+
+#define MXC_F_I3C_REVA_CONT_INTFL_DONE_POS 10 /**< CONT_INTFL_DONE Position */
+#define MXC_F_I3C_REVA_CONT_INTFL_DONE ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTFL_DONE_POS)) /**< CONT_INTFL_DONE Mask */
+
+#define MXC_F_I3C_REVA_CONT_INTFL_RX_RDY_POS 11 /**< CONT_INTFL_RX_RDY Position */
+#define MXC_F_I3C_REVA_CONT_INTFL_RX_RDY ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTFL_RX_RDY_POS)) /**< CONT_INTFL_RX_RDY Mask */
+
+#define MXC_F_I3C_REVA_CONT_INTFL_TX_NFULL_POS 12 /**< CONT_INTFL_TX_NFULL Position */
+#define MXC_F_I3C_REVA_CONT_INTFL_TX_NFULL ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTFL_TX_NFULL_POS)) /**< CONT_INTFL_TX_NFULL Mask */
+
+#define MXC_F_I3C_REVA_CONT_INTFL_IBI_WON_POS 13 /**< CONT_INTFL_IBI_WON Position */
+#define MXC_F_I3C_REVA_CONT_INTFL_IBI_WON ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTFL_IBI_WON_POS)) /**< CONT_INTFL_IBI_WON Mask */
+
+#define MXC_F_I3C_REVA_CONT_INTFL_ERRWARN_POS 15 /**< CONT_INTFL_ERRWARN Position */
+#define MXC_F_I3C_REVA_CONT_INTFL_ERRWARN ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTFL_ERRWARN_POS)) /**< CONT_INTFL_ERRWARN Mask */
+
+#define MXC_F_I3C_REVA_CONT_INTFL_NOW_CONT_POS 19 /**< CONT_INTFL_NOW_CONT Position */
+#define MXC_F_I3C_REVA_CONT_INTFL_NOW_CONT ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTFL_NOW_CONT_POS)) /**< CONT_INTFL_NOW_CONT Mask */
+
+/**@} end of group I3C_REVA_CONT_INTFL_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_CONT_ERRWARN I3C_REVA_CONT_ERRWARN
+ * @brief Controller Error and Warning Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_CONT_ERRWARN_NACK_POS 2 /**< CONT_ERRWARN_NACK Position */
+#define MXC_F_I3C_REVA_CONT_ERRWARN_NACK ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_ERRWARN_NACK_POS)) /**< CONT_ERRWARN_NACK Mask */
+
+#define MXC_F_I3C_REVA_CONT_ERRWARN_TX_ABT_POS 3 /**< CONT_ERRWARN_TX_ABT Position */
+#define MXC_F_I3C_REVA_CONT_ERRWARN_TX_ABT ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_ERRWARN_TX_ABT_POS)) /**< CONT_ERRWARN_TX_ABT Mask */
+
+#define MXC_F_I3C_REVA_CONT_ERRWARN_RX_TERM_POS 4 /**< CONT_ERRWARN_RX_TERM Position */
+#define MXC_F_I3C_REVA_CONT_ERRWARN_RX_TERM ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_ERRWARN_RX_TERM_POS)) /**< CONT_ERRWARN_RX_TERM Mask */
+
+#define MXC_F_I3C_REVA_CONT_ERRWARN_HDR_PAR_POS 9 /**< CONT_ERRWARN_HDR_PAR Position */
+#define MXC_F_I3C_REVA_CONT_ERRWARN_HDR_PAR ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_ERRWARN_HDR_PAR_POS)) /**< CONT_ERRWARN_HDR_PAR Mask */
+
+#define MXC_F_I3C_REVA_CONT_ERRWARN_HDR_CRC_POS 10 /**< CONT_ERRWARN_HDR_CRC Position */
+#define MXC_F_I3C_REVA_CONT_ERRWARN_HDR_CRC ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_ERRWARN_HDR_CRC_POS)) /**< CONT_ERRWARN_HDR_CRC Mask */
+
+#define MXC_F_I3C_REVA_CONT_ERRWARN_RX_UNR_POS 16 /**< CONT_ERRWARN_RX_UNR Position */
+#define MXC_F_I3C_REVA_CONT_ERRWARN_RX_UNR ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_ERRWARN_RX_UNR_POS)) /**< CONT_ERRWARN_RX_UNR Mask */
+
+#define MXC_F_I3C_REVA_CONT_ERRWARN_TX_OVR_POS 17 /**< CONT_ERRWARN_TX_OVR Position */
+#define MXC_F_I3C_REVA_CONT_ERRWARN_TX_OVR ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_ERRWARN_TX_OVR_POS)) /**< CONT_ERRWARN_TX_OVR Mask */
+
+#define MXC_F_I3C_REVA_CONT_ERRWARN_MSG_POS 18 /**< CONT_ERRWARN_MSG Position */
+#define MXC_F_I3C_REVA_CONT_ERRWARN_MSG ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_ERRWARN_MSG_POS)) /**< CONT_ERRWARN_MSG Mask */
+
+#define MXC_F_I3C_REVA_CONT_ERRWARN_INV_REQ_POS 19 /**< CONT_ERRWARN_INV_REQ Position */
+#define MXC_F_I3C_REVA_CONT_ERRWARN_INV_REQ ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_ERRWARN_INV_REQ_POS)) /**< CONT_ERRWARN_INV_REQ Mask */
+
+#define MXC_F_I3C_REVA_CONT_ERRWARN_TO_POS 20 /**< CONT_ERRWARN_TO Position */
+#define MXC_F_I3C_REVA_CONT_ERRWARN_TO ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_ERRWARN_TO_POS)) /**< CONT_ERRWARN_TO Mask */
+
+/**@} end of group I3C_REVA_CONT_ERRWARN_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_CONT_DMACTRL I3C_REVA_CONT_DMACTRL
+ * @brief Controller DMA Control Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_CONT_DMACTRL_RX_EN_POS 0 /**< CONT_DMACTRL_RX_EN Position */
+#define MXC_F_I3C_REVA_CONT_DMACTRL_RX_EN ((uint32_t)(0x3UL << MXC_F_I3C_REVA_CONT_DMACTRL_RX_EN_POS)) /**< CONT_DMACTRL_RX_EN Mask */
+#define MXC_V_I3C_REVA_CONT_DMACTRL_RX_EN_DIS ((uint32_t)0x0UL) /**< CONT_DMACTRL_RX_EN_DIS Value */
+#define MXC_S_I3C_REVA_CONT_DMACTRL_RX_EN_DIS (MXC_V_I3C_REVA_CONT_DMACTRL_RX_EN_DIS << MXC_F_I3C_REVA_CONT_DMACTRL_RX_EN_POS) /**< CONT_DMACTRL_RX_EN_DIS Setting */
+#define MXC_V_I3C_REVA_CONT_DMACTRL_RX_EN_ONE_FR ((uint32_t)0x1UL) /**< CONT_DMACTRL_RX_EN_ONE_FR Value */
+#define MXC_S_I3C_REVA_CONT_DMACTRL_RX_EN_ONE_FR (MXC_V_I3C_REVA_CONT_DMACTRL_RX_EN_ONE_FR << MXC_F_I3C_REVA_CONT_DMACTRL_RX_EN_POS) /**< CONT_DMACTRL_RX_EN_ONE_FR Setting */
+#define MXC_V_I3C_REVA_CONT_DMACTRL_RX_EN_EN ((uint32_t)0x2UL) /**< CONT_DMACTRL_RX_EN_EN Value */
+#define MXC_S_I3C_REVA_CONT_DMACTRL_RX_EN_EN (MXC_V_I3C_REVA_CONT_DMACTRL_RX_EN_EN << MXC_F_I3C_REVA_CONT_DMACTRL_RX_EN_POS) /**< CONT_DMACTRL_RX_EN_EN Setting */
+
+#define MXC_F_I3C_REVA_CONT_DMACTRL_TX_EN_POS 2 /**< CONT_DMACTRL_TX_EN Position */
+#define MXC_F_I3C_REVA_CONT_DMACTRL_TX_EN ((uint32_t)(0x3UL << MXC_F_I3C_REVA_CONT_DMACTRL_TX_EN_POS)) /**< CONT_DMACTRL_TX_EN Mask */
+#define MXC_V_I3C_REVA_CONT_DMACTRL_TX_EN_DIS ((uint32_t)0x0UL) /**< CONT_DMACTRL_TX_EN_DIS Value */
+#define MXC_S_I3C_REVA_CONT_DMACTRL_TX_EN_DIS (MXC_V_I3C_REVA_CONT_DMACTRL_TX_EN_DIS << MXC_F_I3C_REVA_CONT_DMACTRL_TX_EN_POS) /**< CONT_DMACTRL_TX_EN_DIS Setting */
+#define MXC_V_I3C_REVA_CONT_DMACTRL_TX_EN_ONE_FR ((uint32_t)0x1UL) /**< CONT_DMACTRL_TX_EN_ONE_FR Value */
+#define MXC_S_I3C_REVA_CONT_DMACTRL_TX_EN_ONE_FR (MXC_V_I3C_REVA_CONT_DMACTRL_TX_EN_ONE_FR << MXC_F_I3C_REVA_CONT_DMACTRL_TX_EN_POS) /**< CONT_DMACTRL_TX_EN_ONE_FR Setting */
+#define MXC_V_I3C_REVA_CONT_DMACTRL_TX_EN_EN ((uint32_t)0x2UL) /**< CONT_DMACTRL_TX_EN_EN Value */
+#define MXC_S_I3C_REVA_CONT_DMACTRL_TX_EN_EN (MXC_V_I3C_REVA_CONT_DMACTRL_TX_EN_EN << MXC_F_I3C_REVA_CONT_DMACTRL_TX_EN_POS) /**< CONT_DMACTRL_TX_EN_EN Setting */
+
+#define MXC_F_I3C_REVA_CONT_DMACTRL_WIDTH_POS 4 /**< CONT_DMACTRL_WIDTH Position */
+#define MXC_F_I3C_REVA_CONT_DMACTRL_WIDTH ((uint32_t)(0x3UL << MXC_F_I3C_REVA_CONT_DMACTRL_WIDTH_POS)) /**< CONT_DMACTRL_WIDTH Mask */
+#define MXC_V_I3C_REVA_CONT_DMACTRL_WIDTH_BYTE ((uint32_t)0x0UL) /**< CONT_DMACTRL_WIDTH_BYTE Value */
+#define MXC_S_I3C_REVA_CONT_DMACTRL_WIDTH_BYTE (MXC_V_I3C_REVA_CONT_DMACTRL_WIDTH_BYTE << MXC_F_I3C_REVA_CONT_DMACTRL_WIDTH_POS) /**< CONT_DMACTRL_WIDTH_BYTE Setting */
+#define MXC_V_I3C_REVA_CONT_DMACTRL_WIDTH_HALFWORD ((uint32_t)0x2UL) /**< CONT_DMACTRL_WIDTH_HALFWORD Value */
+#define MXC_S_I3C_REVA_CONT_DMACTRL_WIDTH_HALFWORD (MXC_V_I3C_REVA_CONT_DMACTRL_WIDTH_HALFWORD << MXC_F_I3C_REVA_CONT_DMACTRL_WIDTH_POS) /**< CONT_DMACTRL_WIDTH_HALFWORD Setting */
+
+/**@} end of group I3C_REVA_CONT_DMACTRL_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_CONT_FIFOCTRL I3C_REVA_CONT_FIFOCTRL
+ * @brief Controller FIFO Control Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_CONT_FIFOCTRL_TX_FLUSH_POS 0 /**< CONT_FIFOCTRL_TX_FLUSH Position */
+#define MXC_F_I3C_REVA_CONT_FIFOCTRL_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_FIFOCTRL_TX_FLUSH_POS)) /**< CONT_FIFOCTRL_TX_FLUSH Mask */
+
+#define MXC_F_I3C_REVA_CONT_FIFOCTRL_RX_FLUSH_POS 1 /**< CONT_FIFOCTRL_RX_FLUSH Position */
+#define MXC_F_I3C_REVA_CONT_FIFOCTRL_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_FIFOCTRL_RX_FLUSH_POS)) /**< CONT_FIFOCTRL_RX_FLUSH Mask */
+
+#define MXC_F_I3C_REVA_CONT_FIFOCTRL_UNLOCK_POS 3 /**< CONT_FIFOCTRL_UNLOCK Position */
+#define MXC_F_I3C_REVA_CONT_FIFOCTRL_UNLOCK ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_FIFOCTRL_UNLOCK_POS)) /**< CONT_FIFOCTRL_UNLOCK Mask */
+
+#define MXC_F_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_POS 4 /**< CONT_FIFOCTRL_TX_THD_LVL Position */
+#define MXC_F_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL ((uint32_t)(0x3UL << MXC_F_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_POS)) /**< CONT_FIFOCTRL_TX_THD_LVL Mask */
+#define MXC_V_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_EMPTY ((uint32_t)0x0UL) /**< CONT_FIFOCTRL_TX_THD_LVL_EMPTY Value */
+#define MXC_S_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_EMPTY (MXC_V_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_EMPTY << MXC_F_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_POS) /**< CONT_FIFOCTRL_TX_THD_LVL_EMPTY Setting */
+#define MXC_V_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_QUARTER_FULL ((uint32_t)0x1UL) /**< CONT_FIFOCTRL_TX_THD_LVL_QUARTER_FULL Value */
+#define MXC_S_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_QUARTER_FULL (MXC_V_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_QUARTER_FULL << MXC_F_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_POS) /**< CONT_FIFOCTRL_TX_THD_LVL_QUARTER_FULL Setting */
+#define MXC_V_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_HALF_FULL ((uint32_t)0x2UL) /**< CONT_FIFOCTRL_TX_THD_LVL_HALF_FULL Value */
+#define MXC_S_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_HALF_FULL (MXC_V_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_HALF_FULL << MXC_F_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_POS) /**< CONT_FIFOCTRL_TX_THD_LVL_HALF_FULL Setting */
+#define MXC_V_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_ALMOST_FULL ((uint32_t)0x3UL) /**< CONT_FIFOCTRL_TX_THD_LVL_ALMOST_FULL Value */
+#define MXC_S_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_ALMOST_FULL (MXC_V_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_ALMOST_FULL << MXC_F_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_POS) /**< CONT_FIFOCTRL_TX_THD_LVL_ALMOST_FULL Setting */
+
+#define MXC_F_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_POS 6 /**< CONT_FIFOCTRL_RX_THD_LVL Position */
+#define MXC_F_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL ((uint32_t)(0x3UL << MXC_F_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_POS)) /**< CONT_FIFOCTRL_RX_THD_LVL Mask */
+#define MXC_V_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_NOT_EMPTY ((uint32_t)0x0UL) /**< CONT_FIFOCTRL_RX_THD_LVL_NOT_EMPTY Value */
+#define MXC_S_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_NOT_EMPTY (MXC_V_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_NOT_EMPTY << MXC_F_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_POS) /**< CONT_FIFOCTRL_RX_THD_LVL_NOT_EMPTY Setting */
+#define MXC_V_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_QUARTER_FULL ((uint32_t)0x1UL) /**< CONT_FIFOCTRL_RX_THD_LVL_QUARTER_FULL Value */
+#define MXC_S_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_QUARTER_FULL (MXC_V_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_QUARTER_FULL << MXC_F_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_POS) /**< CONT_FIFOCTRL_RX_THD_LVL_QUARTER_FULL Setting */
+#define MXC_V_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_HALF_FULL ((uint32_t)0x2UL) /**< CONT_FIFOCTRL_RX_THD_LVL_HALF_FULL Value */
+#define MXC_S_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_HALF_FULL (MXC_V_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_HALF_FULL << MXC_F_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_POS) /**< CONT_FIFOCTRL_RX_THD_LVL_HALF_FULL Setting */
+#define MXC_V_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL ((uint32_t)0x3UL) /**< CONT_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL Value */
+#define MXC_S_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL (MXC_V_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL << MXC_F_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_POS) /**< CONT_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL Setting */
+
+#define MXC_F_I3C_REVA_CONT_FIFOCTRL_TX_LVL_POS 16 /**< CONT_FIFOCTRL_TX_LVL Position */
+#define MXC_F_I3C_REVA_CONT_FIFOCTRL_TX_LVL ((uint32_t)(0x3FUL << MXC_F_I3C_REVA_CONT_FIFOCTRL_TX_LVL_POS)) /**< CONT_FIFOCTRL_TX_LVL Mask */
+
+#define MXC_F_I3C_REVA_CONT_FIFOCTRL_RX_LVL_POS 24 /**< CONT_FIFOCTRL_RX_LVL Position */
+#define MXC_F_I3C_REVA_CONT_FIFOCTRL_RX_LVL ((uint32_t)(0x3FUL << MXC_F_I3C_REVA_CONT_FIFOCTRL_RX_LVL_POS)) /**< CONT_FIFOCTRL_RX_LVL Mask */
+
+#define MXC_F_I3C_REVA_CONT_FIFOCTRL_TX_FULL_POS 30 /**< CONT_FIFOCTRL_TX_FULL Position */
+#define MXC_F_I3C_REVA_CONT_FIFOCTRL_TX_FULL ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_FIFOCTRL_TX_FULL_POS)) /**< CONT_FIFOCTRL_TX_FULL Mask */
+
+#define MXC_F_I3C_REVA_CONT_FIFOCTRL_RX_EM_POS 31 /**< CONT_FIFOCTRL_RX_EM Position */
+#define MXC_F_I3C_REVA_CONT_FIFOCTRL_RX_EM ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_FIFOCTRL_RX_EM_POS)) /**< CONT_FIFOCTRL_RX_EM Mask */
+
+/**@} end of group I3C_REVA_CONT_FIFOCTRL_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_CONT_TXFIFO8 I3C_REVA_CONT_TXFIFO8
+ * @brief Controller Write Byte Data Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_CONT_TXFIFO8_DATA_POS 0 /**< CONT_TXFIFO8_DATA Position */
+#define MXC_F_I3C_REVA_CONT_TXFIFO8_DATA ((uint32_t)(0xFFUL << MXC_F_I3C_REVA_CONT_TXFIFO8_DATA_POS)) /**< CONT_TXFIFO8_DATA Mask */
+
+#define MXC_F_I3C_REVA_CONT_TXFIFO8_END_POS 8 /**< CONT_TXFIFO8_END Position */
+#define MXC_F_I3C_REVA_CONT_TXFIFO8_END ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_TXFIFO8_END_POS)) /**< CONT_TXFIFO8_END Mask */
+
+#define MXC_F_I3C_REVA_CONT_TXFIFO8_END2_POS 16 /**< CONT_TXFIFO8_END2 Position */
+#define MXC_F_I3C_REVA_CONT_TXFIFO8_END2 ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_TXFIFO8_END2_POS)) /**< CONT_TXFIFO8_END2 Mask */
+
+/**@} end of group I3C_REVA_CONT_TXFIFO8_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_CONT_TXFIFO8E I3C_REVA_CONT_TXFIFO8E
+ * @brief Controller Write Byte Data as End Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_CONT_TXFIFO8E_DATA_POS 0 /**< CONT_TXFIFO8E_DATA Position */
+#define MXC_F_I3C_REVA_CONT_TXFIFO8E_DATA ((uint32_t)(0xFFUL << MXC_F_I3C_REVA_CONT_TXFIFO8E_DATA_POS)) /**< CONT_TXFIFO8E_DATA Mask */
+
+/**@} end of group I3C_REVA_CONT_TXFIFO8E_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_CONT_TXFIFO16 I3C_REVA_CONT_TXFIFO16
+ * @brief Controller Write Half-Word Data Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_CONT_TXFIFO16_DATA_POS 0 /**< CONT_TXFIFO16_DATA Position */
+#define MXC_F_I3C_REVA_CONT_TXFIFO16_DATA ((uint32_t)(0xFFFFUL << MXC_F_I3C_REVA_CONT_TXFIFO16_DATA_POS)) /**< CONT_TXFIFO16_DATA Mask */
+
+#define MXC_F_I3C_REVA_CONT_TXFIFO16_END_POS 16 /**< CONT_TXFIFO16_END Position */
+#define MXC_F_I3C_REVA_CONT_TXFIFO16_END ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_TXFIFO16_END_POS)) /**< CONT_TXFIFO16_END Mask */
+
+/**@} end of group I3C_REVA_CONT_TXFIFO16_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_CONT_TXFIFO16E I3C_REVA_CONT_TXFIFO16E
+ * @brief Controller Write Half-Word Data as End Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_CONT_TXFIFO16E_DATA_POS 0 /**< CONT_TXFIFO16E_DATA Position */
+#define MXC_F_I3C_REVA_CONT_TXFIFO16E_DATA ((uint32_t)(0xFFFFUL << MXC_F_I3C_REVA_CONT_TXFIFO16E_DATA_POS)) /**< CONT_TXFIFO16E_DATA Mask */
+
+/**@} end of group I3C_REVA_CONT_TXFIFO16E_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_CONT_RXFIFO8 I3C_REVA_CONT_RXFIFO8
+ * @brief Controller Read Byte Data Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_CONT_RXFIFO8_DATA_POS 0 /**< CONT_RXFIFO8_DATA Position */
+#define MXC_F_I3C_REVA_CONT_RXFIFO8_DATA ((uint32_t)(0xFFUL << MXC_F_I3C_REVA_CONT_RXFIFO8_DATA_POS)) /**< CONT_RXFIFO8_DATA Mask */
+
+/**@} end of group I3C_REVA_CONT_RXFIFO8_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_CONT_RXFIFO16 I3C_REVA_CONT_RXFIFO16
+ * @brief Controller Read Half-Word Data Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_CONT_RXFIFO16_DATA_POS 0 /**< CONT_RXFIFO16_DATA Position */
+#define MXC_F_I3C_REVA_CONT_RXFIFO16_DATA ((uint32_t)(0xFFFFUL << MXC_F_I3C_REVA_CONT_RXFIFO16_DATA_POS)) /**< CONT_RXFIFO16_DATA Mask */
+
+/**@} end of group I3C_REVA_CONT_RXFIFO16_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_CONT_TXFIFO8O I3C_REVA_CONT_TXFIFO8O
+ * @brief Controller Byte-Only Write Byte Data Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_CONT_TXFIFO8O_DATA_POS 0 /**< CONT_TXFIFO8O_DATA Position */
+#define MXC_F_I3C_REVA_CONT_TXFIFO8O_DATA ((uint32_t)(0xFFUL << MXC_F_I3C_REVA_CONT_TXFIFO8O_DATA_POS)) /**< CONT_TXFIFO8O_DATA Mask */
+
+/**@} end of group I3C_REVA_CONT_TXFIFO8O_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_CONT_TXSDRMSG_CTRL I3C_REVA_CONT_TXSDRMSG_CTRL
+ * @brief Controller Start or Continue SDR Message Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_CONT_TXSDRMSG_CTRL_RDWR_DIR_POS 0 /**< CONT_TXSDRMSG_CTRL_RDWR_DIR Position */
+#define MXC_F_I3C_REVA_CONT_TXSDRMSG_CTRL_RDWR_DIR ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_TXSDRMSG_CTRL_RDWR_DIR_POS)) /**< CONT_TXSDRMSG_CTRL_RDWR_DIR Mask */
+
+#define MXC_F_I3C_REVA_CONT_TXSDRMSG_CTRL_ADDR_POS 1 /**< CONT_TXSDRMSG_CTRL_ADDR Position */
+#define MXC_F_I3C_REVA_CONT_TXSDRMSG_CTRL_ADDR ((uint32_t)(0x7FUL << MXC_F_I3C_REVA_CONT_TXSDRMSG_CTRL_ADDR_POS)) /**< CONT_TXSDRMSG_CTRL_ADDR Mask */
+
+#define MXC_F_I3C_REVA_CONT_TXSDRMSG_CTRL_END_POS 8 /**< CONT_TXSDRMSG_CTRL_END Position */
+#define MXC_F_I3C_REVA_CONT_TXSDRMSG_CTRL_END ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_TXSDRMSG_CTRL_END_POS)) /**< CONT_TXSDRMSG_CTRL_END Mask */
+
+#define MXC_F_I3C_REVA_CONT_TXSDRMSG_CTRL_I2C_EN_POS 10 /**< CONT_TXSDRMSG_CTRL_I2C_EN Position */
+#define MXC_F_I3C_REVA_CONT_TXSDRMSG_CTRL_I2C_EN ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_TXSDRMSG_CTRL_I2C_EN_POS)) /**< CONT_TXSDRMSG_CTRL_I2C_EN Mask */
+
+#define MXC_F_I3C_REVA_CONT_TXSDRMSG_CTRL_LEN_POS 11 /**< CONT_TXSDRMSG_CTRL_LEN Position */
+#define MXC_F_I3C_REVA_CONT_TXSDRMSG_CTRL_LEN ((uint32_t)(0x1FUL << MXC_F_I3C_REVA_CONT_TXSDRMSG_CTRL_LEN_POS)) /**< CONT_TXSDRMSG_CTRL_LEN Mask */
+
+/**@} end of group I3C_REVA_CONT_TXSDRMSG_CTRL_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_CONT_TXSDRMSG_FIFO I3C_REVA_CONT_TXSDRMSG_FIFO
+ * @brief Controller Start or Continue SDR Message Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_CONT_TXSDRMSG_FIFO_DATA_POS 0 /**< CONT_TXSDRMSG_FIFO_DATA Position */
+#define MXC_F_I3C_REVA_CONT_TXSDRMSG_FIFO_DATA ((uint32_t)(0xFFFFUL << MXC_F_I3C_REVA_CONT_TXSDRMSG_FIFO_DATA_POS)) /**< CONT_TXSDRMSG_FIFO_DATA Mask */
+
+/**@} end of group I3C_REVA_CONT_TXSDRMSG_FIFO_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_CONT_RXSDRMSG I3C_REVA_CONT_RXSDRMSG
+ * @brief Controller Read SDR Message Data Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_CONT_RXSDRMSG_DATA_POS 0 /**< CONT_RXSDRMSG_DATA Position */
+#define MXC_F_I3C_REVA_CONT_RXSDRMSG_DATA ((uint32_t)(0xFFFFUL << MXC_F_I3C_REVA_CONT_RXSDRMSG_DATA_POS)) /**< CONT_RXSDRMSG_DATA Mask */
+
+/**@} end of group I3C_REVA_CONT_RXSDRMSG_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_CONT_TXDDRMSG I3C_REVA_CONT_TXDDRMSG
+ * @brief Controller Start or Continue DDR Message Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_CONT_TXDDRMSG_MSG_POS 0 /**< CONT_TXDDRMSG_MSG Position */
+#define MXC_F_I3C_REVA_CONT_TXDDRMSG_MSG ((uint32_t)(0xFFFFUL << MXC_F_I3C_REVA_CONT_TXDDRMSG_MSG_POS)) /**< CONT_TXDDRMSG_MSG Mask */
+
+/**@} end of group I3C_REVA_CONT_TXDDRMSG_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_CONT_RXDDR16 I3C_REVA_CONT_RXDDR16
+ * @brief Controller Read DDR Message Data Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_CONT_RXDDR16_DATA_POS 0 /**< CONT_RXDDR16_DATA Position */
+#define MXC_F_I3C_REVA_CONT_RXDDR16_DATA ((uint32_t)(0xFFFFUL << MXC_F_I3C_REVA_CONT_RXDDR16_DATA_POS)) /**< CONT_RXDDR16_DATA Mask */
+
+/**@} end of group I3C_REVA_CONT_RXDDR16_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_CONT_DYNADDR I3C_REVA_CONT_DYNADDR
+ * @brief Controller Dynamic Address Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_CONT_DYNADDR_ADDR_POS 1 /**< CONT_DYNADDR_ADDR Position */
+#define MXC_F_I3C_REVA_CONT_DYNADDR_ADDR ((uint32_t)(0x7FUL << MXC_F_I3C_REVA_CONT_DYNADDR_ADDR_POS)) /**< CONT_DYNADDR_ADDR Mask */
+
+#define MXC_F_I3C_REVA_CONT_DYNADDR_VALID_POS 8 /**< CONT_DYNADDR_VALID Position */
+#define MXC_F_I3C_REVA_CONT_DYNADDR_VALID ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_DYNADDR_VALID_POS)) /**< CONT_DYNADDR_VALID Mask */
+
+/**@} end of group I3C_REVA_CONT_DYNADDR_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_TARG_GROUPDEF I3C_REVA_TARG_GROUPDEF
+ * @brief Target Group Definition Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_TARG_GROUPDEF_ADDR_EN_POS 0 /**< TARG_GROUPDEF_ADDR_EN Position */
+#define MXC_F_I3C_REVA_TARG_GROUPDEF_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_GROUPDEF_ADDR_EN_POS)) /**< TARG_GROUPDEF_ADDR_EN Mask */
+
+#define MXC_F_I3C_REVA_TARG_GROUPDEF_ADDR_POS 1 /**< TARG_GROUPDEF_ADDR Position */
+#define MXC_F_I3C_REVA_TARG_GROUPDEF_ADDR ((uint32_t)(0x7FUL << MXC_F_I3C_REVA_TARG_GROUPDEF_ADDR_POS)) /**< TARG_GROUPDEF_ADDR Mask */
+
+/**@} end of group I3C_REVA_TARG_GROUPDEF_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_TARG_MAPCTRL0 I3C_REVA_TARG_MAPCTRL0
+ * @brief Target Primary Map Control Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_TARG_MAPCTRL0_DYNADDR_EN_POS 0 /**< TARG_MAPCTRL0_DYNADDR_EN Position */
+#define MXC_F_I3C_REVA_TARG_MAPCTRL0_DYNADDR_EN ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_MAPCTRL0_DYNADDR_EN_POS)) /**< TARG_MAPCTRL0_DYNADDR_EN Mask */
+
+#define MXC_F_I3C_REVA_TARG_MAPCTRL0_DYNADDR_POS 1 /**< TARG_MAPCTRL0_DYNADDR Position */
+#define MXC_F_I3C_REVA_TARG_MAPCTRL0_DYNADDR ((uint32_t)(0x7FUL << MXC_F_I3C_REVA_TARG_MAPCTRL0_DYNADDR_POS)) /**< TARG_MAPCTRL0_DYNADDR Mask */
+
+#define MXC_F_I3C_REVA_TARG_MAPCTRL0_CAUSE_POS 8 /**< TARG_MAPCTRL0_CAUSE Position */
+#define MXC_F_I3C_REVA_TARG_MAPCTRL0_CAUSE ((uint32_t)(0x7UL << MXC_F_I3C_REVA_TARG_MAPCTRL0_CAUSE_POS)) /**< TARG_MAPCTRL0_CAUSE Mask */
+
+/**@} end of group I3C_REVA_TARG_MAPCTRL0_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_TARG_MAPCTRL1 I3C_REVA_TARG_MAPCTRL1
+ * @brief Target Map Control 1 Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_TARG_MAPCTRL1_EN_POS 0 /**< TARG_MAPCTRL1_EN Position */
+#define MXC_F_I3C_REVA_TARG_MAPCTRL1_EN ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_MAPCTRL1_EN_POS)) /**< TARG_MAPCTRL1_EN Mask */
+
+#define MXC_F_I3C_REVA_TARG_MAPCTRL1_ADDR_POS 1 /**< TARG_MAPCTRL1_ADDR Position */
+#define MXC_F_I3C_REVA_TARG_MAPCTRL1_ADDR ((uint32_t)(0x7FUL << MXC_F_I3C_REVA_TARG_MAPCTRL1_ADDR_POS)) /**< TARG_MAPCTRL1_ADDR Mask */
+
+#define MXC_F_I3C_REVA_TARG_MAPCTRL1_STATADDR_EN_POS 8 /**< TARG_MAPCTRL1_STATADDR_EN Position */
+#define MXC_F_I3C_REVA_TARG_MAPCTRL1_STATADDR_EN ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_MAPCTRL1_STATADDR_EN_POS)) /**< TARG_MAPCTRL1_STATADDR_EN Mask */
+
+#define MXC_F_I3C_REVA_TARG_MAPCTRL1_STATADDR_10B_POS 9 /**< TARG_MAPCTRL1_STATADDR_10B Position */
+#define MXC_F_I3C_REVA_TARG_MAPCTRL1_STATADDR_10B ((uint32_t)(0x7UL << MXC_F_I3C_REVA_TARG_MAPCTRL1_STATADDR_10B_POS)) /**< TARG_MAPCTRL1_STATADDR_10B Mask */
+
+#define MXC_F_I3C_REVA_TARG_MAPCTRL1_NACK_POS 12 /**< TARG_MAPCTRL1_NACK Position */
+#define MXC_F_I3C_REVA_TARG_MAPCTRL1_NACK ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_MAPCTRL1_NACK_POS)) /**< TARG_MAPCTRL1_NACK Mask */
+
+/**@} end of group I3C_REVA_TARG_MAPCTRL1_Register */
+
+/**
+ * @ingroup i3c_reva_registers
+ * @defgroup I3C_REVA_TARG_MAPCTRL2 I3C_REVA_TARG_MAPCTRL2
+ * @brief Target Map Control 2 Register.
+ * @{
+ */
+#define MXC_F_I3C_REVA_TARG_MAPCTRL2_EN_POS 0 /**< TARG_MAPCTRL2_EN Position */
+#define MXC_F_I3C_REVA_TARG_MAPCTRL2_EN ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_MAPCTRL2_EN_POS)) /**< TARG_MAPCTRL2_EN Mask */
+
+#define MXC_F_I3C_REVA_TARG_MAPCTRL2_ADDR_POS 1 /**< TARG_MAPCTRL2_ADDR Position */
+#define MXC_F_I3C_REVA_TARG_MAPCTRL2_ADDR ((uint32_t)(0x7FUL << MXC_F_I3C_REVA_TARG_MAPCTRL2_ADDR_POS)) /**< TARG_MAPCTRL2_ADDR Mask */
+
+#define MXC_F_I3C_REVA_TARG_MAPCTRL2_STATADDR_EN_POS 8 /**< TARG_MAPCTRL2_STATADDR_EN Position */
+#define MXC_F_I3C_REVA_TARG_MAPCTRL2_STATADDR_EN ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_MAPCTRL2_STATADDR_EN_POS)) /**< TARG_MAPCTRL2_STATADDR_EN Mask */
+
+#define MXC_F_I3C_REVA_TARG_MAPCTRL2_NACK_POS 12 /**< TARG_MAPCTRL2_NACK Position */
+#define MXC_F_I3C_REVA_TARG_MAPCTRL2_NACK ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_MAPCTRL2_NACK_POS)) /**< TARG_MAPCTRL2_NACK Mask */
+
+#define MXC_F_I3C_REVA_TARG_MAPCTRL2_AUTO_EN_POS 13 /**< TARG_MAPCTRL2_AUTO_EN Position */
+#define MXC_F_I3C_REVA_TARG_MAPCTRL2_AUTO_EN ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_MAPCTRL2_AUTO_EN_POS)) /**< TARG_MAPCTRL2_AUTO_EN Mask */
+
+#define MXC_F_I3C_REVA_TARG_MAPCTRL2_PID_POS 14 /**< TARG_MAPCTRL2_PID Position */
+#define MXC_F_I3C_REVA_TARG_MAPCTRL2_PID ((uint32_t)(0x3FFFFUL << MXC_F_I3C_REVA_TARG_MAPCTRL2_PID_POS)) /**< TARG_MAPCTRL2_PID Mask */
+
+/**@} end of group I3C_REVA_TARG_MAPCTRL2_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_I3C_I3C_REVA_REGS_H_
diff --git a/Libraries/PeriphDrivers/max32657_files.mk b/Libraries/PeriphDrivers/max32657_files.mk
index e568a2be42f..4b198a60a7f 100644
--- a/Libraries/PeriphDrivers/max32657_files.mk
+++ b/Libraries/PeriphDrivers/max32657_files.mk
@@ -73,6 +73,10 @@ PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/GPIO/gpio_common.c
PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/GPIO/gpio_me30.c
PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/GPIO/gpio_reva.c
+PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/I3C
+PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/I3C/i3c_me30.c
+PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/I3C/i3c_reva.c
+
PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/ICC
PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/ICC/icc_common.c
PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/ICC/icc_me30.c