Iris Card and Interconnect Design

[jamesmunns]

Anachro Iris is intended to be the second generation of hardware, succeeding the Anachro Stargazer.

I'd like to rethink how cards are connected here, as a full parallel-connected backplane is not actually fully necessary for an Anachro PC.

Some items I have considered:

• A smaller card connector, allowing for a smaller motherboard
• Potentially a non-card layout, using headers/wires to connect each Card to the Arbitrator (think like an octopus)
• Fewer pins between each card and the backplane. For example, full functionality could be provided with only 8 pins:
  • A single GO line
  • CIPO
  • COPI
  • CSn
  • CLK
  • +5v0 or +3v3
  • GND
  • Reset

There is no ETA for the design of the Iris, and it makes sense to continue prototyping with the Stargazer for now. This issue is for collecting ideas and discussions when it makes sense to iterate.

At the moment, I am not ready to fund the first hardware spins of this, but if you would like to design one of these and would need financial assistance, please get in contact with me.