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Hi amirah-sri I have a small gift for you. If you like to learn about the system verilog, VHDL & Risc-V assembly then there are a links which can help you.
Link 1 Sarah Harris & David Harris Digital Design and Computer Architecture
Link 2 Learning Journey how to write system verilog testbench in C++ using Verilator tool
Book:- https://github.com/muhammadtalhasami/sv_verilator/tree/main/Book
Hi amirah-sri I have a small gift for you. If you like to learn about the system verilog, VHDL & Risc-V assembly then there are a links which can help you.
Link 1 Sarah Harris & David Harris Digital Design and Computer Architecture
Link 2 Learning Journey how to write system verilog testbench in C++ using Verilator tool
Book:-
https://github.com/muhammadtalhasami/sv_verilator/tree/main/Book
Verilator:-
https://github.com/muhammadtalhasami/sv_verilator
I hope you will like this small gift 🎁😊
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