Can I break the max speed limited by clk frequency?

[rliangcn]

Hello,
Because 'prescale' = Fclk/(baud*8), so the max baud is when 'prescale=1' and limited by the clock frequency.
If I want a baud=50mbps, then I need a clock which frequency is higher than about 500mhz.
I guess that the prescale parameter determined the over-sample times (not sure), so is it possible to lessen the over-sample times and achieved a higher baud?

Thank you very much!

[KohakuBlueleaf]

If your uart connection is via an onboard FTDI chip to covert to usb. the max baud rate is determind by that chips.(Normally 6Mbuad or 12MBaud)
And if you are just use two actual wire to connect 2 uart device. Your baud rate will be very hard to get up to over 1Mbaud/s.
(Bcuz real world data transmission is very complicated)

And with the document from xilinx. the prescale should not lower than 16. with some real world cases, prescale should not lower than 32.

[KohakuBlueleaf]

Oh I mistake something.
The prescale can be 1 but recommend to 2~4.
(Wait prescale*8 for 1 bit)