diff --git a/example/Genesys2/fpga/Makefile b/example/Genesys2/fpga/Makefile
new file mode 100644
index 000000000..d318e9b0d
--- /dev/null
+++ b/example/Genesys2/fpga/Makefile
@@ -0,0 +1,25 @@
+# Targets
+TARGETS:=
+
+# Subdirectories
+SUBDIRS = fpga
+SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS))
+
+# Rules
+.PHONY: all
+all: $(SUBDIRS) $(TARGETS)
+
+.PHONY: $(SUBDIRS)
+$(SUBDIRS):
+	cd $@ && $(MAKE)
+
+.PHONY: $(SUBDIRS_CLEAN)
+$(SUBDIRS_CLEAN):
+	cd $(@:.clean=) && $(MAKE) clean
+
+.PHONY: clean
+clean: $(SUBDIRS_CLEAN)
+	-rm -rf $(TARGETS)
+
+program:
+	djtgcfg prog -d Genesys2 --index 0 --file fpga/fpga.bit
diff --git a/example/Genesys2/fpga/README.md b/example/Genesys2/fpga/README.md
new file mode 100644
index 000000000..e987a0b89
--- /dev/null
+++ b/example/Genesys2/fpga/README.md
@@ -0,0 +1,26 @@
+# Verilog Ethernet Genesys2 Example Design
+
+## Introduction
+
+This example design targets the Digilent Genesys FPGA board.
+
+The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
+will echo back any packets received.  The design will also respond correctly
+to ARP requests.  
+
+FPGA: xc7k325tffg900-2
+PHY: Realtek RTL8211E-VL
+
+## How to build
+
+Run make to build.  Ensure that the Xilinx Vivado toolchain components are
+in PATH.  
+
+## How to test
+
+Run make program to program the Nexys Video board with the Digilent command
+line tools.  Then run netcat -u 192.168.1.128 1234 to open a UDP connection to
+port 1234.  Any text entered into netcat will be echoed back after pressing
+enter.  
+
+
diff --git a/example/Genesys2/fpga/common/vivado.mk b/example/Genesys2/fpga/common/vivado.mk
new file mode 100644
index 000000000..a54b530f6
--- /dev/null
+++ b/example/Genesys2/fpga/common/vivado.mk
@@ -0,0 +1,118 @@
+###################################################################
+# 
+# Xilinx Vivado FPGA Makefile
+# 
+# Copyright (c) 2016 Alex Forencich
+# 
+###################################################################
+# 
+# Parameters:
+# FPGA_TOP - Top module name
+# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
+# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
+# SYN_FILES - space-separated list of source files
+# INC_FILES - space-separated list of include files
+# XDC_FILES - space-separated list of timing constraint files
+# XCI_FILES - space-separated list of IP XCI files
+# 
+# Example:
+# 
+# FPGA_TOP = fpga
+# FPGA_FAMILY = VirtexUltrascale
+# FPGA_DEVICE = xcvu095-ffva2104-2-e
+# SYN_FILES = rtl/fpga.v
+# XDC_FILES = fpga.xdc
+# XCI_FILES = ip/pcspma.xci
+# include ../common/vivado.mk
+# 
+###################################################################
+
+# phony targets
+.PHONY: clean fpga
+
+# prevent make from deleting intermediate files and reports
+.PRECIOUS: %.xpr %.bit
+.SECONDARY:
+
+CONFIG ?= config.mk
+-include ../$(CONFIG)
+
+SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES))
+INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES))
+XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES))
+
+ifdef XDC_FILES
+  XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES))
+else
+  XDC_FILES_REL = $(FPGA_TOP).xdc
+endif
+
+###################################################################
+# Main Targets
+#
+# all: build everything
+# clean: remove output files and project files
+###################################################################
+
+all: fpga
+
+fpga: $(FPGA_TOP).bit
+
+tmpclean:
+	-rm -rf *.log *.jou *.cache *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
+	-rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
+
+clean: tmpclean
+	-rm -rf *.bit program.tcl
+
+distclean: clean
+	-rm -rf rev
+
+###################################################################
+# Target implementations
+###################################################################
+
+# Vivado project file
+%.xpr: Makefile $(XCI_FILES_REL)
+	rm -rf defines.v
+	touch defines.v
+	for x in $(DEFS); do echo '`define' $$x >> defines.v; done
+	echo "create_project -force -part $(FPGA_PART) $*" > create_project.tcl
+	echo "add_files -fileset sources_1 defines.v" >> create_project.tcl
+	for x in $(SYN_FILES_REL); do echo "add_files -fileset sources_1 $$x" >> create_project.tcl; done
+	for x in $(XDC_FILES_REL); do echo "add_files -fileset constrs_1 $$x" >> create_project.tcl; done
+	for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> create_project.tcl; done
+	echo "exit" >> create_project.tcl
+	vivado -mode batch -source create_project.tcl
+
+# synthesis run
+%.runs/synth_1/%.dcp: %.xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL)
+	echo "open_project $*.xpr" > run_synth.tcl
+	echo "reset_run synth_1" >> run_synth.tcl
+	echo "launch_runs synth_1" >> run_synth.tcl
+	echo "wait_on_run synth_1" >> run_synth.tcl
+	echo "exit" >> run_synth.tcl
+	vivado -mode batch -source run_synth.tcl
+
+# implementation run
+%.runs/impl_1/%_routed.dcp: %.runs/synth_1/%.dcp
+	echo "open_project $*.xpr" > run_impl.tcl
+	echo "reset_run impl_1" >> run_impl.tcl
+	echo "launch_runs impl_1" >> run_impl.tcl
+	echo "wait_on_run impl_1" >> run_impl.tcl
+	echo "exit" >> run_impl.tcl
+	vivado -mode batch -source run_impl.tcl
+
+# bit file
+%.bit: %.runs/impl_1/%_routed.dcp
+	echo "open_project $*.xpr" > generate_bit.tcl
+	echo "open_run impl_1" >> generate_bit.tcl
+	echo "write_bitstream -force $*.bit" >> generate_bit.tcl
+	echo "exit" >> generate_bit.tcl
+	vivado -mode batch -source generate_bit.tcl
+	mkdir -p rev
+	EXT=bit; COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
+	do let COUNT=COUNT+1; done; \
+	cp $@ rev/$*_rev$$COUNT.$$EXT; \
+	echo "Output: rev/$*_rev$$COUNT.$$EXT";
diff --git a/example/Genesys2/fpga/eth.xdc b/example/Genesys2/fpga/eth.xdc
new file mode 100644
index 000000000..d9780aa1c
--- /dev/null
+++ b/example/Genesys2/fpga/eth.xdc
@@ -0,0 +1,5 @@
+# Ethernet constraints
+
+# IDELAY on RGMII from PHY chip
+set_property IDELAY_VALUE 0 [get_cells {phy_rx_ctl_idelay phy_rxd_idelay_*}]
+
diff --git a/example/Genesys2/fpga/fpga.xdc b/example/Genesys2/fpga/fpga.xdc
new file mode 100644
index 000000000..4dd9d1839
--- /dev/null
+++ b/example/Genesys2/fpga/fpga.xdc
@@ -0,0 +1,70 @@
+# XDC constraints for the Digilent Nexys Video board
+# part: xc7a200tsbg484-1
+
+# General configuration
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+
+# 200 MHz clock
+set_property -dict { PACKAGE_PIN AD11  IOSTANDARD LVDS     } [get_ports { sysclk_n }]; #IO_L12N_T1_MRCC_33 Sch=sysclk_n
+set_property -dict { PACKAGE_PIN AD12  IOSTANDARD LVDS     } [get_ports { sysclk_p }]; #IO_L12P_T1_MRCC_33 Sch=sysclk_p
+#Comment this out if you use clock wizard
+#create_clock -period 5.000 -name clk [get_ports sysclk_p]
+set_clock_groups -asynchronous -group [get_clocks clk -include_generated_clocks]
+
+# LEDs 
+set_property -dict {LOC T28 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {led[0]}]
+set_property -dict {LOC V19 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {led[1]}]
+set_property -dict {LOC U30 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {led[2]}]
+set_property -dict {LOC U29 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {led[3]}]
+set_property -dict {LOC V20 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {led[4]}]
+set_property -dict {LOC V26 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {led[5]}]
+set_property -dict {LOC W24 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {led[6]}]
+set_property -dict {LOC W23 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {led[7]}]
+
+# Reset button
+set_property -dict {LOC R19 IOSTANDARD LVCMOS33} [get_ports reset_n]
+
+# Push buttons
+set_property -dict {LOC B19 IOSTANDARD LVCMOS12} [get_ports btnu]
+set_property -dict {LOC M20 IOSTANDARD LVCMOS12} [get_ports btnl]
+set_property -dict {LOC M19 IOSTANDARD LVCMOS12} [get_ports btnd]
+set_property -dict {LOC C19 IOSTANDARD LVCMOS12} [get_ports btnr]
+set_property -dict {LOC E18 IOSTANDARD LVCMOS12} [get_ports btnc]
+
+# Toggle switches
+set_property -dict {LOC G19 IOSTANDARD LVCMOS12} [get_ports {sw[0]}]
+set_property -dict {LOC G25 IOSTANDARD LVCMOS12} [get_ports {sw[1]}]
+set_property -dict {LOC H24 IOSTANDARD LVCMOS12} [get_ports {sw[2]}]
+set_property -dict {LOC K19 IOSTANDARD LVCMOS12} [get_ports {sw[3]}]
+set_property -dict {LOC N19 IOSTANDARD LVCMOS12} [get_ports {sw[4]}]
+set_property -dict {LOC P19 IOSTANDARD LVCMOS12} [get_ports {sw[5]}]
+set_property -dict {LOC P26 IOSTANDARD LVCMOS33} [get_ports {sw[6]}]
+set_property -dict {LOC P27 IOSTANDARD LVCMOS33} [get_ports {sw[7]}]
+
+# UART
+set_property -dict {LOC Y23 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports uart_txd]
+set_property -dict {LOC Y20 IOSTANDARD LVCMOS33} [get_ports uart_rxd]
+
+# Gigabit Ethernet RGMII PHY
+set_property -dict {LOC AG10 IOSTANDARD LVCMOS15} [get_ports phy_rx_clk]
+set_property -dict {LOC AJ14 IOSTANDARD LVCMOS15} [get_ports {phy_rxd[0]}]
+set_property -dict {LOC AH14 IOSTANDARD LVCMOS15} [get_ports {phy_rxd[1]}]
+set_property -dict {LOC AK13 IOSTANDARD LVCMOS15} [get_ports {phy_rxd[2]}]
+set_property -dict {LOC AJ13 IOSTANDARD LVCMOS15} [get_ports {phy_rxd[3]}]
+set_property -dict {LOC AH11 IOSTANDARD LVCMOS15} [get_ports phy_rx_ctl]
+set_property -dict {LOC AE10 IOSTANDARD LVCMOS15 SLEW FAST DRIVE 16} [get_ports phy_tx_clk]
+set_property -dict {LOC AJ12 IOSTANDARD LVCMOS15 SLEW FAST DRIVE 16} [get_ports {phy_txd[0]}]
+set_property -dict {LOC AK11 IOSTANDARD LVCMOS15 SLEW FAST DRIVE 16} [get_ports {phy_txd[1]}]
+set_property -dict {LOC AJ11 IOSTANDARD LVCMOS15 SLEW FAST DRIVE 16} [get_ports {phy_txd[2]}]
+set_property -dict {LOC AK10 IOSTANDARD LVCMOS15 SLEW FAST DRIVE 16} [get_ports {phy_txd[3]}]
+set_property -dict {LOC AK14 IOSTANDARD LVCMOS15 SLEW FAST DRIVE 16} [get_ports phy_tx_ctl]
+set_property -dict {LOC AH24 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_reset_n]
+set_property -dict {LOC AK16 IOSTANDARD LVCMOS18} [get_ports phy_int_n]
+set_property -dict {LOC AK15 IOSTANDARD LVCMOS18} [get_ports phy_pme_n]
+set_property -dict {LOC AG12 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports phy_mdio]
+set_property -dict {LOC AF12 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports phy_mdc]
+
+create_clock -period 8.000 -name phy_rx_clk [get_ports phy_rx_clk]
+set_clock_groups -asynchronous -group [get_clocks phy_rx_clk -include_generated_clocks]
+
diff --git a/example/Genesys2/fpga/fpga/Makefile b/example/Genesys2/fpga/fpga/Makefile
new file mode 100644
index 000000000..469830ed6
--- /dev/null
+++ b/example/Genesys2/fpga/fpga/Makefile
@@ -0,0 +1,54 @@
+
+# FPGA settings
+FPGA_PART = xc7k325tffg900-2
+FPGA_TOP = fpga
+FPGA_ARCH = kintex7
+
+# Files for synthesis
+SYN_FILES = rtl/fpga.v
+SYN_FILES += rtl/fpga_core.v
+SYN_FILES += rtl/debounce_switch.v
+SYN_FILES += rtl/sync_reset.v
+SYN_FILES += rtl/sync_signal.v
+SYN_FILES += lib/eth/rtl/iddr.v
+SYN_FILES += lib/eth/rtl/oddr.v
+SYN_FILES += lib/eth/rtl/ssio_ddr_in.v
+SYN_FILES += lib/eth/rtl/ssio_ddr_out.v
+SYN_FILES += lib/eth/rtl/rgmii_phy_if.v
+SYN_FILES += lib/eth/rtl/eth_mac_1g_rgmii_fifo.v
+SYN_FILES += lib/eth/rtl/eth_mac_1g_rgmii.v
+SYN_FILES += lib/eth/rtl/eth_mac_1g.v
+SYN_FILES += lib/eth/rtl/axis_gmii_rx.v
+SYN_FILES += lib/eth/rtl/axis_gmii_tx.v
+SYN_FILES += lib/eth/rtl/lfsr.v
+SYN_FILES += lib/eth/rtl/eth_axis_rx.v
+SYN_FILES += lib/eth/rtl/eth_axis_tx.v
+SYN_FILES += lib/eth/rtl/udp_complete.v
+SYN_FILES += lib/eth/rtl/udp_checksum_gen.v
+SYN_FILES += lib/eth/rtl/udp.v
+SYN_FILES += lib/eth/rtl/udp_ip_rx.v
+SYN_FILES += lib/eth/rtl/udp_ip_tx.v
+SYN_FILES += lib/eth/rtl/ip_complete.v
+SYN_FILES += lib/eth/rtl/ip.v
+SYN_FILES += lib/eth/rtl/ip_eth_rx.v
+SYN_FILES += lib/eth/rtl/ip_eth_tx.v
+SYN_FILES += lib/eth/rtl/ip_arb_mux.v
+SYN_FILES += lib/eth/rtl/arp.v
+SYN_FILES += lib/eth/rtl/arp_cache.v
+SYN_FILES += lib/eth/rtl/arp_eth_rx.v
+SYN_FILES += lib/eth/rtl/arp_eth_tx.v
+SYN_FILES += lib/eth/rtl/eth_arb_mux.v
+SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
+SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
+SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
+SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
+
+# XDC files
+XDC_FILES = fpga.xdc
+XDC_FILES += eth.xdc
+
+include ../common/vivado.mk
+
+program: $(FPGA_TOP).bit
+	djtgcfg prog -d Genesys2 --index 0 --file $(FPGA_TOP).bit
+
diff --git a/example/Genesys2/fpga/fpga/generate_bit_iodelay.tcl b/example/Genesys2/fpga/fpga/generate_bit_iodelay.tcl
new file mode 100644
index 000000000..d97f96678
--- /dev/null
+++ b/example/Genesys2/fpga/fpga/generate_bit_iodelay.tcl
@@ -0,0 +1,6 @@
+open_project fpga.xpr
+open_run impl_1
+set_property IDELAY_VALUE 0 [get_cells {phy_rx_ctl_idelay phy_rxd_idelay_*}]
+set_property CLKOUT1_PHASE 90 [get_cells clk_mmcm_inst]
+write_bitstream -force fpga.bit
+exit
diff --git a/example/Genesys2/fpga/lib/eth b/example/Genesys2/fpga/lib/eth
new file mode 120000
index 000000000..11a54ed36
--- /dev/null
+++ b/example/Genesys2/fpga/lib/eth
@@ -0,0 +1 @@
+../../../../
\ No newline at end of file
diff --git a/example/Genesys2/fpga/rtl/debounce_switch.v b/example/Genesys2/fpga/rtl/debounce_switch.v
new file mode 100644
index 000000000..bb631cc35
--- /dev/null
+++ b/example/Genesys2/fpga/rtl/debounce_switch.v
@@ -0,0 +1,89 @@
+/*
+
+Copyright (c) 2014-2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog-2001
+
+`timescale 1 ns / 1 ps
+
+/*
+ * Synchronizes switch and button inputs with a slow sampled shift register
+ */
+module debounce_switch  #(
+    parameter WIDTH=1, // width of the input and output signals
+    parameter N=3, // length of shift register
+    parameter RATE=125000 // clock division factor
+)(
+    input wire clk,
+    input wire rst,
+    input wire [WIDTH-1:0] in,
+    output wire [WIDTH-1:0] out
+);
+
+reg [23:0] cnt_reg = 24'd0;
+
+reg [N-1:0] debounce_reg[WIDTH-1:0];
+
+reg [WIDTH-1:0] state;
+
+/*
+ * The synchronized output is the state register
+ */
+assign out = state;
+
+integer k;
+
+always @(posedge clk or posedge rst) begin
+    if (rst) begin
+        cnt_reg <= 0;
+        state <= 0;
+        
+        for (k = 0; k < WIDTH; k = k + 1) begin
+            debounce_reg[k] <= 0;
+        end
+    end else begin
+        if (cnt_reg < RATE) begin
+            cnt_reg <= cnt_reg + 24'd1;
+        end else begin
+            cnt_reg <= 24'd0;
+        end
+        
+        if (cnt_reg == 24'd0) begin
+            for (k = 0; k < WIDTH; k = k + 1) begin
+                debounce_reg[k] <= {debounce_reg[k][N-2:0], in[k]};
+            end
+        end
+        
+        for (k = 0; k < WIDTH; k = k + 1) begin
+            if (|debounce_reg[k] == 0) begin
+                state[k] <= 0;
+            end else if (&debounce_reg[k] == 1) begin
+                state[k] <= 1;
+            end else begin
+                state[k] <= state[k];
+            end
+        end
+    end
+end
+
+endmodule
diff --git a/example/Genesys2/fpga/rtl/fpga.v b/example/Genesys2/fpga/rtl/fpga.v
new file mode 100644
index 000000000..5f2673494
--- /dev/null
+++ b/example/Genesys2/fpga/rtl/fpga.v
@@ -0,0 +1,375 @@
+/*
+
+Copyright (c) 2014-2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * FPGA top-level module
+ */
+module fpga (
+    /*
+     * Clock: 200MHz
+     * Reset: Push button, active low
+     */
+    input  wire       sysclk_p, sysclk_n,
+    input  wire       reset_n,
+
+    /*
+     * GPIO
+     */
+    input  wire       btnu,
+    input  wire       btnl,
+    input  wire       btnd,
+    input  wire       btnr,
+    input  wire       btnc,
+    input  wire [7:0] sw,
+    output wire [7:0] led,
+
+    /*
+     * Ethernet: 1000BASE-T RGMII
+     */
+    input  wire       phy_rx_clk,
+    input  wire [3:0] phy_rxd,
+    input  wire       phy_rx_ctl,
+    output wire       phy_tx_clk,
+    output wire [3:0] phy_txd,
+    output wire       phy_tx_ctl,
+    output wire       phy_reset_n,
+    input  wire       phy_int_n,
+    input  wire       phy_pme_n,
+
+    /*
+     * UART: 500000 bps, 8N1
+     */
+    input  wire       uart_rxd,
+    output wire       uart_txd
+);
+
+// Clock and reset
+
+wire clk_ibufg;
+wire clk_bufg;
+wire clk_mmcm_out;
+
+// Internal 125 MHz clock
+wire clk_int;
+wire rst_int;   
+
+wire mmcm_rst = ~reset_n;
+wire mmcm_locked;
+wire mmcm_clkfb;
+
+wire clk90_mmcm_out;
+wire clk90_int;
+
+wire clk_200_mmcm_out;
+wire clk_200_int;
+
+IBUFDS #(
+      .DIFF_TERM("FALSE"),       // Differential Termination
+      .IBUF_LOW_PWR("TRUE"),     // Low power="TRUE", Highest performance="FALSE" 
+      .IOSTANDARD("LVDS")        // Specify the input I/O standard
+   ) 
+clk_ibufg_inst(
+    .I(sysclk_p),
+    .IB(sysclk_n),
+    .O(clk_ibufg)
+);
+
+// MMCM instance
+// 100 MHz in, 125 MHz out
+// PFD range: 10 MHz to 550 MHz
+// VCO range: 600 MHz to 1200 MHz
+// M = 10, D = 1 sets Fvco = 1000 MHz (in range)
+// Divide by 8 to get output frequency of 125 MHz
+// Need two 125 MHz outputs with 90 degree offset
+// Also need 200 MHz out for IODELAY
+// 1000 / 5 = 200 MHz
+MMCME2_BASE #(
+    .BANDWIDTH("OPTIMIZED"),
+    .CLKOUT0_DIVIDE_F(8),
+    .CLKOUT0_DUTY_CYCLE(0.5),
+    .CLKOUT0_PHASE(0),
+    .CLKOUT1_DIVIDE(8),
+    .CLKOUT1_DUTY_CYCLE(0.5),
+    .CLKOUT1_PHASE(90),
+    .CLKOUT2_DIVIDE(5),
+    .CLKOUT2_DUTY_CYCLE(0.5),
+    .CLKOUT2_PHASE(0),
+    .CLKOUT3_DIVIDE(1),
+    .CLKOUT3_DUTY_CYCLE(0.5),
+    .CLKOUT3_PHASE(0),
+    .CLKOUT4_DIVIDE(1),
+    .CLKOUT4_DUTY_CYCLE(0.5),
+    .CLKOUT4_PHASE(0),
+    .CLKOUT5_DIVIDE(1),
+    .CLKOUT5_DUTY_CYCLE(0.5),
+    .CLKOUT5_PHASE(0),
+    .CLKOUT6_DIVIDE(1),
+    .CLKOUT6_DUTY_CYCLE(0.5),
+    .CLKOUT6_PHASE(0),
+    .CLKFBOUT_MULT_F(5),
+    .CLKFBOUT_PHASE(0),
+    .DIVCLK_DIVIDE(1),
+    .REF_JITTER1(0.010),
+    .CLKIN1_PERIOD(5.0),
+    .STARTUP_WAIT("FALSE"),
+    .CLKOUT4_CASCADE("FALSE")
+)
+clk_mmcm_inst (
+    .CLKIN1(clk_ibufg),
+    .CLKFBIN(mmcm_clkfb),
+    .RST(mmcm_rst),
+    .PWRDWN(1'b0),
+    .CLKOUT0(clk_mmcm_out),
+    .CLKOUT0B(),
+    .CLKOUT1(clk90_mmcm_out),
+    .CLKOUT1B(),
+    .CLKOUT2(clk_200_mmcm_out),
+    .CLKOUT2B(),
+    .CLKOUT3(),
+    .CLKOUT3B(),
+    .CLKOUT4(),
+    .CLKOUT5(),
+    .CLKOUT6(),
+    .CLKFBOUT(mmcm_clkfb),
+    .CLKFBOUTB(),
+    .LOCKED(mmcm_locked)
+);
+
+BUFG
+clk_bufg_inst (
+    .I(clk_mmcm_out),
+    .O(clk_int)
+);
+
+BUFG
+clk90_bufg_inst (
+    .I(clk90_mmcm_out),
+    .O(clk90_int)
+);
+
+BUFG
+clk_200_bufg_inst (
+    .I(clk_200_mmcm_out),
+    .O(clk_200_int)
+);
+
+sync_reset #(
+    .N(4)
+)
+sync_reset_inst (
+    .clk(clk_int),
+    .rst(~mmcm_locked),
+    .sync_reset_out(rst_int)
+);
+
+// GPIO
+wire btnu_int;
+wire btnl_int;
+wire btnd_int;
+wire btnr_int;
+wire btnc_int;
+wire [7:0] sw_int;
+
+debounce_switch #(
+    .WIDTH(13),
+    .N(4),
+    .RATE(125000)
+)
+debounce_switch_inst (
+    .clk(clk_int),
+    .rst(rst_int),
+    .in({btnu,
+        btnl,
+        btnd,
+        btnr,
+        btnc,
+        sw}),
+    .out({btnu_int,
+        btnl_int,
+        btnd_int,
+        btnr_int,
+        btnc_int,
+        sw_int})
+);
+
+sync_signal #(
+    .WIDTH(1),
+    .N(2)
+)
+sync_signal_inst (
+    .clk(clk_int),
+    .in({uart_rxd}),
+    .out({uart_rxd_int})
+);
+
+// IODELAY elements for RGMII interface to PHY
+wire [3:0] phy_rxd_delay;
+wire       phy_rx_ctl_delay;
+
+IDELAYCTRL
+idelayctrl_inst
+(
+    .REFCLK(clk_200_int),
+    .RST(rst_int),
+    .RDY()
+);
+
+IDELAYE2 #(
+    .IDELAY_TYPE("FIXED")
+)
+phy_rxd_idelay_0
+(
+    .IDATAIN(phy_rxd[0]),
+    .DATAOUT(phy_rxd_delay[0]),
+    .DATAIN(1'b0),
+    .C(1'b0),
+    .CE(1'b0),
+    .INC(1'b0),
+    .CINVCTRL(1'b0),
+    .CNTVALUEIN(5'd0),
+    .CNTVALUEOUT(),
+    .LD(1'b0),
+    .LDPIPEEN(1'b0),
+    .REGRST(1'b0)
+);
+
+IDELAYE2 #(
+    .IDELAY_TYPE("FIXED")
+)
+phy_rxd_idelay_1
+(
+    .IDATAIN(phy_rxd[1]),
+    .DATAOUT(phy_rxd_delay[1]),
+    .DATAIN(1'b0),
+    .C(1'b0),
+    .CE(1'b0),
+    .INC(1'b0),
+    .CINVCTRL(1'b0),
+    .CNTVALUEIN(5'd0),
+    .CNTVALUEOUT(),
+    .LD(1'b0),
+    .LDPIPEEN(1'b0),
+    .REGRST(1'b0)
+);
+
+IDELAYE2 #(
+    .IDELAY_TYPE("FIXED")
+)
+phy_rxd_idelay_2
+(
+    .IDATAIN(phy_rxd[2]),
+    .DATAOUT(phy_rxd_delay[2]),
+    .DATAIN(1'b0),
+    .C(1'b0),
+    .CE(1'b0),
+    .INC(1'b0),
+    .CINVCTRL(1'b0),
+    .CNTVALUEIN(5'd0),
+    .CNTVALUEOUT(),
+    .LD(1'b0),
+    .LDPIPEEN(1'b0),
+    .REGRST(1'b0)
+);
+
+IDELAYE2 #(
+    .IDELAY_TYPE("FIXED")
+)
+phy_rxd_idelay_3
+(
+    .IDATAIN(phy_rxd[3]),
+    .DATAOUT(phy_rxd_delay[3]),
+    .DATAIN(1'b0),
+    .C(1'b0),
+    .CE(1'b0),
+    .INC(1'b0),
+    .CINVCTRL(1'b0),
+    .CNTVALUEIN(5'd0),
+    .CNTVALUEOUT(),
+    .LD(1'b0),
+    .LDPIPEEN(1'b0),
+    .REGRST(1'b0)
+);
+
+IDELAYE2 #(
+    .IDELAY_TYPE("FIXED")
+)
+phy_rx_ctl_idelay
+(
+    .IDATAIN(phy_rx_ctl),
+    .DATAOUT(phy_rx_ctl_delay),
+    .DATAIN(1'b0),
+    .C(1'b0),
+    .CE(1'b0),
+    .INC(1'b0),
+    .CINVCTRL(1'b0),
+    .CNTVALUEIN(5'd0),
+    .CNTVALUEOUT(),
+    .LD(1'b0),
+    .LDPIPEEN(1'b0),
+    .REGRST(1'b0)
+);
+
+fpga_core
+core_inst (
+    /*
+     * Clock: 125MHz
+     * Synchronous reset
+     */
+    .clk(clk_int),
+    .clk90(clk90_int),
+    .rst(rst_int),
+    /*
+     * GPIO
+     */
+    .btnu(btnu_int),
+    .btnl(btnl_int),
+    .btnd(btnd_int),
+    .btnr(btnr_int),
+    .btnc(btnc_int),
+    .sw(sw_int),
+    .led(led),
+    /*
+     * Ethernet: 1000BASE-T RGMII
+     */
+    .phy_rx_clk(phy_rx_clk),
+    .phy_rxd(phy_rxd_delay),
+    .phy_rx_ctl(phy_rx_ctl_delay),
+    .phy_tx_clk(phy_tx_clk),
+    .phy_txd(phy_txd),
+    .phy_tx_ctl(phy_tx_ctl),
+    .phy_reset_n(phy_reset_n),
+    .phy_int_n(phy_int_n),
+    .phy_pme_n(phy_pme_n),
+    /*
+     * UART: 115200 bps, 8N1
+     */
+    .uart_rxd(uart_rxd_int),
+    .uart_txd(uart_txd)
+);
+
+endmodule
diff --git a/example/Genesys2/fpga/rtl/fpga_core.v b/example/Genesys2/fpga/rtl/fpga_core.v
new file mode 100644
index 000000000..96e4a83a0
--- /dev/null
+++ b/example/Genesys2/fpga/rtl/fpga_core.v
@@ -0,0 +1,582 @@
+/*
+
+Copyright (c) 2014-2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * FPGA core logic
+ */
+module fpga_core #
+(
+    parameter TARGET = "XILINX"
+)
+(
+    /*
+     * Clock: 125MHz
+     * Synchronous reset
+     */
+    input  wire       clk,
+    input  wire       clk90,
+    input  wire       rst,
+
+    /*
+     * GPIO
+     */
+    input  wire       btnu,
+    input  wire       btnl,
+    input  wire       btnd,
+    input  wire       btnr,
+    input  wire       btnc,
+    input  wire [7:0] sw,
+    output wire [7:0] led,
+
+    /*
+     * Ethernet: 1000BASE-T RGMII
+     */
+    input  wire       phy_rx_clk,
+    input  wire [3:0] phy_rxd,
+    input  wire       phy_rx_ctl,
+    output wire       phy_tx_clk,
+    output wire [3:0] phy_txd,
+    output wire       phy_tx_ctl,
+    output wire       phy_reset_n,
+    input  wire       phy_int_n,
+    input  wire       phy_pme_n,
+
+    /*
+     * UART: 115200 bps, 8N1
+     */
+    input  wire       uart_rxd,
+    output wire       uart_txd
+);
+
+// AXI between MAC and Ethernet modules
+wire [7:0] rx_axis_tdata;
+wire rx_axis_tvalid;
+wire rx_axis_tready;
+wire rx_axis_tlast;
+wire rx_axis_tuser;
+
+wire [7:0] tx_axis_tdata;
+wire tx_axis_tvalid;
+wire tx_axis_tready;
+wire tx_axis_tlast;
+wire tx_axis_tuser;
+
+// Ethernet frame between Ethernet modules and UDP stack
+wire rx_eth_hdr_ready;
+wire rx_eth_hdr_valid;
+wire [47:0] rx_eth_dest_mac;
+wire [47:0] rx_eth_src_mac;
+wire [15:0] rx_eth_type;
+wire [7:0] rx_eth_payload_axis_tdata;
+wire rx_eth_payload_axis_tvalid;
+wire rx_eth_payload_axis_tready;
+wire rx_eth_payload_axis_tlast;
+wire rx_eth_payload_axis_tuser;
+
+wire tx_eth_hdr_ready;
+wire tx_eth_hdr_valid;
+wire [47:0] tx_eth_dest_mac;
+wire [47:0] tx_eth_src_mac;
+wire [15:0] tx_eth_type;
+wire [7:0] tx_eth_payload_axis_tdata;
+wire tx_eth_payload_axis_tvalid;
+wire tx_eth_payload_axis_tready;
+wire tx_eth_payload_axis_tlast;
+wire tx_eth_payload_axis_tuser;
+
+// IP frame connections
+wire rx_ip_hdr_valid;
+wire rx_ip_hdr_ready;
+wire [47:0] rx_ip_eth_dest_mac;
+wire [47:0] rx_ip_eth_src_mac;
+wire [15:0] rx_ip_eth_type;
+wire [3:0] rx_ip_version;
+wire [3:0] rx_ip_ihl;
+wire [5:0] rx_ip_dscp;
+wire [1:0] rx_ip_ecn;
+wire [15:0] rx_ip_length;
+wire [15:0] rx_ip_identification;
+wire [2:0] rx_ip_flags;
+wire [12:0] rx_ip_fragment_offset;
+wire [7:0] rx_ip_ttl;
+wire [7:0] rx_ip_protocol;
+wire [15:0] rx_ip_header_checksum;
+wire [31:0] rx_ip_source_ip;
+wire [31:0] rx_ip_dest_ip;
+wire [7:0] rx_ip_payload_axis_tdata;
+wire rx_ip_payload_axis_tvalid;
+wire rx_ip_payload_axis_tready;
+wire rx_ip_payload_axis_tlast;
+wire rx_ip_payload_axis_tuser;
+
+wire tx_ip_hdr_valid;
+wire tx_ip_hdr_ready;
+wire [5:0] tx_ip_dscp;
+wire [1:0] tx_ip_ecn;
+wire [15:0] tx_ip_length;
+wire [7:0] tx_ip_ttl;
+wire [7:0] tx_ip_protocol;
+wire [31:0] tx_ip_source_ip;
+wire [31:0] tx_ip_dest_ip;
+wire [7:0] tx_ip_payload_axis_tdata;
+wire tx_ip_payload_axis_tvalid;
+wire tx_ip_payload_axis_tready;
+wire tx_ip_payload_axis_tlast;
+wire tx_ip_payload_axis_tuser;
+
+// UDP frame connections
+wire rx_udp_hdr_valid;
+wire rx_udp_hdr_ready;
+wire [47:0] rx_udp_eth_dest_mac;
+wire [47:0] rx_udp_eth_src_mac;
+wire [15:0] rx_udp_eth_type;
+wire [3:0] rx_udp_ip_version;
+wire [3:0] rx_udp_ip_ihl;
+wire [5:0] rx_udp_ip_dscp;
+wire [1:0] rx_udp_ip_ecn;
+wire [15:0] rx_udp_ip_length;
+wire [15:0] rx_udp_ip_identification;
+wire [2:0] rx_udp_ip_flags;
+wire [12:0] rx_udp_ip_fragment_offset;
+wire [7:0] rx_udp_ip_ttl;
+wire [7:0] rx_udp_ip_protocol;
+wire [15:0] rx_udp_ip_header_checksum;
+wire [31:0] rx_udp_ip_source_ip;
+wire [31:0] rx_udp_ip_dest_ip;
+wire [15:0] rx_udp_source_port;
+wire [15:0] rx_udp_dest_port;
+wire [15:0] rx_udp_length;
+wire [15:0] rx_udp_checksum;
+wire [7:0] rx_udp_payload_axis_tdata;
+wire rx_udp_payload_axis_tvalid;
+wire rx_udp_payload_axis_tready;
+wire rx_udp_payload_axis_tlast;
+wire rx_udp_payload_axis_tuser;
+
+wire tx_udp_hdr_valid;
+wire tx_udp_hdr_ready;
+wire [5:0] tx_udp_ip_dscp;
+wire [1:0] tx_udp_ip_ecn;
+wire [7:0] tx_udp_ip_ttl;
+wire [31:0] tx_udp_ip_source_ip;
+wire [31:0] tx_udp_ip_dest_ip;
+wire [15:0] tx_udp_source_port;
+wire [15:0] tx_udp_dest_port;
+wire [15:0] tx_udp_length;
+wire [15:0] tx_udp_checksum;
+wire [7:0] tx_udp_payload_axis_tdata;
+wire tx_udp_payload_axis_tvalid;
+wire tx_udp_payload_axis_tready;
+wire tx_udp_payload_axis_tlast;
+wire tx_udp_payload_axis_tuser;
+
+wire [7:0] rx_fifo_udp_payload_axis_tdata;
+wire rx_fifo_udp_payload_axis_tvalid;
+wire rx_fifo_udp_payload_axis_tready;
+wire rx_fifo_udp_payload_axis_tlast;
+wire rx_fifo_udp_payload_axis_tuser;
+
+wire [7:0] tx_fifo_udp_payload_axis_tdata;
+wire tx_fifo_udp_payload_axis_tvalid;
+wire tx_fifo_udp_payload_axis_tready;
+wire tx_fifo_udp_payload_axis_tlast;
+wire tx_fifo_udp_payload_axis_tuser;
+
+// Configuration
+wire [47:0] local_mac   = 48'h02_00_00_00_00_00;
+wire [31:0] local_ip    = {8'd192, 8'd168, 8'd1,   8'd128};
+wire [31:0] gateway_ip  = {8'd192, 8'd168, 8'd1,   8'd1};
+wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0};
+
+// IP ports not used
+assign rx_ip_hdr_ready = 1;
+assign rx_ip_payload_axis_tready = 1;
+
+assign tx_ip_hdr_valid = 0;
+assign tx_ip_dscp = 0;
+assign tx_ip_ecn = 0;
+assign tx_ip_length = 0;
+assign tx_ip_ttl = 0;
+assign tx_ip_protocol = 0;
+assign tx_ip_source_ip = 0;
+assign tx_ip_dest_ip = 0;
+assign tx_ip_payload_axis_tdata = 0;
+assign tx_ip_payload_axis_tvalid = 0;
+assign tx_ip_payload_axis_tlast = 0;
+assign tx_ip_payload_axis_tuser = 0;
+
+// Loop back UDP
+wire match_cond = rx_udp_dest_port == 1234;
+wire no_match = !match_cond;
+
+reg match_cond_reg = 0;
+reg no_match_reg = 0;
+
+always @(posedge clk) begin
+    if (rst) begin
+        match_cond_reg <= 0;
+        no_match_reg <= 0;
+    end else begin
+        if (rx_udp_payload_axis_tvalid) begin
+            if ((!match_cond_reg && !no_match_reg) ||
+                (rx_udp_payload_axis_tvalid && rx_udp_payload_axis_tready && rx_udp_payload_axis_tlast)) begin
+                match_cond_reg <= match_cond;
+                no_match_reg <= no_match;
+            end
+        end else begin
+            match_cond_reg <= 0;
+            no_match_reg <= 0;
+        end
+    end
+end
+
+assign tx_udp_hdr_valid = rx_udp_hdr_valid && match_cond;
+assign rx_udp_hdr_ready = (tx_eth_hdr_ready && match_cond) || no_match;
+assign tx_udp_ip_dscp = 0;
+assign tx_udp_ip_ecn = 0;
+assign tx_udp_ip_ttl = 64;
+assign tx_udp_ip_source_ip = local_ip;
+assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip;
+assign tx_udp_source_port = rx_udp_dest_port;
+assign tx_udp_dest_port = rx_udp_source_port;
+assign tx_udp_length = rx_udp_length;
+assign tx_udp_checksum = 0;
+
+assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata;
+assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid;
+assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready;
+assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast;
+assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser;
+
+assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata;
+assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid && match_cond_reg;
+assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready && match_cond_reg) || no_match_reg;
+assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast;
+assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser;
+
+// Place first payload byte onto LEDs
+reg valid_last = 0;
+reg [7:0] led_reg = 0;
+
+always @(posedge clk) begin
+    if (rst) begin
+        led_reg <= 0;
+    end else begin
+        if (tx_udp_payload_axis_tvalid) begin
+            if (!valid_last) begin
+                led_reg <= tx_udp_payload_axis_tdata;
+                valid_last <= 1'b1;
+            end
+            if (tx_udp_payload_axis_tlast) begin
+                valid_last <= 1'b0;
+            end
+        end
+    end
+end
+
+//assign led = sw;
+assign led = led_reg;
+assign phy_reset_n = !rst;
+
+assign uart_txd = 0;
+
+eth_mac_1g_rgmii_fifo #(
+    .TARGET(TARGET),
+    .IODDR_STYLE("IODDR"),
+    .CLOCK_INPUT_STYLE("BUFR"),
+    .USE_CLK90("TRUE"),
+    .ENABLE_PADDING(1),
+    .MIN_FRAME_LENGTH(64),
+    .TX_FIFO_ADDR_WIDTH(12),
+    .TX_FRAME_FIFO(1),
+    .RX_FIFO_ADDR_WIDTH(12),
+    .RX_FRAME_FIFO(1)
+)
+eth_mac_inst (
+    .gtx_clk(clk),
+    .gtx_clk90(clk90),
+    .gtx_rst(rst),
+    .logic_clk(clk),
+    .logic_rst(rst),
+
+    .tx_axis_tdata(tx_axis_tdata),
+    .tx_axis_tvalid(tx_axis_tvalid),
+    .tx_axis_tready(tx_axis_tready),
+    .tx_axis_tlast(tx_axis_tlast),
+    .tx_axis_tuser(tx_axis_tuser),
+
+    .rx_axis_tdata(rx_axis_tdata),
+    .rx_axis_tvalid(rx_axis_tvalid),
+    .rx_axis_tready(rx_axis_tready),
+    .rx_axis_tlast(rx_axis_tlast),
+    .rx_axis_tuser(rx_axis_tuser),
+
+    .rgmii_rx_clk(phy_rx_clk),
+    .rgmii_rxd(phy_rxd),
+    .rgmii_rx_ctl(phy_rx_ctl),
+    .rgmii_tx_clk(phy_tx_clk),
+    .rgmii_txd(phy_txd),
+    .rgmii_tx_ctl(phy_tx_ctl),
+
+    .tx_fifo_overflow(),
+    .tx_fifo_bad_frame(),
+    .tx_fifo_good_frame(),
+    .rx_error_bad_frame(),
+    .rx_error_bad_fcs(),
+    .rx_fifo_overflow(),
+    .rx_fifo_bad_frame(),
+    .rx_fifo_good_frame(),
+    .speed(),
+
+    .ifg_delay(12)
+);
+
+eth_axis_rx
+eth_axis_rx_inst (
+    .clk(clk),
+    .rst(rst),
+    // AXI input
+    .s_axis_tdata(rx_axis_tdata),
+    .s_axis_tvalid(rx_axis_tvalid),
+    .s_axis_tready(rx_axis_tready),
+    .s_axis_tlast(rx_axis_tlast),
+    .s_axis_tuser(rx_axis_tuser),
+    // Ethernet frame output
+    .m_eth_hdr_valid(rx_eth_hdr_valid),
+    .m_eth_hdr_ready(rx_eth_hdr_ready),
+    .m_eth_dest_mac(rx_eth_dest_mac),
+    .m_eth_src_mac(rx_eth_src_mac),
+    .m_eth_type(rx_eth_type),
+    .m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
+    .m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
+    .m_eth_payload_axis_tready(rx_eth_payload_axis_tready),
+    .m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
+    .m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
+    // Status signals
+    .busy(),
+    .error_header_early_termination()
+);
+
+eth_axis_tx
+eth_axis_tx_inst (
+    .clk(clk),
+    .rst(rst),
+    // Ethernet frame input
+    .s_eth_hdr_valid(tx_eth_hdr_valid),
+    .s_eth_hdr_ready(tx_eth_hdr_ready),
+    .s_eth_dest_mac(tx_eth_dest_mac),
+    .s_eth_src_mac(tx_eth_src_mac),
+    .s_eth_type(tx_eth_type),
+    .s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
+    .s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
+    .s_eth_payload_axis_tready(tx_eth_payload_axis_tready),
+    .s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
+    .s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
+    // AXI output
+    .m_axis_tdata(tx_axis_tdata),
+    .m_axis_tvalid(tx_axis_tvalid),
+    .m_axis_tready(tx_axis_tready),
+    .m_axis_tlast(tx_axis_tlast),
+    .m_axis_tuser(tx_axis_tuser),
+    // Status signals
+    .busy()
+);
+
+udp_complete
+udp_complete_inst (
+    .clk(clk),
+    .rst(rst),
+    // Ethernet frame input
+    .s_eth_hdr_valid(rx_eth_hdr_valid),
+    .s_eth_hdr_ready(rx_eth_hdr_ready),
+    .s_eth_dest_mac(rx_eth_dest_mac),
+    .s_eth_src_mac(rx_eth_src_mac),
+    .s_eth_type(rx_eth_type),
+    .s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
+    .s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
+    .s_eth_payload_axis_tready(rx_eth_payload_axis_tready),
+    .s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
+    .s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
+    // Ethernet frame output
+    .m_eth_hdr_valid(tx_eth_hdr_valid),
+    .m_eth_hdr_ready(tx_eth_hdr_ready),
+    .m_eth_dest_mac(tx_eth_dest_mac),
+    .m_eth_src_mac(tx_eth_src_mac),
+    .m_eth_type(tx_eth_type),
+    .m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
+    .m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
+    .m_eth_payload_axis_tready(tx_eth_payload_axis_tready),
+    .m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
+    .m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
+    // IP frame input
+    .s_ip_hdr_valid(tx_ip_hdr_valid),
+    .s_ip_hdr_ready(tx_ip_hdr_ready),
+    .s_ip_dscp(tx_ip_dscp),
+    .s_ip_ecn(tx_ip_ecn),
+    .s_ip_length(tx_ip_length),
+    .s_ip_ttl(tx_ip_ttl),
+    .s_ip_protocol(tx_ip_protocol),
+    .s_ip_source_ip(tx_ip_source_ip),
+    .s_ip_dest_ip(tx_ip_dest_ip),
+    .s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata),
+    .s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid),
+    .s_ip_payload_axis_tready(tx_ip_payload_axis_tready),
+    .s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast),
+    .s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser),
+    // IP frame output
+    .m_ip_hdr_valid(rx_ip_hdr_valid),
+    .m_ip_hdr_ready(rx_ip_hdr_ready),
+    .m_ip_eth_dest_mac(rx_ip_eth_dest_mac),
+    .m_ip_eth_src_mac(rx_ip_eth_src_mac),
+    .m_ip_eth_type(rx_ip_eth_type),
+    .m_ip_version(rx_ip_version),
+    .m_ip_ihl(rx_ip_ihl),
+    .m_ip_dscp(rx_ip_dscp),
+    .m_ip_ecn(rx_ip_ecn),
+    .m_ip_length(rx_ip_length),
+    .m_ip_identification(rx_ip_identification),
+    .m_ip_flags(rx_ip_flags),
+    .m_ip_fragment_offset(rx_ip_fragment_offset),
+    .m_ip_ttl(rx_ip_ttl),
+    .m_ip_protocol(rx_ip_protocol),
+    .m_ip_header_checksum(rx_ip_header_checksum),
+    .m_ip_source_ip(rx_ip_source_ip),
+    .m_ip_dest_ip(rx_ip_dest_ip),
+    .m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata),
+    .m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid),
+    .m_ip_payload_axis_tready(rx_ip_payload_axis_tready),
+    .m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast),
+    .m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser),
+    // UDP frame input
+    .s_udp_hdr_valid(tx_udp_hdr_valid),
+    .s_udp_hdr_ready(tx_udp_hdr_ready),
+    .s_udp_ip_dscp(tx_udp_ip_dscp),
+    .s_udp_ip_ecn(tx_udp_ip_ecn),
+    .s_udp_ip_ttl(tx_udp_ip_ttl),
+    .s_udp_ip_source_ip(tx_udp_ip_source_ip),
+    .s_udp_ip_dest_ip(tx_udp_ip_dest_ip),
+    .s_udp_source_port(tx_udp_source_port),
+    .s_udp_dest_port(tx_udp_dest_port),
+    .s_udp_length(tx_udp_length),
+    .s_udp_checksum(tx_udp_checksum),
+    .s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata),
+    .s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid),
+    .s_udp_payload_axis_tready(tx_udp_payload_axis_tready),
+    .s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast),
+    .s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser),
+    // UDP frame output
+    .m_udp_hdr_valid(rx_udp_hdr_valid),
+    .m_udp_hdr_ready(rx_udp_hdr_ready),
+    .m_udp_eth_dest_mac(rx_udp_eth_dest_mac),
+    .m_udp_eth_src_mac(rx_udp_eth_src_mac),
+    .m_udp_eth_type(rx_udp_eth_type),
+    .m_udp_ip_version(rx_udp_ip_version),
+    .m_udp_ip_ihl(rx_udp_ip_ihl),
+    .m_udp_ip_dscp(rx_udp_ip_dscp),
+    .m_udp_ip_ecn(rx_udp_ip_ecn),
+    .m_udp_ip_length(rx_udp_ip_length),
+    .m_udp_ip_identification(rx_udp_ip_identification),
+    .m_udp_ip_flags(rx_udp_ip_flags),
+    .m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset),
+    .m_udp_ip_ttl(rx_udp_ip_ttl),
+    .m_udp_ip_protocol(rx_udp_ip_protocol),
+    .m_udp_ip_header_checksum(rx_udp_ip_header_checksum),
+    .m_udp_ip_source_ip(rx_udp_ip_source_ip),
+    .m_udp_ip_dest_ip(rx_udp_ip_dest_ip),
+    .m_udp_source_port(rx_udp_source_port),
+    .m_udp_dest_port(rx_udp_dest_port),
+    .m_udp_length(rx_udp_length),
+    .m_udp_checksum(rx_udp_checksum),
+    .m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata),
+    .m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid),
+    .m_udp_payload_axis_tready(rx_udp_payload_axis_tready),
+    .m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast),
+    .m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser),
+    // Status signals
+    .ip_rx_busy(),
+    .ip_tx_busy(),
+    .udp_rx_busy(),
+    .udp_tx_busy(),
+    .ip_rx_error_header_early_termination(),
+    .ip_rx_error_payload_early_termination(),
+    .ip_rx_error_invalid_header(),
+    .ip_rx_error_invalid_checksum(),
+    .ip_tx_error_payload_early_termination(),
+    .ip_tx_error_arp_failed(),
+    .udp_rx_error_header_early_termination(),
+    .udp_rx_error_payload_early_termination(),
+    .udp_tx_error_payload_early_termination(),
+    // Configuration
+    .local_mac(local_mac),
+    .local_ip(local_ip),
+    .gateway_ip(gateway_ip),
+    .subnet_mask(subnet_mask),
+    .clear_arp_cache(0)
+);
+
+axis_fifo #(
+    .ADDR_WIDTH(12),
+    .DATA_WIDTH(8),
+    .KEEP_ENABLE(0),
+    .ID_ENABLE(0),
+    .DEST_ENABLE(0),
+    .USER_ENABLE(1),
+    .USER_WIDTH(1),
+    .FRAME_FIFO(0)
+)
+udp_payload_fifo (
+    .clk(clk),
+    .rst(rst),
+
+    // AXI input
+    .s_axis_tdata(rx_fifo_udp_payload_axis_tdata),
+    .s_axis_tkeep(0),
+    .s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid),
+    .s_axis_tready(rx_fifo_udp_payload_axis_tready),
+    .s_axis_tlast(rx_fifo_udp_payload_axis_tlast),
+    .s_axis_tid(0),
+    .s_axis_tdest(0),
+    .s_axis_tuser(rx_fifo_udp_payload_axis_tuser),
+
+    // AXI output
+    .m_axis_tdata(tx_fifo_udp_payload_axis_tdata),
+    .m_axis_tkeep(),
+    .m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid),
+    .m_axis_tready(tx_fifo_udp_payload_axis_tready),
+    .m_axis_tlast(tx_fifo_udp_payload_axis_tlast),
+    .m_axis_tid(),
+    .m_axis_tdest(),
+    .m_axis_tuser(tx_fifo_udp_payload_axis_tuser),
+
+    // Status
+    .status_overflow(),
+    .status_bad_frame(),
+    .status_good_frame()
+);
+
+endmodule
diff --git a/example/Genesys2/fpga/rtl/sync_reset.v b/example/Genesys2/fpga/rtl/sync_reset.v
new file mode 100644
index 000000000..acbcf1c6e
--- /dev/null
+++ b/example/Genesys2/fpga/rtl/sync_reset.v
@@ -0,0 +1,52 @@
+/*
+
+Copyright (c) 2014-2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog-2001
+
+`timescale 1 ns / 1 ps
+
+/*
+ * Synchronizes an active-high asynchronous reset signal to a given clock by
+ * using a pipeline of N registers.
+ */
+module sync_reset #(
+    parameter N=2 // depth of synchronizer
+)(
+    input wire clk,
+    input wire rst,
+    output wire sync_reset_out
+);
+
+reg [N-1:0] sync_reg = {N{1'b1}};
+
+assign sync_reset_out = sync_reg[N-1];
+
+always @(posedge clk or posedge rst) begin
+    if (rst)
+        sync_reg <= {N{1'b1}};
+    else
+        sync_reg <= {sync_reg[N-2:0], 1'b0};
+end
+
+endmodule
diff --git a/example/Genesys2/fpga/rtl/sync_signal.v b/example/Genesys2/fpga/rtl/sync_signal.v
new file mode 100644
index 000000000..b2a8ce3de
--- /dev/null
+++ b/example/Genesys2/fpga/rtl/sync_signal.v
@@ -0,0 +1,58 @@
+/*
+
+Copyright (c) 2014-2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog-2001
+
+`timescale 1 ns / 1 ps
+
+/*
+ * Synchronizes an asyncronous signal to a given clock by using a pipeline of
+ * two registers.
+ */
+module sync_signal #(
+    parameter WIDTH=1, // width of the input and output signals
+    parameter N=2 // depth of synchronizer
+)(
+    input wire clk,
+    input wire [WIDTH-1:0] in,
+    output wire [WIDTH-1:0] out
+);
+
+reg [WIDTH-1:0] sync_reg[N-1:0];
+
+/*
+ * The synchronized output is the last register in the pipeline.
+ */
+assign out = sync_reg[N-1];
+
+integer k;
+
+always @(posedge clk) begin
+    sync_reg[0] <= in;
+    for (k = 1; k < N; k = k + 1) begin
+        sync_reg[k] <= sync_reg[k-1];
+    end
+end
+
+endmodule
diff --git a/example/Genesys2/fpga/tb/arp_ep.py b/example/Genesys2/fpga/tb/arp_ep.py
new file mode 120000
index 000000000..7b3d3ed97
--- /dev/null
+++ b/example/Genesys2/fpga/tb/arp_ep.py
@@ -0,0 +1 @@
+../lib/eth/tb/arp_ep.py
\ No newline at end of file
diff --git a/example/Genesys2/fpga/tb/axis_ep.py b/example/Genesys2/fpga/tb/axis_ep.py
new file mode 120000
index 000000000..385bb0300
--- /dev/null
+++ b/example/Genesys2/fpga/tb/axis_ep.py
@@ -0,0 +1 @@
+../lib/eth/tb/axis_ep.py
\ No newline at end of file
diff --git a/example/Genesys2/fpga/tb/eth_ep.py b/example/Genesys2/fpga/tb/eth_ep.py
new file mode 120000
index 000000000..bac19feea
--- /dev/null
+++ b/example/Genesys2/fpga/tb/eth_ep.py
@@ -0,0 +1 @@
+../lib/eth/tb/eth_ep.py
\ No newline at end of file
diff --git a/example/Genesys2/fpga/tb/gmii_ep.py b/example/Genesys2/fpga/tb/gmii_ep.py
new file mode 120000
index 000000000..754166f2f
--- /dev/null
+++ b/example/Genesys2/fpga/tb/gmii_ep.py
@@ -0,0 +1 @@
+../lib/eth/tb/gmii_ep.py
\ No newline at end of file
diff --git a/example/Genesys2/fpga/tb/ip_ep.py b/example/Genesys2/fpga/tb/ip_ep.py
new file mode 120000
index 000000000..6dfa928a7
--- /dev/null
+++ b/example/Genesys2/fpga/tb/ip_ep.py
@@ -0,0 +1 @@
+../lib/eth/tb/ip_ep.py
\ No newline at end of file
diff --git a/example/Genesys2/fpga/tb/rgmii_ep.py b/example/Genesys2/fpga/tb/rgmii_ep.py
new file mode 120000
index 000000000..986c56280
--- /dev/null
+++ b/example/Genesys2/fpga/tb/rgmii_ep.py
@@ -0,0 +1 @@
+../lib/eth/tb/rgmii_ep.py
\ No newline at end of file
diff --git a/example/Genesys2/fpga/tb/test_fpga_core.py b/example/Genesys2/fpga/tb/test_fpga_core.py
new file mode 100755
index 000000000..c320ac269
--- /dev/null
+++ b/example/Genesys2/fpga/tb/test_fpga_core.py
@@ -0,0 +1,314 @@
+#!/usr/bin/env python
+"""
+
+Copyright (c) 2015-2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+"""
+
+from myhdl import *
+import os
+
+import eth_ep
+import arp_ep
+import udp_ep
+import rgmii_ep
+
+module = 'fpga_core'
+testbench = 'test_%s' % module
+
+srcs = []
+
+srcs.append("../rtl/%s.v" % module)
+srcs.append("../lib/eth/rtl/iddr.v")
+srcs.append("../lib/eth/rtl/oddr.v")
+srcs.append("../lib/eth/rtl/ssio_ddr_in.v")
+srcs.append("../lib/eth/rtl/ssio_ddr_out.v")
+srcs.append("../lib/eth/rtl/rgmii_phy_if.v")
+srcs.append("../lib/eth/rtl/eth_mac_1g_rgmii_fifo.v")
+srcs.append("../lib/eth/rtl/eth_mac_1g_rgmii.v")
+srcs.append("../lib/eth/rtl/eth_mac_1g.v")
+srcs.append("../lib/eth/rtl/axis_gmii_rx.v")
+srcs.append("../lib/eth/rtl/axis_gmii_tx.v")
+srcs.append("../lib/eth/rtl/lfsr.v")
+srcs.append("../lib/eth/rtl/eth_axis_rx.v")
+srcs.append("../lib/eth/rtl/eth_axis_tx.v")
+srcs.append("../lib/eth/rtl/udp_complete.v")
+srcs.append("../lib/eth/rtl/udp_checksum_gen.v")
+srcs.append("../lib/eth/rtl/udp.v")
+srcs.append("../lib/eth/rtl/udp_ip_rx.v")
+srcs.append("../lib/eth/rtl/udp_ip_tx.v")
+srcs.append("../lib/eth/rtl/ip_complete.v")
+srcs.append("../lib/eth/rtl/ip.v")
+srcs.append("../lib/eth/rtl/ip_eth_rx.v")
+srcs.append("../lib/eth/rtl/ip_eth_tx.v")
+srcs.append("../lib/eth/rtl/ip_arb_mux.v")
+srcs.append("../lib/eth/rtl/arp.v")
+srcs.append("../lib/eth/rtl/arp_cache.v")
+srcs.append("../lib/eth/rtl/arp_eth_rx.v")
+srcs.append("../lib/eth/rtl/arp_eth_tx.v")
+srcs.append("../lib/eth/rtl/eth_arb_mux.v")
+srcs.append("../lib/eth/lib/axis/rtl/arbiter.v")
+srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v")
+srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v")
+srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v")
+srcs.append("%s.v" % testbench)
+
+src = ' '.join(srcs)
+
+build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
+
+def bench():
+
+    # Parameters
+    TARGET = "SIM"
+
+    # Inputs
+    clk = Signal(bool(0))
+    clk90 = Signal(bool(0))
+    rst = Signal(bool(0))
+    current_test = Signal(intbv(0)[8:])
+
+    btnu = Signal(bool(0))
+    btnl = Signal(bool(0))
+    btnd = Signal(bool(0))
+    btnr = Signal(bool(0))
+    btnc = Signal(bool(0))
+    sw = Signal(intbv(0)[8:])
+    phy_rx_clk = Signal(bool(0))
+    phy_rxd = Signal(intbv(0)[4:])
+    phy_rx_ctl = Signal(bool(0))
+    phy_int_n = Signal(bool(1))
+    phy_pme_n = Signal(bool(1))
+    uart_rxd = Signal(bool(0))
+
+    # Outputs
+    led = Signal(intbv(0)[8:])
+    phy_tx_clk = Signal(bool(0))
+    phy_txd = Signal(intbv(0)[4:])
+    phy_tx_ctl = Signal(bool(0))
+    phy_reset_n = Signal(bool(0))
+    uart_txd = Signal(bool(0))
+
+    # sources and sinks
+    mii_select = Signal(bool(0))
+
+    rgmii_source = rgmii_ep.RGMIISource()
+
+    rgmii_source_logic = rgmii_source.create_logic(
+        phy_rx_clk,
+        rst,
+        txd=phy_rxd,
+        tx_ctl=phy_rx_ctl,
+        mii_select=mii_select,
+        name='rgmii_source'
+    )
+
+    rgmii_sink = rgmii_ep.RGMIISink()
+
+    rgmii_sink_logic = rgmii_sink.create_logic(
+        phy_tx_clk,
+        rst,
+        rxd=phy_txd,
+        rx_ctl=phy_tx_ctl,
+        mii_select=mii_select,
+        name='rgmii_sink'
+    )
+
+    # DUT
+    if os.system(build_cmd):
+        raise Exception("Error running build command")
+
+    dut = Cosimulation(
+        "vvp -m myhdl %s.vvp -lxt2" % testbench,
+        clk=clk,
+        clk90=clk90,
+        rst=rst,
+        current_test=current_test,
+
+        btnu=btnu,
+        btnl=btnl,
+        btnd=btnd,
+        btnr=btnr,
+        btnc=btnc,
+        sw=sw,
+        led=led,
+
+        phy_rx_clk=phy_rx_clk,
+        phy_rxd=phy_rxd,
+        phy_rx_ctl=phy_rx_ctl,
+        phy_tx_clk=phy_tx_clk,
+        phy_txd=phy_txd,
+        phy_tx_ctl=phy_tx_ctl,
+        phy_reset_n=phy_reset_n,
+        phy_int_n=phy_int_n,
+        phy_pme_n=phy_pme_n,
+
+        uart_rxd=uart_rxd,
+        uart_txd=uart_txd
+    )
+
+    @always(delay(4))
+    def clkgen():
+        clk.next = not clk
+
+    @instance
+    def clkgen2():
+        yield delay(4+2)
+        while True:
+            clk90.next = not clk90
+            yield delay(4)
+
+    rx_clk_hp = Signal(int(4))
+
+    @instance
+    def rx_clk_gen():
+        while True:
+            yield delay(int(rx_clk_hp))
+            phy_rx_clk.next = not phy_rx_clk
+
+    @instance
+    def check():
+        yield delay(100)
+        yield clk.posedge
+        rst.next = 1
+        yield clk.posedge
+        rst.next = 0
+        yield clk.posedge
+        yield delay(100)
+        yield clk.posedge
+
+        # testbench stimulus
+
+        yield clk.posedge
+        print("test 1: test UDP RX packet")
+        current_test.next = 1
+
+        test_frame = udp_ep.UDPFrame()
+        test_frame.eth_dest_mac = 0x020000000000
+        test_frame.eth_src_mac = 0xDAD1D2D3D4D5
+        test_frame.eth_type = 0x0800
+        test_frame.ip_version = 4
+        test_frame.ip_ihl = 5
+        test_frame.ip_dscp = 0
+        test_frame.ip_ecn = 0
+        test_frame.ip_length = None
+        test_frame.ip_identification = 0
+        test_frame.ip_flags = 2
+        test_frame.ip_fragment_offset = 0
+        test_frame.ip_ttl = 64
+        test_frame.ip_protocol = 0x11
+        test_frame.ip_header_checksum = None
+        test_frame.ip_source_ip = 0xc0a80181
+        test_frame.ip_dest_ip = 0xc0a80180
+        test_frame.udp_source_port = 5678
+        test_frame.udp_dest_port = 1234
+        test_frame.payload = bytearray(range(32))
+        test_frame.build()
+
+        rgmii_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+test_frame.build_eth().build_axis_fcs().data)
+
+        # wait for ARP request packet
+        while rgmii_sink.empty():
+            yield clk.posedge
+
+        rx_frame = rgmii_sink.recv()
+        check_eth_frame = eth_ep.EthFrame()
+        check_eth_frame.parse_axis_fcs(rx_frame.data[8:])
+        check_frame = arp_ep.ARPFrame()
+        check_frame.parse_eth(check_eth_frame)
+
+        print(check_frame)
+
+        assert check_frame.eth_dest_mac == 0xFFFFFFFFFFFF
+        assert check_frame.eth_src_mac == 0x020000000000
+        assert check_frame.eth_type == 0x0806
+        assert check_frame.arp_htype == 0x0001
+        assert check_frame.arp_ptype == 0x0800
+        assert check_frame.arp_hlen == 6
+        assert check_frame.arp_plen == 4
+        assert check_frame.arp_oper == 1
+        assert check_frame.arp_sha == 0x020000000000
+        assert check_frame.arp_spa == 0xc0a80180
+        assert check_frame.arp_tha == 0x000000000000
+        assert check_frame.arp_tpa == 0xc0a80181
+
+        # generate response
+        arp_frame = arp_ep.ARPFrame()
+        arp_frame.eth_dest_mac = 0x020000000000
+        arp_frame.eth_src_mac = 0xDAD1D2D3D4D5
+        arp_frame.eth_type = 0x0806
+        arp_frame.arp_htype = 0x0001
+        arp_frame.arp_ptype = 0x0800
+        arp_frame.arp_hlen = 6
+        arp_frame.arp_plen = 4
+        arp_frame.arp_oper = 2
+        arp_frame.arp_sha = 0xDAD1D2D3D4D5
+        arp_frame.arp_spa = 0xc0a80181
+        arp_frame.arp_tha = 0x020000000000
+        arp_frame.arp_tpa = 0xc0a80180
+
+        rgmii_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+arp_frame.build_eth().build_axis_fcs().data)
+
+        while rgmii_sink.empty():
+            yield clk.posedge
+
+        rx_frame = rgmii_sink.recv()
+        check_eth_frame = eth_ep.EthFrame()
+        check_eth_frame.parse_axis_fcs(rx_frame.data[8:])
+        check_frame = udp_ep.UDPFrame()
+        check_frame.parse_eth(check_eth_frame)
+
+        print(check_frame)
+
+        assert check_frame.eth_dest_mac == 0xDAD1D2D3D4D5
+        assert check_frame.eth_src_mac == 0x020000000000
+        assert check_frame.eth_type == 0x0800
+        assert check_frame.ip_version == 4
+        assert check_frame.ip_ihl == 5
+        assert check_frame.ip_dscp == 0
+        assert check_frame.ip_ecn == 0
+        assert check_frame.ip_identification == 0
+        assert check_frame.ip_flags == 2
+        assert check_frame.ip_fragment_offset == 0
+        assert check_frame.ip_ttl == 64
+        assert check_frame.ip_protocol == 0x11
+        assert check_frame.ip_source_ip == 0xc0a80180
+        assert check_frame.ip_dest_ip == 0xc0a80181
+        assert check_frame.udp_source_port == 1234
+        assert check_frame.udp_dest_port == 5678
+        assert check_frame.payload.data == bytearray(range(32))
+
+        assert rgmii_source.empty()
+        assert rgmii_sink.empty()
+
+        yield delay(100)
+
+        raise StopSimulation
+
+    return instances()
+
+def test_bench():
+    sim = Simulation(bench())
+    sim.run()
+
+if __name__ == '__main__':
+    print("Running test...")
+    test_bench()
diff --git a/example/Genesys2/fpga/tb/test_fpga_core.v b/example/Genesys2/fpga/tb/test_fpga_core.v
new file mode 100644
index 000000000..088a94d2c
--- /dev/null
+++ b/example/Genesys2/fpga/tb/test_fpga_core.v
@@ -0,0 +1,125 @@
+/*
+
+Copyright (c) 2015-2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * Testbench for fpga_core
+ */
+module test_fpga_core;
+
+// Parameters
+parameter TARGET = "SIM";
+
+// Inputs
+reg clk = 0;
+reg clk90 = 0;
+reg rst = 0;
+reg [7:0] current_test = 0;
+
+reg btnu = 0;
+reg btnl = 0;
+reg btnd = 0;
+reg btnr = 0;
+reg btnc = 0;
+reg [7:0] sw = 0;
+reg phy_rx_clk = 0;
+reg [3:0] phy_rxd = 0;
+reg phy_rx_ctl = 0;
+reg phy_int_n = 1;
+reg phy_pme_n = 1;
+reg uart_rxd = 0;
+
+// Outputs
+wire [7:0] led;
+wire phy_tx_clk;
+wire [3:0] phy_txd;
+wire phy_tx_ctl;
+wire phy_reset_n;
+wire uart_txd;
+
+initial begin
+    // myhdl integration
+    $from_myhdl(
+        clk,
+        clk90,
+        rst,
+        current_test,
+        btnu,
+        btnl,
+        btnd,
+        btnr,
+        btnc,
+        sw,
+        phy_rx_clk,
+        phy_rxd,
+        phy_rx_ctl,
+        phy_int_n,
+        phy_pme_n,
+        uart_rxd
+    );
+    $to_myhdl(
+        led,
+        phy_tx_clk,
+        phy_txd,
+        phy_tx_ctl,
+        phy_reset_n,
+        uart_txd
+    );
+
+    // dump file
+    $dumpfile("test_fpga_core.lxt");
+    $dumpvars(0, test_fpga_core);
+end
+
+fpga_core #(
+    .TARGET(TARGET)
+)
+UUT (
+    .clk(clk),
+    .clk90(clk90),
+    .rst(rst),
+    .btnu(btnu),
+    .btnl(btnl),
+    .btnd(btnd),
+    .btnr(btnr),
+    .btnc(btnc),
+    .sw(sw),
+    .led(led),
+    .phy_rx_clk(phy_rx_clk),
+    .phy_rxd(phy_rxd),
+    .phy_rx_ctl(phy_rx_ctl),
+    .phy_tx_clk(phy_tx_clk),
+    .phy_txd(phy_txd),
+    .phy_tx_ctl(phy_tx_ctl),
+    .phy_reset_n(phy_reset_n),
+    .phy_int_n(phy_int_n),
+    .phy_pme_n(phy_pme_n),
+    .uart_rxd(uart_rxd),
+    .uart_txd(uart_txd)
+);
+
+endmodule
diff --git a/example/Genesys2/fpga/tb/udp_ep.py b/example/Genesys2/fpga/tb/udp_ep.py
new file mode 120000
index 000000000..073c5d3c6
--- /dev/null
+++ b/example/Genesys2/fpga/tb/udp_ep.py
@@ -0,0 +1 @@
+../lib/eth/tb/udp_ep.py
\ No newline at end of file