From de818ad62152ccf56abdce739604a64841490b1b Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Fri, 10 Nov 2023 15:30:37 -0800 Subject: [PATCH] Merge AU280 into Alveo example design Signed-off-by: Alex Forencich --- example/AU280/fpga_25g/Makefile | 25 - example/AU280/fpga_25g/README.md | 30 - example/AU280/fpga_25g/common/vivado.mk | 137 ---- example/AU280/fpga_25g/ip/eth_xcvr_gt.tcl | 76 -- example/AU280/fpga_25g/lib/eth | 1 - .../fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v | 395 ----------- .../AU280/fpga_25g/rtl/eth_xcvr_phy_wrapper.v | 307 -------- example/AU280/fpga_25g/rtl/fpga_core.v | 655 ------------------ example/AU280/fpga_25g/rtl/sync_signal.v | 62 -- example/AU280/fpga_25g/tb/fpga_core/Makefile | 95 --- .../fpga_25g/tb/fpga_core/test_fpga_core.py | 227 ------ example/Alveo/fpga_25g/README.md | 1 + .../fpga_25g/fpga_AU280}/Makefile | 4 +- .../fpga_25g/fpga_AU280}/config.tcl | 0 .../fpga_25g/fpga_AU280_10g}/Makefile | 4 +- .../fpga_25g/fpga_AU280_10g}/config.tcl | 0 .../fpga_25g/fpga_au280.xdc} | 4 +- .../fpga_25g/rtl/fpga_au280.v} | 311 +++------ 18 files changed, 120 insertions(+), 2214 deletions(-) delete mode 100644 example/AU280/fpga_25g/Makefile delete mode 100644 example/AU280/fpga_25g/README.md delete mode 100644 example/AU280/fpga_25g/common/vivado.mk delete mode 100644 example/AU280/fpga_25g/ip/eth_xcvr_gt.tcl delete mode 120000 example/AU280/fpga_25g/lib/eth delete mode 100644 example/AU280/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v delete mode 100644 example/AU280/fpga_25g/rtl/eth_xcvr_phy_wrapper.v delete mode 100644 example/AU280/fpga_25g/rtl/fpga_core.v delete mode 100644 example/AU280/fpga_25g/rtl/sync_signal.v delete mode 100644 example/AU280/fpga_25g/tb/fpga_core/Makefile delete mode 100644 example/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py rename example/{AU280/fpga_25g/fpga => Alveo/fpga_25g/fpga_AU280}/Makefile (98%) rename example/{AU280/fpga_25g/fpga => Alveo/fpga_25g/fpga_AU280}/config.tcl (100%) rename example/{AU280/fpga_25g/fpga_10g => Alveo/fpga_25g/fpga_AU280_10g}/Makefile (98%) rename example/{AU280/fpga_25g/fpga_10g => Alveo/fpga_25g/fpga_AU280_10g}/config.tcl (100%) rename example/{AU280/fpga_25g/fpga.xdc => Alveo/fpga_25g/fpga_au280.xdc} (99%) rename example/{AU280/fpga_25g/rtl/fpga.v => Alveo/fpga_25g/rtl/fpga_au280.v} (55%) diff --git a/example/AU280/fpga_25g/Makefile b/example/AU280/fpga_25g/Makefile deleted file mode 100644 index f504bd06f..000000000 --- a/example/AU280/fpga_25g/Makefile +++ /dev/null @@ -1,25 +0,0 @@ -# Targets -TARGETS:= - -# Subdirectories -SUBDIRS = fpga -SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) - -# Rules -.PHONY: all -all: $(SUBDIRS) $(TARGETS) - -.PHONY: $(SUBDIRS) -$(SUBDIRS): - cd $@ && $(MAKE) - -.PHONY: $(SUBDIRS_CLEAN) -$(SUBDIRS_CLEAN): - cd $(@:.clean=) && $(MAKE) clean - -.PHONY: clean -clean: $(SUBDIRS_CLEAN) - -rm -rf $(TARGETS) - -program: - #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit diff --git a/example/AU280/fpga_25g/README.md b/example/AU280/fpga_25g/README.md deleted file mode 100644 index c1e7939d6..000000000 --- a/example/AU280/fpga_25g/README.md +++ /dev/null @@ -1,30 +0,0 @@ -# Verilog Ethernet Alveo U280 Example Design - -## Introduction - -This example design targets the Xilinx Alveo U280 FPGA board. - -The design by default listens to UDP port 1234 at IP address 192.168.1.128 and -will echo back any packets received. The design will also respond correctly -to ARP requests. - -* FPGA: xcu280-fsvh2892-2L-e -* PHY: 10G BASE-R PHY IP core and internal GTY transceiver - -## How to build - -Run make to build. Ensure that the Xilinx Vivado toolchain components are -in PATH. - -## How to test - -Run make program to program the Alveo U280 board with Vivado. Then run - - netcat -u 192.168.1.128 1234 - -to open a UDP connection to port 1234. Any text entered into netcat will be -echoed back after pressing enter. - -It is also possible to use hping to test the design by running - - hping 192.168.1.128 -2 -p 1234 -d 1024 diff --git a/example/AU280/fpga_25g/common/vivado.mk b/example/AU280/fpga_25g/common/vivado.mk deleted file mode 100644 index 1402e2382..000000000 --- a/example/AU280/fpga_25g/common/vivado.mk +++ /dev/null @@ -1,137 +0,0 @@ -################################################################### -# -# Xilinx Vivado FPGA Makefile -# -# Copyright (c) 2016 Alex Forencich -# -################################################################### -# -# Parameters: -# FPGA_TOP - Top module name -# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale) -# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e) -# SYN_FILES - space-separated list of source files -# INC_FILES - space-separated list of include files -# XDC_FILES - space-separated list of timing constraint files -# XCI_FILES - space-separated list of IP XCI files -# -# Example: -# -# FPGA_TOP = fpga -# FPGA_FAMILY = VirtexUltrascale -# FPGA_DEVICE = xcvu095-ffva2104-2-e -# SYN_FILES = rtl/fpga.v -# XDC_FILES = fpga.xdc -# XCI_FILES = ip/pcspma.xci -# include ../common/vivado.mk -# -################################################################### - -# phony targets -.PHONY: fpga vivado tmpclean clean distclean - -# prevent make from deleting intermediate files and reports -.PRECIOUS: %.xpr %.bit %.mcs %.prm -.SECONDARY: - -CONFIG ?= config.mk --include ../$(CONFIG) - -FPGA_TOP ?= fpga -PROJECT ?= $(FPGA_TOP) - -SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -INC_FILES_REL = $(foreach p,$(INC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -XCI_FILES_REL = $(foreach p,$(XCI_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -IP_TCL_FILES_REL = $(foreach p,$(IP_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) - -ifdef XDC_FILES - XDC_FILES_REL = $(foreach p,$(XDC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -else - XDC_FILES_REL = $(PROJECT).xdc -endif - -################################################################### -# Main Targets -# -# all: build everything -# clean: remove output files and project files -################################################################### - -all: fpga - -fpga: $(PROJECT).bit - -vivado: $(PROJECT).xpr - vivado $(PROJECT).xpr - -tmpclean:: - -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v - -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl - -clean:: tmpclean - -rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl - -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt - -distclean:: clean - -rm -rf rev - -################################################################### -# Target implementations -################################################################### - -# Vivado project file -create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL) - rm -rf defines.v - touch defines.v - for x in $(DEFS); do echo '`define' $$x >> defines.v; done - echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@ - echo "add_files -fileset sources_1 defines.v $(SYN_FILES_REL)" >> $@ - echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@ - echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@ - for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done - for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done - for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done - -update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) - echo "open_project -quiet $(PROJECT).xpr" > $@ - for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done - -$(PROJECT).xpr: create_project.tcl update_config.tcl - vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) - -# synthesis run -$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) | $(PROJECT).xpr - echo "open_project $(PROJECT).xpr" > run_synth.tcl - echo "reset_run synth_1" >> run_synth.tcl - echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl - echo "wait_on_run synth_1" >> run_synth.tcl - vivado -nojournal -nolog -mode batch -source run_synth.tcl - -# implementation run -$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp - echo "open_project $(PROJECT).xpr" > run_impl.tcl - echo "reset_run impl_1" >> run_impl.tcl - echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl - echo "wait_on_run impl_1" >> run_impl.tcl - echo "open_run impl_1" >> run_impl.tcl - echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl - echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl - vivado -nojournal -nolog -mode batch -source run_impl.tcl - -# bit file -$(PROJECT).bit $(PROJECT).ltx: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp - echo "open_project $(PROJECT).xpr" > generate_bit.tcl - echo "open_run impl_1" >> generate_bit.tcl - echo "write_bitstream -force $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl - echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl - vivado -nojournal -nolog -mode batch -source generate_bit.tcl - ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit . - if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi - mkdir -p rev - COUNT=100; \ - while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \ - do COUNT=$$((COUNT+1)); done; \ - cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \ - if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi diff --git a/example/AU280/fpga_25g/ip/eth_xcvr_gt.tcl b/example/AU280/fpga_25g/ip/eth_xcvr_gt.tcl deleted file mode 100644 index cecca12f7..000000000 --- a/example/AU280/fpga_25g/ip/eth_xcvr_gt.tcl +++ /dev/null @@ -1,76 +0,0 @@ -# Copyright (c) 2021 Alex Forencich -# -# Permission is hereby granted, free of charge, to any person obtaining a copy -# of this software and associated documentation files (the "Software"), to deal -# in the Software without restriction, including without limitation the rights -# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -# copies of the Software, and to permit persons to whom the Software is -# furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice shall be included in -# all copies or substantial portions of the Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -# THE SOFTWARE. - -set base_name {eth_xcvr_gt} - -set preset {GTY-10GBASE-R} - -set freerun_freq {125} -set line_rate {10.3125} -set refclk_freq {161.1328125} -set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] -set user_data_width {64} -set int_data_width $user_data_width -set extra_ports [list] -set extra_pll_ports [list {qpll0lock_out}] - -set config [dict create] - -dict set config TX_LINE_RATE $line_rate -dict set config TX_REFCLK_FREQUENCY $refclk_freq -dict set config TX_QPLL_FRACN_NUMERATOR $qpll_fracn -dict set config TX_USER_DATA_WIDTH $user_data_width -dict set config TX_INT_DATA_WIDTH $int_data_width -dict set config RX_LINE_RATE $line_rate -dict set config RX_REFCLK_FREQUENCY $refclk_freq -dict set config RX_QPLL_FRACN_NUMERATOR $qpll_fracn -dict set config RX_USER_DATA_WIDTH $user_data_width -dict set config RX_INT_DATA_WIDTH $int_data_width -dict set config ENABLE_OPTIONAL_PORTS $extra_ports -dict set config LOCATE_COMMON {CORE} -dict set config LOCATE_RESET_CONTROLLER {CORE} -dict set config LOCATE_TX_USER_CLOCKING {CORE} -dict set config LOCATE_RX_USER_CLOCKING {CORE} -dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE} -dict set config FREERUN_FREQUENCY $freerun_freq -dict set config DISABLE_LOC_XDC {1} - -proc create_gtwizard_ip {name preset config} { - create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name $name - set ip [get_ips $name] - set_property CONFIG.preset $preset $ip - set config_list {} - dict for {name value} $config { - lappend config_list "CONFIG.${name}" $value - } - set_property -dict $config_list $ip -} - -# variant with channel and common -dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports] -dict set config LOCATE_COMMON {CORE} - -create_gtwizard_ip "${base_name}_full" $preset $config - -# variant with channel only -dict set config ENABLE_OPTIONAL_PORTS $extra_ports -dict set config LOCATE_COMMON {EXAMPLE_DESIGN} - -create_gtwizard_ip "${base_name}_channel" $preset $config diff --git a/example/AU280/fpga_25g/lib/eth b/example/AU280/fpga_25g/lib/eth deleted file mode 120000 index 11a54ed36..000000000 --- a/example/AU280/fpga_25g/lib/eth +++ /dev/null @@ -1 +0,0 @@ -../../../../ \ No newline at end of file diff --git a/example/AU280/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v b/example/AU280/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v deleted file mode 100644 index c910d7906..000000000 --- a/example/AU280/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v +++ /dev/null @@ -1,395 +0,0 @@ -/* - -Copyright (c) 2023 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * Transceiver and PHY quad wrapper - */ -module eth_xcvr_phy_quad_wrapper # -( - parameter COUNT = 4, - parameter DATA_WIDTH = 64, - parameter CTRL_WIDTH = (DATA_WIDTH/8), - parameter HDR_WIDTH = 2, - parameter PRBS31_ENABLE = 0, - parameter TX_SERDES_PIPELINE = 0, - parameter RX_SERDES_PIPELINE = 0, - parameter BITSLIP_HIGH_CYCLES = 1, - parameter BITSLIP_LOW_CYCLES = 8, - parameter COUNT_125US = 125000/6.4 -) -( - input wire xcvr_ctrl_clk, - input wire xcvr_ctrl_rst, - - /* - * Common - */ - output wire xcvr_gtpowergood_out, - - /* - * PLL - */ - input wire xcvr_gtrefclk00_in, - - /* - * Serial data - */ - output wire [COUNT-1:0] xcvr_txp, - output wire [COUNT-1:0] xcvr_txn, - input wire [COUNT-1:0] xcvr_rxp, - input wire [COUNT-1:0] xcvr_rxn, - - /* - * PHY connections - */ - output wire phy_1_tx_clk, - output wire phy_1_tx_rst, - input wire [DATA_WIDTH-1:0] phy_1_xgmii_txd, - input wire [CTRL_WIDTH-1:0] phy_1_xgmii_txc, - output wire phy_1_rx_clk, - output wire phy_1_rx_rst, - output wire [DATA_WIDTH-1:0] phy_1_xgmii_rxd, - output wire [CTRL_WIDTH-1:0] phy_1_xgmii_rxc, - output wire phy_1_tx_bad_block, - output wire [6:0] phy_1_rx_error_count, - output wire phy_1_rx_bad_block, - output wire phy_1_rx_sequence_error, - output wire phy_1_rx_block_lock, - output wire phy_1_rx_high_ber, - output wire phy_1_rx_status, - input wire phy_1_cfg_tx_prbs31_enable, - input wire phy_1_cfg_rx_prbs31_enable, - - output wire phy_2_tx_clk, - output wire phy_2_tx_rst, - input wire [DATA_WIDTH-1:0] phy_2_xgmii_txd, - input wire [CTRL_WIDTH-1:0] phy_2_xgmii_txc, - output wire phy_2_rx_clk, - output wire phy_2_rx_rst, - output wire [DATA_WIDTH-1:0] phy_2_xgmii_rxd, - output wire [CTRL_WIDTH-1:0] phy_2_xgmii_rxc, - output wire phy_2_tx_bad_block, - output wire [6:0] phy_2_rx_error_count, - output wire phy_2_rx_bad_block, - output wire phy_2_rx_sequence_error, - output wire phy_2_rx_block_lock, - output wire phy_2_rx_high_ber, - output wire phy_2_rx_status, - input wire phy_2_cfg_tx_prbs31_enable, - input wire phy_2_cfg_rx_prbs31_enable, - - output wire phy_3_tx_clk, - output wire phy_3_tx_rst, - input wire [DATA_WIDTH-1:0] phy_3_xgmii_txd, - input wire [CTRL_WIDTH-1:0] phy_3_xgmii_txc, - output wire phy_3_rx_clk, - output wire phy_3_rx_rst, - output wire [DATA_WIDTH-1:0] phy_3_xgmii_rxd, - output wire [CTRL_WIDTH-1:0] phy_3_xgmii_rxc, - output wire phy_3_tx_bad_block, - output wire [6:0] phy_3_rx_error_count, - output wire phy_3_rx_bad_block, - output wire phy_3_rx_sequence_error, - output wire phy_3_rx_block_lock, - output wire phy_3_rx_high_ber, - output wire phy_3_rx_status, - input wire phy_3_cfg_tx_prbs31_enable, - input wire phy_3_cfg_rx_prbs31_enable, - - output wire phy_4_tx_clk, - output wire phy_4_tx_rst, - input wire [DATA_WIDTH-1:0] phy_4_xgmii_txd, - input wire [CTRL_WIDTH-1:0] phy_4_xgmii_txc, - output wire phy_4_rx_clk, - output wire phy_4_rx_rst, - output wire [DATA_WIDTH-1:0] phy_4_xgmii_rxd, - output wire [CTRL_WIDTH-1:0] phy_4_xgmii_rxc, - output wire phy_4_tx_bad_block, - output wire [6:0] phy_4_rx_error_count, - output wire phy_4_rx_bad_block, - output wire phy_4_rx_sequence_error, - output wire phy_4_rx_block_lock, - output wire phy_4_rx_high_ber, - output wire phy_4_rx_status, - input wire phy_4_cfg_tx_prbs31_enable, - input wire phy_4_cfg_rx_prbs31_enable -); - -generate - -wire xcvr_qpll0lock; -wire xcvr_qpll0clk; -wire xcvr_qpll0refclk; - -if (COUNT > 0) begin : phy1 - - eth_xcvr_phy_wrapper #( - .HAS_COMMON(1), - .DATA_WIDTH(DATA_WIDTH), - .CTRL_WIDTH(CTRL_WIDTH), - .HDR_WIDTH(HDR_WIDTH), - .PRBS31_ENABLE(PRBS31_ENABLE), - .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), - .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), - .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), - .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), - .COUNT_125US(COUNT_125US) - ) - eth_xcvr_phy_1 ( - .xcvr_ctrl_clk(xcvr_ctrl_clk), - .xcvr_ctrl_rst(xcvr_ctrl_rst), - - // Common - .xcvr_gtpowergood_out(xcvr_gtpowergood_out), - - // PLL out - .xcvr_gtrefclk00_in(xcvr_gtrefclk00_in), - .xcvr_qpll0lock_out(xcvr_qpll0lock), - .xcvr_qpll0clk_out(xcvr_qpll0clk), - .xcvr_qpll0refclk_out(xcvr_qpll0refclk), - - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), - - // Serial data - .xcvr_txp(xcvr_txp[0]), - .xcvr_txn(xcvr_txn[0]), - .xcvr_rxp(xcvr_rxp[0]), - .xcvr_rxn(xcvr_rxn[0]), - - // PHY connections - .phy_tx_clk(phy_1_tx_clk), - .phy_tx_rst(phy_1_tx_rst), - .phy_xgmii_txd(phy_1_xgmii_txd), - .phy_xgmii_txc(phy_1_xgmii_txc), - .phy_rx_clk(phy_1_rx_clk), - .phy_rx_rst(phy_1_rx_rst), - .phy_xgmii_rxd(phy_1_xgmii_rxd), - .phy_xgmii_rxc(phy_1_xgmii_rxc), - .phy_tx_bad_block(phy_1_tx_bad_block), - .phy_rx_error_count(phy_1_rx_error_count), - .phy_rx_bad_block(phy_1_rx_bad_block), - .phy_rx_sequence_error(phy_1_rx_sequence_error), - .phy_rx_block_lock(phy_1_rx_block_lock), - .phy_rx_high_ber(phy_1_rx_high_ber), - .phy_rx_status(phy_1_rx_status), - .phy_cfg_tx_prbs31_enable(phy_1_cfg_tx_prbs31_enable), - .phy_cfg_rx_prbs31_enable(phy_1_cfg_rx_prbs31_enable) - ); - -end - -if (COUNT > 1) begin : phy2 - - eth_xcvr_phy_wrapper #( - .HAS_COMMON(0), - .DATA_WIDTH(DATA_WIDTH), - .CTRL_WIDTH(CTRL_WIDTH), - .HDR_WIDTH(HDR_WIDTH), - .PRBS31_ENABLE(PRBS31_ENABLE), - .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), - .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), - .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), - .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), - .COUNT_125US(COUNT_125US) - ) - eth_xcvr_phy_2 ( - .xcvr_ctrl_clk(xcvr_ctrl_clk), - .xcvr_ctrl_rst(xcvr_ctrl_rst), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0clk_out(), - .xcvr_qpll0refclk_out(), - - // PLL in - .xcvr_qpll0lock_in(xcvr_qpll0lock), - .xcvr_qpll0clk_in(xcvr_qpll0clk), - .xcvr_qpll0refclk_in(xcvr_qpll0refclk), - - // Serial data - .xcvr_txp(xcvr_txp[1]), - .xcvr_txn(xcvr_txn[1]), - .xcvr_rxp(xcvr_rxp[1]), - .xcvr_rxn(xcvr_rxn[1]), - - // PHY connections - .phy_tx_clk(phy_2_tx_clk), - .phy_tx_rst(phy_2_tx_rst), - .phy_xgmii_txd(phy_2_xgmii_txd), - .phy_xgmii_txc(phy_2_xgmii_txc), - .phy_rx_clk(phy_2_rx_clk), - .phy_rx_rst(phy_2_rx_rst), - .phy_xgmii_rxd(phy_2_xgmii_rxd), - .phy_xgmii_rxc(phy_2_xgmii_rxc), - .phy_tx_bad_block(phy_2_tx_bad_block), - .phy_rx_error_count(phy_2_rx_error_count), - .phy_rx_bad_block(phy_2_rx_bad_block), - .phy_rx_sequence_error(phy_2_rx_sequence_error), - .phy_rx_block_lock(phy_2_rx_block_lock), - .phy_rx_high_ber(phy_2_rx_high_ber), - .phy_rx_status(phy_2_rx_status), - .phy_cfg_tx_prbs31_enable(phy_2_cfg_tx_prbs31_enable), - .phy_cfg_rx_prbs31_enable(phy_2_cfg_rx_prbs31_enable) - ); - -end - -if (COUNT > 2) begin : phy3 - - eth_xcvr_phy_wrapper #( - .HAS_COMMON(0), - .DATA_WIDTH(DATA_WIDTH), - .CTRL_WIDTH(CTRL_WIDTH), - .HDR_WIDTH(HDR_WIDTH), - .PRBS31_ENABLE(PRBS31_ENABLE), - .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), - .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), - .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), - .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), - .COUNT_125US(COUNT_125US) - ) - eth_xcvr_phy_3 ( - .xcvr_ctrl_clk(xcvr_ctrl_clk), - .xcvr_ctrl_rst(xcvr_ctrl_rst), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0clk_out(), - .xcvr_qpll0refclk_out(), - - // PLL in - .xcvr_qpll0lock_in(xcvr_qpll0lock), - .xcvr_qpll0clk_in(xcvr_qpll0clk), - .xcvr_qpll0refclk_in(xcvr_qpll0refclk), - - // Serial data - .xcvr_txp(xcvr_txp[2]), - .xcvr_txn(xcvr_txn[2]), - .xcvr_rxp(xcvr_rxp[2]), - .xcvr_rxn(xcvr_rxn[2]), - - // PHY connections - .phy_tx_clk(phy_3_tx_clk), - .phy_tx_rst(phy_3_tx_rst), - .phy_xgmii_txd(phy_3_xgmii_txd), - .phy_xgmii_txc(phy_3_xgmii_txc), - .phy_rx_clk(phy_3_rx_clk), - .phy_rx_rst(phy_3_rx_rst), - .phy_xgmii_rxd(phy_3_xgmii_rxd), - .phy_xgmii_rxc(phy_3_xgmii_rxc), - .phy_tx_bad_block(phy_3_tx_bad_block), - .phy_rx_error_count(phy_3_rx_error_count), - .phy_rx_bad_block(phy_3_rx_bad_block), - .phy_rx_sequence_error(phy_3_rx_sequence_error), - .phy_rx_block_lock(phy_3_rx_block_lock), - .phy_rx_high_ber(phy_3_rx_high_ber), - .phy_rx_status(phy_3_rx_status), - .phy_cfg_tx_prbs31_enable(phy_3_cfg_tx_prbs31_enable), - .phy_cfg_rx_prbs31_enable(phy_3_cfg_rx_prbs31_enable) - ); - -end - -if (COUNT > 3) begin : phy4 - - eth_xcvr_phy_wrapper #( - .HAS_COMMON(0), - .DATA_WIDTH(DATA_WIDTH), - .CTRL_WIDTH(CTRL_WIDTH), - .HDR_WIDTH(HDR_WIDTH), - .PRBS31_ENABLE(PRBS31_ENABLE), - .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), - .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), - .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), - .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), - .COUNT_125US(COUNT_125US) - ) - eth_xcvr_phy_4 ( - .xcvr_ctrl_clk(xcvr_ctrl_clk), - .xcvr_ctrl_rst(xcvr_ctrl_rst), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0clk_out(), - .xcvr_qpll0refclk_out(), - - // PLL in - .xcvr_qpll0lock_in(xcvr_qpll0lock), - .xcvr_qpll0clk_in(xcvr_qpll0clk), - .xcvr_qpll0refclk_in(xcvr_qpll0refclk), - - // Serial data - .xcvr_txp(xcvr_txp[3]), - .xcvr_txn(xcvr_txn[3]), - .xcvr_rxp(xcvr_rxp[3]), - .xcvr_rxn(xcvr_rxn[3]), - - // PHY connections - .phy_tx_clk(phy_4_tx_clk), - .phy_tx_rst(phy_4_tx_rst), - .phy_xgmii_txd(phy_4_xgmii_txd), - .phy_xgmii_txc(phy_4_xgmii_txc), - .phy_rx_clk(phy_4_rx_clk), - .phy_rx_rst(phy_4_rx_rst), - .phy_xgmii_rxd(phy_4_xgmii_rxd), - .phy_xgmii_rxc(phy_4_xgmii_rxc), - .phy_tx_bad_block(phy_4_tx_bad_block), - .phy_rx_error_count(phy_4_rx_error_count), - .phy_rx_bad_block(phy_4_rx_bad_block), - .phy_rx_sequence_error(phy_4_rx_sequence_error), - .phy_rx_block_lock(phy_4_rx_block_lock), - .phy_rx_high_ber(phy_4_rx_high_ber), - .phy_rx_status(phy_4_rx_status), - .phy_cfg_tx_prbs31_enable(phy_4_cfg_tx_prbs31_enable), - .phy_cfg_rx_prbs31_enable(phy_4_cfg_rx_prbs31_enable) - ); - -end - -endgenerate - -endmodule - -`resetall diff --git a/example/AU280/fpga_25g/rtl/eth_xcvr_phy_wrapper.v b/example/AU280/fpga_25g/rtl/eth_xcvr_phy_wrapper.v deleted file mode 100644 index 0d1142eb6..000000000 --- a/example/AU280/fpga_25g/rtl/eth_xcvr_phy_wrapper.v +++ /dev/null @@ -1,307 +0,0 @@ -/* - -Copyright (c) 2021-2023 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * Transceiver and PHY wrapper - */ -module eth_xcvr_phy_wrapper # -( - parameter HAS_COMMON = 1, - parameter DATA_WIDTH = 64, - parameter CTRL_WIDTH = (DATA_WIDTH/8), - parameter HDR_WIDTH = 2, - parameter PRBS31_ENABLE = 0, - parameter TX_SERDES_PIPELINE = 0, - parameter RX_SERDES_PIPELINE = 0, - parameter BITSLIP_HIGH_CYCLES = 1, - parameter BITSLIP_LOW_CYCLES = 8, - parameter COUNT_125US = 125000/6.4 -) -( - input wire xcvr_ctrl_clk, - input wire xcvr_ctrl_rst, - - /* - * Common - */ - output wire xcvr_gtpowergood_out, - - /* - * PLL out - */ - input wire xcvr_gtrefclk00_in, - output wire xcvr_qpll0lock_out, - output wire xcvr_qpll0clk_out, - output wire xcvr_qpll0refclk_out, - - /* - * PLL in - */ - input wire xcvr_qpll0lock_in, - output wire xcvr_qpll0reset_out, - input wire xcvr_qpll0clk_in, - input wire xcvr_qpll0refclk_in, - - /* - * Serial data - */ - output wire xcvr_txp, - output wire xcvr_txn, - input wire xcvr_rxp, - input wire xcvr_rxn, - - /* - * PHY connections - */ - output wire phy_tx_clk, - output wire phy_tx_rst, - input wire [DATA_WIDTH-1:0] phy_xgmii_txd, - input wire [CTRL_WIDTH-1:0] phy_xgmii_txc, - output wire phy_rx_clk, - output wire phy_rx_rst, - output wire [DATA_WIDTH-1:0] phy_xgmii_rxd, - output wire [CTRL_WIDTH-1:0] phy_xgmii_rxc, - output wire phy_tx_bad_block, - output wire [6:0] phy_rx_error_count, - output wire phy_rx_bad_block, - output wire phy_rx_sequence_error, - output wire phy_rx_block_lock, - output wire phy_rx_high_ber, - output wire phy_rx_status, - input wire phy_cfg_tx_prbs31_enable, - input wire phy_cfg_rx_prbs31_enable -); - -wire phy_rx_reset_req; - -wire gt_reset_tx_datapath = 1'b0; -wire gt_reset_rx_datapath = phy_rx_reset_req; - -wire gt_reset_tx_done; -wire gt_reset_rx_done; - -wire [5:0] gt_txheader; -wire [63:0] gt_txdata; -wire gt_rxgearboxslip; -wire [5:0] gt_rxheader; -wire [1:0] gt_rxheadervalid; -wire [63:0] gt_rxdata; -wire [1:0] gt_rxdatavalid; - -generate - -if (HAS_COMMON) begin : xcvr - - eth_xcvr_gt_full - eth_xcvr_gt_full_inst ( - // Common - .gtwiz_reset_clk_freerun_in(xcvr_ctrl_clk), - .gtwiz_reset_all_in(xcvr_ctrl_rst), - .gtpowergood_out(xcvr_gtpowergood_out), - - // PLL - .gtrefclk00_in(xcvr_gtrefclk00_in), - .qpll0lock_out(xcvr_qpll0lock_out), - .qpll0outclk_out(xcvr_qpll0clk_out), - .qpll0outrefclk_out(xcvr_qpll0refclk_out), - - // Serial data - .gtytxp_out(xcvr_txp), - .gtytxn_out(xcvr_txn), - .gtyrxp_in(xcvr_rxp), - .gtyrxn_in(xcvr_rxn), - - // Transmit - .gtwiz_userclk_tx_reset_in(1'b0), - .gtwiz_userclk_tx_srcclk_out(), - .gtwiz_userclk_tx_usrclk_out(), - .gtwiz_userclk_tx_usrclk2_out(phy_tx_clk), - .gtwiz_userclk_tx_active_out(), - .gtwiz_reset_tx_pll_and_datapath_in(1'b0), - .gtwiz_reset_tx_datapath_in(gt_reset_tx_datapath), - .gtwiz_reset_tx_done_out(gt_reset_tx_done), - .txpmaresetdone_out(), - .txprgdivresetdone_out(), - - .gtwiz_userdata_tx_in(gt_txdata), - .txheader_in(gt_txheader), - .txsequence_in(7'b0), - - // Receive - .gtwiz_userclk_rx_reset_in(1'b0), - .gtwiz_userclk_rx_srcclk_out(), - .gtwiz_userclk_rx_usrclk_out(), - .gtwiz_userclk_rx_usrclk2_out(phy_rx_clk), - .gtwiz_userclk_rx_active_out(), - .gtwiz_reset_rx_pll_and_datapath_in(1'b0), - .gtwiz_reset_rx_datapath_in(gt_reset_rx_datapath), - .gtwiz_reset_rx_cdr_stable_out(), - .gtwiz_reset_rx_done_out(gt_reset_rx_done), - .rxpmaresetdone_out(), - .rxprgdivresetdone_out(), - - .rxgearboxslip_in(gt_rxgearboxslip), - .gtwiz_userdata_rx_out(gt_rxdata), - .rxdatavalid_out(gt_rxdatavalid), - .rxheader_out(gt_rxheader), - .rxheadervalid_out(gt_rxheadervalid), - .rxstartofseq_out() - ); - - assign xcvr_qpll0reset_out = 1'b0; - -end else begin : xcvr - - eth_xcvr_gt_channel - eth_xcvr_gt_channel_inst ( - // Common - .gtwiz_reset_clk_freerun_in(xcvr_ctrl_clk), - .gtwiz_reset_all_in(xcvr_ctrl_rst), - .gtpowergood_out(xcvr_gtpowergood_out), - - // PLL - .gtwiz_reset_qpll0lock_in(xcvr_qpll0lock_in), - .gtwiz_reset_qpll0reset_out(xcvr_qpll0reset_out), - .qpll0clk_in(xcvr_qpll0clk_in), - .qpll0refclk_in(xcvr_qpll0refclk_in), - .qpll1clk_in(1'b0), - .qpll1refclk_in(1'b0), - - // Serial data - .gtytxp_out(xcvr_txp), - .gtytxn_out(xcvr_txn), - .gtyrxp_in(xcvr_rxp), - .gtyrxn_in(xcvr_rxn), - - // Transmit - .gtwiz_userclk_tx_reset_in(1'b0), - .gtwiz_userclk_tx_srcclk_out(), - .gtwiz_userclk_tx_usrclk_out(), - .gtwiz_userclk_tx_usrclk2_out(phy_tx_clk), - .gtwiz_userclk_tx_active_out(), - .gtwiz_reset_tx_pll_and_datapath_in(1'b0), - .gtwiz_reset_tx_datapath_in(gt_reset_tx_datapath), - .gtwiz_reset_tx_done_out(gt_reset_tx_done), - .txpmaresetdone_out(), - .txprgdivresetdone_out(), - - .gtwiz_userdata_tx_in(gt_txdata), - .txheader_in(gt_txheader), - .txsequence_in(7'b0), - - // Receive - .gtwiz_userclk_rx_reset_in(1'b0), - .gtwiz_userclk_rx_srcclk_out(), - .gtwiz_userclk_rx_usrclk_out(), - .gtwiz_userclk_rx_usrclk2_out(phy_rx_clk), - .gtwiz_userclk_rx_active_out(), - .gtwiz_reset_rx_pll_and_datapath_in(1'b0), - .gtwiz_reset_rx_datapath_in(gt_reset_rx_datapath), - .gtwiz_reset_rx_cdr_stable_out(), - .gtwiz_reset_rx_done_out(gt_reset_rx_done), - .rxpmaresetdone_out(), - .rxprgdivresetdone_out(), - - .rxgearboxslip_in(gt_rxgearboxslip), - .gtwiz_userdata_rx_out(gt_rxdata), - .rxdatavalid_out(gt_rxdatavalid), - .rxheader_out(gt_rxheader), - .rxheadervalid_out(gt_rxheadervalid), - .rxstartofseq_out() - ); - - assign xcvr_qpll0lock_out = 1'b0; - assign xcvr_qpll0clk_out = 1'b0; - assign xcvr_qpll0refclk_out = 1'b0; - -end - -endgenerate - -sync_reset #( - .N(4) -) -tx_reset_sync_inst ( - .clk(phy_tx_clk), - .rst(!gt_reset_tx_done), - .out(phy_tx_rst) -); - -sync_reset #( - .N(4) -) -rx_reset_sync_inst ( - .clk(phy_rx_clk), - .rst(!gt_reset_rx_done), - .out(phy_rx_rst) -); - -eth_phy_10g #( - .DATA_WIDTH(DATA_WIDTH), - .CTRL_WIDTH(CTRL_WIDTH), - .HDR_WIDTH(HDR_WIDTH), - .BIT_REVERSE(1), - .SCRAMBLER_DISABLE(0), - .PRBS31_ENABLE(PRBS31_ENABLE), - .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), - .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), - .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), - .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), - .COUNT_125US(COUNT_125US) -) -phy_inst ( - .tx_clk(phy_tx_clk), - .tx_rst(phy_tx_rst), - .rx_clk(phy_rx_clk), - .rx_rst(phy_rx_rst), - .xgmii_txd(phy_xgmii_txd), - .xgmii_txc(phy_xgmii_txc), - .xgmii_rxd(phy_xgmii_rxd), - .xgmii_rxc(phy_xgmii_rxc), - .serdes_tx_data(gt_txdata), - .serdes_tx_hdr(gt_txheader), - .serdes_rx_data(gt_rxdata), - .serdes_rx_hdr(gt_rxheader), - .serdes_rx_bitslip(gt_rxgearboxslip), - .serdes_rx_reset_req(phy_rx_reset_req), - .tx_bad_block(phy_tx_bad_block), - .rx_error_count(phy_rx_error_count), - .rx_bad_block(phy_rx_bad_block), - .rx_sequence_error(phy_rx_sequence_error), - .rx_block_lock(phy_rx_block_lock), - .rx_high_ber(phy_rx_high_ber), - .rx_status(phy_rx_status), - .cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable), - .cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable) -); - -endmodule - -`resetall diff --git a/example/AU280/fpga_25g/rtl/fpga_core.v b/example/AU280/fpga_25g/rtl/fpga_core.v deleted file mode 100644 index ee706700d..000000000 --- a/example/AU280/fpga_25g/rtl/fpga_core.v +++ /dev/null @@ -1,655 +0,0 @@ -/* - -Copyright (c) 2014-2021 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * FPGA core logic - */ -module fpga_core # -( - parameter TARGET = "XILINX" -) -( - /* - * Clock: 156.25MHz - * Synchronous reset - */ - input wire clk, - input wire rst, - - /* - * Ethernet: QSFP28 - */ - input wire qsfp0_tx_clk_1, - input wire qsfp0_tx_rst_1, - output wire [63:0] qsfp0_txd_1, - output wire [7:0] qsfp0_txc_1, - input wire qsfp0_rx_clk_1, - input wire qsfp0_rx_rst_1, - input wire [63:0] qsfp0_rxd_1, - input wire [7:0] qsfp0_rxc_1, - input wire qsfp0_tx_clk_2, - input wire qsfp0_tx_rst_2, - output wire [63:0] qsfp0_txd_2, - output wire [7:0] qsfp0_txc_2, - input wire qsfp0_rx_clk_2, - input wire qsfp0_rx_rst_2, - input wire [63:0] qsfp0_rxd_2, - input wire [7:0] qsfp0_rxc_2, - input wire qsfp0_tx_clk_3, - input wire qsfp0_tx_rst_3, - output wire [63:0] qsfp0_txd_3, - output wire [7:0] qsfp0_txc_3, - input wire qsfp0_rx_clk_3, - input wire qsfp0_rx_rst_3, - input wire [63:0] qsfp0_rxd_3, - input wire [7:0] qsfp0_rxc_3, - input wire qsfp0_tx_clk_4, - input wire qsfp0_tx_rst_4, - output wire [63:0] qsfp0_txd_4, - output wire [7:0] qsfp0_txc_4, - input wire qsfp0_rx_clk_4, - input wire qsfp0_rx_rst_4, - input wire [63:0] qsfp0_rxd_4, - input wire [7:0] qsfp0_rxc_4, - input wire qsfp1_tx_clk_1, - input wire qsfp1_tx_rst_1, - output wire [63:0] qsfp1_txd_1, - output wire [7:0] qsfp1_txc_1, - input wire qsfp1_rx_clk_1, - input wire qsfp1_rx_rst_1, - input wire [63:0] qsfp1_rxd_1, - input wire [7:0] qsfp1_rxc_1, - input wire qsfp1_tx_clk_2, - input wire qsfp1_tx_rst_2, - output wire [63:0] qsfp1_txd_2, - output wire [7:0] qsfp1_txc_2, - input wire qsfp1_rx_clk_2, - input wire qsfp1_rx_rst_2, - input wire [63:0] qsfp1_rxd_2, - input wire [7:0] qsfp1_rxc_2, - input wire qsfp1_tx_clk_3, - input wire qsfp1_tx_rst_3, - output wire [63:0] qsfp1_txd_3, - output wire [7:0] qsfp1_txc_3, - input wire qsfp1_rx_clk_3, - input wire qsfp1_rx_rst_3, - input wire [63:0] qsfp1_rxd_3, - input wire [7:0] qsfp1_rxc_3, - input wire qsfp1_tx_clk_4, - input wire qsfp1_tx_rst_4, - output wire [63:0] qsfp1_txd_4, - output wire [7:0] qsfp1_txc_4, - input wire qsfp1_rx_clk_4, - input wire qsfp1_rx_rst_4, - input wire [63:0] qsfp1_rxd_4, - input wire [7:0] qsfp1_rxc_4 -); - -// AXI between MAC and Ethernet modules -wire [63:0] rx_axis_tdata; -wire [7:0] rx_axis_tkeep; -wire rx_axis_tvalid; -wire rx_axis_tready; -wire rx_axis_tlast; -wire rx_axis_tuser; - -wire [63:0] tx_axis_tdata; -wire [7:0] tx_axis_tkeep; -wire tx_axis_tvalid; -wire tx_axis_tready; -wire tx_axis_tlast; -wire tx_axis_tuser; - -// Ethernet frame between Ethernet modules and UDP stack -wire rx_eth_hdr_ready; -wire rx_eth_hdr_valid; -wire [47:0] rx_eth_dest_mac; -wire [47:0] rx_eth_src_mac; -wire [15:0] rx_eth_type; -wire [63:0] rx_eth_payload_axis_tdata; -wire [7:0] rx_eth_payload_axis_tkeep; -wire rx_eth_payload_axis_tvalid; -wire rx_eth_payload_axis_tready; -wire rx_eth_payload_axis_tlast; -wire rx_eth_payload_axis_tuser; - -wire tx_eth_hdr_ready; -wire tx_eth_hdr_valid; -wire [47:0] tx_eth_dest_mac; -wire [47:0] tx_eth_src_mac; -wire [15:0] tx_eth_type; -wire [63:0] tx_eth_payload_axis_tdata; -wire [7:0] tx_eth_payload_axis_tkeep; -wire tx_eth_payload_axis_tvalid; -wire tx_eth_payload_axis_tready; -wire tx_eth_payload_axis_tlast; -wire tx_eth_payload_axis_tuser; - -// IP frame connections -wire rx_ip_hdr_valid; -wire rx_ip_hdr_ready; -wire [47:0] rx_ip_eth_dest_mac; -wire [47:0] rx_ip_eth_src_mac; -wire [15:0] rx_ip_eth_type; -wire [3:0] rx_ip_version; -wire [3:0] rx_ip_ihl; -wire [5:0] rx_ip_dscp; -wire [1:0] rx_ip_ecn; -wire [15:0] rx_ip_length; -wire [15:0] rx_ip_identification; -wire [2:0] rx_ip_flags; -wire [12:0] rx_ip_fragment_offset; -wire [7:0] rx_ip_ttl; -wire [7:0] rx_ip_protocol; -wire [15:0] rx_ip_header_checksum; -wire [31:0] rx_ip_source_ip; -wire [31:0] rx_ip_dest_ip; -wire [63:0] rx_ip_payload_axis_tdata; -wire [7:0] rx_ip_payload_axis_tkeep; -wire rx_ip_payload_axis_tvalid; -wire rx_ip_payload_axis_tready; -wire rx_ip_payload_axis_tlast; -wire rx_ip_payload_axis_tuser; - -wire tx_ip_hdr_valid; -wire tx_ip_hdr_ready; -wire [5:0] tx_ip_dscp; -wire [1:0] tx_ip_ecn; -wire [15:0] tx_ip_length; -wire [7:0] tx_ip_ttl; -wire [7:0] tx_ip_protocol; -wire [31:0] tx_ip_source_ip; -wire [31:0] tx_ip_dest_ip; -wire [63:0] tx_ip_payload_axis_tdata; -wire [7:0] tx_ip_payload_axis_tkeep; -wire tx_ip_payload_axis_tvalid; -wire tx_ip_payload_axis_tready; -wire tx_ip_payload_axis_tlast; -wire tx_ip_payload_axis_tuser; - -// UDP frame connections -wire rx_udp_hdr_valid; -wire rx_udp_hdr_ready; -wire [47:0] rx_udp_eth_dest_mac; -wire [47:0] rx_udp_eth_src_mac; -wire [15:0] rx_udp_eth_type; -wire [3:0] rx_udp_ip_version; -wire [3:0] rx_udp_ip_ihl; -wire [5:0] rx_udp_ip_dscp; -wire [1:0] rx_udp_ip_ecn; -wire [15:0] rx_udp_ip_length; -wire [15:0] rx_udp_ip_identification; -wire [2:0] rx_udp_ip_flags; -wire [12:0] rx_udp_ip_fragment_offset; -wire [7:0] rx_udp_ip_ttl; -wire [7:0] rx_udp_ip_protocol; -wire [15:0] rx_udp_ip_header_checksum; -wire [31:0] rx_udp_ip_source_ip; -wire [31:0] rx_udp_ip_dest_ip; -wire [15:0] rx_udp_source_port; -wire [15:0] rx_udp_dest_port; -wire [15:0] rx_udp_length; -wire [15:0] rx_udp_checksum; -wire [63:0] rx_udp_payload_axis_tdata; -wire [7:0] rx_udp_payload_axis_tkeep; -wire rx_udp_payload_axis_tvalid; -wire rx_udp_payload_axis_tready; -wire rx_udp_payload_axis_tlast; -wire rx_udp_payload_axis_tuser; - -wire tx_udp_hdr_valid; -wire tx_udp_hdr_ready; -wire [5:0] tx_udp_ip_dscp; -wire [1:0] tx_udp_ip_ecn; -wire [7:0] tx_udp_ip_ttl; -wire [31:0] tx_udp_ip_source_ip; -wire [31:0] tx_udp_ip_dest_ip; -wire [15:0] tx_udp_source_port; -wire [15:0] tx_udp_dest_port; -wire [15:0] tx_udp_length; -wire [15:0] tx_udp_checksum; -wire [63:0] tx_udp_payload_axis_tdata; -wire [7:0] tx_udp_payload_axis_tkeep; -wire tx_udp_payload_axis_tvalid; -wire tx_udp_payload_axis_tready; -wire tx_udp_payload_axis_tlast; -wire tx_udp_payload_axis_tuser; - -wire [63:0] rx_fifo_udp_payload_axis_tdata; -wire [7:0] rx_fifo_udp_payload_axis_tkeep; -wire rx_fifo_udp_payload_axis_tvalid; -wire rx_fifo_udp_payload_axis_tready; -wire rx_fifo_udp_payload_axis_tlast; -wire rx_fifo_udp_payload_axis_tuser; - -wire [63:0] tx_fifo_udp_payload_axis_tdata; -wire [7:0] tx_fifo_udp_payload_axis_tkeep; -wire tx_fifo_udp_payload_axis_tvalid; -wire tx_fifo_udp_payload_axis_tready; -wire tx_fifo_udp_payload_axis_tlast; -wire tx_fifo_udp_payload_axis_tuser; - -// Configuration -wire [47:0] local_mac = 48'h02_00_00_00_00_00; -wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128}; -wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1}; -wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0}; - -// IP ports not used -assign rx_ip_hdr_ready = 1; -assign rx_ip_payload_axis_tready = 1; - -assign tx_ip_hdr_valid = 0; -assign tx_ip_dscp = 0; -assign tx_ip_ecn = 0; -assign tx_ip_length = 0; -assign tx_ip_ttl = 0; -assign tx_ip_protocol = 0; -assign tx_ip_source_ip = 0; -assign tx_ip_dest_ip = 0; -assign tx_ip_payload_axis_tdata = 0; -assign tx_ip_payload_axis_tkeep = 0; -assign tx_ip_payload_axis_tvalid = 0; -assign tx_ip_payload_axis_tlast = 0; -assign tx_ip_payload_axis_tuser = 0; - -// Loop back UDP -wire match_cond = rx_udp_dest_port == 1234; -wire no_match = !match_cond; - -reg match_cond_reg = 0; -reg no_match_reg = 0; - -always @(posedge clk) begin - if (rst) begin - match_cond_reg <= 0; - no_match_reg <= 0; - end else begin - if (rx_udp_payload_axis_tvalid) begin - if ((!match_cond_reg && !no_match_reg) || - (rx_udp_payload_axis_tvalid && rx_udp_payload_axis_tready && rx_udp_payload_axis_tlast)) begin - match_cond_reg <= match_cond; - no_match_reg <= no_match; - end - end else begin - match_cond_reg <= 0; - no_match_reg <= 0; - end - end -end - -assign tx_udp_hdr_valid = rx_udp_hdr_valid && match_cond; -assign rx_udp_hdr_ready = (tx_eth_hdr_ready && match_cond) || no_match; -assign tx_udp_ip_dscp = 0; -assign tx_udp_ip_ecn = 0; -assign tx_udp_ip_ttl = 64; -assign tx_udp_ip_source_ip = local_ip; -assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip; -assign tx_udp_source_port = rx_udp_dest_port; -assign tx_udp_dest_port = rx_udp_source_port; -assign tx_udp_length = rx_udp_length; -assign tx_udp_checksum = 0; - -assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata; -assign tx_udp_payload_axis_tkeep = tx_fifo_udp_payload_axis_tkeep; -assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid; -assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready; -assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast; -assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser; - -assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata; -assign rx_fifo_udp_payload_axis_tkeep = rx_udp_payload_axis_tkeep; -assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid && match_cond_reg; -assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready && match_cond_reg) || no_match_reg; -assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast; -assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser; - -// Place first payload byte onto LEDs -reg valid_last = 0; -reg [7:0] led_reg = 0; - -always @(posedge clk) begin - if (rst) begin - led_reg <= 0; - end else begin - valid_last <= tx_udp_payload_axis_tvalid; - if (tx_udp_payload_axis_tvalid && !valid_last) begin - led_reg <= tx_udp_payload_axis_tdata; - end - end -end - -assign qsfp0_txd_2 = 64'h0707070707070707; -assign qsfp0_txc_2 = 8'hff; -assign qsfp0_txd_3 = 64'h0707070707070707; -assign qsfp0_txc_3 = 8'hff; -assign qsfp0_txd_4 = 64'h0707070707070707; -assign qsfp0_txc_4 = 8'hff; - -assign qsfp1_txd_1 = 64'h0707070707070707; -assign qsfp1_txc_1 = 8'hff; -assign qsfp1_txd_2 = 64'h0707070707070707; -assign qsfp1_txc_2 = 8'hff; -assign qsfp1_txd_3 = 64'h0707070707070707; -assign qsfp1_txc_3 = 8'hff; -assign qsfp1_txd_4 = 64'h0707070707070707; -assign qsfp1_txc_4 = 8'hff; - -eth_mac_10g_fifo #( - .ENABLE_PADDING(1), - .ENABLE_DIC(1), - .MIN_FRAME_LENGTH(64), - .TX_FIFO_DEPTH(4096), - .TX_FRAME_FIFO(1), - .RX_FIFO_DEPTH(4096), - .RX_FRAME_FIFO(1) -) -eth_mac_10g_fifo_inst ( - .rx_clk(qsfp0_rx_clk_1), - .rx_rst(qsfp0_rx_rst_1), - .tx_clk(qsfp0_tx_clk_1), - .tx_rst(qsfp0_tx_rst_1), - .logic_clk(clk), - .logic_rst(rst), - - .tx_axis_tdata(tx_axis_tdata), - .tx_axis_tkeep(tx_axis_tkeep), - .tx_axis_tvalid(tx_axis_tvalid), - .tx_axis_tready(tx_axis_tready), - .tx_axis_tlast(tx_axis_tlast), - .tx_axis_tuser(tx_axis_tuser), - - .rx_axis_tdata(rx_axis_tdata), - .rx_axis_tkeep(rx_axis_tkeep), - .rx_axis_tvalid(rx_axis_tvalid), - .rx_axis_tready(rx_axis_tready), - .rx_axis_tlast(rx_axis_tlast), - .rx_axis_tuser(rx_axis_tuser), - - .xgmii_rxd(qsfp0_rxd_1), - .xgmii_rxc(qsfp0_rxc_1), - .xgmii_txd(qsfp0_txd_1), - .xgmii_txc(qsfp0_txc_1), - - .tx_fifo_overflow(), - .tx_fifo_bad_frame(), - .tx_fifo_good_frame(), - .rx_error_bad_frame(), - .rx_error_bad_fcs(), - .rx_fifo_overflow(), - .rx_fifo_bad_frame(), - .rx_fifo_good_frame(), - - .cfg_ifg(8'd12), - .cfg_tx_enable(1'b1), - .cfg_rx_enable(1'b1) -); - -eth_axis_rx #( - .DATA_WIDTH(64) -) -eth_axis_rx_inst ( - .clk(clk), - .rst(rst), - // AXI input - .s_axis_tdata(rx_axis_tdata), - .s_axis_tkeep(rx_axis_tkeep), - .s_axis_tvalid(rx_axis_tvalid), - .s_axis_tready(rx_axis_tready), - .s_axis_tlast(rx_axis_tlast), - .s_axis_tuser(rx_axis_tuser), - // Ethernet frame output - .m_eth_hdr_valid(rx_eth_hdr_valid), - .m_eth_hdr_ready(rx_eth_hdr_ready), - .m_eth_dest_mac(rx_eth_dest_mac), - .m_eth_src_mac(rx_eth_src_mac), - .m_eth_type(rx_eth_type), - .m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata), - .m_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep), - .m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid), - .m_eth_payload_axis_tready(rx_eth_payload_axis_tready), - .m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast), - .m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser), - // Status signals - .busy(), - .error_header_early_termination() -); - -eth_axis_tx #( - .DATA_WIDTH(64) -) -eth_axis_tx_inst ( - .clk(clk), - .rst(rst), - // Ethernet frame input - .s_eth_hdr_valid(tx_eth_hdr_valid), - .s_eth_hdr_ready(tx_eth_hdr_ready), - .s_eth_dest_mac(tx_eth_dest_mac), - .s_eth_src_mac(tx_eth_src_mac), - .s_eth_type(tx_eth_type), - .s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata), - .s_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep), - .s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid), - .s_eth_payload_axis_tready(tx_eth_payload_axis_tready), - .s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast), - .s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser), - // AXI output - .m_axis_tdata(tx_axis_tdata), - .m_axis_tkeep(tx_axis_tkeep), - .m_axis_tvalid(tx_axis_tvalid), - .m_axis_tready(tx_axis_tready), - .m_axis_tlast(tx_axis_tlast), - .m_axis_tuser(tx_axis_tuser), - // Status signals - .busy() -); - -udp_complete_64 -udp_complete_inst ( - .clk(clk), - .rst(rst), - // Ethernet frame input - .s_eth_hdr_valid(rx_eth_hdr_valid), - .s_eth_hdr_ready(rx_eth_hdr_ready), - .s_eth_dest_mac(rx_eth_dest_mac), - .s_eth_src_mac(rx_eth_src_mac), - .s_eth_type(rx_eth_type), - .s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata), - .s_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep), - .s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid), - .s_eth_payload_axis_tready(rx_eth_payload_axis_tready), - .s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast), - .s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser), - // Ethernet frame output - .m_eth_hdr_valid(tx_eth_hdr_valid), - .m_eth_hdr_ready(tx_eth_hdr_ready), - .m_eth_dest_mac(tx_eth_dest_mac), - .m_eth_src_mac(tx_eth_src_mac), - .m_eth_type(tx_eth_type), - .m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata), - .m_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep), - .m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid), - .m_eth_payload_axis_tready(tx_eth_payload_axis_tready), - .m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast), - .m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser), - // IP frame input - .s_ip_hdr_valid(tx_ip_hdr_valid), - .s_ip_hdr_ready(tx_ip_hdr_ready), - .s_ip_dscp(tx_ip_dscp), - .s_ip_ecn(tx_ip_ecn), - .s_ip_length(tx_ip_length), - .s_ip_ttl(tx_ip_ttl), - .s_ip_protocol(tx_ip_protocol), - .s_ip_source_ip(tx_ip_source_ip), - .s_ip_dest_ip(tx_ip_dest_ip), - .s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata), - .s_ip_payload_axis_tkeep(tx_ip_payload_axis_tkeep), - .s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid), - .s_ip_payload_axis_tready(tx_ip_payload_axis_tready), - .s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast), - .s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser), - // IP frame output - .m_ip_hdr_valid(rx_ip_hdr_valid), - .m_ip_hdr_ready(rx_ip_hdr_ready), - .m_ip_eth_dest_mac(rx_ip_eth_dest_mac), - .m_ip_eth_src_mac(rx_ip_eth_src_mac), - .m_ip_eth_type(rx_ip_eth_type), - .m_ip_version(rx_ip_version), - .m_ip_ihl(rx_ip_ihl), - .m_ip_dscp(rx_ip_dscp), - .m_ip_ecn(rx_ip_ecn), - .m_ip_length(rx_ip_length), - .m_ip_identification(rx_ip_identification), - .m_ip_flags(rx_ip_flags), - .m_ip_fragment_offset(rx_ip_fragment_offset), - .m_ip_ttl(rx_ip_ttl), - .m_ip_protocol(rx_ip_protocol), - .m_ip_header_checksum(rx_ip_header_checksum), - .m_ip_source_ip(rx_ip_source_ip), - .m_ip_dest_ip(rx_ip_dest_ip), - .m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata), - .m_ip_payload_axis_tkeep(rx_ip_payload_axis_tkeep), - .m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid), - .m_ip_payload_axis_tready(rx_ip_payload_axis_tready), - .m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast), - .m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser), - // UDP frame input - .s_udp_hdr_valid(tx_udp_hdr_valid), - .s_udp_hdr_ready(tx_udp_hdr_ready), - .s_udp_ip_dscp(tx_udp_ip_dscp), - .s_udp_ip_ecn(tx_udp_ip_ecn), - .s_udp_ip_ttl(tx_udp_ip_ttl), - .s_udp_ip_source_ip(tx_udp_ip_source_ip), - .s_udp_ip_dest_ip(tx_udp_ip_dest_ip), - .s_udp_source_port(tx_udp_source_port), - .s_udp_dest_port(tx_udp_dest_port), - .s_udp_length(tx_udp_length), - .s_udp_checksum(tx_udp_checksum), - .s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata), - .s_udp_payload_axis_tkeep(tx_udp_payload_axis_tkeep), - .s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid), - .s_udp_payload_axis_tready(tx_udp_payload_axis_tready), - .s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast), - .s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser), - // UDP frame output - .m_udp_hdr_valid(rx_udp_hdr_valid), - .m_udp_hdr_ready(rx_udp_hdr_ready), - .m_udp_eth_dest_mac(rx_udp_eth_dest_mac), - .m_udp_eth_src_mac(rx_udp_eth_src_mac), - .m_udp_eth_type(rx_udp_eth_type), - .m_udp_ip_version(rx_udp_ip_version), - .m_udp_ip_ihl(rx_udp_ip_ihl), - .m_udp_ip_dscp(rx_udp_ip_dscp), - .m_udp_ip_ecn(rx_udp_ip_ecn), - .m_udp_ip_length(rx_udp_ip_length), - .m_udp_ip_identification(rx_udp_ip_identification), - .m_udp_ip_flags(rx_udp_ip_flags), - .m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset), - .m_udp_ip_ttl(rx_udp_ip_ttl), - .m_udp_ip_protocol(rx_udp_ip_protocol), - .m_udp_ip_header_checksum(rx_udp_ip_header_checksum), - .m_udp_ip_source_ip(rx_udp_ip_source_ip), - .m_udp_ip_dest_ip(rx_udp_ip_dest_ip), - .m_udp_source_port(rx_udp_source_port), - .m_udp_dest_port(rx_udp_dest_port), - .m_udp_length(rx_udp_length), - .m_udp_checksum(rx_udp_checksum), - .m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata), - .m_udp_payload_axis_tkeep(rx_udp_payload_axis_tkeep), - .m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid), - .m_udp_payload_axis_tready(rx_udp_payload_axis_tready), - .m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast), - .m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser), - // Status signals - .ip_rx_busy(), - .ip_tx_busy(), - .udp_rx_busy(), - .udp_tx_busy(), - .ip_rx_error_header_early_termination(), - .ip_rx_error_payload_early_termination(), - .ip_rx_error_invalid_header(), - .ip_rx_error_invalid_checksum(), - .ip_tx_error_payload_early_termination(), - .ip_tx_error_arp_failed(), - .udp_rx_error_header_early_termination(), - .udp_rx_error_payload_early_termination(), - .udp_tx_error_payload_early_termination(), - // Configuration - .local_mac(local_mac), - .local_ip(local_ip), - .gateway_ip(gateway_ip), - .subnet_mask(subnet_mask), - .clear_arp_cache(1'b0) -); - -axis_fifo #( - .DEPTH(8192), - .DATA_WIDTH(64), - .KEEP_ENABLE(1), - .KEEP_WIDTH(8), - .ID_ENABLE(0), - .DEST_ENABLE(0), - .USER_ENABLE(1), - .USER_WIDTH(1), - .FRAME_FIFO(0) -) -udp_payload_fifo ( - .clk(clk), - .rst(rst), - - // AXI input - .s_axis_tdata(rx_fifo_udp_payload_axis_tdata), - .s_axis_tkeep(rx_fifo_udp_payload_axis_tkeep), - .s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid), - .s_axis_tready(rx_fifo_udp_payload_axis_tready), - .s_axis_tlast(rx_fifo_udp_payload_axis_tlast), - .s_axis_tid(0), - .s_axis_tdest(0), - .s_axis_tuser(rx_fifo_udp_payload_axis_tuser), - - // AXI output - .m_axis_tdata(tx_fifo_udp_payload_axis_tdata), - .m_axis_tkeep(tx_fifo_udp_payload_axis_tkeep), - .m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid), - .m_axis_tready(tx_fifo_udp_payload_axis_tready), - .m_axis_tlast(tx_fifo_udp_payload_axis_tlast), - .m_axis_tid(), - .m_axis_tdest(), - .m_axis_tuser(tx_fifo_udp_payload_axis_tuser), - - // Status - .status_overflow(), - .status_bad_frame(), - .status_good_frame() -); - -endmodule - -`resetall diff --git a/example/AU280/fpga_25g/rtl/sync_signal.v b/example/AU280/fpga_25g/rtl/sync_signal.v deleted file mode 100644 index 74b855fa1..000000000 --- a/example/AU280/fpga_25g/rtl/sync_signal.v +++ /dev/null @@ -1,62 +0,0 @@ -/* - -Copyright (c) 2014-2018 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog-2001 - -`resetall -`timescale 1 ns / 1 ps -`default_nettype none - -/* - * Synchronizes an asyncronous signal to a given clock by using a pipeline of - * two registers. - */ -module sync_signal #( - parameter WIDTH=1, // width of the input and output signals - parameter N=2 // depth of synchronizer -)( - input wire clk, - input wire [WIDTH-1:0] in, - output wire [WIDTH-1:0] out -); - -reg [WIDTH-1:0] sync_reg[N-1:0]; - -/* - * The synchronized output is the last register in the pipeline. - */ -assign out = sync_reg[N-1]; - -integer k; - -always @(posedge clk) begin - sync_reg[0] <= in; - for (k = 1; k < N; k = k + 1) begin - sync_reg[k] <= sync_reg[k-1]; - end -end - -endmodule - -`resetall diff --git a/example/AU280/fpga_25g/tb/fpga_core/Makefile b/example/AU280/fpga_25g/tb/fpga_core/Makefile deleted file mode 100644 index d840fbe00..000000000 --- a/example/AU280/fpga_25g/tb/fpga_core/Makefile +++ /dev/null @@ -1,95 +0,0 @@ -# Copyright (c) 2020 Alex Forencich -# -# Permission is hereby granted, free of charge, to any person obtaining a copy -# of this software and associated documentation files (the "Software"), to deal -# in the Software without restriction, including without limitation the rights -# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -# copies of the Software, and to permit persons to whom the Software is -# furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice shall be included in -# all copies or substantial portions of the Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -# THE SOFTWARE. - -TOPLEVEL_LANG = verilog - -SIM ?= icarus -WAVES ?= 0 - -COCOTB_HDL_TIMEUNIT = 1ns -COCOTB_HDL_TIMEPRECISION = 1ps - -DUT = fpga_core -TOPLEVEL = $(DUT) -MODULE = test_$(DUT) -VERILOG_SOURCES += ../../rtl/$(DUT).v -VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g_fifo.v -VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g.v -VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_rx_64.v -VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_tx_64.v -VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v -VERILOG_SOURCES += ../../lib/eth/rtl/eth_axis_rx.v -VERILOG_SOURCES += ../../lib/eth/rtl/eth_axis_tx.v -VERILOG_SOURCES += ../../lib/eth/rtl/udp_complete_64.v -VERILOG_SOURCES += ../../lib/eth/rtl/udp_checksum_gen_64.v -VERILOG_SOURCES += ../../lib/eth/rtl/udp_64.v -VERILOG_SOURCES += ../../lib/eth/rtl/udp_ip_rx_64.v -VERILOG_SOURCES += ../../lib/eth/rtl/udp_ip_tx_64.v -VERILOG_SOURCES += ../../lib/eth/rtl/ip_complete_64.v -VERILOG_SOURCES += ../../lib/eth/rtl/ip_64.v -VERILOG_SOURCES += ../../lib/eth/rtl/ip_eth_rx_64.v -VERILOG_SOURCES += ../../lib/eth/rtl/ip_eth_tx_64.v -VERILOG_SOURCES += ../../lib/eth/rtl/ip_arb_mux.v -VERILOG_SOURCES += ../../lib/eth/rtl/arp.v -VERILOG_SOURCES += ../../lib/eth/rtl/arp_cache.v -VERILOG_SOURCES += ../../lib/eth/rtl/arp_eth_rx.v -VERILOG_SOURCES += ../../lib/eth/rtl/arp_eth_tx.v -VERILOG_SOURCES += ../../lib/eth/rtl/eth_arb_mux.v -VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/arbiter.v -VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/priority_encoder.v -VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_fifo.v -VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v -VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v - -# module parameters -#export PARAM_A := value - -ifeq ($(SIM), icarus) - PLUSARGS += -fst - -# COMPILE_ARGS += -P $(TOPLEVEL).A=$(PARAM_A) - - ifeq ($(WAVES), 1) - VERILOG_SOURCES += iverilog_dump.v - COMPILE_ARGS += -s iverilog_dump - endif -else ifeq ($(SIM), verilator) - COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - -# COMPILE_ARGS += -GA=$(PARAM_A) - - ifeq ($(WAVES), 1) - COMPILE_ARGS += --trace-fst - endif -endif - -include $(shell cocotb-config --makefiles)/Makefile.sim - -iverilog_dump.v: - echo 'module iverilog_dump();' > $@ - echo 'initial begin' >> $@ - echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ - echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ - echo 'end' >> $@ - echo 'endmodule' >> $@ - -clean:: - @rm -rf iverilog_dump.v - @rm -rf dump.fst $(TOPLEVEL).fst diff --git a/example/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py b/example/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py deleted file mode 100644 index ef36bbec9..000000000 --- a/example/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py +++ /dev/null @@ -1,227 +0,0 @@ -""" - -Copyright (c) 2020 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -""" - -import logging -import os - -from scapy.layers.l2 import Ether, ARP -from scapy.layers.inet import IP, UDP - -import cocotb_test.simulator - -import cocotb -from cocotb.log import SimLog -from cocotb.clock import Clock -from cocotb.triggers import RisingEdge - -from cocotbext.eth import XgmiiFrame, XgmiiSource, XgmiiSink - - -class TB: - def __init__(self, dut): - self.dut = dut - - self.log = SimLog("cocotb.tb") - self.log.setLevel(logging.DEBUG) - - cocotb.start_soon(Clock(dut.clk, 2.56, units="ns").start()) - - # Ethernet - self.qsfp_source = [] - self.qsfp_sink = [] - - for x in range(2): - sources = [] - sinks = [] - for y in range(1, 5): - cocotb.start_soon(Clock(getattr(dut, f"qsfp{x}_rx_clk_{y}"), 2.56, units="ns").start()) - source = XgmiiSource(getattr(dut, f"qsfp{x}_rxd_{y}"), getattr(dut, f"qsfp{x}_rxc_{y}"), getattr(dut, f"qsfp{x}_rx_clk_{y}"), getattr(dut, f"qsfp{x}_rx_rst_{y}")) - sources.append(source) - cocotb.start_soon(Clock(getattr(dut, f"qsfp{x}_tx_clk_{y}"), 2.56, units="ns").start()) - sink = XgmiiSink(getattr(dut, f"qsfp{x}_txd_{y}"), getattr(dut, f"qsfp{x}_txc_{y}"), getattr(dut, f"qsfp{x}_tx_clk_{y}"), getattr(dut, f"qsfp{x}_tx_rst_{y}")) - sinks.append(sink) - self.qsfp_source.append(sources) - self.qsfp_sink.append(sinks) - - async def init(self): - - self.dut.rst.setimmediatevalue(0) - for x in range(2): - for y in range(1, 5): - getattr(self.dut, f"qsfp{x}_rx_rst_{y}").setimmediatevalue(0) - getattr(self.dut, f"qsfp{x}_tx_rst_{y}").setimmediatevalue(0) - - for k in range(10): - await RisingEdge(self.dut.clk) - - self.dut.rst.value = 1 - for x in range(2): - for y in range(1, 5): - getattr(self.dut, f"qsfp{x}_rx_rst_{y}").value = 1 - getattr(self.dut, f"qsfp{x}_tx_rst_{y}").value = 1 - - for k in range(10): - await RisingEdge(self.dut.clk) - - self.dut.rst.value = 0 - for x in range(2): - for y in range(1, 5): - getattr(self.dut, f"qsfp{x}_rx_rst_{y}").value = 0 - getattr(self.dut, f"qsfp{x}_tx_rst_{y}").value = 0 - - -@cocotb.test() -async def run_test(dut): - - tb = TB(dut) - - await tb.init() - - tb.log.info("test UDP RX packet") - - payload = bytes([x % 256 for x in range(256)]) - eth = Ether(src='5a:51:52:53:54:55', dst='02:00:00:00:00:00') - ip = IP(src='192.168.1.100', dst='192.168.1.128') - udp = UDP(sport=5678, dport=1234) - test_pkt = eth / ip / udp / payload - - test_frame = XgmiiFrame.from_payload(test_pkt.build()) - - await tb.qsfp_source[0][0].send(test_frame) - - tb.log.info("receive ARP request") - - rx_frame = await tb.qsfp_sink[0][0].recv() - - rx_pkt = Ether(bytes(rx_frame.get_payload())) - - tb.log.info("RX packet: %s", repr(rx_pkt)) - - assert rx_pkt.dst == 'ff:ff:ff:ff:ff:ff' - assert rx_pkt.src == test_pkt.dst - assert rx_pkt[ARP].hwtype == 1 - assert rx_pkt[ARP].ptype == 0x0800 - assert rx_pkt[ARP].hwlen == 6 - assert rx_pkt[ARP].plen == 4 - assert rx_pkt[ARP].op == 1 - assert rx_pkt[ARP].hwsrc == test_pkt.dst - assert rx_pkt[ARP].psrc == test_pkt[IP].dst - assert rx_pkt[ARP].hwdst == '00:00:00:00:00:00' - assert rx_pkt[ARP].pdst == test_pkt[IP].src - - tb.log.info("send ARP response") - - eth = Ether(src=test_pkt.src, dst=test_pkt.dst) - arp = ARP(hwtype=1, ptype=0x0800, hwlen=6, plen=4, op=2, - hwsrc=test_pkt.src, psrc=test_pkt[IP].src, - hwdst=test_pkt.dst, pdst=test_pkt[IP].dst) - resp_pkt = eth / arp - - resp_frame = XgmiiFrame.from_payload(resp_pkt.build()) - - await tb.qsfp_source[0][0].send(resp_frame) - - tb.log.info("receive UDP packet") - - rx_frame = await tb.qsfp_sink[0][0].recv() - - rx_pkt = Ether(bytes(rx_frame.get_payload())) - - tb.log.info("RX packet: %s", repr(rx_pkt)) - - assert rx_pkt.dst == test_pkt.src - assert rx_pkt.src == test_pkt.dst - assert rx_pkt[IP].dst == test_pkt[IP].src - assert rx_pkt[IP].src == test_pkt[IP].dst - assert rx_pkt[UDP].dport == test_pkt[UDP].sport - assert rx_pkt[UDP].sport == test_pkt[UDP].dport - assert rx_pkt[UDP].payload == test_pkt[UDP].payload - - await RisingEdge(dut.clk) - await RisingEdge(dut.clk) - - -# cocotb-test - -tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) -lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) -axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'lib', 'axis', 'rtl')) -eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl')) - - -def test_fpga_core(request): - dut = "fpga_core" - module = os.path.splitext(os.path.basename(__file__))[0] - toplevel = dut - - verilog_sources = [ - os.path.join(rtl_dir, f"{dut}.v"), - os.path.join(eth_rtl_dir, "eth_mac_10g_fifo.v"), - os.path.join(eth_rtl_dir, "eth_mac_10g.v"), - os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"), - os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"), - os.path.join(eth_rtl_dir, "lfsr.v"), - os.path.join(eth_rtl_dir, "eth_axis_rx.v"), - os.path.join(eth_rtl_dir, "eth_axis_tx.v"), - os.path.join(eth_rtl_dir, "udp_complete_64.v"), - os.path.join(eth_rtl_dir, "udp_checksum_gen_64.v"), - os.path.join(eth_rtl_dir, "udp_64.v"), - os.path.join(eth_rtl_dir, "udp_ip_rx_64.v"), - os.path.join(eth_rtl_dir, "udp_ip_tx_64.v"), - os.path.join(eth_rtl_dir, "ip_complete_64.v"), - os.path.join(eth_rtl_dir, "ip_64.v"), - os.path.join(eth_rtl_dir, "ip_eth_rx_64.v"), - os.path.join(eth_rtl_dir, "ip_eth_tx_64.v"), - os.path.join(eth_rtl_dir, "ip_arb_mux.v"), - os.path.join(eth_rtl_dir, "arp.v"), - os.path.join(eth_rtl_dir, "arp_cache.v"), - os.path.join(eth_rtl_dir, "arp_eth_rx.v"), - os.path.join(eth_rtl_dir, "arp_eth_tx.v"), - os.path.join(eth_rtl_dir, "eth_arb_mux.v"), - os.path.join(axis_rtl_dir, "arbiter.v"), - os.path.join(axis_rtl_dir, "priority_encoder.v"), - os.path.join(axis_rtl_dir, "axis_fifo.v"), - os.path.join(axis_rtl_dir, "axis_async_fifo.v"), - os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), - ] - - parameters = {} - - # parameters['A'] = val - - extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} - - sim_build = os.path.join(tests_dir, "sim_build", - request.node.name.replace('[', '-').replace(']', '')) - - cocotb_test.simulator.run( - python_search=[tests_dir], - verilog_sources=verilog_sources, - toplevel=toplevel, - module=module, - parameters=parameters, - sim_build=sim_build, - extra_env=extra_env, - ) diff --git a/example/Alveo/fpga_25g/README.md b/example/Alveo/fpga_25g/README.md index a02a6418e..c8d44624f 100644 --- a/example/Alveo/fpga_25g/README.md +++ b/example/Alveo/fpga_25g/README.md @@ -9,6 +9,7 @@ The design by default listens to UDP port 1234 at IP address 192.168.1.128 and w * FPGA * AU200: xcu200-fsgd2104-2-e * AU250: xcu250-fsgd2104-2-e + * AU280: xcu280-fsvh2892-2L-e * VCU1525: xcvu9p-fsgd2104-2L-e * PHY: 10G BASE-R PHY IP core and internal GTY transceiver diff --git a/example/AU280/fpga_25g/fpga/Makefile b/example/Alveo/fpga_25g/fpga_AU280/Makefile similarity index 98% rename from example/AU280/fpga_25g/fpga/Makefile rename to example/Alveo/fpga_25g/fpga_AU280/Makefile index 0cb457f14..ec17f5b76 100644 --- a/example/AU280/fpga_25g/fpga/Makefile +++ b/example/Alveo/fpga_25g/fpga_AU280/Makefile @@ -5,7 +5,7 @@ FPGA_TOP = fpga FPGA_ARCH = virtexuplus # Files for synthesis -SYN_FILES = rtl/fpga.v +SYN_FILES = rtl/fpga_au280.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/eth_xcvr_phy_wrapper.v SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v @@ -51,7 +51,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v # XDC files -XDC_FILES = fpga.xdc +XDC_FILES = fpga_au280.xdc XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl diff --git a/example/AU280/fpga_25g/fpga/config.tcl b/example/Alveo/fpga_25g/fpga_AU280/config.tcl similarity index 100% rename from example/AU280/fpga_25g/fpga/config.tcl rename to example/Alveo/fpga_25g/fpga_AU280/config.tcl diff --git a/example/AU280/fpga_25g/fpga_10g/Makefile b/example/Alveo/fpga_25g/fpga_AU280_10g/Makefile similarity index 98% rename from example/AU280/fpga_25g/fpga_10g/Makefile rename to example/Alveo/fpga_25g/fpga_AU280_10g/Makefile index 0cb457f14..ec17f5b76 100644 --- a/example/AU280/fpga_25g/fpga_10g/Makefile +++ b/example/Alveo/fpga_25g/fpga_AU280_10g/Makefile @@ -5,7 +5,7 @@ FPGA_TOP = fpga FPGA_ARCH = virtexuplus # Files for synthesis -SYN_FILES = rtl/fpga.v +SYN_FILES = rtl/fpga_au280.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/eth_xcvr_phy_wrapper.v SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v @@ -51,7 +51,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v # XDC files -XDC_FILES = fpga.xdc +XDC_FILES = fpga_au280.xdc XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl diff --git a/example/AU280/fpga_25g/fpga_10g/config.tcl b/example/Alveo/fpga_25g/fpga_AU280_10g/config.tcl similarity index 100% rename from example/AU280/fpga_25g/fpga_10g/config.tcl rename to example/Alveo/fpga_25g/fpga_AU280_10g/config.tcl diff --git a/example/AU280/fpga_25g/fpga.xdc b/example/Alveo/fpga_25g/fpga_au280.xdc similarity index 99% rename from example/AU280/fpga_25g/fpga.xdc rename to example/Alveo/fpga_25g/fpga_au280.xdc index 0c65a0b72..6d45dff82 100644 --- a/example/AU280/fpga_25g/fpga.xdc +++ b/example/Alveo/fpga_25g/fpga_au280.xdc @@ -45,8 +45,8 @@ set_false_path -from [get_ports {reset}] set_input_delay 0 [get_ports {reset}] # UART -#set_property -dict {LOC A28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports usb_uart_txd] -#set_property -dict {LOC B33 IOSTANDARD LVCMOS18} [get_ports usb_uart_rxd] +set_property -dict {LOC A28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_txd] +set_property -dict {LOC B33 IOSTANDARD LVCMOS18} [get_ports uart_rxd] #set_false_path -to [get_ports {uart_txd}] #set_output_delay 0 [get_ports {uart_txd}] diff --git a/example/AU280/fpga_25g/rtl/fpga.v b/example/Alveo/fpga_25g/rtl/fpga_au280.v similarity index 55% rename from example/AU280/fpga_25g/rtl/fpga.v rename to example/Alveo/fpga_25g/rtl/fpga_au280.v index 634923269..3527d1e4c 100644 --- a/example/AU280/fpga_25g/rtl/fpga.v +++ b/example/Alveo/fpga_25g/rtl/fpga_au280.v @@ -42,6 +42,12 @@ module fpga ( */ output wire hbm_cattrip, + /* + * UART + */ + output wire uart_txd, + input wire uart_rxd, + /* * Ethernet: QSFP28 */ @@ -162,47 +168,25 @@ sync_reset_125mhz_inst ( assign hbm_cattrip = 1'b0; // XGMII 10G PHY +localparam QSFP_CNT = 2; +localparam CH_CNT = QSFP_CNT*4; + +wire [CH_CNT-1:0] eth_tx_clk; +wire [CH_CNT-1:0] eth_tx_rst; +wire [CH_CNT*64-1:0] eth_txd; +wire [CH_CNT*8-1:0] eth_txc; +wire [CH_CNT-1:0] eth_rx_clk; +wire [CH_CNT-1:0] eth_rx_rst; +wire [CH_CNT*64-1:0] eth_rxd; +wire [CH_CNT*8-1:0] eth_rxc; + +assign clk_156mhz_int = eth_tx_clk[0]; +assign rst_156mhz_int = eth_tx_rst[0]; // QSFP0 assign qsfp0_refclk_oe_b = 1'b0; assign qsfp0_refclk_fs = 1'b1; -wire qsfp0_tx_clk_1_int; -wire qsfp0_tx_rst_1_int; -wire [63:0] qsfp0_txd_1_int; -wire [7:0] qsfp0_txc_1_int; -wire qsfp0_rx_clk_1_int; -wire qsfp0_rx_rst_1_int; -wire [63:0] qsfp0_rxd_1_int; -wire [7:0] qsfp0_rxc_1_int; -wire qsfp0_tx_clk_2_int; -wire qsfp0_tx_rst_2_int; -wire [63:0] qsfp0_txd_2_int; -wire [7:0] qsfp0_txc_2_int; -wire qsfp0_rx_clk_2_int; -wire qsfp0_rx_rst_2_int; -wire [63:0] qsfp0_rxd_2_int; -wire [7:0] qsfp0_rxc_2_int; -wire qsfp0_tx_clk_3_int; -wire qsfp0_tx_rst_3_int; -wire [63:0] qsfp0_txd_3_int; -wire [7:0] qsfp0_txc_3_int; -wire qsfp0_rx_clk_3_int; -wire qsfp0_rx_rst_3_int; -wire [63:0] qsfp0_rxd_3_int; -wire [7:0] qsfp0_rxc_3_int; -wire qsfp0_tx_clk_4_int; -wire qsfp0_tx_rst_4_int; -wire [63:0] qsfp0_txd_4_int; -wire [7:0] qsfp0_txc_4_int; -wire qsfp0_rx_clk_4_int; -wire qsfp0_rx_rst_4_int; -wire [63:0] qsfp0_rxd_4_int; -wire [7:0] qsfp0_rxc_4_int; - -assign clk_156mhz_int = qsfp0_tx_clk_1_int; -assign rst_156mhz_int = qsfp0_tx_rst_1_int; - wire qsfp0_rx_block_lock_1; wire qsfp0_rx_block_lock_2; wire qsfp0_rx_block_lock_3; @@ -264,14 +248,14 @@ qsfp0_phy_inst ( /* * PHY connections */ - .phy_1_tx_clk(qsfp0_tx_clk_1_int), - .phy_1_tx_rst(qsfp0_tx_rst_1_int), - .phy_1_xgmii_txd(qsfp0_txd_1_int), - .phy_1_xgmii_txc(qsfp0_txc_1_int), - .phy_1_rx_clk(qsfp0_rx_clk_1_int), - .phy_1_rx_rst(qsfp0_rx_rst_1_int), - .phy_1_xgmii_rxd(qsfp0_rxd_1_int), - .phy_1_xgmii_rxc(qsfp0_rxc_1_int), + .phy_1_tx_clk(eth_tx_clk[0*4+0 +: 1]), + .phy_1_tx_rst(eth_tx_rst[0*4+0 +: 1]), + .phy_1_xgmii_txd(eth_txd[(0*4+0)*64 +: 64]), + .phy_1_xgmii_txc(eth_txc[(0*4+0)*8 +: 8]), + .phy_1_rx_clk(eth_rx_clk[0*4+0 +: 1]), + .phy_1_rx_rst(eth_rx_rst[0*4+0 +: 1]), + .phy_1_xgmii_rxd(eth_rxd[(0*4+0)*64 +: 64]), + .phy_1_xgmii_rxc(eth_rxc[(0*4+0)*8 +: 8]), .phy_1_tx_bad_block(), .phy_1_rx_error_count(), .phy_1_rx_bad_block(), @@ -281,14 +265,14 @@ qsfp0_phy_inst ( .phy_1_cfg_tx_prbs31_enable(1'b0), .phy_1_cfg_rx_prbs31_enable(1'b0), - .phy_2_tx_clk(qsfp0_tx_clk_2_int), - .phy_2_tx_rst(qsfp0_tx_rst_2_int), - .phy_2_xgmii_txd(qsfp0_txd_2_int), - .phy_2_xgmii_txc(qsfp0_txc_2_int), - .phy_2_rx_clk(qsfp0_rx_clk_2_int), - .phy_2_rx_rst(qsfp0_rx_rst_2_int), - .phy_2_xgmii_rxd(qsfp0_rxd_2_int), - .phy_2_xgmii_rxc(qsfp0_rxc_2_int), + .phy_2_tx_clk(eth_tx_clk[0*4+1 +: 1]), + .phy_2_tx_rst(eth_tx_rst[0*4+1 +: 1]), + .phy_2_xgmii_txd(eth_txd[(0*4+1)*64 +: 64]), + .phy_2_xgmii_txc(eth_txc[(0*4+1)*8 +: 8]), + .phy_2_rx_clk(eth_rx_clk[0*4+1 +: 1]), + .phy_2_rx_rst(eth_rx_rst[0*4+1 +: 1]), + .phy_2_xgmii_rxd(eth_rxd[(0*4+1)*64 +: 64]), + .phy_2_xgmii_rxc(eth_rxc[(0*4+1)*8 +: 8]), .phy_2_tx_bad_block(), .phy_2_rx_error_count(), .phy_2_rx_bad_block(), @@ -298,14 +282,14 @@ qsfp0_phy_inst ( .phy_2_cfg_tx_prbs31_enable(1'b0), .phy_2_cfg_rx_prbs31_enable(1'b0), - .phy_3_tx_clk(qsfp0_tx_clk_3_int), - .phy_3_tx_rst(qsfp0_tx_rst_3_int), - .phy_3_xgmii_txd(qsfp0_txd_3_int), - .phy_3_xgmii_txc(qsfp0_txc_3_int), - .phy_3_rx_clk(qsfp0_rx_clk_3_int), - .phy_3_rx_rst(qsfp0_rx_rst_3_int), - .phy_3_xgmii_rxd(qsfp0_rxd_3_int), - .phy_3_xgmii_rxc(qsfp0_rxc_3_int), + .phy_3_tx_clk(eth_tx_clk[0*4+2 +: 1]), + .phy_3_tx_rst(eth_tx_rst[0*4+2 +: 1]), + .phy_3_xgmii_txd(eth_txd[(0*4+2)*64 +: 64]), + .phy_3_xgmii_txc(eth_txc[(0*4+2)*8 +: 8]), + .phy_3_rx_clk(eth_rx_clk[0*4+2 +: 1]), + .phy_3_rx_rst(eth_rx_rst[0*4+2 +: 1]), + .phy_3_xgmii_rxd(eth_rxd[(0*4+2)*64 +: 64]), + .phy_3_xgmii_rxc(eth_rxc[(0*4+2)*8 +: 8]), .phy_3_tx_bad_block(), .phy_3_rx_error_count(), .phy_3_rx_bad_block(), @@ -315,14 +299,14 @@ qsfp0_phy_inst ( .phy_3_cfg_tx_prbs31_enable(1'b0), .phy_3_cfg_rx_prbs31_enable(1'b0), - .phy_4_tx_clk(qsfp0_tx_clk_4_int), - .phy_4_tx_rst(qsfp0_tx_rst_4_int), - .phy_4_xgmii_txd(qsfp0_txd_4_int), - .phy_4_xgmii_txc(qsfp0_txc_4_int), - .phy_4_rx_clk(qsfp0_rx_clk_4_int), - .phy_4_rx_rst(qsfp0_rx_rst_4_int), - .phy_4_xgmii_rxd(qsfp0_rxd_4_int), - .phy_4_xgmii_rxc(qsfp0_rxc_4_int), + .phy_4_tx_clk(eth_tx_clk[0*4+3 +: 1]), + .phy_4_tx_rst(eth_tx_rst[0*4+3 +: 1]), + .phy_4_xgmii_txd(eth_txd[(0*4+3)*64 +: 64]), + .phy_4_xgmii_txc(eth_txc[(0*4+3)*8 +: 8]), + .phy_4_rx_clk(eth_rx_clk[0*4+3 +: 1]), + .phy_4_rx_rst(eth_rx_rst[0*4+3 +: 1]), + .phy_4_xgmii_rxd(eth_rxd[(0*4+3)*64 +: 64]), + .phy_4_xgmii_rxc(eth_rxc[(0*4+3)*8 +: 8]), .phy_4_tx_bad_block(), .phy_4_rx_error_count(), .phy_4_rx_bad_block(), @@ -337,39 +321,6 @@ qsfp0_phy_inst ( assign qsfp1_refclk_oe_b = 1'b0; assign qsfp1_refclk_fs = 1'b1; -wire qsfp1_tx_clk_1_int; -wire qsfp1_tx_rst_1_int; -wire [63:0] qsfp1_txd_1_int; -wire [7:0] qsfp1_txc_1_int; -wire qsfp1_rx_clk_1_int; -wire qsfp1_rx_rst_1_int; -wire [63:0] qsfp1_rxd_1_int; -wire [7:0] qsfp1_rxc_1_int; -wire qsfp1_tx_clk_2_int; -wire qsfp1_tx_rst_2_int; -wire [63:0] qsfp1_txd_2_int; -wire [7:0] qsfp1_txc_2_int; -wire qsfp1_rx_clk_2_int; -wire qsfp1_rx_rst_2_int; -wire [63:0] qsfp1_rxd_2_int; -wire [7:0] qsfp1_rxc_2_int; -wire qsfp1_tx_clk_3_int; -wire qsfp1_tx_rst_3_int; -wire [63:0] qsfp1_txd_3_int; -wire [7:0] qsfp1_txc_3_int; -wire qsfp1_rx_clk_3_int; -wire qsfp1_rx_rst_3_int; -wire [63:0] qsfp1_rxd_3_int; -wire [7:0] qsfp1_rxc_3_int; -wire qsfp1_tx_clk_4_int; -wire qsfp1_tx_rst_4_int; -wire [63:0] qsfp1_txd_4_int; -wire [7:0] qsfp1_txc_4_int; -wire qsfp1_rx_clk_4_int; -wire qsfp1_rx_rst_4_int; -wire [63:0] qsfp1_rxd_4_int; -wire [7:0] qsfp1_rxc_4_int; - wire qsfp1_rx_block_lock_1; wire qsfp1_rx_block_lock_2; wire qsfp1_rx_block_lock_3; @@ -415,14 +366,14 @@ qsfp1_phy_inst ( /* * PHY connections */ - .phy_1_tx_clk(qsfp1_tx_clk_1_int), - .phy_1_tx_rst(qsfp1_tx_rst_1_int), - .phy_1_xgmii_txd(qsfp1_txd_1_int), - .phy_1_xgmii_txc(qsfp1_txc_1_int), - .phy_1_rx_clk(qsfp1_rx_clk_1_int), - .phy_1_rx_rst(qsfp1_rx_rst_1_int), - .phy_1_xgmii_rxd(qsfp1_rxd_1_int), - .phy_1_xgmii_rxc(qsfp1_rxc_1_int), + .phy_1_tx_clk(eth_tx_clk[1*4+0 +: 1]), + .phy_1_tx_rst(eth_tx_rst[1*4+0 +: 1]), + .phy_1_xgmii_txd(eth_txd[(1*4+0)*64 +: 64]), + .phy_1_xgmii_txc(eth_txc[(1*4+0)*8 +: 8]), + .phy_1_rx_clk(eth_rx_clk[1*4+0 +: 1]), + .phy_1_rx_rst(eth_rx_rst[1*4+0 +: 1]), + .phy_1_xgmii_rxd(eth_rxd[(1*4+0)*64 +: 64]), + .phy_1_xgmii_rxc(eth_rxc[(1*4+0)*8 +: 8]), .phy_1_tx_bad_block(), .phy_1_rx_error_count(), .phy_1_rx_bad_block(), @@ -432,14 +383,14 @@ qsfp1_phy_inst ( .phy_1_cfg_tx_prbs31_enable(1'b0), .phy_1_cfg_rx_prbs31_enable(1'b0), - .phy_2_tx_clk(qsfp1_tx_clk_2_int), - .phy_2_tx_rst(qsfp1_tx_rst_2_int), - .phy_2_xgmii_txd(qsfp1_txd_2_int), - .phy_2_xgmii_txc(qsfp1_txc_2_int), - .phy_2_rx_clk(qsfp1_rx_clk_2_int), - .phy_2_rx_rst(qsfp1_rx_rst_2_int), - .phy_2_xgmii_rxd(qsfp1_rxd_2_int), - .phy_2_xgmii_rxc(qsfp1_rxc_2_int), + .phy_2_tx_clk(eth_tx_clk[1*4+1 +: 1]), + .phy_2_tx_rst(eth_tx_rst[1*4+1 +: 1]), + .phy_2_xgmii_txd(eth_txd[(1*4+1)*64 +: 64]), + .phy_2_xgmii_txc(eth_txc[(1*4+1)*8 +: 8]), + .phy_2_rx_clk(eth_rx_clk[1*4+1 +: 1]), + .phy_2_rx_rst(eth_rx_rst[1*4+1 +: 1]), + .phy_2_xgmii_rxd(eth_rxd[(1*4+1)*64 +: 64]), + .phy_2_xgmii_rxc(eth_rxc[(1*4+1)*8 +: 8]), .phy_2_tx_bad_block(), .phy_2_rx_error_count(), .phy_2_rx_bad_block(), @@ -449,14 +400,14 @@ qsfp1_phy_inst ( .phy_2_cfg_tx_prbs31_enable(1'b0), .phy_2_cfg_rx_prbs31_enable(1'b0), - .phy_3_tx_clk(qsfp1_tx_clk_3_int), - .phy_3_tx_rst(qsfp1_tx_rst_3_int), - .phy_3_xgmii_txd(qsfp1_txd_3_int), - .phy_3_xgmii_txc(qsfp1_txc_3_int), - .phy_3_rx_clk(qsfp1_rx_clk_3_int), - .phy_3_rx_rst(qsfp1_rx_rst_3_int), - .phy_3_xgmii_rxd(qsfp1_rxd_3_int), - .phy_3_xgmii_rxc(qsfp1_rxc_3_int), + .phy_3_tx_clk(eth_tx_clk[1*4+2 +: 1]), + .phy_3_tx_rst(eth_tx_rst[1*4+2 +: 1]), + .phy_3_xgmii_txd(eth_txd[(1*4+2)*64 +: 64]), + .phy_3_xgmii_txc(eth_txc[(1*4+2)*8 +: 8]), + .phy_3_rx_clk(eth_rx_clk[1*4+2 +: 1]), + .phy_3_rx_rst(eth_rx_rst[1*4+2 +: 1]), + .phy_3_xgmii_rxd(eth_rxd[(1*4+2)*64 +: 64]), + .phy_3_xgmii_rxc(eth_rxc[(1*4+2)*8 +: 8]), .phy_3_tx_bad_block(), .phy_3_rx_error_count(), .phy_3_rx_bad_block(), @@ -466,14 +417,14 @@ qsfp1_phy_inst ( .phy_3_cfg_tx_prbs31_enable(1'b0), .phy_3_cfg_rx_prbs31_enable(1'b0), - .phy_4_tx_clk(qsfp1_tx_clk_4_int), - .phy_4_tx_rst(qsfp1_tx_rst_4_int), - .phy_4_xgmii_txd(qsfp1_txd_4_int), - .phy_4_xgmii_txc(qsfp1_txc_4_int), - .phy_4_rx_clk(qsfp1_rx_clk_4_int), - .phy_4_rx_rst(qsfp1_rx_rst_4_int), - .phy_4_xgmii_rxd(qsfp1_rxd_4_int), - .phy_4_xgmii_rxc(qsfp1_rxc_4_int), + .phy_4_tx_clk(eth_tx_clk[1*4+3 +: 1]), + .phy_4_tx_rst(eth_tx_rst[1*4+3 +: 1]), + .phy_4_xgmii_txd(eth_txd[(1*4+3)*64 +: 64]), + .phy_4_xgmii_txc(eth_txc[(1*4+3)*8 +: 8]), + .phy_4_rx_clk(eth_rx_clk[1*4+3 +: 1]), + .phy_4_rx_rst(eth_rx_rst[1*4+3 +: 1]), + .phy_4_xgmii_rxd(eth_rxd[(1*4+3)*64 +: 64]), + .phy_4_xgmii_rxc(eth_rxc[(1*4+3)*8 +: 8]), .phy_4_tx_bad_block(), .phy_4_rx_error_count(), .phy_4_rx_bad_block(), @@ -484,7 +435,11 @@ qsfp1_phy_inst ( .phy_4_cfg_rx_prbs31_enable(1'b0) ); -fpga_core +fpga_core #( + .UART_CNT(1), + .QSFP_CNT(QSFP_CNT), + .CH_CNT(CH_CNT) +) core_inst ( /* * Clock: 156.25 MHz @@ -492,73 +447,33 @@ core_inst ( */ .clk(clk_156mhz_int), .rst(rst_156mhz_int), + + /* + * GPIO + */ + .sw(0), + .led(), + .qsfp_led_act(), + .qsfp_led_stat_g(), + .qsfp_led_stat_y(), + + /* + * UART + */ + .uart_txd(uart_txd), + .uart_rxd(uart_rxd), + /* * Ethernet: QSFP28 */ - .qsfp0_tx_clk_1(qsfp0_tx_clk_1_int), - .qsfp0_tx_rst_1(qsfp0_tx_rst_1_int), - .qsfp0_txd_1(qsfp0_txd_1_int), - .qsfp0_txc_1(qsfp0_txc_1_int), - .qsfp0_rx_clk_1(qsfp0_rx_clk_1_int), - .qsfp0_rx_rst_1(qsfp0_rx_rst_1_int), - .qsfp0_rxd_1(qsfp0_rxd_1_int), - .qsfp0_rxc_1(qsfp0_rxc_1_int), - .qsfp0_tx_clk_2(qsfp0_tx_clk_2_int), - .qsfp0_tx_rst_2(qsfp0_tx_rst_2_int), - .qsfp0_txd_2(qsfp0_txd_2_int), - .qsfp0_txc_2(qsfp0_txc_2_int), - .qsfp0_rx_clk_2(qsfp0_rx_clk_2_int), - .qsfp0_rx_rst_2(qsfp0_rx_rst_2_int), - .qsfp0_rxd_2(qsfp0_rxd_2_int), - .qsfp0_rxc_2(qsfp0_rxc_2_int), - .qsfp0_tx_clk_3(qsfp0_tx_clk_3_int), - .qsfp0_tx_rst_3(qsfp0_tx_rst_3_int), - .qsfp0_txd_3(qsfp0_txd_3_int), - .qsfp0_txc_3(qsfp0_txc_3_int), - .qsfp0_rx_clk_3(qsfp0_rx_clk_3_int), - .qsfp0_rx_rst_3(qsfp0_rx_rst_3_int), - .qsfp0_rxd_3(qsfp0_rxd_3_int), - .qsfp0_rxc_3(qsfp0_rxc_3_int), - .qsfp0_tx_clk_4(qsfp0_tx_clk_4_int), - .qsfp0_tx_rst_4(qsfp0_tx_rst_4_int), - .qsfp0_txd_4(qsfp0_txd_4_int), - .qsfp0_txc_4(qsfp0_txc_4_int), - .qsfp0_rx_clk_4(qsfp0_rx_clk_4_int), - .qsfp0_rx_rst_4(qsfp0_rx_rst_4_int), - .qsfp0_rxd_4(qsfp0_rxd_4_int), - .qsfp0_rxc_4(qsfp0_rxc_4_int), - .qsfp1_tx_clk_1(qsfp1_tx_clk_1_int), - .qsfp1_tx_rst_1(qsfp1_tx_rst_1_int), - .qsfp1_txd_1(qsfp1_txd_1_int), - .qsfp1_txc_1(qsfp1_txc_1_int), - .qsfp1_rx_clk_1(qsfp1_rx_clk_1_int), - .qsfp1_rx_rst_1(qsfp1_rx_rst_1_int), - .qsfp1_rxd_1(qsfp1_rxd_1_int), - .qsfp1_rxc_1(qsfp1_rxc_1_int), - .qsfp1_tx_clk_2(qsfp1_tx_clk_2_int), - .qsfp1_tx_rst_2(qsfp1_tx_rst_2_int), - .qsfp1_txd_2(qsfp1_txd_2_int), - .qsfp1_txc_2(qsfp1_txc_2_int), - .qsfp1_rx_clk_2(qsfp1_rx_clk_2_int), - .qsfp1_rx_rst_2(qsfp1_rx_rst_2_int), - .qsfp1_rxd_2(qsfp1_rxd_2_int), - .qsfp1_rxc_2(qsfp1_rxc_2_int), - .qsfp1_tx_clk_3(qsfp1_tx_clk_3_int), - .qsfp1_tx_rst_3(qsfp1_tx_rst_3_int), - .qsfp1_txd_3(qsfp1_txd_3_int), - .qsfp1_txc_3(qsfp1_txc_3_int), - .qsfp1_rx_clk_3(qsfp1_rx_clk_3_int), - .qsfp1_rx_rst_3(qsfp1_rx_rst_3_int), - .qsfp1_rxd_3(qsfp1_rxd_3_int), - .qsfp1_rxc_3(qsfp1_rxc_3_int), - .qsfp1_tx_clk_4(qsfp1_tx_clk_4_int), - .qsfp1_tx_rst_4(qsfp1_tx_rst_4_int), - .qsfp1_txd_4(qsfp1_txd_4_int), - .qsfp1_txc_4(qsfp1_txc_4_int), - .qsfp1_rx_clk_4(qsfp1_rx_clk_4_int), - .qsfp1_rx_rst_4(qsfp1_rx_rst_4_int), - .qsfp1_rxd_4(qsfp1_rxd_4_int), - .qsfp1_rxc_4(qsfp1_rxc_4_int) + .eth_tx_clk(eth_tx_clk), + .eth_tx_rst(eth_tx_rst), + .eth_txd(eth_txd), + .eth_txc(eth_txc), + .eth_rx_clk(eth_rx_clk), + .eth_rx_rst(eth_rx_rst), + .eth_rxd(eth_rxd), + .eth_rxc(eth_rxc) ); endmodule