From b1177eb4ed7884ce4a404c41638c0ccce1e6aac6 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Fri, 21 Jul 2023 18:17:26 -0700 Subject: [PATCH] Rename HXT100G to HTG-640 Signed-off-by: Alex Forencich --- README.md | 2 +- example/{HXT100G => HTG640}/fpga/Makefile | 0 example/{HXT100G => HTG640}/fpga/README.md | 6 +++--- example/{HXT100G => HTG640}/fpga/common/xilinx.mk | 0 example/{HXT100G => HTG640}/fpga/coregen/Makefile | 0 example/{HXT100G => HTG640}/fpga/coregen/coregen.cgp | 0 .../fpga/coregen/ten_gig_eth_pcs_pma_v2_6.xco | 0 .../fpga/coregen/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper.xco | 0 example/{HXT100G => HTG640}/fpga/fpga.ucf | 0 example/{HXT100G => HTG640}/fpga/fpga/Makefile | 0 example/{HXT100G => HTG640}/fpga/lib/eth | 0 example/{HXT100G => HTG640}/fpga/rtl/debounce_switch.v | 0 example/{HXT100G => HTG640}/fpga/rtl/eth_gth_phy_quad.v | 0 example/{HXT100G => HTG640}/fpga/rtl/fpga.v | 0 example/{HXT100G => HTG640}/fpga/rtl/fpga_core.v | 0 example/{HXT100G => HTG640}/fpga/rtl/gth_i2c_init.v | 0 example/{HXT100G => HTG640}/fpga/rtl/i2c_master.v | 0 example/{HXT100G => HTG640}/fpga/rtl/sync_signal.v | 0 example/{HXT100G => HTG640}/fpga/tb/fpga_core/Makefile | 0 .../{HXT100G => HTG640}/fpga/tb/fpga_core/test_fpga_core.py | 0 example/{HXT100G => HTG640}/fpga_cxpt16/Makefile | 0 example/{HXT100G => HTG640}/fpga_cxpt16/README.md | 4 ++-- example/{HXT100G => HTG640}/fpga_cxpt16/common/xilinx.mk | 0 example/{HXT100G => HTG640}/fpga_cxpt16/coregen/Makefile | 0 example/{HXT100G => HTG640}/fpga_cxpt16/coregen/coregen.cgp | 0 .../fpga_cxpt16/coregen/ten_gig_eth_pcs_pma_v2_6.xco | 0 .../coregen/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper.xco | 0 example/{HXT100G => HTG640}/fpga_cxpt16/fpga.ucf | 0 example/{HXT100G => HTG640}/fpga_cxpt16/fpga/Makefile | 0 example/{HXT100G => HTG640}/fpga_cxpt16/lib/eth | 0 .../{HXT100G => HTG640}/fpga_cxpt16/rtl/debounce_switch.v | 0 .../{HXT100G => HTG640}/fpga_cxpt16/rtl/eth_gth_phy_quad.v | 0 example/{HXT100G => HTG640}/fpga_cxpt16/rtl/fpga.v | 0 example/{HXT100G => HTG640}/fpga_cxpt16/rtl/fpga_core.v | 0 example/{HXT100G => HTG640}/fpga_cxpt16/rtl/gth_i2c_init.v | 0 example/{HXT100G => HTG640}/fpga_cxpt16/rtl/i2c_master.v | 0 example/{HXT100G => HTG640}/fpga_cxpt16/rtl/sync_signal.v | 0 .../{HXT100G => HTG640}/fpga_cxpt16/tb/fpga_core/Makefile | 0 .../fpga_cxpt16/tb/fpga_core/test_fpga_core.py | 0 39 files changed, 6 insertions(+), 6 deletions(-) rename example/{HXT100G => HTG640}/fpga/Makefile (100%) rename example/{HXT100G => HTG640}/fpga/README.md (77%) rename example/{HXT100G => HTG640}/fpga/common/xilinx.mk (100%) rename example/{HXT100G => HTG640}/fpga/coregen/Makefile (100%) rename example/{HXT100G => HTG640}/fpga/coregen/coregen.cgp (100%) rename example/{HXT100G => HTG640}/fpga/coregen/ten_gig_eth_pcs_pma_v2_6.xco (100%) rename example/{HXT100G => HTG640}/fpga/coregen/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper.xco (100%) rename example/{HXT100G => HTG640}/fpga/fpga.ucf (100%) rename example/{HXT100G => HTG640}/fpga/fpga/Makefile (100%) rename example/{HXT100G => HTG640}/fpga/lib/eth (100%) rename example/{HXT100G => HTG640}/fpga/rtl/debounce_switch.v (100%) rename example/{HXT100G => HTG640}/fpga/rtl/eth_gth_phy_quad.v (100%) rename example/{HXT100G => HTG640}/fpga/rtl/fpga.v (100%) rename example/{HXT100G => HTG640}/fpga/rtl/fpga_core.v (100%) rename example/{HXT100G => HTG640}/fpga/rtl/gth_i2c_init.v (100%) rename example/{HXT100G => HTG640}/fpga/rtl/i2c_master.v (100%) rename example/{HXT100G => HTG640}/fpga/rtl/sync_signal.v (100%) rename example/{HXT100G => HTG640}/fpga/tb/fpga_core/Makefile (100%) rename example/{HXT100G => HTG640}/fpga/tb/fpga_core/test_fpga_core.py (100%) rename example/{HXT100G => HTG640}/fpga_cxpt16/Makefile (100%) rename example/{HXT100G => HTG640}/fpga_cxpt16/README.md (87%) rename example/{HXT100G => HTG640}/fpga_cxpt16/common/xilinx.mk (100%) rename example/{HXT100G => HTG640}/fpga_cxpt16/coregen/Makefile (100%) rename example/{HXT100G => HTG640}/fpga_cxpt16/coregen/coregen.cgp (100%) rename example/{HXT100G => HTG640}/fpga_cxpt16/coregen/ten_gig_eth_pcs_pma_v2_6.xco (100%) rename example/{HXT100G => HTG640}/fpga_cxpt16/coregen/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper.xco (100%) rename example/{HXT100G => HTG640}/fpga_cxpt16/fpga.ucf (100%) rename example/{HXT100G => HTG640}/fpga_cxpt16/fpga/Makefile (100%) rename example/{HXT100G => HTG640}/fpga_cxpt16/lib/eth (100%) rename example/{HXT100G => HTG640}/fpga_cxpt16/rtl/debounce_switch.v (100%) rename example/{HXT100G => HTG640}/fpga_cxpt16/rtl/eth_gth_phy_quad.v (100%) rename example/{HXT100G => HTG640}/fpga_cxpt16/rtl/fpga.v (100%) rename example/{HXT100G => HTG640}/fpga_cxpt16/rtl/fpga_core.v (100%) rename example/{HXT100G => HTG640}/fpga_cxpt16/rtl/gth_i2c_init.v (100%) rename example/{HXT100G => HTG640}/fpga_cxpt16/rtl/i2c_master.v (100%) rename example/{HXT100G => HTG640}/fpga_cxpt16/rtl/sync_signal.v (100%) rename example/{HXT100G => HTG640}/fpga_cxpt16/tb/fpga_core/Makefile (100%) rename example/{HXT100G => HTG640}/fpga_cxpt16/tb/fpga_core/test_fpga_core.py (100%) diff --git a/README.md b/README.md index b7f6e64aa..0ade5cedf 100644 --- a/README.md +++ b/README.md @@ -46,7 +46,7 @@ following boards: * Exablaze ExaNIC X10 (Xilinx Kintex UltraScale XCKU035) * Exablaze ExaNIC X25 (Xilinx Kintex UltraScale+ XCKU3P) * HiTech Global HTG-9200 (Xilinx UltraScale+ XCVU9P) -* HiTech Global HTG-V6HXT-100GIG-565 (Xilinx Virtex 6 XC6VHX565T) +* HiTech Global HTG-640 (HTG-V6HXT-100GIG-565) (Xilinx Virtex 6 XC6VHX565T) * Silicom fb2CG@KU15P (Xilinx Kintex UltraScale+ XCKU15P) * Xilinx KC705 (Xilinx Kintex 7 XC7K325T) * Xilinx ML605 (Xilinx Virtex 6 XC6VLX240T) diff --git a/example/HXT100G/fpga/Makefile b/example/HTG640/fpga/Makefile similarity index 100% rename from example/HXT100G/fpga/Makefile rename to example/HTG640/fpga/Makefile diff --git a/example/HXT100G/fpga/README.md b/example/HTG640/fpga/README.md similarity index 77% rename from example/HXT100G/fpga/README.md rename to example/HTG640/fpga/README.md index 2a46b7101..b66a59bf5 100644 --- a/example/HXT100G/fpga/README.md +++ b/example/HTG640/fpga/README.md @@ -1,8 +1,8 @@ -# Verilog Ethernet HXT100G Example Design +# Verilog Ethernet HTG-640 Example Design ## Introduction -This example design targets the HiTech Global HXT100G FPGA board. +This example design targets the HiTech Global HTG-640 (HTG-V6HXT-100GIG-565) FPGA board. The design by default listens to UDP port 1234 at IP address 192.168.1.128 and will echo back any packets received. The design will also respond correctly @@ -18,7 +18,7 @@ in PATH. ## How to test -Run make program to program the HXT100G board with the Xilinx Impact software. +Run make program to program the HTG-640 board with the Xilinx Impact software. Then run netcat -u 192.168.1.128 1234 diff --git a/example/HXT100G/fpga/common/xilinx.mk b/example/HTG640/fpga/common/xilinx.mk similarity index 100% rename from example/HXT100G/fpga/common/xilinx.mk rename to example/HTG640/fpga/common/xilinx.mk diff --git a/example/HXT100G/fpga/coregen/Makefile b/example/HTG640/fpga/coregen/Makefile similarity index 100% rename from example/HXT100G/fpga/coregen/Makefile rename to example/HTG640/fpga/coregen/Makefile diff --git a/example/HXT100G/fpga/coregen/coregen.cgp b/example/HTG640/fpga/coregen/coregen.cgp similarity index 100% rename from example/HXT100G/fpga/coregen/coregen.cgp rename to example/HTG640/fpga/coregen/coregen.cgp diff --git a/example/HXT100G/fpga/coregen/ten_gig_eth_pcs_pma_v2_6.xco b/example/HTG640/fpga/coregen/ten_gig_eth_pcs_pma_v2_6.xco similarity index 100% rename from example/HXT100G/fpga/coregen/ten_gig_eth_pcs_pma_v2_6.xco rename to example/HTG640/fpga/coregen/ten_gig_eth_pcs_pma_v2_6.xco diff --git a/example/HXT100G/fpga/coregen/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper.xco b/example/HTG640/fpga/coregen/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper.xco similarity index 100% rename from example/HXT100G/fpga/coregen/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper.xco rename to example/HTG640/fpga/coregen/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper.xco diff --git a/example/HXT100G/fpga/fpga.ucf b/example/HTG640/fpga/fpga.ucf similarity index 100% rename from example/HXT100G/fpga/fpga.ucf rename to example/HTG640/fpga/fpga.ucf diff --git a/example/HXT100G/fpga/fpga/Makefile b/example/HTG640/fpga/fpga/Makefile similarity index 100% rename from example/HXT100G/fpga/fpga/Makefile rename to example/HTG640/fpga/fpga/Makefile diff --git a/example/HXT100G/fpga/lib/eth b/example/HTG640/fpga/lib/eth similarity index 100% rename from example/HXT100G/fpga/lib/eth rename to example/HTG640/fpga/lib/eth diff --git a/example/HXT100G/fpga/rtl/debounce_switch.v b/example/HTG640/fpga/rtl/debounce_switch.v similarity index 100% rename from example/HXT100G/fpga/rtl/debounce_switch.v rename to example/HTG640/fpga/rtl/debounce_switch.v diff --git a/example/HXT100G/fpga/rtl/eth_gth_phy_quad.v b/example/HTG640/fpga/rtl/eth_gth_phy_quad.v similarity index 100% rename from example/HXT100G/fpga/rtl/eth_gth_phy_quad.v rename to example/HTG640/fpga/rtl/eth_gth_phy_quad.v diff --git a/example/HXT100G/fpga/rtl/fpga.v b/example/HTG640/fpga/rtl/fpga.v similarity index 100% rename from example/HXT100G/fpga/rtl/fpga.v rename to example/HTG640/fpga/rtl/fpga.v diff --git a/example/HXT100G/fpga/rtl/fpga_core.v b/example/HTG640/fpga/rtl/fpga_core.v similarity index 100% rename from example/HXT100G/fpga/rtl/fpga_core.v rename to example/HTG640/fpga/rtl/fpga_core.v diff --git a/example/HXT100G/fpga/rtl/gth_i2c_init.v b/example/HTG640/fpga/rtl/gth_i2c_init.v similarity index 100% rename from example/HXT100G/fpga/rtl/gth_i2c_init.v rename to example/HTG640/fpga/rtl/gth_i2c_init.v diff --git a/example/HXT100G/fpga/rtl/i2c_master.v b/example/HTG640/fpga/rtl/i2c_master.v similarity index 100% rename from example/HXT100G/fpga/rtl/i2c_master.v rename to example/HTG640/fpga/rtl/i2c_master.v diff --git a/example/HXT100G/fpga/rtl/sync_signal.v b/example/HTG640/fpga/rtl/sync_signal.v similarity index 100% rename from example/HXT100G/fpga/rtl/sync_signal.v rename to example/HTG640/fpga/rtl/sync_signal.v diff --git a/example/HXT100G/fpga/tb/fpga_core/Makefile b/example/HTG640/fpga/tb/fpga_core/Makefile similarity index 100% rename from example/HXT100G/fpga/tb/fpga_core/Makefile rename to example/HTG640/fpga/tb/fpga_core/Makefile diff --git a/example/HXT100G/fpga/tb/fpga_core/test_fpga_core.py b/example/HTG640/fpga/tb/fpga_core/test_fpga_core.py similarity index 100% rename from example/HXT100G/fpga/tb/fpga_core/test_fpga_core.py rename to example/HTG640/fpga/tb/fpga_core/test_fpga_core.py diff --git a/example/HXT100G/fpga_cxpt16/Makefile b/example/HTG640/fpga_cxpt16/Makefile similarity index 100% rename from example/HXT100G/fpga_cxpt16/Makefile rename to example/HTG640/fpga_cxpt16/Makefile diff --git a/example/HXT100G/fpga_cxpt16/README.md b/example/HTG640/fpga_cxpt16/README.md similarity index 87% rename from example/HXT100G/fpga_cxpt16/README.md rename to example/HTG640/fpga_cxpt16/README.md index c31e812af..806220684 100644 --- a/example/HXT100G/fpga_cxpt16/README.md +++ b/example/HTG640/fpga_cxpt16/README.md @@ -1,8 +1,8 @@ -# Verilog Ethernet HXT100G Crosspoint Switch Design +# Verilog Ethernet HTG-640 Crosspoint Switch Design ## Introduction -This design targets the HiTech Global HXT100G FPGA board. +This design targets the HiTech Global HTG-640 (HTG-V6HXT-100GIG-565) FPGA board. The design forms a 16x16 crosspoint switch for 10G Ethernet. It is capable of connecting any output port to any input port based on configuration frames diff --git a/example/HXT100G/fpga_cxpt16/common/xilinx.mk b/example/HTG640/fpga_cxpt16/common/xilinx.mk similarity index 100% rename from example/HXT100G/fpga_cxpt16/common/xilinx.mk rename to example/HTG640/fpga_cxpt16/common/xilinx.mk diff --git a/example/HXT100G/fpga_cxpt16/coregen/Makefile b/example/HTG640/fpga_cxpt16/coregen/Makefile similarity index 100% rename from example/HXT100G/fpga_cxpt16/coregen/Makefile rename to example/HTG640/fpga_cxpt16/coregen/Makefile diff --git a/example/HXT100G/fpga_cxpt16/coregen/coregen.cgp b/example/HTG640/fpga_cxpt16/coregen/coregen.cgp similarity index 100% rename from example/HXT100G/fpga_cxpt16/coregen/coregen.cgp rename to example/HTG640/fpga_cxpt16/coregen/coregen.cgp diff --git a/example/HXT100G/fpga_cxpt16/coregen/ten_gig_eth_pcs_pma_v2_6.xco b/example/HTG640/fpga_cxpt16/coregen/ten_gig_eth_pcs_pma_v2_6.xco similarity index 100% rename from example/HXT100G/fpga_cxpt16/coregen/ten_gig_eth_pcs_pma_v2_6.xco rename to example/HTG640/fpga_cxpt16/coregen/ten_gig_eth_pcs_pma_v2_6.xco diff --git a/example/HXT100G/fpga_cxpt16/coregen/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper.xco b/example/HTG640/fpga_cxpt16/coregen/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper.xco similarity index 100% rename from example/HXT100G/fpga_cxpt16/coregen/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper.xco rename to example/HTG640/fpga_cxpt16/coregen/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper.xco diff --git a/example/HXT100G/fpga_cxpt16/fpga.ucf b/example/HTG640/fpga_cxpt16/fpga.ucf similarity index 100% rename from example/HXT100G/fpga_cxpt16/fpga.ucf rename to example/HTG640/fpga_cxpt16/fpga.ucf diff --git a/example/HXT100G/fpga_cxpt16/fpga/Makefile b/example/HTG640/fpga_cxpt16/fpga/Makefile similarity index 100% rename from example/HXT100G/fpga_cxpt16/fpga/Makefile rename to example/HTG640/fpga_cxpt16/fpga/Makefile diff --git a/example/HXT100G/fpga_cxpt16/lib/eth b/example/HTG640/fpga_cxpt16/lib/eth similarity index 100% rename from example/HXT100G/fpga_cxpt16/lib/eth rename to example/HTG640/fpga_cxpt16/lib/eth diff --git a/example/HXT100G/fpga_cxpt16/rtl/debounce_switch.v b/example/HTG640/fpga_cxpt16/rtl/debounce_switch.v similarity index 100% rename from example/HXT100G/fpga_cxpt16/rtl/debounce_switch.v rename to example/HTG640/fpga_cxpt16/rtl/debounce_switch.v diff --git a/example/HXT100G/fpga_cxpt16/rtl/eth_gth_phy_quad.v b/example/HTG640/fpga_cxpt16/rtl/eth_gth_phy_quad.v similarity index 100% rename from example/HXT100G/fpga_cxpt16/rtl/eth_gth_phy_quad.v rename to example/HTG640/fpga_cxpt16/rtl/eth_gth_phy_quad.v diff --git a/example/HXT100G/fpga_cxpt16/rtl/fpga.v b/example/HTG640/fpga_cxpt16/rtl/fpga.v similarity index 100% rename from example/HXT100G/fpga_cxpt16/rtl/fpga.v rename to example/HTG640/fpga_cxpt16/rtl/fpga.v diff --git a/example/HXT100G/fpga_cxpt16/rtl/fpga_core.v b/example/HTG640/fpga_cxpt16/rtl/fpga_core.v similarity index 100% rename from example/HXT100G/fpga_cxpt16/rtl/fpga_core.v rename to example/HTG640/fpga_cxpt16/rtl/fpga_core.v diff --git a/example/HXT100G/fpga_cxpt16/rtl/gth_i2c_init.v b/example/HTG640/fpga_cxpt16/rtl/gth_i2c_init.v similarity index 100% rename from example/HXT100G/fpga_cxpt16/rtl/gth_i2c_init.v rename to example/HTG640/fpga_cxpt16/rtl/gth_i2c_init.v diff --git a/example/HXT100G/fpga_cxpt16/rtl/i2c_master.v b/example/HTG640/fpga_cxpt16/rtl/i2c_master.v similarity index 100% rename from example/HXT100G/fpga_cxpt16/rtl/i2c_master.v rename to example/HTG640/fpga_cxpt16/rtl/i2c_master.v diff --git a/example/HXT100G/fpga_cxpt16/rtl/sync_signal.v b/example/HTG640/fpga_cxpt16/rtl/sync_signal.v similarity index 100% rename from example/HXT100G/fpga_cxpt16/rtl/sync_signal.v rename to example/HTG640/fpga_cxpt16/rtl/sync_signal.v diff --git a/example/HXT100G/fpga_cxpt16/tb/fpga_core/Makefile b/example/HTG640/fpga_cxpt16/tb/fpga_core/Makefile similarity index 100% rename from example/HXT100G/fpga_cxpt16/tb/fpga_core/Makefile rename to example/HTG640/fpga_cxpt16/tb/fpga_core/Makefile diff --git a/example/HXT100G/fpga_cxpt16/tb/fpga_core/test_fpga_core.py b/example/HTG640/fpga_cxpt16/tb/fpga_core/test_fpga_core.py similarity index 100% rename from example/HXT100G/fpga_cxpt16/tb/fpga_core/test_fpga_core.py rename to example/HTG640/fpga_cxpt16/tb/fpga_core/test_fpga_core.py