From 5560fa2b3276b8a1a893bdc64e70e45eb49191e3 Mon Sep 17 00:00:00 2001
From: Alex Forencich <alex@alexforencich.com>
Date: Thu, 30 Nov 2023 14:05:16 -0800
Subject: [PATCH] Fix timestamp capture/sync logic

Signed-off-by: Alex Forencich <alex@alexforencich.com>
---
 rtl/ptp_clock_cdc.v | 10 ++++++----
 rtl/ptp_td_leaf.v   | 12 ++++++------
 2 files changed, 12 insertions(+), 10 deletions(-)

diff --git a/rtl/ptp_clock_cdc.v b/rtl/ptp_clock_cdc.v
index 13ce0de3..48dfe748 100644
--- a/rtl/ptp_clock_cdc.v
+++ b/rtl/ptp_clock_cdc.v
@@ -491,8 +491,6 @@ always @(posedge output_clk) begin
         ts_capt_valid_reg <= 1'b1;
     end
 
-    ts_sync_valid_reg <= 1'b0;
-
     if (src_sync_sync2_reg ^ src_sync_sync3_reg) begin
         // store captured source TS
         if (TS_WIDTH == 96) begin
@@ -501,7 +499,11 @@ always @(posedge output_clk) begin
         src_ts_ns_sync_reg <= src_ts_ns_capt_reg;
         src_ts_step_sync_reg <= src_ts_step_capt_reg;
 
-        ts_sync_valid_reg <= ts_capt_valid_reg;
+        ts_sync_valid_reg <= 1'b1;
+    end
+
+    if (ts_sync_valid_reg && ts_capt_valid_reg) begin
+        ts_sync_valid_reg <= 1'b0;
         ts_capt_valid_reg <= 1'b0;
     end
 
@@ -595,7 +597,7 @@ always @* begin
         ts_ns_next = ts_ns_reg + period_ns_reg;
     end
 
-    if (ts_sync_valid_reg) begin
+    if (ts_sync_valid_reg && ts_capt_valid_reg) begin
         // Read new value
         if (TS_WIDTH == 96) begin
             if (src_ts_step_sync_reg || load_ts_reg) begin
diff --git a/rtl/ptp_td_leaf.v b/rtl/ptp_td_leaf.v
index e4690d5f..1bf5bfe5 100644
--- a/rtl/ptp_td_leaf.v
+++ b/rtl/ptp_td_leaf.v
@@ -533,14 +533,11 @@ always @(posedge clk) begin
         dst_load_cnt_reg <= dst_load_cnt_reg + 1;
     end
 
-    ts_sync_valid_reg <= 1'b0;
-
     if (src_sync_sync2_reg ^ src_sync_sync3_reg) begin
         // store captured source TS
         src_ns_sync_reg <= src_ns_reg >> (SRC_FNS_W-CMP_FNS_W);
 
-        ts_sync_valid_reg <= ts_capt_valid_reg;
-        ts_capt_valid_reg <= 1'b0;
+        ts_sync_valid_reg <= 1'b1;
     end
 
     if (src_marker_sync2_reg ^ src_marker_sync3_reg) begin
@@ -548,9 +545,12 @@ always @(posedge clk) begin
     end
 
     phase_err_out_valid_reg <= 1'b0;
-    if (ts_sync_valid_reg) begin
+    if (ts_sync_valid_reg && ts_capt_valid_reg) begin
         // coarse phase locking
 
+        ts_sync_valid_reg <= 1'b0;
+        ts_capt_valid_reg <= 1'b0;
+
         // phase and frequency detector
         phase_last_src_reg <= src_ns_sync_reg[8+CMP_FNS_W];
         phase_last_dst_reg <= dst_ns_capt_reg[8+CMP_FNS_W];
@@ -827,7 +827,7 @@ always @* begin
         end
     end
 
-    if (ts_sync_valid_reg) begin
+    if (ts_sync_valid_reg && ts_capt_valid_reg) begin
         // compute difference
         ts_ns_diff_valid_next = freq_locked_reg;
         ts_ns_diff_next = src_ns_sync_reg - dst_ns_capt_reg;