From c6ecd770e731f8d6c02a4501b776d4a8e3baea9b Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Fri, 26 Jan 2024 12:35:27 -0800 Subject: [PATCH 1/2] Fix spurious multi-driven net issue in axis_ram_switch when S_ID_WIDTH = 0 Signed-off-by: Alex Forencich --- rtl/axis_ram_switch.v | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/rtl/axis_ram_switch.v b/rtl/axis_ram_switch.v index ac31dcca2..6e08a921a 100644 --- a/rtl/axis_ram_switch.v +++ b/rtl/axis_ram_switch.v @@ -611,7 +611,9 @@ generate assign int_cmd_len[m*ADDR_WIDTH +: ADDR_WIDTH] = cmd_len_reg; assign int_cmd_id[m*CMD_ADDR_WIDTH +: CMD_ADDR_WIDTH] = cmd_id_reg; assign int_cmd_tkeep[m*KEEP_WIDTH +: KEEP_WIDTH] = cmd_tkeep_reg; - assign int_cmd_tid[m*S_ID_WIDTH +: S_ID_WIDTH_INT] = cmd_tid_reg; + if (ID_ENABLE && S_ID_WIDTH > 0) begin + assign int_cmd_tid[m*S_ID_WIDTH +: S_ID_WIDTH_INT] = cmd_tid_reg; + end assign int_cmd_tdest[m*S_DEST_WIDTH +: S_DEST_WIDTH] = cmd_tdest_reg; assign int_cmd_tuser[m*USER_WIDTH +: USER_WIDTH] = cmd_tuser_reg; assign int_cmd_valid[m*M_COUNT +: M_COUNT] = cmd_valid_reg; From 10b6d2f5bc50f965d6aee213415b60f1f9af58e5 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sun, 28 Jan 2024 16:38:38 -0800 Subject: [PATCH 2/2] Force AXIS RAM switch output FIFO into distributed RAM Signed-off-by: Alex Forencich --- rtl/axis_ram_switch.v | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/rtl/axis_ram_switch.v b/rtl/axis_ram_switch.v index 6e08a921a..56dc66a51 100644 --- a/rtl/axis_ram_switch.v +++ b/rtl/axis_ram_switch.v @@ -912,11 +912,17 @@ generate assign port_cmd_status_ready[m] = int_cmd_status_ready[m*M_COUNT+n]; end + (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [DATA_WIDTH-1:0] out_fifo_tdata[31:0]; + (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [KEEP_WIDTH-1:0] out_fifo_tkeep[31:0]; + (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg out_fifo_tlast[31:0]; + (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [M_ID_WIDTH-1:0] out_fifo_tid[31:0]; + (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [M_DEST_WIDTH-1:0] out_fifo_tdest[31:0]; + (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [USER_WIDTH-1:0] out_fifo_tuser[31:0]; reg [5:0] out_fifo_data_wr_ptr_reg = 0;