diff --git a/example/VCU108/fpga_10g/fpga.xdc b/example/VCU108/fpga_10g/fpga.xdc index 30d4f8db..c10d6120 100644 --- a/example/VCU108/fpga_10g/fpga.xdc +++ b/example/VCU108/fpga_10g/fpga.xdc @@ -29,6 +29,11 @@ create_clock -period 8.000 -name clk_125mhz [get_ports clk_125mhz_p] #set_property -dict {LOC AL20 IOSTANDARD LVCMOS18} [get_ports clk_90mhz] #create_clock -period 11.111 -name clk_90mhz [get_ports clk_90mhz] +# User SMA clock J34/J35 +#set_property -dict {LOC AR14 IOSTANDARD LVDS} [get_ports user_sma_clk_p] +#set_property -dict {LOC AT14 IOSTANDARD LVDS} [get_ports user_sma_clk_n] +#create_clock -period 8.000 -name user_sma_clk [get_ports user_sma_clk_p] + # LEDs set_property -dict {LOC AT32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}] set_property -dict {LOC AV34 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[1]}] diff --git a/example/VCU108/fpga_1g/fpga.xdc b/example/VCU108/fpga_1g/fpga.xdc index 4a56a829..c5f785e1 100644 --- a/example/VCU108/fpga_1g/fpga.xdc +++ b/example/VCU108/fpga_1g/fpga.xdc @@ -29,6 +29,11 @@ create_clock -period 8.000 -name clk_125mhz [get_ports clk_125mhz_p] #set_property -dict {LOC AL20 IOSTANDARD LVCMOS18} [get_ports clk_90mhz] #create_clock -period 11.111 -name clk_90mhz [get_ports clk_90mhz] +# User SMA clock J34/J35 +#set_property -dict {LOC AR14 IOSTANDARD LVDS} [get_ports user_sma_clk_p] +#set_property -dict {LOC AT14 IOSTANDARD LVDS} [get_ports user_sma_clk_n] +#create_clock -period 8.000 -name user_sma_clk [get_ports user_sma_clk_p] + # LEDs set_property -dict {LOC AT32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}] set_property -dict {LOC AV34 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[1]}] diff --git a/example/VCU118/fpga_1g/fpga.xdc b/example/VCU118/fpga_1g/fpga.xdc index a7aa10bb..54bf9a81 100644 --- a/example/VCU118/fpga_1g/fpga.xdc +++ b/example/VCU118/fpga_1g/fpga.xdc @@ -35,6 +35,11 @@ create_clock -period 8.000 -name clk_125mhz [get_ports clk_125mhz_p] #set_property -dict {LOC AL20 IOSTANDARD LVCMOS18} [get_ports clk_90mhz] #create_clock -period 11.111 -name clk_90mhz [get_ports clk_90mhz] +# User SMA clock J34/J35 +#set_property -dict {LOC R32 IOSTANDARD LVDS} [get_ports user_sma_clk_p] +#set_property -dict {LOC P32 IOSTANDARD LVDS} [get_ports user_sma_clk_n] +#create_clock -period 8.000 -name user_sma_clk [get_ports user_sma_clk_p] + # LEDs set_property -dict {LOC AT32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}] set_property -dict {LOC AV34 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[1]}] diff --git a/example/VCU118/fpga_25g/fpga.xdc b/example/VCU118/fpga_25g/fpga.xdc index df08d8be..bee73a41 100644 --- a/example/VCU118/fpga_25g/fpga.xdc +++ b/example/VCU118/fpga_25g/fpga.xdc @@ -35,6 +35,11 @@ create_clock -period 8.000 -name clk_125mhz [get_ports clk_125mhz_p] #set_property -dict {LOC AL20 IOSTANDARD LVCMOS18} [get_ports clk_90mhz] #create_clock -period 11.111 -name clk_90mhz [get_ports clk_90mhz] +# User SMA clock J34/J35 +#set_property -dict {LOC R32 IOSTANDARD LVDS} [get_ports user_sma_clk_p] +#set_property -dict {LOC P32 IOSTANDARD LVDS} [get_ports user_sma_clk_n] +#create_clock -period 8.000 -name user_sma_clk [get_ports user_sma_clk_p] + # LEDs set_property -dict {LOC AT32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}] set_property -dict {LOC AV34 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[1]}] diff --git a/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga.xdc b/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga.xdc index 8d5fb3f8..e09ee025 100644 --- a/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga.xdc +++ b/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga.xdc @@ -35,6 +35,11 @@ create_clock -period 8.000 -name clk_125mhz [get_ports clk_125mhz_p] #set_property -dict {LOC AL20 IOSTANDARD LVCMOS18} [get_ports clk_90mhz] #create_clock -period 11.111 -name clk_90mhz [get_ports clk_90mhz] +# User SMA clock J34/J35 +#set_property -dict {LOC R32 IOSTANDARD LVDS} [get_ports user_sma_clk_p] +#set_property -dict {LOC P32 IOSTANDARD LVDS} [get_ports user_sma_clk_n] +#create_clock -period 8.000 -name user_sma_clk [get_ports user_sma_clk_p] + # LEDs set_property -dict {LOC AT32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}] set_property -dict {LOC AV34 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[1]}]