From e55a6dc64d0be7307b4ef5847a68cd0fb88b8814 Mon Sep 17 00:00:00 2001 From: ajayswar-s <139959004+ajayswar-s@users.noreply.github.com> Date: Thu, 24 Oct 2024 15:26:26 +0530 Subject: [PATCH] Errata 756 and 758: UART Condition (#367) -In BSA The UART rule is relaxed based on particular UART -IN Sbsa A new rule is added S_l3PER_01 for UART without relax Change-Id: I3250ffef41e35894c8c83122eb822b9645197683 Signed-off-by: Ajayswar S --- docs/arm_bsa_testcase_checklist.rst | 4 ++-- .../operating_system/test_os_d003.c | 23 ++++++++++++------- .../operating_system/test_os_d005.c | 13 ++++++++--- 3 files changed, 27 insertions(+), 13 deletions(-) diff --git a/docs/arm_bsa_testcase_checklist.rst b/docs/arm_bsa_testcase_checklist.rst index 39007a48..77af1461 100644 --- a/docs/arm_bsa_testcase_checklist.rst +++ b/docs/arm_bsa_testcase_checklist.rst @@ -132,13 +132,13 @@ The below table provides the following details +-------+--------------------------------------------+------------------------------------------------------------+-----+-----+-----+-----+----------+-----+-------------------+ |602 |Check SATA CTRL Interface |B_PER_03 |Yes |Yes |Yes |Yes |Yes |No |No | +-------+--------------------------------------------+------------------------------------------------------------+-----+-----+-----+-----+----------+-----+-------------------+ -|603 |Check Arm BSA UART register offsets |B_PER_05 |Yes |Yes |Yes |Yes |Yes |No |No | +|603 |Check Arm BSA UART register offsets |B_PER_05, S_L3PER_01 |Yes |Yes |Yes |Yes |Yes |No |No | +-------+--------------------------------------------+------------------------------------------------------------+-----+-----+-----+-----+----------+-----+-------------------+ |604 |Check Arm GENERIC UART Interrupt |B_PER_06, B_PER_07 |Yes |Yes |Yes |Yes |Yes |No |No | +-------+--------------------------------------------+------------------------------------------------------------+-----+-----+-----+-----+----------+-----+-------------------+ |605 |Memory Attribute of DMA |B_PER_09, B_PER_10 |Yes |Yes |Yes |Yes# |Yes |Yes |No | +-------+--------------------------------------------+------------------------------------------------------------+-----+-----+-----+-----+----------+-----+-------------------+ -|606 |16550 compatible UART |B_PER_05 |Yes |Yes |Yes |Yes |Yes |No |No | +|606 |16550 compatible UART |B_PER_05, S_L3PER_01 |Yes |Yes |Yes |Yes |Yes |No |No | +-------+--------------------------------------------+------------------------------------------------------------+-----+-----+-----+-----+----------+-----+-------------------+ |701 |Non Secure Watchdog Access |B_WD_01, B_WD_02, S_L3WD_01 |Yes |Yes |Yes |Yes |Yes |No |No | +-------+--------------------------------------------+------------------------------------------------------------+-----+-----+-----+-----+----------+-----+-------------------+ diff --git a/test_pool/peripherals/operating_system/test_os_d003.c b/test_pool/peripherals/operating_system/test_os_d003.c index cbd62778..c0a8b3e6 100644 --- a/test_pool/peripherals/operating_system/test_os_d003.c +++ b/test_pool/peripherals/operating_system/test_os_d003.c @@ -25,7 +25,8 @@ #include "val/common/sys_arch_src/gic/v3/gic_v3.h" #define TEST_NUM (ACS_PER_TEST_NUM_BASE + 3) -#define TEST_RULE "B_PER_05" +#define TEST_RULE_BSA "B_PER_05" +#define TEST_RULE_SBSA "S_L3PER_01" #define TEST_DESC "Check Arm BSA UART register offsets " #define TEST_NUM1 (ACS_PER_TEST_NUM_BASE + 4) #define TEST_RULE1 "B_PER_06, B_PER_07" @@ -145,10 +146,13 @@ payload() branch_to_test = &&exception_taken; if (count == 0) { val_print(ACS_PRINT_ERR, "\n No UART defined by Platform ", 0); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + if (g_build_sbsa) + val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + else + val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } - val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); + val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); while (count != 0) { interface_type = val_peripheral_get_info(UART_INTERFACE_TYPE, count - 1); @@ -158,7 +162,7 @@ payload() { l_uart_base = val_peripheral_get_info(UART_BASE0, count - 1); if (l_uart_base == 0) { - val_set_status(index, RESULT_SKIP(TEST_NUM, 2)); + val_set_status(index, RESULT_SKIP(TEST_NUM, 3)); return; } @@ -189,10 +193,10 @@ payload1() if (count == 0) { val_print(ACS_PRINT_ERR, "\n No UART defined by Platform ", 0); - val_set_status(index, RESULT_FAIL(TEST_NUM1, 1)); + val_set_status(index, RESULT_SKIP(TEST_NUM1, 1)); return; } - val_set_status(index, RESULT_SKIP(TEST_NUM1, 1)); + val_set_status(index, RESULT_SKIP(TEST_NUM1, 2)); while (count != 0) { timeout = TIMEOUT_MEDIUM; int_id = val_peripheral_get_info(UART_GSIV, count - 1); @@ -236,7 +240,7 @@ payload1() test_fail++; } } else { - val_set_status(index, RESULT_SKIP(TEST_NUM1, 2)); + val_set_status(index, RESULT_SKIP(TEST_NUM1, 3)); } } count--; @@ -268,7 +272,10 @@ os_d003_entry(uint32_t num_pe) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + if (g_build_sbsa) + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE_SBSA); + else + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE_BSA); val_report_status(0, ACS_END(TEST_NUM), NULL); diff --git a/test_pool/peripherals/operating_system/test_os_d005.c b/test_pool/peripherals/operating_system/test_os_d005.c index dbdd0b0a..363860cf 100644 --- a/test_pool/peripherals/operating_system/test_os_d005.c +++ b/test_pool/peripherals/operating_system/test_os_d005.c @@ -20,7 +20,8 @@ #include "val/common/include/acs_pcie.h" #define TEST_NUM (ACS_PER_TEST_NUM_BASE + 6) -#define TEST_RULE "B_PER_05" +#define TEST_RULE_BSA "B_PER_05" +#define TEST_RULE_SBSA "S_L3PER_01" #define TEST_DESC "16550 compatible UART " static @@ -81,7 +82,10 @@ payload() if (count == 0) { val_print(ACS_PRINT_ERR, "\n No UART defined by Platform ", 0); - val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + if (g_build_sbsa) + val_set_status(index, RESULT_FAIL(TEST_NUM, 1)); + else + val_set_status(index, RESULT_SKIP(TEST_NUM, 1)); return; } @@ -217,7 +221,10 @@ os_d005_entry(uint32_t num_pe) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + if (g_build_sbsa) + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE_SBSA); + else + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE_BSA); val_report_status(0, ACS_END(TEST_NUM), NULL);