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pll25.qip
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pll25.qip
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############################################################################
# Copyright 2019 Intel Corporation.
#
# This reference design file is subject licensed to you by the terms and
# conditions of the applicable License Terms and Conditions for Hardware
# Reference Designs and/or Design Examples (either as signed by you or
# found at https://www.altera.com/common/legal/leg-license_agreement.html ).
#
# As stated in the license, you agree to only use this reference design
# solely in conjunction with Intel FPGAs or Intel CPLDs.
#
# THE REFERENCE DESIGN IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
# WARRANTY OF ANY KIND INCLUDING WARRANTIES OF MERCHANTABILITY,
# NONINFRINGEMENT, OR FITNESS FOR A PARTICULAR PURPOSE. Intel does not
# warrant or assume responsibility for the accuracy or completeness of any
# information, links or other items within the Reference Design and any
# accompanying materials.
#
# In the event that you do not agree with such terms and conditions, do not
# use the reference design file.
############################################################################
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "18.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll25.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll25_bb.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll25.ppf"]