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UNRATIFIED RISC-V: Add 'Zcmop' extension
[DO NOT MERGE] Until the 'Zcmop' extension is frozen/ratified and final version number is determined, this patch should not be merged upstream. This commit uses version 0.1 as a placeholder. This commit adds support for the compressed "May Be Operations (MOP)" (Zcmop) extension which adds 8 compressed MOP instructions. By default, they are the same as NOP. However, if certain feature is supported (and optionally enabled), it is allowed to alter architectural state unlike HINT instructions. This commit is based on the TENTATIVE specification: <riscv/riscv-cfi#131> bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): Add 'Zcmop' -> 'Zca' implication. (riscv_supported_std_z_ext): Add 'Zcmop'. (riscv_multi_subset_supports): Support new instruction class. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/zcmop.s: New test for 'Zcmop'. * testsuite/gas/riscv/zcmop.d: Likewise. include/ChangeLog: * opcode/riscv-opc.h ( MATCH_C_MOP_0, MASK_C_MOP_0, MATCH_C_MOP_1, MASK_C_MOP_1, MATCH_C_MOP_2, MASK_C_MOP_2, MATCH_C_MOP_3, MASK_C_MOP_3, MATCH_C_MOP_4, MASK_C_MOP_4, MATCH_C_MOP_5, MASK_C_MOP_5, MATCH_C_MOP_6, MASK_C_MOP_6, MATCH_C_MOP_7, MASK_C_MOP_7): New. * opcode/riscv.h (enum riscv_insn_class): Add new instruction class INSN_CLASS_ZCMOP. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Add new "may be" operations from the 'Zcmop' extension near the bottom.
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‎bfd/elfxx-riscv.c‎

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Original file line numberDiff line numberDiff line change
@@ -1182,6 +1182,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
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{"zcf", "zca", check_implicit_always},
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{"zcd", "zca", check_implicit_always},
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{"zcb", "zca", check_implicit_always},
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{"zcmop", "zca", check_implicit_always},
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{"smaia", "ssaia", check_implicit_always},
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{"smcntrpmf", "zicsr", check_implicit_always},
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{"smstateen", "ssstateen", check_implicit_always},
@@ -1325,6 +1326,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
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{"zcb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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{"zcf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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{"zcd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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{"zcmop", ISA_SPEC_CLASS_DRAFT, 0, 1, 0 },
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{NULL, 0, 0, 0, 0}
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};
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@@ -2549,6 +2551,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
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case INSN_CLASS_ZCB_AND_ZMMUL:
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return (riscv_subset_supports (rps, "zcb")
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&& riscv_subset_supports (rps, "zmmul"));
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case INSN_CLASS_ZCMOP:
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return riscv_subset_supports (rps, "zcmop");
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case INSN_CLASS_SVINVAL:
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return riscv_subset_supports (rps, "svinval");
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case INSN_CLASS_H:
@@ -2791,6 +2795,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
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return _("zcb' and `zbb");
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case INSN_CLASS_ZCB_AND_ZMMUL:
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return _("zcb' and `zmmul', or `zcb' and `m");
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case INSN_CLASS_ZCMOP:
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return "zcmop";
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case INSN_CLASS_SVINVAL:
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return "svinval";
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case INSN_CLASS_H:

‎gas/testsuite/gas/riscv/zcmop.d‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,16 @@
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#as: -march=rv32i_zcmop
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#objdump: -d
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.*:[ ]+file format .*
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Disassembly of section .text:
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0+000 <target>:
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[ ]+[0-9a-f]+:[ ]+6081[ ]+c\.mop\.0
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[ ]+[0-9a-f]+:[ ]+6181[ ]+c\.mop\.1
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[ ]+[0-9a-f]+:[ ]+6281[ ]+c\.mop\.2
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[ ]+[0-9a-f]+:[ ]+6381[ ]+c\.mop\.3
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[ ]+[0-9a-f]+:[ ]+6481[ ]+c\.mop\.4
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[ ]+[0-9a-f]+:[ ]+6581[ ]+c\.mop\.5
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[ ]+[0-9a-f]+:[ ]+6681[ ]+c\.mop\.6
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[ ]+[0-9a-f]+:[ ]+6781[ ]+c\.mop\.7

‎gas/testsuite/gas/riscv/zcmop.s‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,9 @@
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target:
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c.mop.0
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c.mop.1
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c.mop.2
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c.mop.3
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c.mop.4
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c.mop.5
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c.mop.6
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c.mop.7

‎include/opcode/riscv-opc.h‎

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2401,6 +2401,23 @@
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#define MASK_WRS_NTO 0xffffffff
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#define MATCH_WRS_STO 0x01d00073
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#define MASK_WRS_STO 0xffffffff
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/* Zcmop "may be" operations. */
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#define MATCH_C_MOP_0 0x6081
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#define MASK_C_MOP_0 0xffff
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#define MATCH_C_MOP_1 0x6181
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#define MASK_C_MOP_1 0xffff
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#define MATCH_C_MOP_2 0x6281
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#define MASK_C_MOP_2 0xffff
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#define MATCH_C_MOP_3 0x6381
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#define MASK_C_MOP_3 0xffff
2413+
#define MATCH_C_MOP_4 0x6481
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#define MASK_C_MOP_4 0xffff
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#define MATCH_C_MOP_5 0x6581
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#define MASK_C_MOP_5 0xffff
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#define MATCH_C_MOP_6 0x6681
2418+
#define MASK_C_MOP_6 0xffff
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#define MATCH_C_MOP_7 0x6781
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#define MASK_C_MOP_7 0xffff
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/* Vendor-specific (T-Head) XTheadBa instructions. */
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#define MATCH_TH_ADDSL 0x0000100b
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#define MASK_TH_ADDSL 0xf800707f
@@ -3556,6 +3573,15 @@ DECLARE_INSN(c_lhu, MATCH_C_LHU, MASK_C_LHU)
35563573
DECLARE_INSN(c_lh, MATCH_C_LH, MASK_C_LH)
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DECLARE_INSN(c_sb, MATCH_C_SB, MASK_C_SB)
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DECLARE_INSN(c_sh, MATCH_C_SH, MASK_C_SH)
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/* Zcmop "may be" operations. */
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DECLARE_INSN(c_mop_0, MATCH_C_MOP_0, MASK_C_MOP_0)
3578+
DECLARE_INSN(c_mop_1, MATCH_C_MOP_1, MASK_C_MOP_1)
3579+
DECLARE_INSN(c_mop_2, MATCH_C_MOP_2, MASK_C_MOP_2)
3580+
DECLARE_INSN(c_mop_3, MATCH_C_MOP_3, MASK_C_MOP_3)
3581+
DECLARE_INSN(c_mop_4, MATCH_C_MOP_4, MASK_C_MOP_4)
3582+
DECLARE_INSN(c_mop_5, MATCH_C_MOP_5, MASK_C_MOP_5)
3583+
DECLARE_INSN(c_mop_6, MATCH_C_MOP_6, MASK_C_MOP_6)
3584+
DECLARE_INSN(c_mop_7, MATCH_C_MOP_7, MASK_C_MOP_7)
35593585
/* Vendor-specific (T-Head) XTheadBa instructions. */
35603586
DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
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/* Vendor-specific (T-Head) XTheadBb instructions. */

‎include/opcode/riscv.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -439,6 +439,7 @@ enum riscv_insn_class
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INSN_CLASS_ZCB_AND_ZBA,
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INSN_CLASS_ZCB_AND_ZBB,
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INSN_CLASS_ZCB_AND_ZMMUL,
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INSN_CLASS_ZCMOP,
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INSN_CLASS_SVINVAL,
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INSN_CLASS_ZICBOM,
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INSN_CLASS_ZICBOP,

‎opcodes/riscv-opc.c‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2021,6 +2021,16 @@ const struct riscv_opcode riscv_opcodes[] =
20212021
{"mop.rr.6", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_6, MASK_MOP_RR_6, match_opcode, 0 },
20222022
{"mop.rr.7", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_7, MASK_MOP_RR_7, match_opcode, 0 },
20232023

2024+
/* Zcmop "may be" operations. */
2025+
{"c.mop.0", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_0, MASK_C_MOP_0, match_opcode, 0 },
2026+
{"c.mop.1", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_1, MASK_C_MOP_1, match_opcode, 0 },
2027+
{"c.mop.2", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_2, MASK_C_MOP_2, match_opcode, 0 },
2028+
{"c.mop.3", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_3, MASK_C_MOP_3, match_opcode, 0 },
2029+
{"c.mop.4", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_4, MASK_C_MOP_4, match_opcode, 0 },
2030+
{"c.mop.5", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_5, MASK_C_MOP_5, match_opcode, 0 },
2031+
{"c.mop.6", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_6, MASK_C_MOP_6, match_opcode, 0 },
2032+
{"c.mop.7", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_7, MASK_C_MOP_7, match_opcode, 0 },
2033+
20242034
/* Supervisor instructions. */
20252035
{"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
20262036
{"csrwi", 0, INSN_CLASS_ZICSR, "E,Z", MATCH_CSRRWI, MASK_CSRRWI|MASK_RD, match_opcode, INSN_ALIAS },

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