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RISC-V: Add support for 'Zacas' atomic CAS
This commit adds support for the 'Zacas' extension, adding atomic CAS instructions. Beware that this extension also introduces the concept of register pairs and it checks the validity of rs1 and rs2 if applicable. This is based on the latest (frozen) draft: <https://github.com/riscv/riscv-zacas/releases/tag/v1.0-rc5> bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): Make 'Zacas' to imply 'A' extension. (riscv_supported_std_z_ext): Add 'Zacas' to the supported list. (riscv_multi_subset_supports, riscv_multi_subset_supports_ext): Add handling for new instruction class. gas/ChangeLog: * testsuite/gas/riscv/zacas-32.s: New test. * testsuite/gas/riscv/zacas-32.d: Likewise. * testsuite/gas/riscv/zacas-64.s: Likewise. * testsuite/gas/riscv/zacas-64.d: Likewise. * testsuite/gas/riscv/zacas-32-fail.s: New failure test. * testsuite/gas/riscv/zacas-32-fail.d: Likewise. * testsuite/gas/riscv/zacas-32-fail.l: Likewise. * testsuite/gas/riscv/zacas-64-fail.s: New failure test. * testsuite/gas/riscv/zacas-64-fail.d: Likewise. * testsuite/gas/riscv/zacas-64-fail.l: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_AMOCAS_D, MASK_AMOCAS_D, MATCH_AMOCAS_Q, MASK_AMOCAS_Q, MATCH_AMOCAS_W, MASK_AMOCAS_W): New. * opcode/riscv.h (enum riscv_insn_class): Add new instruction class INSN_CLASS_ZACAS. opcodes/ChangeLog: * riscv-opc.c (REGGROUP_REGS_x, REGGROUP_REGS_1, REGGROUP_REGS_2, DEFINE_MATCH_FUNC_R): New match function template with register groups. (match_reggroup_r_1_1_1, match_reggroup_r_1_2_2): New. (riscv_opcodes): Add atomic CAS instructions.
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‎bfd/elfxx-riscv.c‎

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@@ -1148,6 +1148,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
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{"zhinx", "zhinxmin", check_implicit_always},
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{"zhinxmin", "zfinx", check_implicit_always},
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{"zfinx", "zicsr", check_implicit_always},
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{"zacas", "a", check_implicit_always},
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{"zk", "zkn", check_implicit_always},
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{"zk", "zkr", check_implicit_always},
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{"zk", "zkt", check_implicit_always},
@@ -1259,6 +1260,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
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{"zihintntl", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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{"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 },
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{"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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{"zacas", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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{"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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{"zfa", ISA_SPEC_CLASS_DRAFT, 0, 1, 0 },
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{"zfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2409,6 +2411,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
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return riscv_subset_supports (rps, "zmmul");
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case INSN_CLASS_A:
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return riscv_subset_supports (rps, "a");
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case INSN_CLASS_ZACAS:
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return riscv_subset_supports (rps, "zacas");
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case INSN_CLASS_ZAWRS:
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return riscv_subset_supports (rps, "zawrs");
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case INSN_CLASS_F:
@@ -2619,6 +2623,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
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return _ ("m' or `zmmul");
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case INSN_CLASS_A:
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return "a";
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case INSN_CLASS_ZACAS:
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return "zacas";
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case INSN_CLASS_ZAWRS:
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return "zawrs";
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case INSN_CLASS_F:

‎gas/testsuite/gas/riscv/zacas-32-fail.d‎

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#as: -march=rv32i_zacas
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#error_output: zacas-32-fail.l

‎gas/testsuite/gas/riscv/zacas-32-fail.l‎

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.*: Assembler messages:
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.*: Error: illegal operands `amocas\.d a1,a4,\(a3\)'
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.*: Error: illegal operands `amocas\.d a0,a5,\(a3\)'
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.*: Error: illegal operands `amocas\.d\.aq a1,a4,\(a3\)'
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.*: Error: illegal operands `amocas\.d\.aq a0,a5,\(a3\)'
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.*: Error: illegal operands `amocas\.d\.rl a1,a4,\(a3\)'
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.*: Error: illegal operands `amocas\.d\.rl a0,a5,\(a3\)'
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.*: Error: illegal operands `amocas\.d\.aqrl a1,a4,\(a3\)'
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.*: Error: illegal operands `amocas\.d\.aqrl a0,a5,\(a3\)'

‎gas/testsuite/gas/riscv/zacas-32-fail.s‎

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target:
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# amocas.d (RV32): rd (operand 1) and rs2 (operand 2) must be even.
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amocas.d a1, a4, (a3)
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amocas.d a0, a5, (a3)
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amocas.d.aq a1, a4, (a3)
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amocas.d.aq a0, a5, (a3)
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amocas.d.rl a1, a4, (a3)
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amocas.d.rl a0, a5, (a3)
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amocas.d.aqrl a1, a4, (a3)
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amocas.d.aqrl a0, a5, (a3)

‎gas/testsuite/gas/riscv/zacas-32.d‎

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#as: -march=rv32i_zacas
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#objdump: -d
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.*:[ ]+file format .*
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Disassembly of section .text:
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0+000 <target>:
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[ ]+[0-9a-f]+:[ ]+28f6a5af[ ]+amocas\.w[ ]+a1,a5,\(a3\)
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[ ]+[0-9a-f]+:[ ]+2cf6a5af[ ]+amocas\.w\.aq[ ]+a1,a5,\(a3\)
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[ ]+[0-9a-f]+:[ ]+2af6a5af[ ]+amocas\.w\.rl[ ]+a1,a5,\(a3\)
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[ ]+[0-9a-f]+:[ ]+2ef6a5af[ ]+amocas\.w\.aqrl[ ]+a1,a5,\(a3\)
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[ ]+[0-9a-f]+:[ ]+28e6b52f[ ]+amocas\.d[ ]+a0,a4,\(a3\)
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[ ]+[0-9a-f]+:[ ]+2ce6b52f[ ]+amocas\.d\.aq[ ]+a0,a4,\(a3\)
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[ ]+[0-9a-f]+:[ ]+2ae6b52f[ ]+amocas\.d\.rl[ ]+a0,a4,\(a3\)
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[ ]+[0-9a-f]+:[ ]+2ee6b52f[ ]+amocas\.d\.aqrl[ ]+a0,a4,\(a3\)

‎gas/testsuite/gas/riscv/zacas-32.s‎

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target:
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amocas.w a1, a5, (a3)
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amocas.w.aq a1, a5, (a3)
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amocas.w.rl a1, a5, (a3)
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amocas.w.aqrl a1, a5, (a3)
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amocas.d a0, a4, (a3)
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amocas.d.aq a0, a4, (a3)
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amocas.d.rl a0, a4, (a3)
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amocas.d.aqrl a0, a4, (a3)

‎gas/testsuite/gas/riscv/zacas-64-fail.d‎

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#as: -march=rv64i_zacas
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#error_output: zacas-64-fail.l

‎gas/testsuite/gas/riscv/zacas-64-fail.l‎

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.*: Assembler messages:
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.*: Error: illegal operands `amocas\.q a1,a4,\(a3\)'
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.*: Error: illegal operands `amocas\.q a0,a5,\(a3\)'
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.*: Error: illegal operands `amocas\.q\.aq a1,a4,\(a3\)'
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.*: Error: illegal operands `amocas\.q\.aq a0,a5,\(a3\)'
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.*: Error: illegal operands `amocas\.q\.rl a1,a4,\(a3\)'
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.*: Error: illegal operands `amocas\.q\.rl a0,a5,\(a3\)'
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.*: Error: illegal operands `amocas\.q\.aqrl a1,a4,\(a3\)'
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.*: Error: illegal operands `amocas\.q\.aqrl a0,a5,\(a3\)'

‎gas/testsuite/gas/riscv/zacas-64-fail.s‎

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target:
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# amocas.q (RV64): rd (operand 1) and rs2 (operand 2) must be even.
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amocas.q a1, a4, (a3)
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amocas.q a0, a5, (a3)
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amocas.q.aq a1, a4, (a3)
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amocas.q.aq a0, a5, (a3)
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amocas.q.rl a1, a4, (a3)
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amocas.q.rl a0, a5, (a3)
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amocas.q.aqrl a1, a4, (a3)
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amocas.q.aqrl a0, a5, (a3)

‎gas/testsuite/gas/riscv/zacas-64.d‎

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#as: -march=rv64i_zacas
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#objdump: -d
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.*:[ ]+file format .*
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Disassembly of section .text:
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0+000 <target>:
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[ ]+[0-9a-f]+:[ ]+28f6a5af[ ]+amocas\.w[ ]+a1,a5,\(a3\)
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[ ]+[0-9a-f]+:[ ]+2cf6a5af[ ]+amocas\.w\.aq[ ]+a1,a5,\(a3\)
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[ ]+[0-9a-f]+:[ ]+2af6a5af[ ]+amocas\.w\.rl[ ]+a1,a5,\(a3\)
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[ ]+[0-9a-f]+:[ ]+2ef6a5af[ ]+amocas\.w\.aqrl[ ]+a1,a5,\(a3\)
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[ ]+[0-9a-f]+:[ ]+28f6b5af[ ]+amocas\.d[ ]+a1,a5,\(a3\)
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[ ]+[0-9a-f]+:[ ]+2cf6b5af[ ]+amocas\.d\.aq[ ]+a1,a5,\(a3\)
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[ ]+[0-9a-f]+:[ ]+2af6b5af[ ]+amocas\.d\.rl[ ]+a1,a5,\(a3\)
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[ ]+[0-9a-f]+:[ ]+2ef6b5af[ ]+amocas\.d\.aqrl[ ]+a1,a5,\(a3\)
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[ ]+[0-9a-f]+:[ ]+28e6c52f[ ]+amocas\.q[ ]+a0,a4,\(a3\)
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[ ]+[0-9a-f]+:[ ]+2ce6c52f[ ]+amocas\.q\.aq[ ]+a0,a4,\(a3\)
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[ ]+[0-9a-f]+:[ ]+2ae6c52f[ ]+amocas\.q\.rl[ ]+a0,a4,\(a3\)
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[ ]+[0-9a-f]+:[ ]+2ee6c52f[ ]+amocas\.q\.aqrl[ ]+a0,a4,\(a3\)

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