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RISC-V: Rounding mode on widening instructions
This commit adds support for rounding modes on widening instructions to the assembler/disassembler. On the disassembler, non-default rounding mode is displayed when "no-aliases" option is given or the rounding mode itself is invalid. On the assembler, specifying such rounding modes is prohibited unless we have supported in the past. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Add rounding mode support to widening instructions. (riscv_ip): Likewise. * testsuite/gas/riscv/rounding-dis-widening.d: New disasm test. * testsuite/gas/riscv/rounding-dis-widening.s: Likewise. * testsuite/gas/riscv/rounding-dis-widening-na.d: Likewise. * testsuite/gas/riscv/rounding-fail.d: Add testcases for widening instructions. * testsuite/gas/riscv/rounding-fail.l: Likewise. * testsuite/gas/riscv/rounding-fail.s: Likewise. * testsuite/gas/riscv/rounding-fcvt.q.l.d: New test. * testsuite/gas/riscv/rounding-fcvt.q.l.l: Likewise. * testsuite/gas/riscv/rounding-fcvt.q.l.s: Likewise. * testsuite/gas/riscv/rounding-fcvt.q.l-na.d: Likewise. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add rounding mode support to widening instructions. * riscv-opc.c (riscv_opcodes): Use new operand types. Idea-by: Tsukasa OI <[email protected]> Idea-by: S Pawan Kumar <[email protected]>
1 parent 7444df0 commit 80097fa

13 files changed

+155
-15
lines changed

‎gas/config/tc-riscv.c‎

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1421,6 +1421,8 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
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case 'f':
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switch (*++oparg)
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{
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case 'M': /* Fall through. */
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case 'm': USE_BITS (OP_MASK_RM, OP_SH_RM); break;
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case 'v': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
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default:
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goto unknown_validate_operand;
@@ -3545,6 +3547,33 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
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case 'f':
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switch (*++oparg)
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{
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case 'M':
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case 'm':
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/* Optional rounding mode (widening conversion)
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'M': operand either disallowed or not recommended
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(considered to be non-useful to normal software).
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'm': operand allowed for compatibility reasons
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(display a warning instead). */
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if (*asarg == '\0')
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{
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INSERT_OPERAND (RM, *ip, 0);
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continue;
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}
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else if (*asarg == ',' && asarg++
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&& arg_lookup (&asarg, riscv_rm,
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ARRAY_SIZE (riscv_rm), &regno))
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{
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INSERT_OPERAND (RM, *ip, regno);
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if (*oparg == 'M')
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as_bad (_ ("rounding mode cannot be specified "
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"on widening conversion"));
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else
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as_warn (
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_ ("specifying a rounding mode is strongly "
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"discourged on widening conversion"));
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continue;
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}
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break;
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case 'v':
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/* FLI.[HSDQ] value field for 'Zfa' extension. */
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if (!arg_lookup (&asarg, riscv_fli_symval,

‎gas/testsuite/gas/riscv/rounding-dis-widening-na.d‎

Lines changed: 13 additions & 0 deletions
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@@ -0,0 +1,13 @@
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#as: -march=rv32ifd
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#source: rounding-dis-widening.s
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#objdump: -d -M no-aliases
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.*:[ ]+file format .*
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Disassembly of section .text:
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0+000 <target>:
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[ ]+[0-9a-f]+:[ ]+420100d3[ ]+fcvt\.d\.s[ ]+ft1,ft2
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[ ]+[0-9a-f]+:[ ]+420100d3[ ]+fcvt\.d\.s[ ]+ft1,ft2
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[ ]+[0-9a-f]+:[ ]+420170d3[ ]+fcvt\.d\.s[ ]+ft1,ft2,dyn

‎gas/testsuite/gas/riscv/rounding-dis-widening.d‎

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@@ -0,0 +1,13 @@
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#as: -march=rv32ifd
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#source: rounding-dis-widening.s
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#objdump: -d
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.*:[ ]+file format .*
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Disassembly of section .text:
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0+000 <target>:
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[ ]+[0-9a-f]+:[ ]+420100d3[ ]+fcvt\.d\.s[ ]+ft1,ft2
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[ ]+[0-9a-f]+:[ ]+420100d3[ ]+fcvt\.d\.s[ ]+ft1,ft2
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[ ]+[0-9a-f]+:[ ]+420170d3[ ]+fcvt\.d\.s[ ]+ft1,ft2

‎gas/testsuite/gas/riscv/rounding-dis-widening.s‎

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@@ -0,0 +1,8 @@
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target:
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fcvt.d.s ft1, ft2
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# Standard encoding:
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# - 2nd operand is the rounding mode (RNE [0b000] is preferred).
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# - 6th operand (additional function) is zero for FCVT.D.S.
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.insn r OP_FP, 0x0, 0x21, ft1, ft2, f0
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# Non-standard encoding
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.insn r OP_FP, 0x7, 0x21, ft1, ft2, f0

‎gas/testsuite/gas/riscv/rounding-fail.d‎

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Original file line numberDiff line numberDiff line change
@@ -1,3 +1,3 @@
1-
#as: -march=rv32ifd
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#as: -march=rv32ifdq_zfh
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#source: rounding-fail.s
33
#error_output: rounding-fail.l

‎gas/testsuite/gas/riscv/rounding-fail.l‎

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Original file line numberDiff line numberDiff line change
@@ -3,3 +3,14 @@
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.*: Error: illegal operands `fadd.d fa1,fa1,fa1,'
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.*: Error: illegal operands `fadd.s fa1,fa1,fa1,unknown'
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.*: Error: illegal operands `fadd.d fa1,fa1,fa1,unknown'
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.*: Error: rounding mode cannot be specified on widening conversion
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.*: Error: rounding mode cannot be specified on widening conversion
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.*: Error: rounding mode cannot be specified on widening conversion
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.*: Error: rounding mode cannot be specified on widening conversion
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.*: Error: rounding mode cannot be specified on widening conversion
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.*: Error: rounding mode cannot be specified on widening conversion
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.*: Error: rounding mode cannot be specified on widening conversion
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.*: Error: rounding mode cannot be specified on widening conversion
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.*: Error: rounding mode cannot be specified on widening conversion
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.*: Error: rounding mode cannot be specified on widening conversion
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.*: Error: illegal operands `fcvt\.q\.wu ft1,t0,unknown'

‎gas/testsuite/gas/riscv/rounding-fail.s‎

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Original file line numberDiff line numberDiff line change
@@ -5,3 +5,19 @@ target:
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# Invalid rounding mode
66
fadd.s fa1,fa1,fa1,unknown
77
fadd.d fa1,fa1,fa1,unknown
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# Rounding mode cannot be specified on widening conversion
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# unless we have supported in the past.
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fcvt.s.h ft1,ft2,dyn
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fcvt.d.h ft1,ft2,dyn
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fcvt.q.h ft1,ft2,dyn
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fcvt.d.s ft1,ft2,dyn
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fcvt.q.s ft1,ft2,dyn
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fcvt.q.d ft1,ft2,dyn
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fcvt.d.w ft1,t0,dyn
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fcvt.d.wu ft1,t0,dyn
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fcvt.q.w ft1,t0,dyn
20+
fcvt.q.wu ft1,t0,dyn
21+
22+
# Different error message because of an invalid rounding mode
23+
fcvt.q.wu ft1,t0,unknown

‎gas/testsuite/gas/riscv/rounding-fcvt.q.l-na.d‎

Lines changed: 15 additions & 0 deletions
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@@ -0,0 +1,15 @@
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#as: -march=rv64ifdq
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#source: rounding-fcvt.q.l.s
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#warning_output: rounding-fcvt.q.l.l
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#objdump: -d -M no-aliases
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.*:[ ]+file format .*
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8+
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Disassembly of section .text:
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0+000 <target>:
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[ ]+[0-9a-f]+:[ ]+d62280d3[ ]+fcvt\.q\.l[ ]+ft1,t0
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[ ]+[0-9a-f]+:[ ]+d622f0d3[ ]+fcvt\.q\.l[ ]+ft1,t0,dyn
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[ ]+[0-9a-f]+:[ ]+d63280d3[ ]+fcvt\.q\.lu[ ]+ft1,t0
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[ ]+[0-9a-f]+:[ ]+d632f0d3[ ]+fcvt\.q\.lu[ ]+ft1,t0,dyn

‎gas/testsuite/gas/riscv/rounding-fcvt.q.l.d‎

Lines changed: 15 additions & 0 deletions
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@@ -0,0 +1,15 @@
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#as: -march=rv64ifdq
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#source: rounding-fcvt.q.l.s
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#warning_output: rounding-fcvt.q.l.l
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#objdump: -d
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.*:[ ]+file format .*
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Disassembly of section .text:
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0+000 <target>:
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[ ]+[0-9a-f]+:[ ]+d62280d3[ ]+fcvt\.q\.l[ ]+ft1,t0
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[ ]+[0-9a-f]+:[ ]+d622f0d3[ ]+fcvt\.q\.l[ ]+ft1,t0
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[ ]+[0-9a-f]+:[ ]+d63280d3[ ]+fcvt\.q\.lu[ ]+ft1,t0
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[ ]+[0-9a-f]+:[ ]+d632f0d3[ ]+fcvt\.q\.lu[ ]+ft1,t0

‎gas/testsuite/gas/riscv/rounding-fcvt.q.l.l‎

Lines changed: 3 additions & 0 deletions
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@@ -0,0 +1,3 @@
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.*: Assembler messages:
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.*: Warning: specifying a rounding mode is strongly discourged on widening conversion
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.*: Warning: specifying a rounding mode is strongly discourged on widening conversion

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