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generic: Allow bel pins without wires
Signed-off-by: gatecat <[email protected]>
1 parent fcf2bf6 commit c4e47ba

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1 file changed

+6
-3
lines changed

1 file changed

+6
-3
lines changed

generic/arch.cc

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -119,7 +119,8 @@ void Arch::addBelInput(BelId bel, IdString name, WireId wire)
119119
pi.wire = wire;
120120
pi.type = PORT_IN;
121121

122-
wire_info(wire).bel_pins.push_back(BelPin{bel, name});
122+
if (wire != WireId())
123+
wire_info(wire).bel_pins.push_back(BelPin{bel, name});
123124
}
124125

125126
void Arch::addBelOutput(BelId bel, IdString name, WireId wire)
@@ -131,7 +132,8 @@ void Arch::addBelOutput(BelId bel, IdString name, WireId wire)
131132
pi.wire = wire;
132133
pi.type = PORT_OUT;
133134

134-
wire_info(wire).bel_pins.push_back(BelPin{bel, name});
135+
if (wire != WireId())
136+
wire_info(wire).bel_pins.push_back(BelPin{bel, name});
135137
}
136138

137139
void Arch::addBelInout(BelId bel, IdString name, WireId wire)
@@ -143,7 +145,8 @@ void Arch::addBelInout(BelId bel, IdString name, WireId wire)
143145
pi.wire = wire;
144146
pi.type = PORT_INOUT;
145147

146-
wire_info(wire).bel_pins.push_back(BelPin{bel, name});
148+
if (wire != WireId())
149+
wire_info(wire).bel_pins.push_back(BelPin{bel, name});
147150
}
148151

149152
void Arch::addGroupBel(IdStringList group, BelId bel) { groups[group].bels.push_back(bel); }

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