From 00aa2e85929b41c3907ffbb024d75434b624a240 Mon Sep 17 00:00:00 2001 From: Varalaxmi Bingi Date: Thu, 8 Dec 2022 12:18:16 +0530 Subject: [PATCH] adding AMD copy right info. Adding AMD copyright information along with old copyright informarion Signed-off-by: Varalaxmi Bingi Acked-by: Raju Kumar Pothuraju --- RM/data/RM.mdd | 3 ++- RM/data/RM.tcl | 3 ++- ai_engine/data/ai_engine.mdd | 3 ++- ai_engine/data/ai_engine.tcl | 3 ++- ams/data/ams.mdd | 3 ++- ams/data/ams.tcl | 3 ++- apmps/data/apmps.mdd | 3 ++- apmps/data/apmps.tcl | 3 ++- audio_embed/data/audio_embed.mdd | 3 ++- audio_embed/data/audio_embed.tcl | 3 ++- audio_formatter/data/audio_formatter.mdd | 3 ++- audio_formatter/data/audio_formatter.tcl | 3 ++- audio_spdif/data/audio_spdif.mdd | 3 ++- audio_spdif/data/audio_spdif.tcl | 3 ++- axi_can/data/axi_can.mdd | 3 ++- axi_can/data/axi_can.tcl | 3 ++- axi_cdma/data/axi_cdma.mdd | 3 ++- axi_cdma/data/axi_cdma.tcl | 5 +++-- axi_clk_wiz/data/axi_clk_wiz.mdd | 3 ++- axi_clk_wiz/data/axi_clk_wiz.tcl | 3 ++- axi_dma/data/axi_dma.mdd | 3 ++- axi_dma/data/axi_dma.tcl | 5 +++-- axi_emc/data/axi_emc.mdd | 3 ++- axi_emc/data/axi_emc.tcl | 5 +++-- axi_ethernet/data/axi_ethernet.mdd | 3 ++- axi_ethernet/data/axi_ethernet.tcl | 5 +++-- axi_gpio/data/gpio.mdd | 3 ++- axi_gpio/data/gpio.tcl | 3 ++- axi_iic/data/axi_iic.mdd | 3 ++- axi_iic/data/axi_iic.tcl | 3 ++- axi_mcdma/data/axi_mcdma.mdd | 3 ++- axi_mcdma/data/axi_mcdma.tcl | 3 ++- axi_pcie/data/axi_pcie.mdd | 3 ++- axi_pcie/data/axi_pcie.tcl | 3 ++- axi_perf_mon/data/axi_perf_mon.mdd | 3 ++- axi_perf_mon/data/axi_perf_mon.tcl | 3 ++- axi_qspi/data/axi_qspi.mdd | 3 ++- axi_qspi/data/axi_qspi.tcl | 3 ++- axi_sysace/data/axi_sysace.mdd | 3 ++- axi_sysace/data/axi_sysace.tcl | 3 ++- axi_tft/data/axi_tft.mdd | 3 ++- axi_tft/data/axi_tft.tcl | 3 ++- axi_timebase_wdt/data/axi_timebase_wdt.mdd | 3 ++- axi_timebase_wdt/data/axi_timebase_wdt.tcl | 3 ++- axi_traffic_gen/data/axi_traffic_gen.mdd | 3 ++- axi_traffic_gen/data/axi_traffic_gen.tcl | 3 ++- axi_usb2_device/data/axi_usb2_device.mdd | 3 ++- axi_usb2_device/data/axi_usb2_device.tcl | 3 ++- axi_vcu/data/axi_vcu.mdd | 3 ++- axi_vcu/data/axi_vcu.tcl | 3 ++- axi_vdma/data/axi_vdma.mdd | 3 ++- axi_vdma/data/axi_vdma.tcl | 5 +++-- axi_vdu/data/axi_vdu.mdd | 3 ++- axi_vdu/data/axi_vdu.tcl | 3 ++- axi_xadc/data/axi_xadc.mdd | 3 ++- axi_xadc/data/axi_xadc.tcl | 3 ++- axis_switch/data/axis_switch.mdd | 3 ++- axis_switch/data/axis_switch.tcl | 3 ++- canfdps/data/canfdps.mdd | 3 ++- canfdps/data/canfdps.tcl | 3 ++- canps/data/canps.mdd | 3 ++- canps/data/canps.tcl | 3 ++- cpu/data/cpu.mdd | 3 ++- cpu/data/cpu.tcl | 5 +++-- cpu_cortexa53/data/cpu_cortexa53.mdd | 3 ++- cpu_cortexa53/data/cpu_cortexa53.tcl | 3 ++- cpu_cortexa72/data/cpu_cortexa72.mdd | 3 ++- cpu_cortexa72/data/cpu_cortexa72.tcl | 3 ++- cpu_cortexa78/data/cpu_cortexa78.mdd | 3 ++- cpu_cortexa78/data/cpu_cortexa78.tcl | 3 ++- cpu_cortexa9/data/cpu_cortexa9.mdd | 3 ++- cpu_cortexa9/data/cpu_cortexa9.tcl | 3 ++- ddrcps/data/ddrcps.mdd | 3 ++- ddrcps/data/ddrcps.tcl | 3 ++- ddrps/data/ddrps.mdd | 3 ++- ddrps/data/ddrps.tcl | 3 ++- ddrpsv/data/ddrpsv.mdd | 3 ++- ddrpsv/data/ddrpsv.tcl | 3 ++- debug_bridge/data/debug_bridge.mdd | 3 ++- debug_bridge/data/debug_bridge.tcl | 3 ++- demosaic/data/demosaic.mdd | 3 ++- demosaic/data/demosaic.tcl | 3 ++- devcfg/data/devcfg.mdd | 3 ++- devcfg/data/devcfg.tcl | 3 ++- device_tree/data/common_proc.tcl | 5 +++-- device_tree/data/device_tree.mld | 5 +++-- device_tree/data/device_tree.mss | 5 +++-- device_tree/data/device_tree.tcl | 5 +++-- device_tree/data/kernel_dtsi/2014.4/zynq/zynq-7000.dtsi | 3 ++- device_tree/data/kernel_dtsi/2015.1/zynq/zynq-7000.dtsi | 3 ++- device_tree/data/kernel_dtsi/2015.2/zynq/zynq-7000.dtsi | 3 ++- device_tree/data/kernel_dtsi/2015.3/zynq/zynq-7000.dtsi | 3 ++- device_tree/data/kernel_dtsi/2015.4/zynq/zynq-7000.dtsi | 3 ++- device_tree/data/kernel_dtsi/2015.4/zynqmp/zynqmp-clk.dtsi | 3 ++- device_tree/data/kernel_dtsi/2015.4/zynqmp/zynqmp.dtsi | 3 ++- device_tree/data/kernel_dtsi/2016.1/zynq/zynq-7000.dtsi | 3 ++- device_tree/data/kernel_dtsi/2016.1/zynqmp/zynqmp-clk.dtsi | 3 ++- device_tree/data/kernel_dtsi/2016.1/zynqmp/zynqmp.dtsi | 3 ++- device_tree/data/kernel_dtsi/2016.2/zynq/zynq-7000.dtsi | 3 ++- device_tree/data/kernel_dtsi/2016.2/zynqmp/zynqmp-clk.dtsi | 3 ++- device_tree/data/kernel_dtsi/2016.2/zynqmp/zynqmp.dtsi | 3 ++- device_tree/data/kernel_dtsi/2016.3/zynq/zynq-7000.dtsi | 3 ++- device_tree/data/kernel_dtsi/2016.3/zynqmp/zynqmp-clk.dtsi | 3 ++- device_tree/data/kernel_dtsi/2016.3/zynqmp/zynqmp.dtsi | 3 ++- device_tree/data/kernel_dtsi/2016.4/zynq/zynq-7000.dtsi | 3 ++- device_tree/data/kernel_dtsi/2016.4/zynqmp/zynqmp-clk.dtsi | 3 ++- device_tree/data/kernel_dtsi/2016.4/zynqmp/zynqmp.dtsi | 3 ++- device_tree/data/kernel_dtsi/2017.1/zynq/zynq-7000.dtsi | 3 ++- .../data/kernel_dtsi/2017.1/zynqmp/zynqmp-clk-ccf.dtsi | 3 ++- device_tree/data/kernel_dtsi/2017.1/zynqmp/zynqmp-clk.dtsi | 3 ++- device_tree/data/kernel_dtsi/2017.1/zynqmp/zynqmp.dtsi | 3 ++- device_tree/data/kernel_dtsi/2017.2/zynq/zynq-7000.dtsi | 3 ++- .../data/kernel_dtsi/2017.2/zynqmp/zynqmp-clk-ccf.dtsi | 3 ++- device_tree/data/kernel_dtsi/2017.2/zynqmp/zynqmp-clk.dtsi | 3 ++- device_tree/data/kernel_dtsi/2017.2/zynqmp/zynqmp.dtsi | 3 ++- device_tree/data/kernel_dtsi/2017.3/BOARD/zc1232-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2017.3/BOARD/zc1254-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2017.3/BOARD/zc1275-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2017.3/BOARD/zcu100-revc.dtsi | 3 ++- device_tree/data/kernel_dtsi/2017.3/BOARD/zcu104-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2017.3/zynq/zynq-7000.dtsi | 3 ++- .../data/kernel_dtsi/2017.3/zynqmp/zynqmp-clk-ccf.dtsi | 3 ++- device_tree/data/kernel_dtsi/2017.3/zynqmp/zynqmp-clk.dtsi | 3 ++- device_tree/data/kernel_dtsi/2017.3/zynqmp/zynqmp.dtsi | 3 ++- device_tree/data/kernel_dtsi/2017.4/BOARD/zc1232-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2017.4/BOARD/zc1254-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2017.4/BOARD/zc1275-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2017.4/BOARD/zcu100-revc.dtsi | 3 ++- device_tree/data/kernel_dtsi/2017.4/BOARD/zcu104-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2017.4/zynq/zynq-7000.dtsi | 3 ++- .../data/kernel_dtsi/2017.4/zynqmp/zynqmp-clk-ccf.dtsi | 3 ++- device_tree/data/kernel_dtsi/2017.4/zynqmp/zynqmp-clk.dtsi | 3 ++- device_tree/data/kernel_dtsi/2017.4/zynqmp/zynqmp.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.1/BOARD/zc1232-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.1/BOARD/zc1254-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.1/BOARD/zc1275-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.1/BOARD/zc1275-revb.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.1/BOARD/zcu100-revc.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.1/BOARD/zcu104-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.1/BOARD/zcu104-revc.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.1/BOARD/zcu111-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.1/zynq/zynq-7000.dtsi | 3 ++- .../data/kernel_dtsi/2018.1/zynqmp/zynqmp-clk-ccf.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.1/zynqmp/zynqmp.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.2/BOARD/zc1232-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.2/BOARD/zc1254-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.2/BOARD/zc1275-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.2/BOARD/zc1275-revb.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.2/BOARD/zc1751-dc1.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.2/BOARD/zc1751-dc2.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.2/BOARD/zc702.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.2/BOARD/zc706.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.2/BOARD/zcu100-revc.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.2/BOARD/zcu102-rev1.0.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.2/BOARD/zcu102-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.2/BOARD/zcu102-revb.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.2/BOARD/zcu104-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.2/BOARD/zcu104-revc.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.2/BOARD/zcu106-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.2/BOARD/zcu111-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.2/zynq/zynq-7000.dtsi | 3 ++- .../data/kernel_dtsi/2018.2/zynqmp/zynqmp-clk-ccf.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.2/zynqmp/zynqmp.dtsi | 3 ++- .../data/kernel_dtsi/2018.3/BOARD/avnet-ultra96-rev1.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.3/BOARD/zc1232-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.3/BOARD/zc1254-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.3/BOARD/zc1275-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.3/BOARD/zc1275-revb.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.3/BOARD/zc1751-dc1.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.3/BOARD/zc1751-dc2.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.3/BOARD/zc702.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.3/BOARD/zc706.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.3/BOARD/zcu100-revc.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.3/BOARD/zcu102-rev1.0.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.3/BOARD/zcu102-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.3/BOARD/zcu102-revb.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.3/BOARD/zcu104-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.3/BOARD/zcu104-revc.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.3/BOARD/zcu106-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.3/BOARD/zcu111-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.3/zynq/zynq-7000.dtsi | 3 ++- .../data/kernel_dtsi/2018.3/zynqmp/zynqmp-clk-ccf.dtsi | 3 ++- device_tree/data/kernel_dtsi/2018.3/zynqmp/zynqmp.dtsi | 3 ++- .../data/kernel_dtsi/2019.1/BOARD/avnet-ultra96-rev1.dtsi | 3 ++- .../data/kernel_dtsi/2019.1/BOARD/versal-a2197-sc-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2019.1/BOARD/zc1232-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2019.1/BOARD/zc1254-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2019.1/BOARD/zc1275-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2019.1/BOARD/zc1275-revb.dtsi | 3 ++- device_tree/data/kernel_dtsi/2019.1/BOARD/zc1751-dc1.dtsi | 3 ++- device_tree/data/kernel_dtsi/2019.1/BOARD/zc1751-dc2.dtsi | 3 ++- device_tree/data/kernel_dtsi/2019.1/BOARD/zc702.dtsi | 3 ++- device_tree/data/kernel_dtsi/2019.1/BOARD/zc706.dtsi | 3 ++- device_tree/data/kernel_dtsi/2019.1/BOARD/zcu100-revc.dtsi | 3 ++- device_tree/data/kernel_dtsi/2019.1/BOARD/zcu102-rev1.0.dtsi | 3 ++- device_tree/data/kernel_dtsi/2019.1/BOARD/zcu102-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2019.1/BOARD/zcu102-revb.dtsi | 3 ++- device_tree/data/kernel_dtsi/2019.1/BOARD/zcu104-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2019.1/BOARD/zcu104-revc.dtsi | 3 ++- device_tree/data/kernel_dtsi/2019.1/BOARD/zcu106-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2019.1/BOARD/zcu111-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2019.1/BOARD/zcu1285-reva.dtsi | 3 ++- .../data/kernel_dtsi/2019.1/BOARD/zynqmp-a2197-g-reva.dtsi | 3 ++- .../data/kernel_dtsi/2019.1/BOARD/zynqmp-a2197-m-reva.dtsi | 3 ++- .../data/kernel_dtsi/2019.1/BOARD/zynqmp-a2197-p-reva.dtsi | 3 ++- .../data/kernel_dtsi/2019.1/BOARD/zynqmp-a2197-reva.dtsi | 3 ++- .../2019.1/include/dt-bindings/pinctrl/pinctrl-zynqmp.h | 3 ++- device_tree/data/kernel_dtsi/2019.1/zynq/zynq-7000.dtsi | 3 ++- .../data/kernel_dtsi/2019.1/zynqmp/zynqmp-clk-ccf.dtsi | 3 ++- device_tree/data/kernel_dtsi/2019.1/zynqmp/zynqmp.dtsi | 3 ++- .../data/kernel_dtsi/2019.2/BOARD/avnet-ultra96-rev1.dtsi | 3 ++- .../data/kernel_dtsi/2019.2/BOARD/versal-v350-reva.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi | 3 ++- .../kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva.dtsi | 3 ++- .../2019.2/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi | 3 ++- .../data/kernel_dtsi/2019.2/BOARD/versal-vck190-reva.dtsi | 3 ++- .../2019.2/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi | 3 ++- .../data/kernel_dtsi/2019.2/BOARD/versal-vmk180-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2019.2/BOARD/zc1232-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2019.2/BOARD/zc1254-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2019.2/BOARD/zc1751-dc1.dtsi | 3 ++- device_tree/data/kernel_dtsi/2019.2/BOARD/zc1751-dc2.dtsi | 3 ++- device_tree/data/kernel_dtsi/2019.2/BOARD/zc702.dtsi | 3 ++- device_tree/data/kernel_dtsi/2019.2/BOARD/zc706.dtsi | 3 ++- device_tree/data/kernel_dtsi/2019.2/BOARD/zcu100-revc.dtsi | 3 ++- device_tree/data/kernel_dtsi/2019.2/BOARD/zcu102-rev1.0.dtsi | 3 ++- device_tree/data/kernel_dtsi/2019.2/BOARD/zcu102-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2019.2/BOARD/zcu102-revb.dtsi | 3 ++- device_tree/data/kernel_dtsi/2019.2/BOARD/zcu104-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2019.2/BOARD/zcu104-revc.dtsi | 3 ++- device_tree/data/kernel_dtsi/2019.2/BOARD/zcu106-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2019.2/BOARD/zcu111-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2019.2/BOARD/zcu1275-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2019.2/BOARD/zcu1275-revb.dtsi | 3 ++- device_tree/data/kernel_dtsi/2019.2/BOARD/zcu1285-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2019.2/BOARD/zcu216-reva.dtsi | 3 ++- .../data/kernel_dtsi/2019.2/BOARD/zynqmp-a2197-reva.dtsi | 3 ++- .../kernel_dtsi/2019.2/BOARD/zynqmp-e-a2197-00-reva.dtsi | 3 ++- .../2019.2/include/dt-bindings/pinctrl/pinctrl-zynqmp.h | 3 ++- device_tree/data/kernel_dtsi/2019.2/versal/versal-clk.dtsi | 3 ++- device_tree/data/kernel_dtsi/2019.2/versal/versal.dtsi | 3 ++- device_tree/data/kernel_dtsi/2019.2/zynq/zynq-7000.dtsi | 3 ++- .../data/kernel_dtsi/2019.2/zynqmp/zynqmp-clk-ccf.dtsi | 3 ++- device_tree/data/kernel_dtsi/2019.2/zynqmp/zynqmp.dtsi | 3 ++- .../data/kernel_dtsi/2020.1/BOARD/avnet-ultra96-rev1.dtsi | 3 ++- .../data/kernel_dtsi/2020.1/BOARD/versal-a2197-sc-reva.dtsi | 3 ++- .../kernel_dtsi/2020.1/BOARD/versal-spp-itr8-cn13940875.dtsi | 3 ++- .../data/kernel_dtsi/2020.1/BOARD/versal-v350-reva.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi | 3 ++- .../kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva.dtsi | 3 ++- .../2020.1/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi | 3 ++- .../2020.1/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi | 3 ++- .../2020.1/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi | 3 ++- .../data/kernel_dtsi/2020.1/BOARD/versal-vck190-reva.dtsi | 3 ++- .../2020.1/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi | 3 ++- .../2020.1/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi | 3 ++- .../2020.1/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi | 3 ++- .../data/kernel_dtsi/2020.1/BOARD/versal-vmk180-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2020.1/BOARD/zc1232-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2020.1/BOARD/zc1254-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2020.1/BOARD/zc1751-dc1.dtsi | 3 ++- device_tree/data/kernel_dtsi/2020.1/BOARD/zc1751-dc2.dtsi | 3 ++- device_tree/data/kernel_dtsi/2020.1/BOARD/zc702.dtsi | 3 ++- device_tree/data/kernel_dtsi/2020.1/BOARD/zc706.dtsi | 3 ++- device_tree/data/kernel_dtsi/2020.1/BOARD/zcu100-revc.dtsi | 3 ++- device_tree/data/kernel_dtsi/2020.1/BOARD/zcu102-rev1.0.dtsi | 3 ++- device_tree/data/kernel_dtsi/2020.1/BOARD/zcu102-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2020.1/BOARD/zcu102-revb.dtsi | 3 ++- device_tree/data/kernel_dtsi/2020.1/BOARD/zcu104-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2020.1/BOARD/zcu104-revc.dtsi | 3 ++- device_tree/data/kernel_dtsi/2020.1/BOARD/zcu106-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2020.1/BOARD/zcu111-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2020.1/BOARD/zcu1275-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2020.1/BOARD/zcu1275-revb.dtsi | 3 ++- device_tree/data/kernel_dtsi/2020.1/BOARD/zcu1285-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2020.1/BOARD/zcu208-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2020.1/BOARD/zcu216-reva.dtsi | 3 ++- .../data/kernel_dtsi/2020.1/BOARD/zynqmp-a2197-reva.dtsi | 3 ++- .../kernel_dtsi/2020.1/BOARD/zynqmp-e-a2197-00-reva.dtsi | 3 ++- .../kernel_dtsi/2020.1/BOARD/zynqmp-g-a2197-00-reva.dtsi | 3 ++- .../kernel_dtsi/2020.1/BOARD/zynqmp-m-a2197-01-reva.dtsi | 3 ++- .../kernel_dtsi/2020.1/BOARD/zynqmp-m-a2197-02-reva.dtsi | 3 ++- .../kernel_dtsi/2020.1/BOARD/zynqmp-m-a2197-03-reva.dtsi | 3 ++- .../2020.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi | 3 ++- .../2020.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi | 3 ++- .../2020.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi | 3 ++- .../2020.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi | 3 ++- .../2020.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi | 3 ++- .../kernel_dtsi/2020.1/BOARD/zynqmp-p-a2197-00-reva.dtsi | 3 ++- .../2020.1/include/dt-bindings/clock/xlnx-versal-clk.h | 3 ++- .../2020.1/include/dt-bindings/clock/xlnx-zynqmp-clk.h | 3 ++- .../2020.1/include/dt-bindings/pinctrl/pinctrl-zynqmp.h | 3 ++- .../2020.1/include/dt-bindings/power/xlnx-versal-power.h | 3 ++- .../2020.1/include/dt-bindings/power/xlnx-zynqmp-power.h | 3 ++- .../2020.1/include/dt-bindings/reset/xlnx-zynqmp-resets.h | 3 ++- device_tree/data/kernel_dtsi/2020.1/versal/versal-clk.dtsi | 3 ++- .../data/kernel_dtsi/2020.1/versal/versal-spp-pm.dtsi | 3 ++- device_tree/data/kernel_dtsi/2020.1/versal/versal.dtsi | 3 ++- device_tree/data/kernel_dtsi/2020.1/zynq/zynq-7000.dtsi | 3 ++- .../data/kernel_dtsi/2020.1/zynqmp/zynqmp-clk-ccf.dtsi | 3 ++- device_tree/data/kernel_dtsi/2020.1/zynqmp/zynqmp.dtsi | 3 ++- .../data/kernel_dtsi/2020.2/BOARD/avnet-ultra96-rev1.dtsi | 3 ++- .../data/kernel_dtsi/2020.2/BOARD/versal-a2197-sc-reva.dtsi | 3 ++- .../kernel_dtsi/2020.2/BOARD/versal-spp-itr8-cn13940875.dtsi | 3 ++- .../data/kernel_dtsi/2020.2/BOARD/versal-v350-reva.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi | 3 ++- .../kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva.dtsi | 3 ++- .../2020.2/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi | 3 ++- .../2020.2/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi | 3 ++- .../2020.2/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi | 3 ++- .../data/kernel_dtsi/2020.2/BOARD/versal-vck190-reva.dtsi | 3 ++- .../data/kernel_dtsi/2020.2/BOARD/versal-vck5000-reva.dtsi | 3 ++- .../2020.2/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi | 3 ++- .../2020.2/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi | 3 ++- .../2020.2/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi | 3 ++- .../data/kernel_dtsi/2020.2/BOARD/versal-vmk180-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2020.2/BOARD/zc1232-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2020.2/BOARD/zc1254-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2020.2/BOARD/zc1751-dc1.dtsi | 3 ++- device_tree/data/kernel_dtsi/2020.2/BOARD/zc1751-dc2.dtsi | 3 ++- device_tree/data/kernel_dtsi/2020.2/BOARD/zc702.dtsi | 3 ++- device_tree/data/kernel_dtsi/2020.2/BOARD/zc706.dtsi | 3 ++- device_tree/data/kernel_dtsi/2020.2/BOARD/zcu100-revc.dtsi | 3 ++- device_tree/data/kernel_dtsi/2020.2/BOARD/zcu102-rev1.0.dtsi | 3 ++- device_tree/data/kernel_dtsi/2020.2/BOARD/zcu102-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2020.2/BOARD/zcu102-revb.dtsi | 3 ++- device_tree/data/kernel_dtsi/2020.2/BOARD/zcu104-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2020.2/BOARD/zcu104-revc.dtsi | 3 ++- device_tree/data/kernel_dtsi/2020.2/BOARD/zcu106-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2020.2/BOARD/zcu111-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2020.2/BOARD/zcu1275-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2020.2/BOARD/zcu1275-revb.dtsi | 3 ++- device_tree/data/kernel_dtsi/2020.2/BOARD/zcu1285-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2020.2/BOARD/zcu208-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2020.2/BOARD/zcu216-reva.dtsi | 3 ++- .../data/kernel_dtsi/2020.2/BOARD/zynqmp-a2197-reva.dtsi | 3 ++- .../kernel_dtsi/2020.2/BOARD/zynqmp-e-a2197-00-reva.dtsi | 3 ++- .../kernel_dtsi/2020.2/BOARD/zynqmp-g-a2197-00-reva.dtsi | 3 ++- .../kernel_dtsi/2020.2/BOARD/zynqmp-m-a2197-01-reva.dtsi | 3 ++- .../kernel_dtsi/2020.2/BOARD/zynqmp-m-a2197-02-reva.dtsi | 3 ++- .../kernel_dtsi/2020.2/BOARD/zynqmp-m-a2197-03-reva.dtsi | 3 ++- .../2020.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi | 3 ++- .../2020.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi | 3 ++- .../2020.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi | 3 ++- .../2020.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi | 3 ++- .../2020.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi | 3 ++- .../kernel_dtsi/2020.2/BOARD/zynqmp-p-a2197-00-reva.dtsi | 3 ++- .../2020.2/include/dt-bindings/clock/xlnx-versal-clk.h | 3 ++- .../2020.2/include/dt-bindings/clock/xlnx-zynqmp-clk.h | 3 ++- .../2020.2/include/dt-bindings/pinctrl/pinctrl-zynqmp.h | 3 ++- .../2020.2/include/dt-bindings/power/xlnx-versal-power.h | 3 ++- .../2020.2/include/dt-bindings/power/xlnx-zynqmp-power.h | 3 ++- .../2020.2/include/dt-bindings/reset/xlnx-zynqmp-resets.h | 3 ++- device_tree/data/kernel_dtsi/2020.2/versal/versal-clk.dtsi | 3 ++- .../data/kernel_dtsi/2020.2/versal/versal-spp-pm.dtsi | 3 ++- device_tree/data/kernel_dtsi/2020.2/versal/versal.dtsi | 3 ++- device_tree/data/kernel_dtsi/2020.2/zynq/zynq-7000.dtsi | 3 ++- .../data/kernel_dtsi/2020.2/zynqmp/zynqmp-clk-ccf.dtsi | 3 ++- device_tree/data/kernel_dtsi/2020.2/zynqmp/zynqmp.dtsi | 3 ++- .../data/kernel_dtsi/2021.1/BOARD/avnet-ultra96-rev1.dtsi | 3 ++- .../data/kernel_dtsi/2021.1/BOARD/versal-a2197-sc-reva.dtsi | 3 ++- .../kernel_dtsi/2021.1/BOARD/versal-spp-itr8-cn13940875.dtsi | 3 ++- .../data/kernel_dtsi/2021.1/BOARD/versal-v350-reva.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi | 3 ++- .../kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva.dtsi | 3 ++- .../2021.1/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi | 3 ++- .../2021.1/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi | 3 ++- .../2021.1/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi | 3 ++- .../data/kernel_dtsi/2021.1/BOARD/versal-vck190-reva.dtsi | 3 ++- .../data/kernel_dtsi/2021.1/BOARD/versal-vck5000-reva.dtsi | 3 ++- .../2021.1/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi | 3 ++- .../2021.1/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi | 3 ++- .../2021.1/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi | 3 ++- .../data/kernel_dtsi/2021.1/BOARD/versal-vmk180-reva.dtsi | 3 ++- .../kernel_dtsi/2021.1/BOARD/versal-vp-x-a2785-00-reva.dtsi | 3 ++- .../data/kernel_dtsi/2021.1/BOARD/versal-vpk120-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.1/BOARD/zc1232-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.1/BOARD/zc1254-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.1/BOARD/zc1751-dc1.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.1/BOARD/zc1751-dc2.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.1/BOARD/zc702.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.1/BOARD/zc706.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.1/BOARD/zcu100-revc.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.1/BOARD/zcu102-rev1.0.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.1/BOARD/zcu102-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.1/BOARD/zcu102-revb.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.1/BOARD/zcu104-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.1/BOARD/zcu104-revc.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.1/BOARD/zcu106-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.1/BOARD/zcu111-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.1/BOARD/zcu1275-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.1/BOARD/zcu1275-revb.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.1/BOARD/zcu1285-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.1/BOARD/zcu208-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.1/BOARD/zcu216-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.1/BOARD/zcu670-reva.dtsi | 3 ++- .../data/kernel_dtsi/2021.1/BOARD/zynqmp-a2197-reva.dtsi | 3 ++- .../kernel_dtsi/2021.1/BOARD/zynqmp-e-a2197-00-reva.dtsi | 3 ++- .../kernel_dtsi/2021.1/BOARD/zynqmp-g-a2197-00-reva.dtsi | 3 ++- .../kernel_dtsi/2021.1/BOARD/zynqmp-m-a2197-01-reva.dtsi | 3 ++- .../kernel_dtsi/2021.1/BOARD/zynqmp-m-a2197-02-reva.dtsi | 3 ++- .../kernel_dtsi/2021.1/BOARD/zynqmp-m-a2197-03-reva.dtsi | 3 ++- .../2021.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi | 3 ++- .../2021.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi | 3 ++- .../2021.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi | 3 ++- .../2021.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi | 3 ++- .../2021.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi | 3 ++- .../kernel_dtsi/2021.1/BOARD/zynqmp-p-a2197-00-reva.dtsi | 3 ++- .../kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-reva-mlcc.dtsi | 3 ++- .../data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-reva.dtsi | 3 ++- .../kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-reva01-mlcc.dtsi | 3 ++- .../data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-reva01.dtsi | 3 ++- .../kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-revb-mlcc.dtsi | 3 ++- .../data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-revb.dtsi | 3 ++- .../kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-revb01-mlcc.dtsi | 3 ++- .../data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-revb01.dtsi | 3 ++- .../data/kernel_dtsi/2021.1/BOARD/zynqmp-smk-k26-reva.dtsi | 3 ++- .../kernel_dtsi/2021.1/BOARD/zynqmp-vp-x-a2785-00-reva.dtsi | 3 ++- .../data/kernel_dtsi/2021.1/BOARD/zynqmp-vpk120-reva.dtsi | 3 ++- .../2021.1/include/dt-bindings/clock/xlnx-versal-clk.h | 3 ++- .../2021.1/include/dt-bindings/clock/xlnx-zynqmp-clk.h | 3 ++- .../2021.1/include/dt-bindings/pinctrl/pinctrl-zynqmp.h | 3 ++- .../2021.1/include/dt-bindings/power/xlnx-versal-power.h | 3 ++- .../2021.1/include/dt-bindings/power/xlnx-zynqmp-power.h | 3 ++- .../2021.1/include/dt-bindings/reset/xlnx-zynqmp-resets.h | 3 ++- device_tree/data/kernel_dtsi/2021.1/versal/versal-clk.dtsi | 3 ++- .../data/kernel_dtsi/2021.1/versal/versal-spp-pm.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.1/versal/versal.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.1/zynq/zynq-7000.dtsi | 3 ++- .../data/kernel_dtsi/2021.1/zynqmp/zynqmp-clk-ccf.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.1/zynqmp/zynqmp.dtsi | 3 ++- .../data/kernel_dtsi/2021.2/BOARD/avnet-ultra96-rev1.dtsi | 3 ++- .../data/kernel_dtsi/2021.2/BOARD/versal-a2197-sc-reva.dtsi | 3 ++- .../kernel_dtsi/2021.2/BOARD/versal-spp-itr8-cn13940875.dtsi | 3 ++- .../data/kernel_dtsi/2021.2/BOARD/versal-v350-reva.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi | 3 ++- .../kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva.dtsi | 3 ++- .../2021.2/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi | 3 ++- .../2021.2/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi | 3 ++- .../2021.2/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi | 3 ++- .../data/kernel_dtsi/2021.2/BOARD/versal-vck190-reva.dtsi | 3 ++- .../data/kernel_dtsi/2021.2/BOARD/versal-vck5000-reva.dtsi | 3 ++- .../2021.2/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi | 3 ++- .../2021.2/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi | 3 ++- .../2021.2/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi | 3 ++- .../data/kernel_dtsi/2021.2/BOARD/versal-vmk180-reva.dtsi | 3 ++- .../kernel_dtsi/2021.2/BOARD/versal-vp-x-a2785-00-reva.dtsi | 3 ++- .../data/kernel_dtsi/2021.2/BOARD/versal-vpk120-reva.dtsi | 3 ++- .../data/kernel_dtsi/2021.2/BOARD/versal-vpk120-revb.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.2/BOARD/zc1232-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.2/BOARD/zc1254-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.2/BOARD/zc1751-dc1.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.2/BOARD/zc1751-dc2.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.2/BOARD/zc702.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.2/BOARD/zc706.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.2/BOARD/zcu100-revc.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.2/BOARD/zcu102-rev1.0.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.2/BOARD/zcu102-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.2/BOARD/zcu102-revb.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.2/BOARD/zcu104-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.2/BOARD/zcu104-revc.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.2/BOARD/zcu106-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.2/BOARD/zcu111-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.2/BOARD/zcu1275-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.2/BOARD/zcu1275-revb.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.2/BOARD/zcu1285-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.2/BOARD/zcu208-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.2/BOARD/zcu216-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.2/BOARD/zcu670-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.2/BOARD/zcu670-revb.dtsi | 3 ++- .../data/kernel_dtsi/2021.2/BOARD/zynqmp-a2197-reva.dtsi | 3 ++- .../kernel_dtsi/2021.2/BOARD/zynqmp-e-a2197-00-reva.dtsi | 3 ++- .../kernel_dtsi/2021.2/BOARD/zynqmp-g-a2197-00-reva.dtsi | 3 ++- .../kernel_dtsi/2021.2/BOARD/zynqmp-m-a2197-01-reva.dtsi | 3 ++- .../kernel_dtsi/2021.2/BOARD/zynqmp-m-a2197-02-reva.dtsi | 3 ++- .../kernel_dtsi/2021.2/BOARD/zynqmp-m-a2197-03-reva.dtsi | 3 ++- .../2021.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi | 3 ++- .../2021.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi | 3 ++- .../2021.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi | 3 ++- .../2021.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi | 3 ++- .../2021.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi | 3 ++- .../kernel_dtsi/2021.2/BOARD/zynqmp-p-a2197-00-reva.dtsi | 3 ++- .../data/kernel_dtsi/2021.2/BOARD/zynqmp-sc-revb.dtsi | 3 ++- .../data/kernel_dtsi/2021.2/BOARD/zynqmp-sm-k26-reva.dtsi | 3 ++- .../data/kernel_dtsi/2021.2/BOARD/zynqmp-smk-k26-reva.dtsi | 3 ++- .../kernel_dtsi/2021.2/BOARD/zynqmp-vp-x-a2785-00-reva.dtsi | 3 ++- .../data/kernel_dtsi/2021.2/BOARD/zynqmp-vpk120-reva.dtsi | 3 ++- .../2021.2/include/dt-bindings/clock/xlnx-versal-clk.h | 3 ++- .../2021.2/include/dt-bindings/clock/xlnx-zynqmp-clk.h | 3 ++- .../2021.2/include/dt-bindings/pinctrl/pinctrl-zynqmp.h | 3 ++- .../2021.2/include/dt-bindings/power/xlnx-versal-power.h | 3 ++- .../2021.2/include/dt-bindings/power/xlnx-zynqmp-power.h | 3 ++- .../2021.2/include/dt-bindings/reset/xlnx-zynqmp-resets.h | 3 ++- device_tree/data/kernel_dtsi/2021.2/versal/versal-clk.dtsi | 3 ++- .../data/kernel_dtsi/2021.2/versal/versal-spp-pm.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.2/versal/versal.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.2/zynq/zynq-7000.dtsi | 3 ++- .../data/kernel_dtsi/2021.2/zynqmp/zynqmp-clk-ccf.dtsi | 3 ++- device_tree/data/kernel_dtsi/2021.2/zynqmp/zynqmp.dtsi | 3 ++- .../data/kernel_dtsi/2022.1/BOARD/avnet-ultra96-rev1.dtsi | 3 ++- .../data/kernel_dtsi/2022.1/BOARD/versal-a2197-sc-reva.dtsi | 3 ++- .../kernel_dtsi/2022.1/BOARD/versal-spp-itr8-cn13940875.dtsi | 3 ++- .../data/kernel_dtsi/2022.1/BOARD/versal-v350-reva.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi | 3 ++- .../kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva.dtsi | 3 ++- .../2022.1/BOARD/versal-vck190-rev1.1-x-ebm-01-reva.dtsi | 3 ++- .../2022.1/BOARD/versal-vck190-rev1.1-x-ebm-02-reva.dtsi | 3 ++- .../2022.1/BOARD/versal-vck190-rev1.1-x-ebm-03-reva.dtsi | 3 ++- .../data/kernel_dtsi/2022.1/BOARD/versal-vck190-rev1.1.dtsi | 3 ++- .../2022.1/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi | 3 ++- .../2022.1/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi | 3 ++- .../2022.1/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi | 3 ++- .../data/kernel_dtsi/2022.1/BOARD/versal-vck190-reva.dtsi | 3 ++- .../data/kernel_dtsi/2022.1/BOARD/versal-vck5000-reva.dtsi | 3 ++- .../data/kernel_dtsi/2022.1/BOARD/versal-vhk158-reva.dtsi | 3 ++- .../2022.1/BOARD/versal-vmk180-rev1.1-x-ebm-01-reva.dtsi | 3 ++- .../2022.1/BOARD/versal-vmk180-rev1.1-x-ebm-02-reva.dtsi | 3 ++- .../2022.1/BOARD/versal-vmk180-rev1.1-x-ebm-03-reva.dtsi | 3 ++- .../data/kernel_dtsi/2022.1/BOARD/versal-vmk180-rev1.1.dtsi | 3 ++- .../2022.1/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi | 3 ++- .../2022.1/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi | 3 ++- .../2022.1/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi | 3 ++- .../data/kernel_dtsi/2022.1/BOARD/versal-vmk180-reva.dtsi | 3 ++- .../kernel_dtsi/2022.1/BOARD/versal-vp-x-a2785-00-reva.dtsi | 3 ++- .../data/kernel_dtsi/2022.1/BOARD/versal-vpk120-reva.dtsi | 3 ++- .../data/kernel_dtsi/2022.1/BOARD/versal-vpk120-revb.dtsi | 3 ++- .../data/kernel_dtsi/2022.1/BOARD/versal-vpk180-reva.dtsi | 3 ++- .../data/kernel_dtsi/2022.1/BOARD/versal-x-ebm-01-reva.dtsi | 3 ++- .../data/kernel_dtsi/2022.1/BOARD/versal-x-ebm-02-reva.dtsi | 3 ++- .../data/kernel_dtsi/2022.1/BOARD/versal-x-ebm-03-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.1/BOARD/zc1232-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.1/BOARD/zc1254-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.1/BOARD/zc1751-dc1.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.1/BOARD/zc1751-dc2.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.1/BOARD/zc702.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.1/BOARD/zc706.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.1/BOARD/zcu100-revc.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.1/BOARD/zcu102-rev1.0.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.1/BOARD/zcu102-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.1/BOARD/zcu102-revb.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.1/BOARD/zcu104-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.1/BOARD/zcu104-revc.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.1/BOARD/zcu106-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.1/BOARD/zcu111-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.1/BOARD/zcu1275-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.1/BOARD/zcu1275-revb.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.1/BOARD/zcu1285-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.1/BOARD/zcu208-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.1/BOARD/zcu216-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.1/BOARD/zcu670-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.1/BOARD/zcu670-revb.dtsi | 3 ++- .../data/kernel_dtsi/2022.1/BOARD/zynqmp-a2197-reva.dtsi | 3 ++- .../kernel_dtsi/2022.1/BOARD/zynqmp-e-a2197-00-reva.dtsi | 3 ++- .../kernel_dtsi/2022.1/BOARD/zynqmp-g-a2197-00-reva.dtsi | 3 ++- .../kernel_dtsi/2022.1/BOARD/zynqmp-m-a2197-01-reva.dtsi | 3 ++- .../kernel_dtsi/2022.1/BOARD/zynqmp-m-a2197-02-reva.dtsi | 3 ++- .../kernel_dtsi/2022.1/BOARD/zynqmp-m-a2197-03-reva.dtsi | 3 ++- .../2022.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi | 3 ++- .../2022.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi | 3 ++- .../2022.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi | 3 ++- .../2022.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi | 3 ++- .../2022.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi | 3 ++- .../kernel_dtsi/2022.1/BOARD/zynqmp-p-a2197-00-reva.dtsi | 3 ++- .../data/kernel_dtsi/2022.1/BOARD/zynqmp-sc-revb.dtsi | 3 ++- .../data/kernel_dtsi/2022.1/BOARD/zynqmp-sm-k26-reva.dtsi | 3 ++- .../data/kernel_dtsi/2022.1/BOARD/zynqmp-smk-k26-reva.dtsi | 3 ++- .../kernel_dtsi/2022.1/BOARD/zynqmp-vp-x-a2785-00-reva.dtsi | 3 ++- .../data/kernel_dtsi/2022.1/BOARD/zynqmp-vpk120-reva.dtsi | 3 ++- .../2022.1/include/dt-bindings/clock/xlnx-versal-clk.h | 3 ++- .../2022.1/include/dt-bindings/clock/xlnx-zynqmp-clk.h | 3 ++- .../2022.1/include/dt-bindings/pinctrl/pinctrl-zynqmp.h | 3 ++- .../2022.1/include/dt-bindings/power/xlnx-versal-power.h | 3 ++- .../2022.1/include/dt-bindings/power/xlnx-zynqmp-power.h | 3 ++- .../2022.1/include/dt-bindings/reset/xlnx-zynqmp-resets.h | 3 ++- device_tree/data/kernel_dtsi/2022.1/versal/versal-clk.dtsi | 3 ++- .../data/kernel_dtsi/2022.1/versal/versal-spp-pm.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.1/versal/versal.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.1/zynq/zynq-7000.dtsi | 3 ++- .../data/kernel_dtsi/2022.1/zynqmp/zynqmp-clk-ccf.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.1/zynqmp/zynqmp.dtsi | 3 ++- .../data/kernel_dtsi/2022.2/BOARD/avnet-ultra96-rev1.dtsi | 3 ++- .../data/kernel_dtsi/2022.2/BOARD/versal-a2197-sc-reva.dtsi | 3 ++- .../data/kernel_dtsi/2022.2/BOARD/versal-net-emu-rev1.9.dtsi | 3 ++- .../kernel_dtsi/2022.2/BOARD/versal-net-ipp-rev1.9-ospi.dtsi | 3 ++- .../data/kernel_dtsi/2022.2/BOARD/versal-net-ipp-rev1.9.dtsi | 3 ++- .../kernel_dtsi/2022.2/BOARD/versal-spp-itr8-cn13940875.dtsi | 3 ++- .../data/kernel_dtsi/2022.2/BOARD/versal-v350-reva.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi | 3 ++- .../kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva.dtsi | 3 ++- .../2022.2/BOARD/versal-vck190-rev1.1-x-ebm-01-reva.dtsi | 3 ++- .../2022.2/BOARD/versal-vck190-rev1.1-x-ebm-02-reva.dtsi | 3 ++- .../2022.2/BOARD/versal-vck190-rev1.1-x-ebm-03-reva.dtsi | 3 ++- .../data/kernel_dtsi/2022.2/BOARD/versal-vck190-rev1.1.dtsi | 3 ++- .../2022.2/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi | 3 ++- .../2022.2/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi | 3 ++- .../2022.2/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi | 3 ++- .../data/kernel_dtsi/2022.2/BOARD/versal-vck190-reva.dtsi | 3 ++- .../data/kernel_dtsi/2022.2/BOARD/versal-vck5000-reva.dtsi | 3 ++- .../data/kernel_dtsi/2022.2/BOARD/versal-vhk158-reva.dtsi | 3 ++- .../2022.2/BOARD/versal-vmk180-rev1.1-x-ebm-01-reva.dtsi | 3 ++- .../2022.2/BOARD/versal-vmk180-rev1.1-x-ebm-02-reva.dtsi | 3 ++- .../2022.2/BOARD/versal-vmk180-rev1.1-x-ebm-03-reva.dtsi | 3 ++- .../data/kernel_dtsi/2022.2/BOARD/versal-vmk180-rev1.1.dtsi | 3 ++- .../2022.2/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi | 3 ++- .../2022.2/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi | 3 ++- .../2022.2/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi | 3 ++- .../data/kernel_dtsi/2022.2/BOARD/versal-vmk180-reva.dtsi | 3 ++- .../kernel_dtsi/2022.2/BOARD/versal-vp-x-a2785-00-reva.dtsi | 3 ++- .../data/kernel_dtsi/2022.2/BOARD/versal-vpk120-reva.dtsi | 3 ++- .../data/kernel_dtsi/2022.2/BOARD/versal-vpk120-revb.dtsi | 3 ++- .../data/kernel_dtsi/2022.2/BOARD/versal-vpk180-reva.dtsi | 3 ++- .../data/kernel_dtsi/2022.2/BOARD/versal-x-ebm-01-reva.dtsi | 3 ++- .../data/kernel_dtsi/2022.2/BOARD/versal-x-ebm-02-reva.dtsi | 3 ++- .../data/kernel_dtsi/2022.2/BOARD/versal-x-ebm-03-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.2/BOARD/zc1232-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.2/BOARD/zc1254-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.2/BOARD/zc1751-dc1.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.2/BOARD/zc1751-dc2.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.2/BOARD/zc702.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.2/BOARD/zc706.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.2/BOARD/zcu100-revc.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.2/BOARD/zcu102-rev1.0.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.2/BOARD/zcu102-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.2/BOARD/zcu102-revb.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.2/BOARD/zcu104-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.2/BOARD/zcu104-revc.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.2/BOARD/zcu106-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.2/BOARD/zcu111-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.2/BOARD/zcu1275-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.2/BOARD/zcu1275-revb.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.2/BOARD/zcu1285-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.2/BOARD/zcu208-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.2/BOARD/zcu216-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.2/BOARD/zcu670-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.2/BOARD/zcu670-revb.dtsi | 3 ++- .../data/kernel_dtsi/2022.2/BOARD/zynqmp-a2197-reva.dtsi | 3 ++- .../kernel_dtsi/2022.2/BOARD/zynqmp-e-a2197-00-reva.dtsi | 3 ++- .../kernel_dtsi/2022.2/BOARD/zynqmp-e-a2197-00-revb.dtsi | 3 ++- .../kernel_dtsi/2022.2/BOARD/zynqmp-g-a2197-00-reva.dtsi | 3 ++- .../kernel_dtsi/2022.2/BOARD/zynqmp-m-a2197-01-reva.dtsi | 3 ++- .../kernel_dtsi/2022.2/BOARD/zynqmp-m-a2197-02-reva.dtsi | 3 ++- .../kernel_dtsi/2022.2/BOARD/zynqmp-m-a2197-03-reva.dtsi | 3 ++- .../2022.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi | 3 ++- .../2022.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi | 3 ++- .../2022.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi | 3 ++- .../2022.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi | 3 ++- .../2022.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi | 3 ++- .../kernel_dtsi/2022.2/BOARD/zynqmp-p-a2197-00-reva.dtsi | 3 ++- .../data/kernel_dtsi/2022.2/BOARD/zynqmp-sc-revb.dtsi | 3 ++- .../data/kernel_dtsi/2022.2/BOARD/zynqmp-sm-k26-reva.dtsi | 3 ++- .../data/kernel_dtsi/2022.2/BOARD/zynqmp-smk-k26-reva.dtsi | 3 ++- .../kernel_dtsi/2022.2/BOARD/zynqmp-vp-x-a2785-00-reva.dtsi | 3 ++- .../data/kernel_dtsi/2022.2/BOARD/zynqmp-vpk120-reva.dtsi | 3 ++- .../2022.2/include/dt-bindings/clock/xlnx-versal-clk.h | 3 ++- .../2022.2/include/dt-bindings/clock/xlnx-zynqmp-clk.h | 3 ++- .../2022.2/include/dt-bindings/pinctrl/pinctrl-zynqmp.h | 3 ++- .../2022.2/include/dt-bindings/power/xlnx-versal-net-power.h | 3 ++- .../2022.2/include/dt-bindings/power/xlnx-versal-power.h | 3 ++- .../2022.2/include/dt-bindings/power/xlnx-versal-regnode.h | 3 ++- .../2022.2/include/dt-bindings/power/xlnx-zynqmp-power.h | 3 ++- .../include/dt-bindings/reset/xlnx-versal-net-resets.h | 3 ++- .../2022.2/include/dt-bindings/reset/xlnx-versal-resets.h | 3 ++- .../2022.2/include/dt-bindings/reset/xlnx-zynqmp-resets.h | 3 ++- .../kernel_dtsi/2022.2/versal-net/versal-net-ipp-rev1.9.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.2/versal/versal-clk.dtsi | 3 ++- .../data/kernel_dtsi/2022.2/versal/versal-spp-pm.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.2/versal/versal.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.2/zynq/zynq-7000.dtsi | 3 ++- .../data/kernel_dtsi/2022.2/zynqmp/zynqmp-clk-ccf.dtsi | 3 ++- device_tree/data/kernel_dtsi/2022.2/zynqmp/zynqmp.dtsi | 3 ++- .../data/kernel_dtsi/2023.1/BOARD/avnet-ultra96-rev1.dtsi | 3 ++- .../data/kernel_dtsi/2023.1/BOARD/versal-a2197-sc-reva.dtsi | 3 ++- .../data/kernel_dtsi/2023.1/BOARD/versal-net-emu-rev1.9.dtsi | 3 ++- .../kernel_dtsi/2023.1/BOARD/versal-net-ipp-rev1.9-ospi.dtsi | 3 ++- .../data/kernel_dtsi/2023.1/BOARD/versal-net-ipp-rev1.9.dtsi | 3 ++- .../kernel_dtsi/2023.1/BOARD/versal-spp-itr8-cn13940875.dtsi | 3 ++- .../data/kernel_dtsi/2023.1/BOARD/versal-v350-reva.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi | 3 ++- .../BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi | 3 ++- .../kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva.dtsi | 3 ++- .../2023.1/BOARD/versal-vck190-rev1.1-x-ebm-01-reva.dtsi | 3 ++- .../2023.1/BOARD/versal-vck190-rev1.1-x-ebm-02-reva.dtsi | 3 ++- .../2023.1/BOARD/versal-vck190-rev1.1-x-ebm-03-reva.dtsi | 3 ++- .../data/kernel_dtsi/2023.1/BOARD/versal-vck190-rev1.1.dtsi | 3 ++- .../2023.1/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi | 3 ++- .../2023.1/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi | 3 ++- .../2023.1/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi | 3 ++- .../data/kernel_dtsi/2023.1/BOARD/versal-vck190-reva.dtsi | 3 ++- .../data/kernel_dtsi/2023.1/BOARD/versal-vck5000-reva.dtsi | 3 ++- .../data/kernel_dtsi/2023.1/BOARD/versal-vhk158-reva.dtsi | 3 ++- .../2023.1/BOARD/versal-vmk180-rev1.1-x-ebm-01-reva.dtsi | 3 ++- .../2023.1/BOARD/versal-vmk180-rev1.1-x-ebm-02-reva.dtsi | 3 ++- .../2023.1/BOARD/versal-vmk180-rev1.1-x-ebm-03-reva.dtsi | 3 ++- .../data/kernel_dtsi/2023.1/BOARD/versal-vmk180-rev1.1.dtsi | 3 ++- .../2023.1/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi | 3 ++- .../2023.1/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi | 3 ++- .../2023.1/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi | 3 ++- .../data/kernel_dtsi/2023.1/BOARD/versal-vmk180-reva.dtsi | 3 ++- .../kernel_dtsi/2023.1/BOARD/versal-vp-x-a2785-00-reva.dtsi | 3 ++- .../data/kernel_dtsi/2023.1/BOARD/versal-vpk120-reva.dtsi | 3 ++- .../data/kernel_dtsi/2023.1/BOARD/versal-vpk120-revb.dtsi | 3 ++- .../data/kernel_dtsi/2023.1/BOARD/versal-vpk180-reva.dtsi | 3 ++- .../data/kernel_dtsi/2023.1/BOARD/versal-x-ebm-01-reva.dtsi | 3 ++- .../data/kernel_dtsi/2023.1/BOARD/versal-x-ebm-02-reva.dtsi | 3 ++- .../data/kernel_dtsi/2023.1/BOARD/versal-x-ebm-03-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2023.1/BOARD/zc1232-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2023.1/BOARD/zc1254-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2023.1/BOARD/zc1751-dc1.dtsi | 3 ++- device_tree/data/kernel_dtsi/2023.1/BOARD/zc1751-dc2.dtsi | 3 ++- device_tree/data/kernel_dtsi/2023.1/BOARD/zc702.dtsi | 3 ++- device_tree/data/kernel_dtsi/2023.1/BOARD/zc706.dtsi | 3 ++- device_tree/data/kernel_dtsi/2023.1/BOARD/zcu100-revc.dtsi | 3 ++- device_tree/data/kernel_dtsi/2023.1/BOARD/zcu102-rev1.0.dtsi | 3 ++- device_tree/data/kernel_dtsi/2023.1/BOARD/zcu102-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2023.1/BOARD/zcu102-revb.dtsi | 3 ++- device_tree/data/kernel_dtsi/2023.1/BOARD/zcu104-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2023.1/BOARD/zcu104-revc.dtsi | 3 ++- device_tree/data/kernel_dtsi/2023.1/BOARD/zcu106-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2023.1/BOARD/zcu111-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2023.1/BOARD/zcu1275-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2023.1/BOARD/zcu1275-revb.dtsi | 3 ++- device_tree/data/kernel_dtsi/2023.1/BOARD/zcu1285-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2023.1/BOARD/zcu208-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2023.1/BOARD/zcu216-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2023.1/BOARD/zcu670-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/2023.1/BOARD/zcu670-revb.dtsi | 3 ++- .../data/kernel_dtsi/2023.1/BOARD/zynqmp-a2197-reva.dtsi | 3 ++- .../kernel_dtsi/2023.1/BOARD/zynqmp-e-a2197-00-reva.dtsi | 3 ++- .../kernel_dtsi/2023.1/BOARD/zynqmp-e-a2197-00-revb.dtsi | 3 ++- .../kernel_dtsi/2023.1/BOARD/zynqmp-g-a2197-00-reva.dtsi | 3 ++- .../kernel_dtsi/2023.1/BOARD/zynqmp-m-a2197-01-reva.dtsi | 3 ++- .../kernel_dtsi/2023.1/BOARD/zynqmp-m-a2197-02-reva.dtsi | 3 ++- .../kernel_dtsi/2023.1/BOARD/zynqmp-m-a2197-03-reva.dtsi | 3 ++- .../2023.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi | 3 ++- .../2023.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi | 3 ++- .../2023.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi | 3 ++- .../2023.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi | 3 ++- .../2023.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi | 3 ++- .../kernel_dtsi/2023.1/BOARD/zynqmp-p-a2197-00-reva.dtsi | 3 ++- .../data/kernel_dtsi/2023.1/BOARD/zynqmp-sc-revb.dtsi | 3 ++- .../data/kernel_dtsi/2023.1/BOARD/zynqmp-sc-revc.dtsi | 4 ++-- .../data/kernel_dtsi/2023.1/BOARD/zynqmp-sm-k26-reva.dtsi | 3 ++- .../data/kernel_dtsi/2023.1/BOARD/zynqmp-smk-k26-reva.dtsi | 3 ++- .../kernel_dtsi/2023.1/BOARD/zynqmp-vp-x-a2785-00-reva.dtsi | 3 ++- .../data/kernel_dtsi/2023.1/BOARD/zynqmp-vpk120-reva.dtsi | 3 ++- .../2023.1/include/dt-bindings/clock/xlnx-versal-clk.h | 3 ++- .../2023.1/include/dt-bindings/clock/xlnx-versal-net-clk.h | 3 ++- .../2023.1/include/dt-bindings/clock/xlnx-zynqmp-clk.h | 3 ++- .../2023.1/include/dt-bindings/pinctrl/pinctrl-zynqmp.h | 3 ++- .../2023.1/include/dt-bindings/power/xlnx-versal-net-power.h | 3 ++- .../2023.1/include/dt-bindings/power/xlnx-versal-power.h | 3 ++- .../2023.1/include/dt-bindings/power/xlnx-versal-regnode.h | 3 ++- .../2023.1/include/dt-bindings/power/xlnx-zynqmp-power.h | 3 ++- .../include/dt-bindings/reset/xlnx-versal-net-resets.h | 3 ++- .../2023.1/include/dt-bindings/reset/xlnx-versal-resets.h | 3 ++- .../2023.1/include/dt-bindings/reset/xlnx-zynqmp-resets.h | 3 ++- .../kernel_dtsi/2023.1/versal-net/versal-net-ipp-rev1.9.dtsi | 3 ++- device_tree/data/kernel_dtsi/2023.1/versal/versal-clk.dtsi | 3 ++- .../data/kernel_dtsi/2023.1/versal/versal-spp-pm.dtsi | 3 ++- device_tree/data/kernel_dtsi/2023.1/versal/versal.dtsi | 3 ++- device_tree/data/kernel_dtsi/2023.1/zynq/zynq-7000.dtsi | 3 ++- .../data/kernel_dtsi/2023.1/zynqmp/zynqmp-clk-ccf.dtsi | 3 ++- device_tree/data/kernel_dtsi/2023.1/zynqmp/zynqmp.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.17/board/zc1232-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.17/board/zc1254-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.17/board/zc1275-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.17/board/zc1751-dc1.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.17/board/zc1751-dc2.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.17/board/zc1751-dc3.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.17/board/zc1751-dc4.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.17/board/zc1751-dc5.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.17/board/zcep108.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.17/board/zcu100-revc.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.17/board/zcu102-rev1.0.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.17/board/zcu102-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.17/board/zcu102-revb.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.17/board/zcu104-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.17/board/zcu106-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.17/board/zcu111-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.17/zynqmp/zynqmp-clk.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.17/zynqmp/zynqmp.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.18/board/zc1232-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.18/board/zc1254-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.18/board/zc1275-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.18/board/zc1751-dc1.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.18/board/zc1751-dc2.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.18/board/zc1751-dc3.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.18/board/zc1751-dc4.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.18/board/zc1751-dc5.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.18/board/zcu100-revc.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.18/board/zcu102-rev1.0.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.18/board/zcu102-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.18/board/zcu102-revb.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.18/board/zcu104-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.18/board/zcu106-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.18/board/zcu111-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.18/zynqmp/zynqmp-clk.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.18/zynqmp/zynqmp.dtsi | 3 ++- .../data/kernel_dtsi/v4.19/board/avnet-ultra96-rev1.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.19/board/zc1232-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.19/board/zc1254-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.19/board/zc1275-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.19/board/zc1751-dc1.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.19/board/zc1751-dc2.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.19/board/zc1751-dc3.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.19/board/zc1751-dc4.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.19/board/zc1751-dc5.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.19/board/zcu100-revc.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.19/board/zcu102-rev1.0.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.19/board/zcu102-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.19/board/zcu102-revb.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.19/board/zcu104-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.19/board/zcu106-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.19/board/zcu111-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.19/zynqmp/zynqmp-clk.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.19/zynqmp/zynqmp.dtsi | 3 ++- .../data/kernel_dtsi/v4.20/board/avnet-ultra96-rev1.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.20/board/zc1232-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.20/board/zc1254-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.20/board/zc1275-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.20/board/zc1751-dc1.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.20/board/zc1751-dc2.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.20/board/zc1751-dc3.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.20/board/zc1751-dc4.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.20/board/zc1751-dc5.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.20/board/zcu100-revc.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.20/board/zcu102-rev1.0.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.20/board/zcu102-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.20/board/zcu102-revb.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.20/board/zcu104-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.20/board/zcu106-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.20/board/zcu111-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.20/zynqmp/zynqmp-clk.dtsi | 3 ++- device_tree/data/kernel_dtsi/v4.20/zynqmp/zynqmp.dtsi | 3 ++- .../data/kernel_dtsi/v5.0/board/avnet-ultra96-rev1.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.0/board/zc1232-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.0/board/zc1254-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.0/board/zc1275-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.0/board/zc1751-dc1.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.0/board/zc1751-dc2.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.0/board/zc1751-dc3.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.0/board/zc1751-dc4.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.0/board/zc1751-dc5.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.0/board/zcu100-revc.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.0/board/zcu102-rev1.0.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.0/board/zcu102-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.0/board/zcu102-revb.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.0/board/zcu104-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.0/board/zcu106-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.0/board/zcu111-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.0/zynqmp/zynqmp-clk.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.0/zynqmp/zynqmp.dtsi | 3 ++- .../data/kernel_dtsi/v5.1/board/avnet-ultra96-rev1.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.1/board/zc1232-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.1/board/zc1254-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.1/board/zc1275-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.1/board/zc1751-dc1.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.1/board/zc1751-dc2.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.1/board/zc1751-dc3.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.1/board/zc1751-dc4.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.1/board/zc1751-dc5.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.1/board/zcu100-revc.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.1/board/zcu102-rev1.0.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.1/board/zcu102-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.1/board/zcu102-revb.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.1/board/zcu104-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.1/board/zcu106-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.1/board/zcu111-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.1/zynqmp/zynqmp-clk.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.1/zynqmp/zynqmp.dtsi | 3 ++- .../data/kernel_dtsi/v5.2/board/avnet-ultra96-rev1.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.2/board/zc1232-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.2/board/zc1254-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.2/board/zc1275-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.2/board/zc1751-dc1.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.2/board/zc1751-dc2.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.2/board/zc1751-dc3.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.2/board/zc1751-dc4.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.2/board/zc1751-dc5.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.2/board/zcu100-revc.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.2/board/zcu102-rev1.0.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.2/board/zcu102-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.2/board/zcu102-revb.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.2/board/zcu104-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.2/board/zcu106-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.2/board/zcu111-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.2/zynqmp/zynqmp-clk.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.2/zynqmp/zynqmp.dtsi | 3 ++- .../data/kernel_dtsi/v5.3/board/avnet-ultra96-rev1.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.3/board/zc1232-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.3/board/zc1254-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.3/board/zc1275-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.3/board/zc1751-dc1.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.3/board/zc1751-dc2.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.3/board/zc1751-dc3.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.3/board/zc1751-dc4.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.3/board/zc1751-dc5.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.3/board/zcu100-revc.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.3/board/zcu102-rev1.0.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.3/board/zcu102-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.3/board/zcu102-revb.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.3/board/zcu104-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.3/board/zcu106-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.3/board/zcu111-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.3/zynqmp/zynqmp-clk.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.3/zynqmp/zynqmp.dtsi | 3 ++- .../data/kernel_dtsi/v5.4/board/avnet-ultra96-rev1.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.4/board/zc1232-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.4/board/zc1254-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.4/board/zc1275-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.4/board/zc1751-dc1.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.4/board/zc1751-dc2.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.4/board/zc1751-dc3.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.4/board/zc1751-dc4.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.4/board/zc1751-dc5.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.4/board/zcu100-revc.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.4/board/zcu102-rev1.0.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.4/board/zcu102-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.4/board/zcu102-revb.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.4/board/zcu104-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.4/board/zcu106-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.4/board/zcu111-reva.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.4/zynqmp/zynqmp-clk.dtsi | 3 ++- device_tree/data/kernel_dtsi/v5.4/zynqmp/zynqmp.dtsi | 3 ++- dmaps/data/dmaps.mdd | 3 ++- dmaps/data/dmaps.tcl | 3 ++- dp/data/dp.mdd | 3 ++- dp/data/dp.tcl | 3 ++- dp_rx/data/dp_rx.mdd | 3 ++- dp_rx/data/dp_rx.tcl | 3 ++- dp_tx/data/dp_tx.mdd | 3 ++- dp_tx/data/dp_tx.tcl | 3 ++- dpu_eu/data/dpu_eu.mdd | 3 ++- dpu_eu/data/dpu_eu.tcl | 3 ++- emaclite/data/emaclite.mdd | 3 ++- emaclite/data/emaclite.tcl | 3 ++- emacps/data/emacps.mdd | 3 ++- emacps/data/emacps.tcl | 5 +++-- ernic/data/ernic.mdd | 3 ++- ernic/data/ernic.tcl | 3 ++- framebuf_rd/data/framebuf_rd.mdd | 3 ++- framebuf_rd/data/framebuf_rd.tcl | 3 ++- framebuf_wr/data/framebuf_wr.mdd | 3 ++- framebuf_wr/data/framebuf_wr.tcl | 3 ++- gamma_lut/data/gamma_lut.mdd | 3 ++- gamma_lut/data/gamma_lut.tcl | 3 ++- generic/data/generic.mdd | 3 ++- generic/data/generic.tcl | 3 ++- globaltimerps/data/globaltimerps.mdd | 3 ++- globaltimerps/data/globaltimerps.tcl | 3 ++- gpiops/data/gpiops.mdd | 3 ++- gpiops/data/gpiops.tcl | 5 +++-- hdmi_ctrl/data/hdmi_ctrl.mdd | 3 ++- hdmi_ctrl/data/hdmi_ctrl.tcl | 3 ++- hdmi_gt_ctrl/data/hdmi_gt_ctrl.mdd | 3 ++- hdmi_gt_ctrl/data/hdmi_gt_ctrl.tcl | 3 ++- hdmi_rx_ss/data/hdmi_rx_ss.mdd | 3 ++- hdmi_rx_ss/data/hdmi_rx_ss.tcl | 3 ++- hdmi_tx_ss/data/hdmi_tx_ss.mdd | 3 ++- hdmi_tx_ss/data/hdmi_tx_ss.tcl | 3 ++- i2s_receiver/data/i2s_receiver.mdd | 3 ++- i2s_receiver/data/i2s_receiver.tcl | 3 ++- i2s_transmitter/data/i2s_transmitter.mdd | 3 ++- i2s_transmitter/data/i2s_transmitter.tcl | 3 ++- i3cpsx/data/i3cpsx.mdd | 3 ++- i3cpsx/data/i3cpsx.tcl | 3 ++- iicps/data/iicps.mdd | 3 ++- iicps/data/iicps.tcl | 3 ++- intc/data/intc.mdd | 3 ++- intc/data/intc.tcl | 5 +++-- mig_7series/data/mig_7series.mdd | 3 ++- mig_7series/data/mig_7series.tcl | 3 ++- mipi_csi2_rx/data/mipi_csi2_rx.mdd | 3 ++- mipi_csi2_rx/data/mipi_csi2_rx.tcl | 3 ++- mipi_dsi_tx/data/mipi_dsi_tx.mdd | 3 ++- mipi_dsi_tx/data/mipi_dsi_tx.tcl | 3 ++- mixer/data/mixer.mdd | 3 ++- mixer/data/mixer.tcl | 3 ++- mrmac/data/mrmac.mdd | 3 ++- mrmac/data/mrmac.tcl | 3 ++- multi_scaler/data/multi_scaler.mdd | 3 ++- multi_scaler/data/multi_scaler.tcl | 3 ++- nandps/data/nandps.mdd | 3 ++- nandps/data/nandps.tcl | 3 ++- norps/data/norps.mdd | 3 ++- norps/data/norps.tcl | 3 ++- nvme_aggr/data/nvme_aggr.mdd | 3 ++- nvme_aggr/data/nvme_aggr.tcl | 3 ++- ocmcps/data/ocmcps.mdd | 3 ++- ocmcps/data/ocmcps.tcl | 3 ++- ospips/data/ospips.mdd | 3 ++- ospips/data/ospips.tcl | 3 ++- pl310ps/data/pl310ps.mdd | 3 ++- pl310ps/data/pl310ps.tcl | 3 ++- pmups/data/pmups.mdd | 3 ++- pmups/data/pmups.tcl | 3 ++- pr_decoupler/data/pr_decoupler.mdd | 3 ++- pr_decoupler/data/pr_decoupler.tcl | 3 ++- ptp_1588_timer_syncer/data/ptp_1588_timer_syncer.mdd | 3 ++- ptp_1588_timer_syncer/data/ptp_1588_timer_syncer.tcl | 3 ++- qspips/data/qspips.mdd | 3 ++- qspips/data/qspips.tcl | 3 ++- ramps/data/ramps.mdd | 3 ++- ramps/data/ramps.tcl | 3 ++- rfdc/data/rfdc.mdd | 3 ++- rfdc/data/rfdc.tcl | 3 ++- scene_change_detector/data/scene_change_detector.mdd | 3 ++- scene_change_detector/data/scene_change_detector.tcl | 3 ++- scugic/data/scugic.mdd | 3 ++- scugic/data/scugic.tcl | 3 ++- scutimer/data/scutimer.mdd | 3 ++- scutimer/data/scutimer.tcl | 3 ++- scuwdt/data/scuwdt.mdd | 3 ++- scuwdt/data/scuwdt.tcl | 3 ++- sdfec/data/sdfec.mdd | 3 ++- sdfec/data/sdfec.tcl | 3 ++- sdi_rx/data/sdi_rx.mdd | 3 ++- sdi_rx/data/sdi_rx.tcl | 3 ++- sdi_tx/data/sdi_tx.mdd | 3 ++- sdi_tx/data/sdi_tx.tcl | 3 ++- sdps/data/sdps.mdd | 3 ++- sdps/data/sdps.tcl | 3 ++- slcrps/data/slcrps.mdd | 3 ++- slcrps/data/slcrps.tcl | 3 ++- smccps/data/smccps.mdd | 3 ++- smccps/data/smccps.tcl | 3 ++- spips/data/spips.mdd | 3 ++- spips/data/spips.tcl | 3 ++- sync_ip/data/sync_ip.mdd | 3 ++- sync_ip/data/sync_ip.tcl | 3 ++- sysmonpsv/data/sysmonpsv.mdd | 3 ++- sysmonpsv/data/sysmonpsv.tcl | 3 ++- tmrctr/data/tmrctr.mdd | 3 ++- tmrctr/data/tmrctr.tcl | 3 ++- tpg/data/tpg.mdd | 3 ++- tpg/data/tpg.tcl | 3 ++- tsn/data/tsn.mdd | 3 ++- tsn/data/tsn.tcl | 3 ++- ttcps/data/ttcps.mdd | 3 ++- ttcps/data/ttcps.tcl | 3 ++- uartlite/data/uartlite.mdd | 3 ++- uartlite/data/uartlite.tcl | 5 +++-- uartns/data/uartns.mdd | 3 ++- uartns/data/uartns.tcl | 5 +++-- uartps/data/uartps.mdd | 3 ++- uartps/data/uartps.tcl | 5 +++-- usbps/data/usbps.mdd | 3 ++- usbps/data/usbps.tcl | 3 ++- vid_phy_ctrl/data/vid_phy_ctrl.mdd | 3 ++- vid_phy_ctrl/data/vid_phy_ctrl.tcl | 3 ++- vproc_ss/data/vproc_ss.mdd | 3 ++- vproc_ss/data/vproc_ss.tcl | 3 ++- vtc/data/vtc.mdd | 3 ++- vtc/data/vtc.tcl | 3 ++- wdtps/data/wdtps.mdd | 3 ++- wdtps/data/wdtps.tcl | 3 ++- xadcps/data/xadcps.mdd | 3 ++- xadcps/data/xadcps.tcl | 3 ++- 1113 files changed, 2242 insertions(+), 1130 deletions(-) diff --git a/RM/data/RM.mdd b/RM/data/RM.mdd index 985ad2cc..29fc9f17 100644 --- a/RM/data/RM.mdd +++ b/RM/data/RM.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2017 Xilinx, Inc. +# (C) Copyright 2017-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/RM/data/RM.tcl b/RM/data/RM.tcl index 42cc91d8..cd2670fc 100644 --- a/RM/data/RM.tcl +++ b/RM/data/RM.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2017 Xilinx, Inc. +# (C) Copyright 2017-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/ai_engine/data/ai_engine.mdd b/ai_engine/data/ai_engine.mdd index 31cb0fd6..e18bc0d2 100644 --- a/ai_engine/data/ai_engine.mdd +++ b/ai_engine/data/ai_engine.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/ai_engine/data/ai_engine.tcl b/ai_engine/data/ai_engine.tcl index 2285e8fc..3dd9c1cc 100644 --- a/ai_engine/data/ai_engine.tcl +++ b/ai_engine/data/ai_engine.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/ams/data/ams.mdd b/ams/data/ams.mdd index af090871..0f86d5f3 100644 --- a/ams/data/ams.mdd +++ b/ams/data/ams.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2017 Xilinx, Inc. +# (C) Copyright 2017-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/ams/data/ams.tcl b/ams/data/ams.tcl index e88200f4..804e2f96 100644 --- a/ams/data/ams.tcl +++ b/ams/data/ams.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2017 Xilinx, Inc. +# (C) Copyright 2017-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/apmps/data/apmps.mdd b/apmps/data/apmps.mdd index db10b392..41c3a46b 100644 --- a/apmps/data/apmps.mdd +++ b/apmps/data/apmps.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2019 Xilinx, Inc. +# (C) Copyright 2019-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/apmps/data/apmps.tcl b/apmps/data/apmps.tcl index fcbdd02e..2e186e93 100644 --- a/apmps/data/apmps.tcl +++ b/apmps/data/apmps.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2019 Xilinx, Inc. +# (C) Copyright 2019-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/audio_embed/data/audio_embed.mdd b/audio_embed/data/audio_embed.mdd index 36f7b9dd..a5d3df30 100644 --- a/audio_embed/data/audio_embed.mdd +++ b/audio_embed/data/audio_embed.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/audio_embed/data/audio_embed.tcl b/audio_embed/data/audio_embed.tcl index 9fed542d..b1c667b0 100644 --- a/audio_embed/data/audio_embed.tcl +++ b/audio_embed/data/audio_embed.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/audio_formatter/data/audio_formatter.mdd b/audio_formatter/data/audio_formatter.mdd index 7f8d285e..72de7c06 100644 --- a/audio_formatter/data/audio_formatter.mdd +++ b/audio_formatter/data/audio_formatter.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/audio_formatter/data/audio_formatter.tcl b/audio_formatter/data/audio_formatter.tcl index 7bc5a642..2b82927e 100644 --- a/audio_formatter/data/audio_formatter.tcl +++ b/audio_formatter/data/audio_formatter.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/audio_spdif/data/audio_spdif.mdd b/audio_spdif/data/audio_spdif.mdd index 3f05646c..caaa2a2e 100644 --- a/audio_spdif/data/audio_spdif.mdd +++ b/audio_spdif/data/audio_spdif.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/audio_spdif/data/audio_spdif.tcl b/audio_spdif/data/audio_spdif.tcl index 7e38749b..868c5e1c 100644 --- a/audio_spdif/data/audio_spdif.tcl +++ b/audio_spdif/data/audio_spdif.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/axi_can/data/axi_can.mdd b/axi_can/data/axi_can.mdd index 1a2cc67a..231ff876 100644 --- a/axi_can/data/axi_can.mdd +++ b/axi_can/data/axi_can.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/axi_can/data/axi_can.tcl b/axi_can/data/axi_can.tcl index 675e09e3..6a731312 100644 --- a/axi_can/data/axi_can.tcl +++ b/axi_can/data/axi_can.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/axi_cdma/data/axi_cdma.mdd b/axi_cdma/data/axi_cdma.mdd index 9c06b438..0da75944 100644 --- a/axi_cdma/data/axi_cdma.mdd +++ b/axi_cdma/data/axi_cdma.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/axi_cdma/data/axi_cdma.tcl b/axi_cdma/data/axi_cdma.tcl index dec66db6..eab86cf2 100644 --- a/axi_cdma/data/axi_cdma.tcl +++ b/axi_cdma/data/axi_cdma.tcl @@ -1,8 +1,9 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd # Based on original code: # (C) Copyright 2007-2014 Michal Simek -# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # Michal SIMEK # diff --git a/axi_clk_wiz/data/axi_clk_wiz.mdd b/axi_clk_wiz/data/axi_clk_wiz.mdd index 303fbe7b..cc0ea972 100644 --- a/axi_clk_wiz/data/axi_clk_wiz.mdd +++ b/axi_clk_wiz/data/axi_clk_wiz.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/axi_clk_wiz/data/axi_clk_wiz.tcl b/axi_clk_wiz/data/axi_clk_wiz.tcl index 8e2f2fbf..6844bf44 100644 --- a/axi_clk_wiz/data/axi_clk_wiz.tcl +++ b/axi_clk_wiz/data/axi_clk_wiz.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/axi_dma/data/axi_dma.mdd b/axi_dma/data/axi_dma.mdd index 44ded388..c3c3e1ac 100644 --- a/axi_dma/data/axi_dma.mdd +++ b/axi_dma/data/axi_dma.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/axi_dma/data/axi_dma.tcl b/axi_dma/data/axi_dma.tcl index a16d2ad9..bd957f65 100644 --- a/axi_dma/data/axi_dma.tcl +++ b/axi_dma/data/axi_dma.tcl @@ -1,8 +1,9 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd # Based on original code: # (C) Copyright 2007-2014 Michal Simek -# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # Michal SIMEK # diff --git a/axi_emc/data/axi_emc.mdd b/axi_emc/data/axi_emc.mdd index 23f9d582..2c29f3e7 100644 --- a/axi_emc/data/axi_emc.mdd +++ b/axi_emc/data/axi_emc.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/axi_emc/data/axi_emc.tcl b/axi_emc/data/axi_emc.tcl index 8cc75b69..6ea0d0fe 100644 --- a/axi_emc/data/axi_emc.tcl +++ b/axi_emc/data/axi_emc.tcl @@ -1,8 +1,9 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd # Based on original code: # (C) Copyright 2007-2014 Michal Simek -# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # Michal SIMEK # diff --git a/axi_ethernet/data/axi_ethernet.mdd b/axi_ethernet/data/axi_ethernet.mdd index 216e8d1e..166a2abc 100644 --- a/axi_ethernet/data/axi_ethernet.mdd +++ b/axi_ethernet/data/axi_ethernet.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/axi_ethernet/data/axi_ethernet.tcl b/axi_ethernet/data/axi_ethernet.tcl index 0741d830..ff56421b 100644 --- a/axi_ethernet/data/axi_ethernet.tcl +++ b/axi_ethernet/data/axi_ethernet.tcl @@ -1,8 +1,9 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd # Based on original code: # (C) Copyright 2007-2014 Michal Simek -# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # Michal SIMEK # diff --git a/axi_gpio/data/gpio.mdd b/axi_gpio/data/gpio.mdd index c4ec88a0..43050b6f 100644 --- a/axi_gpio/data/gpio.mdd +++ b/axi_gpio/data/gpio.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/axi_gpio/data/gpio.tcl b/axi_gpio/data/gpio.tcl index 680d0929..89365ef8 100644 --- a/axi_gpio/data/gpio.tcl +++ b/axi_gpio/data/gpio.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/axi_iic/data/axi_iic.mdd b/axi_iic/data/axi_iic.mdd index a42947ab..63a7174c 100644 --- a/axi_iic/data/axi_iic.mdd +++ b/axi_iic/data/axi_iic.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/axi_iic/data/axi_iic.tcl b/axi_iic/data/axi_iic.tcl index 96fd082a..4d3684df 100644 --- a/axi_iic/data/axi_iic.tcl +++ b/axi_iic/data/axi_iic.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/axi_mcdma/data/axi_mcdma.mdd b/axi_mcdma/data/axi_mcdma.mdd index 3f116968..f739903c 100644 --- a/axi_mcdma/data/axi_mcdma.mdd +++ b/axi_mcdma/data/axi_mcdma.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2019-2020 Xilinx, Inc. +# (C) Copyright 2019-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/axi_mcdma/data/axi_mcdma.tcl b/axi_mcdma/data/axi_mcdma.tcl index f26587d3..55b5dc02 100644 --- a/axi_mcdma/data/axi_mcdma.tcl +++ b/axi_mcdma/data/axi_mcdma.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2019-2020 Xilinx, Inc. +# (C) Copyright 2019-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # # This program is free software; you can redistribute it and/or diff --git a/axi_pcie/data/axi_pcie.mdd b/axi_pcie/data/axi_pcie.mdd index e1172087..e72af942 100644 --- a/axi_pcie/data/axi_pcie.mdd +++ b/axi_pcie/data/axi_pcie.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/axi_pcie/data/axi_pcie.tcl b/axi_pcie/data/axi_pcie.tcl index bce483ff..c938581f 100644 --- a/axi_pcie/data/axi_pcie.tcl +++ b/axi_pcie/data/axi_pcie.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/axi_perf_mon/data/axi_perf_mon.mdd b/axi_perf_mon/data/axi_perf_mon.mdd index b6e6667d..73f1eb8d 100644 --- a/axi_perf_mon/data/axi_perf_mon.mdd +++ b/axi_perf_mon/data/axi_perf_mon.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/axi_perf_mon/data/axi_perf_mon.tcl b/axi_perf_mon/data/axi_perf_mon.tcl index 6e307fda..3ead3fa5 100644 --- a/axi_perf_mon/data/axi_perf_mon.tcl +++ b/axi_perf_mon/data/axi_perf_mon.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/axi_qspi/data/axi_qspi.mdd b/axi_qspi/data/axi_qspi.mdd index 0666964f..939d7f60 100644 --- a/axi_qspi/data/axi_qspi.mdd +++ b/axi_qspi/data/axi_qspi.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/axi_qspi/data/axi_qspi.tcl b/axi_qspi/data/axi_qspi.tcl index 90c3040d..a916abc2 100644 --- a/axi_qspi/data/axi_qspi.tcl +++ b/axi_qspi/data/axi_qspi.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/axi_sysace/data/axi_sysace.mdd b/axi_sysace/data/axi_sysace.mdd index b7a6eb49..46f68ab1 100644 --- a/axi_sysace/data/axi_sysace.mdd +++ b/axi_sysace/data/axi_sysace.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/axi_sysace/data/axi_sysace.tcl b/axi_sysace/data/axi_sysace.tcl index 89449912..83c75cd0 100644 --- a/axi_sysace/data/axi_sysace.tcl +++ b/axi_sysace/data/axi_sysace.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/axi_tft/data/axi_tft.mdd b/axi_tft/data/axi_tft.mdd index 267445b2..8b31ec89 100644 --- a/axi_tft/data/axi_tft.mdd +++ b/axi_tft/data/axi_tft.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/axi_tft/data/axi_tft.tcl b/axi_tft/data/axi_tft.tcl index 89449912..83c75cd0 100644 --- a/axi_tft/data/axi_tft.tcl +++ b/axi_tft/data/axi_tft.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/axi_timebase_wdt/data/axi_timebase_wdt.mdd b/axi_timebase_wdt/data/axi_timebase_wdt.mdd index e3c41fe6..0a5a36c7 100644 --- a/axi_timebase_wdt/data/axi_timebase_wdt.mdd +++ b/axi_timebase_wdt/data/axi_timebase_wdt.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/axi_timebase_wdt/data/axi_timebase_wdt.tcl b/axi_timebase_wdt/data/axi_timebase_wdt.tcl index 105da362..072605de 100644 --- a/axi_timebase_wdt/data/axi_timebase_wdt.tcl +++ b/axi_timebase_wdt/data/axi_timebase_wdt.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/axi_traffic_gen/data/axi_traffic_gen.mdd b/axi_traffic_gen/data/axi_traffic_gen.mdd index 165cf411..fde18871 100644 --- a/axi_traffic_gen/data/axi_traffic_gen.mdd +++ b/axi_traffic_gen/data/axi_traffic_gen.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/axi_traffic_gen/data/axi_traffic_gen.tcl b/axi_traffic_gen/data/axi_traffic_gen.tcl index 448363b2..fd339e05 100644 --- a/axi_traffic_gen/data/axi_traffic_gen.tcl +++ b/axi_traffic_gen/data/axi_traffic_gen.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/axi_usb2_device/data/axi_usb2_device.mdd b/axi_usb2_device/data/axi_usb2_device.mdd index e825c46d..7538bcfe 100644 --- a/axi_usb2_device/data/axi_usb2_device.mdd +++ b/axi_usb2_device/data/axi_usb2_device.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/axi_usb2_device/data/axi_usb2_device.tcl b/axi_usb2_device/data/axi_usb2_device.tcl index 915522d9..f9c018d5 100644 --- a/axi_usb2_device/data/axi_usb2_device.tcl +++ b/axi_usb2_device/data/axi_usb2_device.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/axi_vcu/data/axi_vcu.mdd b/axi_vcu/data/axi_vcu.mdd index 388fcb28..f473acc6 100644 --- a/axi_vcu/data/axi_vcu.mdd +++ b/axi_vcu/data/axi_vcu.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2017 Xilinx, Inc. +# (C) Copyright 2017-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/axi_vcu/data/axi_vcu.tcl b/axi_vcu/data/axi_vcu.tcl index 0a3de89c..94e0ed98 100644 --- a/axi_vcu/data/axi_vcu.tcl +++ b/axi_vcu/data/axi_vcu.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2017 Xilinx, Inc. +# (C) Copyright 2017-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/axi_vdma/data/axi_vdma.mdd b/axi_vdma/data/axi_vdma.mdd index f7a3136e..0fa5fb1e 100644 --- a/axi_vdma/data/axi_vdma.mdd +++ b/axi_vdma/data/axi_vdma.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/axi_vdma/data/axi_vdma.tcl b/axi_vdma/data/axi_vdma.tcl index fcbd8570..63cfa016 100644 --- a/axi_vdma/data/axi_vdma.tcl +++ b/axi_vdma/data/axi_vdma.tcl @@ -1,8 +1,9 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd # Based on original code: # (C) Copyright 2007-2014 Michal Simek -# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # Michal SIMEK # diff --git a/axi_vdu/data/axi_vdu.mdd b/axi_vdu/data/axi_vdu.mdd index 2e42b989..6beb2fcb 100644 --- a/axi_vdu/data/axi_vdu.mdd +++ b/axi_vdu/data/axi_vdu.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2017 Xilinx, Inc. +# (C) Copyright 2017-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/axi_vdu/data/axi_vdu.tcl b/axi_vdu/data/axi_vdu.tcl index 04b4b3e4..1d2da901 100644 --- a/axi_vdu/data/axi_vdu.tcl +++ b/axi_vdu/data/axi_vdu.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2017 Xilinx, Inc. +# (C) Copyright 2017-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/axi_xadc/data/axi_xadc.mdd b/axi_xadc/data/axi_xadc.mdd index 9f403714..49f4d3b0 100644 --- a/axi_xadc/data/axi_xadc.mdd +++ b/axi_xadc/data/axi_xadc.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2015 Xilinx, Inc. +# (C) Copyright 2015-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/axi_xadc/data/axi_xadc.tcl b/axi_xadc/data/axi_xadc.tcl index 6d318806..16a30ae1 100644 --- a/axi_xadc/data/axi_xadc.tcl +++ b/axi_xadc/data/axi_xadc.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2015 Xilinx, Inc. +# (C) Copyright 2015-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/axis_switch/data/axis_switch.mdd b/axis_switch/data/axis_switch.mdd index 3fe34ed2..3eaa4a6e 100644 --- a/axis_switch/data/axis_switch.mdd +++ b/axis_switch/data/axis_switch.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2020-2021 Xilinx, Inc. +# (C) Copyright 2020-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/axis_switch/data/axis_switch.tcl b/axis_switch/data/axis_switch.tcl index e994a22c..25035604 100644 --- a/axis_switch/data/axis_switch.tcl +++ b/axis_switch/data/axis_switch.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2020-2021 Xilinx, Inc. +# (C) Copyright 2020-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # # This program is free software; you can redistribute it and/or diff --git a/canfdps/data/canfdps.mdd b/canfdps/data/canfdps.mdd index 2ec7afb5..79f855fb 100644 --- a/canfdps/data/canfdps.mdd +++ b/canfdps/data/canfdps.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2019 Xilinx, Inc. +# (C) Copyright 2019-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/canfdps/data/canfdps.tcl b/canfdps/data/canfdps.tcl index b579c35b..2e186e93 100644 --- a/canfdps/data/canfdps.tcl +++ b/canfdps/data/canfdps.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2019 Xilinx, Inc. +# (C) Copyright 2019-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/canps/data/canps.mdd b/canps/data/canps.mdd index 5ab1b8fd..16f135d3 100644 --- a/canps/data/canps.mdd +++ b/canps/data/canps.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/canps/data/canps.tcl b/canps/data/canps.tcl index 304b3bcd..734ec2b0 100644 --- a/canps/data/canps.tcl +++ b/canps/data/canps.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/cpu/data/cpu.mdd b/cpu/data/cpu.mdd index 61e8c950..59e63232 100644 --- a/cpu/data/cpu.mdd +++ b/cpu/data/cpu.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/cpu/data/cpu.tcl b/cpu/data/cpu.tcl index b757a56e..33c6ee3a 100644 --- a/cpu/data/cpu.tcl +++ b/cpu/data/cpu.tcl @@ -1,8 +1,9 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd # Based on original code: # (C) Copyright 2007-2014 Michal Simek -# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # Michal SIMEK # diff --git a/cpu_cortexa53/data/cpu_cortexa53.mdd b/cpu_cortexa53/data/cpu_cortexa53.mdd index e40bb24b..1d8c0297 100644 --- a/cpu_cortexa53/data/cpu_cortexa53.mdd +++ b/cpu_cortexa53/data/cpu_cortexa53.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/cpu_cortexa53/data/cpu_cortexa53.tcl b/cpu_cortexa53/data/cpu_cortexa53.tcl index 9ec02107..8ac7c0cb 100644 --- a/cpu_cortexa53/data/cpu_cortexa53.tcl +++ b/cpu_cortexa53/data/cpu_cortexa53.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/cpu_cortexa72/data/cpu_cortexa72.mdd b/cpu_cortexa72/data/cpu_cortexa72.mdd index a99ea286..36839b72 100644 --- a/cpu_cortexa72/data/cpu_cortexa72.mdd +++ b/cpu_cortexa72/data/cpu_cortexa72.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2018-2019 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/cpu_cortexa72/data/cpu_cortexa72.tcl b/cpu_cortexa72/data/cpu_cortexa72.tcl index e4ac7cfb..54b992e7 100644 --- a/cpu_cortexa72/data/cpu_cortexa72.tcl +++ b/cpu_cortexa72/data/cpu_cortexa72.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2018-2019 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/cpu_cortexa78/data/cpu_cortexa78.mdd b/cpu_cortexa78/data/cpu_cortexa78.mdd index 7af50aba..f27f8ac7 100644 --- a/cpu_cortexa78/data/cpu_cortexa78.mdd +++ b/cpu_cortexa78/data/cpu_cortexa78.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2018-2019 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/cpu_cortexa78/data/cpu_cortexa78.tcl b/cpu_cortexa78/data/cpu_cortexa78.tcl index aef17f8d..1e944266 100644 --- a/cpu_cortexa78/data/cpu_cortexa78.tcl +++ b/cpu_cortexa78/data/cpu_cortexa78.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2018-2019 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/cpu_cortexa9/data/cpu_cortexa9.mdd b/cpu_cortexa9/data/cpu_cortexa9.mdd index 23cd4575..fa553635 100644 --- a/cpu_cortexa9/data/cpu_cortexa9.mdd +++ b/cpu_cortexa9/data/cpu_cortexa9.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/cpu_cortexa9/data/cpu_cortexa9.tcl b/cpu_cortexa9/data/cpu_cortexa9.tcl index df215ffc..121c9968 100644 --- a/cpu_cortexa9/data/cpu_cortexa9.tcl +++ b/cpu_cortexa9/data/cpu_cortexa9.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/ddrcps/data/ddrcps.mdd b/ddrcps/data/ddrcps.mdd index 0531b2d1..fee403a4 100644 --- a/ddrcps/data/ddrcps.mdd +++ b/ddrcps/data/ddrcps.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/ddrcps/data/ddrcps.tcl b/ddrcps/data/ddrcps.tcl index 304b3bcd..734ec2b0 100644 --- a/ddrcps/data/ddrcps.tcl +++ b/ddrcps/data/ddrcps.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/ddrps/data/ddrps.mdd b/ddrps/data/ddrps.mdd index 6da4ae44..c6d42048 100644 --- a/ddrps/data/ddrps.mdd +++ b/ddrps/data/ddrps.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/ddrps/data/ddrps.tcl b/ddrps/data/ddrps.tcl index 4eaee3ae..297622bd 100644 --- a/ddrps/data/ddrps.tcl +++ b/ddrps/data/ddrps.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/ddrpsv/data/ddrpsv.mdd b/ddrpsv/data/ddrpsv.mdd index 1b4a87b1..bbdad07c 100644 --- a/ddrpsv/data/ddrpsv.mdd +++ b/ddrpsv/data/ddrpsv.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2019 Xilinx, Inc. +# (C) Copyright 2019-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/ddrpsv/data/ddrpsv.tcl b/ddrpsv/data/ddrpsv.tcl index c7d9b1be..f65be3b8 100644 --- a/ddrpsv/data/ddrpsv.tcl +++ b/ddrpsv/data/ddrpsv.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2019 Xilinx, Inc. +# (C) Copyright 2019-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/debug_bridge/data/debug_bridge.mdd b/debug_bridge/data/debug_bridge.mdd index 4b0281c1..e98b7678 100644 --- a/debug_bridge/data/debug_bridge.mdd +++ b/debug_bridge/data/debug_bridge.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2020 Xilinx, Inc. +# (C) Copyright 2020-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/debug_bridge/data/debug_bridge.tcl b/debug_bridge/data/debug_bridge.tcl index 65c1243b..99131678 100644 --- a/debug_bridge/data/debug_bridge.tcl +++ b/debug_bridge/data/debug_bridge.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2020 Xilinx, Inc. +# (C) Copyright 2020-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/demosaic/data/demosaic.mdd b/demosaic/data/demosaic.mdd index 0e303d53..c7444671 100644 --- a/demosaic/data/demosaic.mdd +++ b/demosaic/data/demosaic.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/demosaic/data/demosaic.tcl b/demosaic/data/demosaic.tcl index 5a212dec..a9d3e13f 100644 --- a/demosaic/data/demosaic.tcl +++ b/demosaic/data/demosaic.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/devcfg/data/devcfg.mdd b/devcfg/data/devcfg.mdd index 8e2a4ea3..46ff2956 100644 --- a/devcfg/data/devcfg.mdd +++ b/devcfg/data/devcfg.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/devcfg/data/devcfg.tcl b/devcfg/data/devcfg.tcl index 304b3bcd..734ec2b0 100644 --- a/devcfg/data/devcfg.tcl +++ b/devcfg/data/devcfg.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/device_tree/data/common_proc.tcl b/device_tree/data/common_proc.tcl index 6c4d6cdf..8c61c6af 100644 --- a/device_tree/data/common_proc.tcl +++ b/device_tree/data/common_proc.tcl @@ -1,8 +1,9 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd # Based on original code: # (C) Copyright 2007-2014 Michal Simek -# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # Michal SIMEK # diff --git a/device_tree/data/device_tree.mld b/device_tree/data/device_tree.mld index 588d64ab..7e276764 100644 --- a/device_tree/data/device_tree.mld +++ b/device_tree/data/device_tree.mld @@ -1,8 +1,9 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd # Based on original code: # (C) Copyright 2007-2014 Michal Simek -# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # Michal SIMEK # diff --git a/device_tree/data/device_tree.mss b/device_tree/data/device_tree.mss index 2b12fd5e..242e2f53 100644 --- a/device_tree/data/device_tree.mss +++ b/device_tree/data/device_tree.mss @@ -1,8 +1,9 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd # Based on original code: # (C) Copyright 2007-2014 Michal Simek -# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # Michal SIMEK # diff --git a/device_tree/data/device_tree.tcl b/device_tree/data/device_tree.tcl index 1fc25b6c..76e7ab44 100644 --- a/device_tree/data/device_tree.tcl +++ b/device_tree/data/device_tree.tcl @@ -1,8 +1,9 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd # Based on original code: # (C) Copyright 2007-2014 Michal Simek -# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # Michal SIMEK # diff --git a/device_tree/data/kernel_dtsi/2014.4/zynq/zynq-7000.dtsi b/device_tree/data/kernel_dtsi/2014.4/zynq/zynq-7000.dtsi index 2556e8d0..e0b485cf 100644 --- a/device_tree/data/kernel_dtsi/2014.4/zynq/zynq-7000.dtsi +++ b/device_tree/data/kernel_dtsi/2014.4/zynq/zynq-7000.dtsi @@ -1,5 +1,6 @@ /* - * Copyright (C) 2011 - 2014 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and diff --git a/device_tree/data/kernel_dtsi/2015.1/zynq/zynq-7000.dtsi b/device_tree/data/kernel_dtsi/2015.1/zynq/zynq-7000.dtsi index cb1b3667..87f8f55d 100644 --- a/device_tree/data/kernel_dtsi/2015.1/zynq/zynq-7000.dtsi +++ b/device_tree/data/kernel_dtsi/2015.1/zynq/zynq-7000.dtsi @@ -1,5 +1,6 @@ /* - * Copyright (C) 2011 - 2014 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and diff --git a/device_tree/data/kernel_dtsi/2015.2/zynq/zynq-7000.dtsi b/device_tree/data/kernel_dtsi/2015.2/zynq/zynq-7000.dtsi index 425597d6..ba4a03c6 100644 --- a/device_tree/data/kernel_dtsi/2015.2/zynq/zynq-7000.dtsi +++ b/device_tree/data/kernel_dtsi/2015.2/zynq/zynq-7000.dtsi @@ -1,5 +1,6 @@ /* - * Copyright (C) 2011 - 2014 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and diff --git a/device_tree/data/kernel_dtsi/2015.3/zynq/zynq-7000.dtsi b/device_tree/data/kernel_dtsi/2015.3/zynq/zynq-7000.dtsi index ea1affda..74bd1f75 100644 --- a/device_tree/data/kernel_dtsi/2015.3/zynq/zynq-7000.dtsi +++ b/device_tree/data/kernel_dtsi/2015.3/zynq/zynq-7000.dtsi @@ -1,5 +1,6 @@ /* - * Copyright (C) 2011 - 2015 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and diff --git a/device_tree/data/kernel_dtsi/2015.4/zynq/zynq-7000.dtsi b/device_tree/data/kernel_dtsi/2015.4/zynq/zynq-7000.dtsi index 20275cfc..74e3424e 100644 --- a/device_tree/data/kernel_dtsi/2015.4/zynq/zynq-7000.dtsi +++ b/device_tree/data/kernel_dtsi/2015.4/zynq/zynq-7000.dtsi @@ -1,5 +1,6 @@ /* - * Copyright (C) 2011 - 2014 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and diff --git a/device_tree/data/kernel_dtsi/2015.4/zynqmp/zynqmp-clk.dtsi b/device_tree/data/kernel_dtsi/2015.4/zynqmp/zynqmp-clk.dtsi index 98f2bca1..a9b1134f 100644 --- a/device_tree/data/kernel_dtsi/2015.4/zynqmp/zynqmp-clk.dtsi +++ b/device_tree/data/kernel_dtsi/2015.4/zynqmp/zynqmp-clk.dtsi @@ -1,7 +1,8 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2015, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/2015.4/zynqmp/zynqmp.dtsi b/device_tree/data/kernel_dtsi/2015.4/zynqmp/zynqmp.dtsi index 0fa9197e..9efd822d 100644 --- a/device_tree/data/kernel_dtsi/2015.4/zynqmp/zynqmp.dtsi +++ b/device_tree/data/kernel_dtsi/2015.4/zynqmp/zynqmp.dtsi @@ -1,7 +1,8 @@ /* * dts file for Xilinx ZynqMP * - * (C) Copyright 2014 - 2015, Xilinx, Inc. + * (C) Copyright 2014-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/2016.1/zynq/zynq-7000.dtsi b/device_tree/data/kernel_dtsi/2016.1/zynq/zynq-7000.dtsi index 346b6a76..b4d48f09 100644 --- a/device_tree/data/kernel_dtsi/2016.1/zynq/zynq-7000.dtsi +++ b/device_tree/data/kernel_dtsi/2016.1/zynq/zynq-7000.dtsi @@ -1,5 +1,6 @@ /* - * Copyright (C) 2011 - 2014 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and diff --git a/device_tree/data/kernel_dtsi/2016.1/zynqmp/zynqmp-clk.dtsi b/device_tree/data/kernel_dtsi/2016.1/zynqmp/zynqmp-clk.dtsi index c7c936a9..6fcc62be 100644 --- a/device_tree/data/kernel_dtsi/2016.1/zynqmp/zynqmp-clk.dtsi +++ b/device_tree/data/kernel_dtsi/2016.1/zynqmp/zynqmp-clk.dtsi @@ -1,7 +1,8 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2015, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/2016.1/zynqmp/zynqmp.dtsi b/device_tree/data/kernel_dtsi/2016.1/zynqmp/zynqmp.dtsi index 2e66ab29..0c7f3546 100644 --- a/device_tree/data/kernel_dtsi/2016.1/zynqmp/zynqmp.dtsi +++ b/device_tree/data/kernel_dtsi/2016.1/zynqmp/zynqmp.dtsi @@ -1,7 +1,8 @@ /* * dts file for Xilinx ZynqMP * - * (C) Copyright 2014 - 2015, Xilinx, Inc. + * (C) Copyright 2014-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/2016.2/zynq/zynq-7000.dtsi b/device_tree/data/kernel_dtsi/2016.2/zynq/zynq-7000.dtsi index 346b6a76..b4d48f09 100644 --- a/device_tree/data/kernel_dtsi/2016.2/zynq/zynq-7000.dtsi +++ b/device_tree/data/kernel_dtsi/2016.2/zynq/zynq-7000.dtsi @@ -1,5 +1,6 @@ /* - * Copyright (C) 2011 - 2014 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and diff --git a/device_tree/data/kernel_dtsi/2016.2/zynqmp/zynqmp-clk.dtsi b/device_tree/data/kernel_dtsi/2016.2/zynqmp/zynqmp-clk.dtsi index c7c936a9..6fcc62be 100644 --- a/device_tree/data/kernel_dtsi/2016.2/zynqmp/zynqmp-clk.dtsi +++ b/device_tree/data/kernel_dtsi/2016.2/zynqmp/zynqmp-clk.dtsi @@ -1,7 +1,8 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2015, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/2016.2/zynqmp/zynqmp.dtsi b/device_tree/data/kernel_dtsi/2016.2/zynqmp/zynqmp.dtsi index 52ec9689..5be58cfa 100755 --- a/device_tree/data/kernel_dtsi/2016.2/zynqmp/zynqmp.dtsi +++ b/device_tree/data/kernel_dtsi/2016.2/zynqmp/zynqmp.dtsi @@ -1,7 +1,8 @@ /* * dts file for Xilinx ZynqMP * - * (C) Copyright 2014 - 2015, Xilinx, Inc. + * (C) Copyright 2014-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/2016.3/zynq/zynq-7000.dtsi b/device_tree/data/kernel_dtsi/2016.3/zynq/zynq-7000.dtsi index 2fe9c89f..8a3924da 100644 --- a/device_tree/data/kernel_dtsi/2016.3/zynq/zynq-7000.dtsi +++ b/device_tree/data/kernel_dtsi/2016.3/zynq/zynq-7000.dtsi @@ -1,5 +1,6 @@ /* - * Copyright (C) 2011 - 2014 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and diff --git a/device_tree/data/kernel_dtsi/2016.3/zynqmp/zynqmp-clk.dtsi b/device_tree/data/kernel_dtsi/2016.3/zynqmp/zynqmp-clk.dtsi index c7c936a9..6fcc62be 100644 --- a/device_tree/data/kernel_dtsi/2016.3/zynqmp/zynqmp-clk.dtsi +++ b/device_tree/data/kernel_dtsi/2016.3/zynqmp/zynqmp-clk.dtsi @@ -1,7 +1,8 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2015, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/2016.3/zynqmp/zynqmp.dtsi b/device_tree/data/kernel_dtsi/2016.3/zynqmp/zynqmp.dtsi index 6d1fe880..1652d6e6 100755 --- a/device_tree/data/kernel_dtsi/2016.3/zynqmp/zynqmp.dtsi +++ b/device_tree/data/kernel_dtsi/2016.3/zynqmp/zynqmp.dtsi @@ -1,7 +1,8 @@ /* * dts file for Xilinx ZynqMP * - * (C) Copyright 2014 - 2015, Xilinx, Inc. + * (C) Copyright 2014-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/2016.4/zynq/zynq-7000.dtsi b/device_tree/data/kernel_dtsi/2016.4/zynq/zynq-7000.dtsi index 1114cc11..d086090b 100644 --- a/device_tree/data/kernel_dtsi/2016.4/zynq/zynq-7000.dtsi +++ b/device_tree/data/kernel_dtsi/2016.4/zynq/zynq-7000.dtsi @@ -1,5 +1,6 @@ /* - * Copyright (C) 2011 - 2014 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and diff --git a/device_tree/data/kernel_dtsi/2016.4/zynqmp/zynqmp-clk.dtsi b/device_tree/data/kernel_dtsi/2016.4/zynqmp/zynqmp-clk.dtsi index f52df440..406d1fb2 100644 --- a/device_tree/data/kernel_dtsi/2016.4/zynqmp/zynqmp-clk.dtsi +++ b/device_tree/data/kernel_dtsi/2016.4/zynqmp/zynqmp-clk.dtsi @@ -1,7 +1,8 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2015, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/2016.4/zynqmp/zynqmp.dtsi b/device_tree/data/kernel_dtsi/2016.4/zynqmp/zynqmp.dtsi index 04dda1a7..385c358e 100755 --- a/device_tree/data/kernel_dtsi/2016.4/zynqmp/zynqmp.dtsi +++ b/device_tree/data/kernel_dtsi/2016.4/zynqmp/zynqmp.dtsi @@ -1,7 +1,8 @@ /* * dts file for Xilinx ZynqMP * - * (C) Copyright 2014 - 2015, Xilinx, Inc. + * (C) Copyright 2014-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/2017.1/zynq/zynq-7000.dtsi b/device_tree/data/kernel_dtsi/2017.1/zynq/zynq-7000.dtsi index 90474def..ca2f094b 100644 --- a/device_tree/data/kernel_dtsi/2017.1/zynq/zynq-7000.dtsi +++ b/device_tree/data/kernel_dtsi/2017.1/zynq/zynq-7000.dtsi @@ -1,5 +1,6 @@ /* - * Copyright (C) 2011 - 2014 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and diff --git a/device_tree/data/kernel_dtsi/2017.1/zynqmp/zynqmp-clk-ccf.dtsi b/device_tree/data/kernel_dtsi/2017.1/zynqmp/zynqmp-clk-ccf.dtsi index 66fa6e76..332e9c24 100644 --- a/device_tree/data/kernel_dtsi/2017.1/zynqmp/zynqmp-clk-ccf.dtsi +++ b/device_tree/data/kernel_dtsi/2017.1/zynqmp/zynqmp-clk-ccf.dtsi @@ -1,7 +1,8 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2017, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/2017.1/zynqmp/zynqmp-clk.dtsi b/device_tree/data/kernel_dtsi/2017.1/zynqmp/zynqmp-clk.dtsi index e6d4f25a..3fb31927 100644 --- a/device_tree/data/kernel_dtsi/2017.1/zynqmp/zynqmp-clk.dtsi +++ b/device_tree/data/kernel_dtsi/2017.1/zynqmp/zynqmp-clk.dtsi @@ -1,7 +1,8 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2015, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/2017.1/zynqmp/zynqmp.dtsi b/device_tree/data/kernel_dtsi/2017.1/zynqmp/zynqmp.dtsi index 2bca1a11..880b7a0f 100644 --- a/device_tree/data/kernel_dtsi/2017.1/zynqmp/zynqmp.dtsi +++ b/device_tree/data/kernel_dtsi/2017.1/zynqmp/zynqmp.dtsi @@ -1,7 +1,8 @@ /* * dts file for Xilinx ZynqMP * - * (C) Copyright 2014 - 2015, Xilinx, Inc. + * (C) Copyright 2014-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/2017.2/zynq/zynq-7000.dtsi b/device_tree/data/kernel_dtsi/2017.2/zynq/zynq-7000.dtsi index 90474def..ca2f094b 100644 --- a/device_tree/data/kernel_dtsi/2017.2/zynq/zynq-7000.dtsi +++ b/device_tree/data/kernel_dtsi/2017.2/zynq/zynq-7000.dtsi @@ -1,5 +1,6 @@ /* - * Copyright (C) 2011 - 2014 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and diff --git a/device_tree/data/kernel_dtsi/2017.2/zynqmp/zynqmp-clk-ccf.dtsi b/device_tree/data/kernel_dtsi/2017.2/zynqmp/zynqmp-clk-ccf.dtsi index 66fa6e76..332e9c24 100644 --- a/device_tree/data/kernel_dtsi/2017.2/zynqmp/zynqmp-clk-ccf.dtsi +++ b/device_tree/data/kernel_dtsi/2017.2/zynqmp/zynqmp-clk-ccf.dtsi @@ -1,7 +1,8 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2017, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/2017.2/zynqmp/zynqmp-clk.dtsi b/device_tree/data/kernel_dtsi/2017.2/zynqmp/zynqmp-clk.dtsi index e6d4f25a..3fb31927 100644 --- a/device_tree/data/kernel_dtsi/2017.2/zynqmp/zynqmp-clk.dtsi +++ b/device_tree/data/kernel_dtsi/2017.2/zynqmp/zynqmp-clk.dtsi @@ -1,7 +1,8 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2015, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/2017.2/zynqmp/zynqmp.dtsi b/device_tree/data/kernel_dtsi/2017.2/zynqmp/zynqmp.dtsi index 2bca1a11..880b7a0f 100644 --- a/device_tree/data/kernel_dtsi/2017.2/zynqmp/zynqmp.dtsi +++ b/device_tree/data/kernel_dtsi/2017.2/zynqmp/zynqmp.dtsi @@ -1,7 +1,8 @@ /* * dts file for Xilinx ZynqMP * - * (C) Copyright 2014 - 2015, Xilinx, Inc. + * (C) Copyright 2014-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/2017.3/BOARD/zc1232-reva.dtsi b/device_tree/data/kernel_dtsi/2017.3/BOARD/zc1232-reva.dtsi index c373fe22..1f7a8b40 100644 --- a/device_tree/data/kernel_dtsi/2017.3/BOARD/zc1232-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2017.3/BOARD/zc1232-reva.dtsi @@ -1,7 +1,8 @@ /* * dts file for Xilinx ZynqMP ZC1232 * - * (C) Copyright 2017, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/2017.3/BOARD/zc1254-reva.dtsi b/device_tree/data/kernel_dtsi/2017.3/BOARD/zc1254-reva.dtsi index 138749f1..28d3ec34 100644 --- a/device_tree/data/kernel_dtsi/2017.3/BOARD/zc1254-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2017.3/BOARD/zc1254-reva.dtsi @@ -1,7 +1,8 @@ /* * dts file for Xilinx ZynqMP ZC1254 * - * (C) Copyright 2015 - 2017, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2017.3/BOARD/zc1275-reva.dtsi b/device_tree/data/kernel_dtsi/2017.3/BOARD/zc1275-reva.dtsi index cbb04343..61027a8f 100644 --- a/device_tree/data/kernel_dtsi/2017.3/BOARD/zc1275-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2017.3/BOARD/zc1275-reva.dtsi @@ -1,7 +1,8 @@ /* * dts file for Xilinx ZynqMP ZC1275 * - * (C) Copyright 2017, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2017.3/BOARD/zcu100-revc.dtsi b/device_tree/data/kernel_dtsi/2017.3/BOARD/zcu100-revc.dtsi index 1f86f9c9..63d44ce8 100644 --- a/device_tree/data/kernel_dtsi/2017.3/BOARD/zcu100-revc.dtsi +++ b/device_tree/data/kernel_dtsi/2017.3/BOARD/zcu100-revc.dtsi @@ -1,7 +1,8 @@ /* * dts file for Xilinx ZynqMP ZCU100 revC * - * (C) Copyright 2016, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy diff --git a/device_tree/data/kernel_dtsi/2017.3/BOARD/zcu104-reva.dtsi b/device_tree/data/kernel_dtsi/2017.3/BOARD/zcu104-reva.dtsi index 312d82f3..a52bb08a 100644 --- a/device_tree/data/kernel_dtsi/2017.3/BOARD/zcu104-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2017.3/BOARD/zcu104-reva.dtsi @@ -1,7 +1,8 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/2017.3/zynq/zynq-7000.dtsi b/device_tree/data/kernel_dtsi/2017.3/zynq/zynq-7000.dtsi index 90474def..ca2f094b 100644 --- a/device_tree/data/kernel_dtsi/2017.3/zynq/zynq-7000.dtsi +++ b/device_tree/data/kernel_dtsi/2017.3/zynq/zynq-7000.dtsi @@ -1,5 +1,6 @@ /* - * Copyright (C) 2011 - 2014 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and diff --git a/device_tree/data/kernel_dtsi/2017.3/zynqmp/zynqmp-clk-ccf.dtsi b/device_tree/data/kernel_dtsi/2017.3/zynqmp/zynqmp-clk-ccf.dtsi index d8d0be15..c0700c49 100644 --- a/device_tree/data/kernel_dtsi/2017.3/zynqmp/zynqmp-clk-ccf.dtsi +++ b/device_tree/data/kernel_dtsi/2017.3/zynqmp/zynqmp-clk-ccf.dtsi @@ -1,7 +1,8 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2017, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/2017.3/zynqmp/zynqmp-clk.dtsi b/device_tree/data/kernel_dtsi/2017.3/zynqmp/zynqmp-clk.dtsi index e6d4f25a..3fb31927 100644 --- a/device_tree/data/kernel_dtsi/2017.3/zynqmp/zynqmp-clk.dtsi +++ b/device_tree/data/kernel_dtsi/2017.3/zynqmp/zynqmp-clk.dtsi @@ -1,7 +1,8 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2015, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/2017.3/zynqmp/zynqmp.dtsi b/device_tree/data/kernel_dtsi/2017.3/zynqmp/zynqmp.dtsi index c99855ca..4addfc3f 100644 --- a/device_tree/data/kernel_dtsi/2017.3/zynqmp/zynqmp.dtsi +++ b/device_tree/data/kernel_dtsi/2017.3/zynqmp/zynqmp.dtsi @@ -1,7 +1,8 @@ /* * dts file for Xilinx ZynqMP * - * (C) Copyright 2014 - 2015, Xilinx, Inc. + * (C) Copyright 2014-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/2017.4/BOARD/zc1232-reva.dtsi b/device_tree/data/kernel_dtsi/2017.4/BOARD/zc1232-reva.dtsi index c373fe22..1f7a8b40 100644 --- a/device_tree/data/kernel_dtsi/2017.4/BOARD/zc1232-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2017.4/BOARD/zc1232-reva.dtsi @@ -1,7 +1,8 @@ /* * dts file for Xilinx ZynqMP ZC1232 * - * (C) Copyright 2017, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/2017.4/BOARD/zc1254-reva.dtsi b/device_tree/data/kernel_dtsi/2017.4/BOARD/zc1254-reva.dtsi index 138749f1..28d3ec34 100644 --- a/device_tree/data/kernel_dtsi/2017.4/BOARD/zc1254-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2017.4/BOARD/zc1254-reva.dtsi @@ -1,7 +1,8 @@ /* * dts file for Xilinx ZynqMP ZC1254 * - * (C) Copyright 2015 - 2017, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2017.4/BOARD/zc1275-reva.dtsi b/device_tree/data/kernel_dtsi/2017.4/BOARD/zc1275-reva.dtsi index cbb04343..61027a8f 100644 --- a/device_tree/data/kernel_dtsi/2017.4/BOARD/zc1275-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2017.4/BOARD/zc1275-reva.dtsi @@ -1,7 +1,8 @@ /* * dts file for Xilinx ZynqMP ZC1275 * - * (C) Copyright 2017, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2017.4/BOARD/zcu100-revc.dtsi b/device_tree/data/kernel_dtsi/2017.4/BOARD/zcu100-revc.dtsi index 1f86f9c9..63d44ce8 100644 --- a/device_tree/data/kernel_dtsi/2017.4/BOARD/zcu100-revc.dtsi +++ b/device_tree/data/kernel_dtsi/2017.4/BOARD/zcu100-revc.dtsi @@ -1,7 +1,8 @@ /* * dts file for Xilinx ZynqMP ZCU100 revC * - * (C) Copyright 2016, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy diff --git a/device_tree/data/kernel_dtsi/2017.4/BOARD/zcu104-reva.dtsi b/device_tree/data/kernel_dtsi/2017.4/BOARD/zcu104-reva.dtsi index 312d82f3..a52bb08a 100644 --- a/device_tree/data/kernel_dtsi/2017.4/BOARD/zcu104-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2017.4/BOARD/zcu104-reva.dtsi @@ -1,7 +1,8 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/2017.4/zynq/zynq-7000.dtsi b/device_tree/data/kernel_dtsi/2017.4/zynq/zynq-7000.dtsi index 418e4199..60f3f51b 100644 --- a/device_tree/data/kernel_dtsi/2017.4/zynq/zynq-7000.dtsi +++ b/device_tree/data/kernel_dtsi/2017.4/zynq/zynq-7000.dtsi @@ -1,5 +1,6 @@ /* - * Copyright (C) 2011 - 2014 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and diff --git a/device_tree/data/kernel_dtsi/2017.4/zynqmp/zynqmp-clk-ccf.dtsi b/device_tree/data/kernel_dtsi/2017.4/zynqmp/zynqmp-clk-ccf.dtsi index d8d0be15..c0700c49 100644 --- a/device_tree/data/kernel_dtsi/2017.4/zynqmp/zynqmp-clk-ccf.dtsi +++ b/device_tree/data/kernel_dtsi/2017.4/zynqmp/zynqmp-clk-ccf.dtsi @@ -1,7 +1,8 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2017, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/2017.4/zynqmp/zynqmp-clk.dtsi b/device_tree/data/kernel_dtsi/2017.4/zynqmp/zynqmp-clk.dtsi index e6d4f25a..3fb31927 100644 --- a/device_tree/data/kernel_dtsi/2017.4/zynqmp/zynqmp-clk.dtsi +++ b/device_tree/data/kernel_dtsi/2017.4/zynqmp/zynqmp-clk.dtsi @@ -1,7 +1,8 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2015, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/2017.4/zynqmp/zynqmp.dtsi b/device_tree/data/kernel_dtsi/2017.4/zynqmp/zynqmp.dtsi index c99855ca..4addfc3f 100644 --- a/device_tree/data/kernel_dtsi/2017.4/zynqmp/zynqmp.dtsi +++ b/device_tree/data/kernel_dtsi/2017.4/zynqmp/zynqmp.dtsi @@ -1,7 +1,8 @@ /* * dts file for Xilinx ZynqMP * - * (C) Copyright 2014 - 2015, Xilinx, Inc. + * (C) Copyright 2014-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/2018.1/BOARD/zc1232-reva.dtsi b/device_tree/data/kernel_dtsi/2018.1/BOARD/zc1232-reva.dtsi index d266d393..1e6f83ed 100644 --- a/device_tree/data/kernel_dtsi/2018.1/BOARD/zc1232-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2018.1/BOARD/zc1232-reva.dtsi @@ -1,7 +1,8 @@ /* * dts file for Xilinx ZynqMP ZC1232 * - * (C) Copyright 2017, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/2018.1/BOARD/zc1254-reva.dtsi b/device_tree/data/kernel_dtsi/2018.1/BOARD/zc1254-reva.dtsi index 138749f1..28d3ec34 100644 --- a/device_tree/data/kernel_dtsi/2018.1/BOARD/zc1254-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2018.1/BOARD/zc1254-reva.dtsi @@ -1,7 +1,8 @@ /* * dts file for Xilinx ZynqMP ZC1254 * - * (C) Copyright 2015 - 2017, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2018.1/BOARD/zc1275-reva.dtsi b/device_tree/data/kernel_dtsi/2018.1/BOARD/zc1275-reva.dtsi index cbb04343..61027a8f 100644 --- a/device_tree/data/kernel_dtsi/2018.1/BOARD/zc1275-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2018.1/BOARD/zc1275-reva.dtsi @@ -1,7 +1,8 @@ /* * dts file for Xilinx ZynqMP ZC1275 * - * (C) Copyright 2017, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2018.1/BOARD/zc1275-revb.dtsi b/device_tree/data/kernel_dtsi/2018.1/BOARD/zc1275-revb.dtsi index fb3953b9..2420e5b4 100644 --- a/device_tree/data/kernel_dtsi/2018.1/BOARD/zc1275-revb.dtsi +++ b/device_tree/data/kernel_dtsi/2018.1/BOARD/zc1275-revb.dtsi @@ -1,7 +1,8 @@ /* * dts file for Xilinx ZynqMP ZC1275 RevB * - * (C) Copyright 2018, Xilinx, Inc. + * (C) Copyright 2018-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2018.1/BOARD/zcu100-revc.dtsi b/device_tree/data/kernel_dtsi/2018.1/BOARD/zcu100-revc.dtsi index eeacd09c..1b554483 100644 --- a/device_tree/data/kernel_dtsi/2018.1/BOARD/zcu100-revc.dtsi +++ b/device_tree/data/kernel_dtsi/2018.1/BOARD/zcu100-revc.dtsi @@ -1,7 +1,8 @@ /* * dts file for Xilinx ZynqMP ZCU100 revC * - * (C) Copyright 2016, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy diff --git a/device_tree/data/kernel_dtsi/2018.1/BOARD/zcu104-reva.dtsi b/device_tree/data/kernel_dtsi/2018.1/BOARD/zcu104-reva.dtsi index 514e5081..f82e2956 100644 --- a/device_tree/data/kernel_dtsi/2018.1/BOARD/zcu104-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2018.1/BOARD/zcu104-reva.dtsi @@ -1,7 +1,8 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/2018.1/BOARD/zcu104-revc.dtsi b/device_tree/data/kernel_dtsi/2018.1/BOARD/zcu104-revc.dtsi index f4c2ebd8..436c3379 100644 --- a/device_tree/data/kernel_dtsi/2018.1/BOARD/zcu104-revc.dtsi +++ b/device_tree/data/kernel_dtsi/2018.1/BOARD/zcu104-revc.dtsi @@ -1,7 +1,8 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/2018.1/BOARD/zcu111-reva.dtsi b/device_tree/data/kernel_dtsi/2018.1/BOARD/zcu111-reva.dtsi index b35cd2ba..dcd487d6 100644 --- a/device_tree/data/kernel_dtsi/2018.1/BOARD/zcu111-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2018.1/BOARD/zcu111-reva.dtsi @@ -1,7 +1,8 @@ /* * dts file for Xilinx ZynqMP ZCU111 * - * (C) Copyright 2017, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/2018.1/zynq/zynq-7000.dtsi b/device_tree/data/kernel_dtsi/2018.1/zynq/zynq-7000.dtsi index 765a45d7..ed828567 100644 --- a/device_tree/data/kernel_dtsi/2018.1/zynq/zynq-7000.dtsi +++ b/device_tree/data/kernel_dtsi/2018.1/zynq/zynq-7000.dtsi @@ -1,5 +1,6 @@ /* - * Copyright (C) 2011 - 2014 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and diff --git a/device_tree/data/kernel_dtsi/2018.1/zynqmp/zynqmp-clk-ccf.dtsi b/device_tree/data/kernel_dtsi/2018.1/zynqmp/zynqmp-clk-ccf.dtsi index e91970b8..c7c47df3 100644 --- a/device_tree/data/kernel_dtsi/2018.1/zynqmp/zynqmp-clk-ccf.dtsi +++ b/device_tree/data/kernel_dtsi/2018.1/zynqmp/zynqmp-clk-ccf.dtsi @@ -1,7 +1,8 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2017, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/2018.1/zynqmp/zynqmp.dtsi b/device_tree/data/kernel_dtsi/2018.1/zynqmp/zynqmp.dtsi index 14ae4a10..eadb9a11 100644 --- a/device_tree/data/kernel_dtsi/2018.1/zynqmp/zynqmp.dtsi +++ b/device_tree/data/kernel_dtsi/2018.1/zynqmp/zynqmp.dtsi @@ -1,7 +1,8 @@ /* * dts file for Xilinx ZynqMP * - * (C) Copyright 2014 - 2015, Xilinx, Inc. + * (C) Copyright 2014-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/2018.2/BOARD/zc1232-reva.dtsi b/device_tree/data/kernel_dtsi/2018.2/BOARD/zc1232-reva.dtsi index 5d63966e..2f3b19ea 100644 --- a/device_tree/data/kernel_dtsi/2018.2/BOARD/zc1232-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2018.2/BOARD/zc1232-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1232 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2018.2/BOARD/zc1254-reva.dtsi b/device_tree/data/kernel_dtsi/2018.2/BOARD/zc1254-reva.dtsi index 4f6e2002..c0a99ed6 100644 --- a/device_tree/data/kernel_dtsi/2018.2/BOARD/zc1254-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2018.2/BOARD/zc1254-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1254 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2018.2/BOARD/zc1275-reva.dtsi b/device_tree/data/kernel_dtsi/2018.2/BOARD/zc1275-reva.dtsi index fb000907..ef1f44ed 100644 --- a/device_tree/data/kernel_dtsi/2018.2/BOARD/zc1275-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2018.2/BOARD/zc1275-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1275 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2018.2/BOARD/zc1275-revb.dtsi b/device_tree/data/kernel_dtsi/2018.2/BOARD/zc1275-revb.dtsi index fb3953b9..2420e5b4 100644 --- a/device_tree/data/kernel_dtsi/2018.2/BOARD/zc1275-revb.dtsi +++ b/device_tree/data/kernel_dtsi/2018.2/BOARD/zc1275-revb.dtsi @@ -1,7 +1,8 @@ /* * dts file for Xilinx ZynqMP ZC1275 RevB * - * (C) Copyright 2018, Xilinx, Inc. + * (C) Copyright 2018-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2018.2/BOARD/zc1751-dc1.dtsi b/device_tree/data/kernel_dtsi/2018.2/BOARD/zc1751-dc1.dtsi index d3d451c5..5055b0eb 100644 --- a/device_tree/data/kernel_dtsi/2018.2/BOARD/zc1751-dc1.dtsi +++ b/device_tree/data/kernel_dtsi/2018.2/BOARD/zc1751-dc1.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2018.2/BOARD/zc1751-dc2.dtsi b/device_tree/data/kernel_dtsi/2018.2/BOARD/zc1751-dc2.dtsi index ce98b048..c8d22340 100644 --- a/device_tree/data/kernel_dtsi/2018.2/BOARD/zc1751-dc2.dtsi +++ b/device_tree/data/kernel_dtsi/2018.2/BOARD/zc1751-dc2.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2018.2/BOARD/zc702.dtsi b/device_tree/data/kernel_dtsi/2018.2/BOARD/zc702.dtsi index bbb91ff3..6ee18e9d 100644 --- a/device_tree/data/kernel_dtsi/2018.2/BOARD/zc702.dtsi +++ b/device_tree/data/kernel_dtsi/2018.2/BOARD/zc702.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2011 - 2015 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ diff --git a/device_tree/data/kernel_dtsi/2018.2/BOARD/zc706.dtsi b/device_tree/data/kernel_dtsi/2018.2/BOARD/zc706.dtsi index 7009e083..5409c355 100644 --- a/device_tree/data/kernel_dtsi/2018.2/BOARD/zc706.dtsi +++ b/device_tree/data/kernel_dtsi/2018.2/BOARD/zc706.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2011 - 2015 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ diff --git a/device_tree/data/kernel_dtsi/2018.2/BOARD/zcu100-revc.dtsi b/device_tree/data/kernel_dtsi/2018.2/BOARD/zcu100-revc.dtsi index f1f1d624..460f06e6 100644 --- a/device_tree/data/kernel_dtsi/2018.2/BOARD/zcu100-revc.dtsi +++ b/device_tree/data/kernel_dtsi/2018.2/BOARD/zcu100-revc.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU100 revC * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy diff --git a/device_tree/data/kernel_dtsi/2018.2/BOARD/zcu102-rev1.0.dtsi b/device_tree/data/kernel_dtsi/2018.2/BOARD/zcu102-rev1.0.dtsi index 26737226..d6ec6bbd 100644 --- a/device_tree/data/kernel_dtsi/2018.2/BOARD/zcu102-rev1.0.dtsi +++ b/device_tree/data/kernel_dtsi/2018.2/BOARD/zcu102-rev1.0.dtsi @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2018.2/BOARD/zcu102-reva.dtsi b/device_tree/data/kernel_dtsi/2018.2/BOARD/zcu102-reva.dtsi index b5d7f117..63a8d866 100644 --- a/device_tree/data/kernel_dtsi/2018.2/BOARD/zcu102-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2018.2/BOARD/zcu102-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevA * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2018.2/BOARD/zcu102-revb.dtsi b/device_tree/data/kernel_dtsi/2018.2/BOARD/zcu102-revb.dtsi index b4091cd9..9ac9d914 100644 --- a/device_tree/data/kernel_dtsi/2018.2/BOARD/zcu102-revb.dtsi +++ b/device_tree/data/kernel_dtsi/2018.2/BOARD/zcu102-revb.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevB * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2018.2/BOARD/zcu104-reva.dtsi b/device_tree/data/kernel_dtsi/2018.2/BOARD/zcu104-reva.dtsi index 4ba2b62c..50e028f8 100644 --- a/device_tree/data/kernel_dtsi/2018.2/BOARD/zcu104-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2018.2/BOARD/zcu104-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2018.2/BOARD/zcu104-revc.dtsi b/device_tree/data/kernel_dtsi/2018.2/BOARD/zcu104-revc.dtsi index c49b61ce..f418e22f 100644 --- a/device_tree/data/kernel_dtsi/2018.2/BOARD/zcu104-revc.dtsi +++ b/device_tree/data/kernel_dtsi/2018.2/BOARD/zcu104-revc.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2018.2/BOARD/zcu106-reva.dtsi b/device_tree/data/kernel_dtsi/2018.2/BOARD/zcu106-reva.dtsi index 08fd074c..466b42cc 100644 --- a/device_tree/data/kernel_dtsi/2018.2/BOARD/zcu106-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2018.2/BOARD/zcu106-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU106 * - * (C) Copyright 2016, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2018.2/BOARD/zcu111-reva.dtsi b/device_tree/data/kernel_dtsi/2018.2/BOARD/zcu111-reva.dtsi index 0ea4e095..c60aa797 100644 --- a/device_tree/data/kernel_dtsi/2018.2/BOARD/zcu111-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2018.2/BOARD/zcu111-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU111 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2018.2/zynq/zynq-7000.dtsi b/device_tree/data/kernel_dtsi/2018.2/zynq/zynq-7000.dtsi index 1727f32b..615a8903 100644 --- a/device_tree/data/kernel_dtsi/2018.2/zynq/zynq-7000.dtsi +++ b/device_tree/data/kernel_dtsi/2018.2/zynq/zynq-7000.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2011 - 2015 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and diff --git a/device_tree/data/kernel_dtsi/2018.2/zynqmp/zynqmp-clk-ccf.dtsi b/device_tree/data/kernel_dtsi/2018.2/zynqmp/zynqmp-clk-ccf.dtsi index a02ad793..cb580231 100644 --- a/device_tree/data/kernel_dtsi/2018.2/zynqmp/zynqmp-clk-ccf.dtsi +++ b/device_tree/data/kernel_dtsi/2018.2/zynqmp/zynqmp-clk-ccf.dtsi @@ -2,7 +2,8 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2017, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2018.2/zynqmp/zynqmp.dtsi b/device_tree/data/kernel_dtsi/2018.2/zynqmp/zynqmp.dtsi index 55a3d210..e27e21a3 100644 --- a/device_tree/data/kernel_dtsi/2018.2/zynqmp/zynqmp.dtsi +++ b/device_tree/data/kernel_dtsi/2018.2/zynqmp/zynqmp.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP * - * (C) Copyright 2014 - 2015, Xilinx, Inc. + * (C) Copyright 2014-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/2018.3/BOARD/avnet-ultra96-rev1.dtsi b/device_tree/data/kernel_dtsi/2018.3/BOARD/avnet-ultra96-rev1.dtsi index bb12bcbc..038404c3 100644 --- a/device_tree/data/kernel_dtsi/2018.3/BOARD/avnet-ultra96-rev1.dtsi +++ b/device_tree/data/kernel_dtsi/2018.3/BOARD/avnet-ultra96-rev1.dtsi @@ -2,7 +2,8 @@ /* * dts file for Avnet Ultra96 rev1 * - * (C) Copyright 2018, Xilinx, Inc. + * (C) Copyright 2018-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2018.3/BOARD/zc1232-reva.dtsi b/device_tree/data/kernel_dtsi/2018.3/BOARD/zc1232-reva.dtsi index 8fcef490..0e533429 100644 --- a/device_tree/data/kernel_dtsi/2018.3/BOARD/zc1232-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2018.3/BOARD/zc1232-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1232 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2018.3/BOARD/zc1254-reva.dtsi b/device_tree/data/kernel_dtsi/2018.3/BOARD/zc1254-reva.dtsi index 96225767..3ed797c6 100644 --- a/device_tree/data/kernel_dtsi/2018.3/BOARD/zc1254-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2018.3/BOARD/zc1254-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1254 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2018.3/BOARD/zc1275-reva.dtsi b/device_tree/data/kernel_dtsi/2018.3/BOARD/zc1275-reva.dtsi index 71ea5b64..cde8e42d 100644 --- a/device_tree/data/kernel_dtsi/2018.3/BOARD/zc1275-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2018.3/BOARD/zc1275-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1275 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2018.3/BOARD/zc1275-revb.dtsi b/device_tree/data/kernel_dtsi/2018.3/BOARD/zc1275-revb.dtsi index 6efc8d8a..913d99fc 100644 --- a/device_tree/data/kernel_dtsi/2018.3/BOARD/zc1275-revb.dtsi +++ b/device_tree/data/kernel_dtsi/2018.3/BOARD/zc1275-revb.dtsi @@ -1,7 +1,8 @@ /* * dts file for Xilinx ZynqMP ZC1275 RevB * - * (C) Copyright 2018, Xilinx, Inc. + * (C) Copyright 2018-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2018.3/BOARD/zc1751-dc1.dtsi b/device_tree/data/kernel_dtsi/2018.3/BOARD/zc1751-dc1.dtsi index 8f0ce38b..e832c35e 100644 --- a/device_tree/data/kernel_dtsi/2018.3/BOARD/zc1751-dc1.dtsi +++ b/device_tree/data/kernel_dtsi/2018.3/BOARD/zc1751-dc1.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2018.3/BOARD/zc1751-dc2.dtsi b/device_tree/data/kernel_dtsi/2018.3/BOARD/zc1751-dc2.dtsi index 2d470ca5..31bcdfa8 100644 --- a/device_tree/data/kernel_dtsi/2018.3/BOARD/zc1751-dc2.dtsi +++ b/device_tree/data/kernel_dtsi/2018.3/BOARD/zc1751-dc2.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2018.3/BOARD/zc702.dtsi b/device_tree/data/kernel_dtsi/2018.3/BOARD/zc702.dtsi index d30e5126..40f310b1 100644 --- a/device_tree/data/kernel_dtsi/2018.3/BOARD/zc702.dtsi +++ b/device_tree/data/kernel_dtsi/2018.3/BOARD/zc702.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2011 - 2015 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ diff --git a/device_tree/data/kernel_dtsi/2018.3/BOARD/zc706.dtsi b/device_tree/data/kernel_dtsi/2018.3/BOARD/zc706.dtsi index c1620418..18e76f8c 100644 --- a/device_tree/data/kernel_dtsi/2018.3/BOARD/zc706.dtsi +++ b/device_tree/data/kernel_dtsi/2018.3/BOARD/zc706.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2011 - 2015 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ diff --git a/device_tree/data/kernel_dtsi/2018.3/BOARD/zcu100-revc.dtsi b/device_tree/data/kernel_dtsi/2018.3/BOARD/zcu100-revc.dtsi index 99b5fc5f..ff3704c3 100644 --- a/device_tree/data/kernel_dtsi/2018.3/BOARD/zcu100-revc.dtsi +++ b/device_tree/data/kernel_dtsi/2018.3/BOARD/zcu100-revc.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU100 revC * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy diff --git a/device_tree/data/kernel_dtsi/2018.3/BOARD/zcu102-rev1.0.dtsi b/device_tree/data/kernel_dtsi/2018.3/BOARD/zcu102-rev1.0.dtsi index 26737226..d6ec6bbd 100644 --- a/device_tree/data/kernel_dtsi/2018.3/BOARD/zcu102-rev1.0.dtsi +++ b/device_tree/data/kernel_dtsi/2018.3/BOARD/zcu102-rev1.0.dtsi @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2018.3/BOARD/zcu102-reva.dtsi b/device_tree/data/kernel_dtsi/2018.3/BOARD/zcu102-reva.dtsi index a6195eca..3fc63203 100644 --- a/device_tree/data/kernel_dtsi/2018.3/BOARD/zcu102-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2018.3/BOARD/zcu102-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevA * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2018.3/BOARD/zcu102-revb.dtsi b/device_tree/data/kernel_dtsi/2018.3/BOARD/zcu102-revb.dtsi index b4091cd9..9ac9d914 100644 --- a/device_tree/data/kernel_dtsi/2018.3/BOARD/zcu102-revb.dtsi +++ b/device_tree/data/kernel_dtsi/2018.3/BOARD/zcu102-revb.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevB * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2018.3/BOARD/zcu104-reva.dtsi b/device_tree/data/kernel_dtsi/2018.3/BOARD/zcu104-reva.dtsi index e5715746..55e92ea7 100644 --- a/device_tree/data/kernel_dtsi/2018.3/BOARD/zcu104-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2018.3/BOARD/zcu104-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2018.3/BOARD/zcu104-revc.dtsi b/device_tree/data/kernel_dtsi/2018.3/BOARD/zcu104-revc.dtsi index e35e2759..538c8d33 100644 --- a/device_tree/data/kernel_dtsi/2018.3/BOARD/zcu104-revc.dtsi +++ b/device_tree/data/kernel_dtsi/2018.3/BOARD/zcu104-revc.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2018.3/BOARD/zcu106-reva.dtsi b/device_tree/data/kernel_dtsi/2018.3/BOARD/zcu106-reva.dtsi index ca81055e..0e94cd02 100644 --- a/device_tree/data/kernel_dtsi/2018.3/BOARD/zcu106-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2018.3/BOARD/zcu106-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU106 * - * (C) Copyright 2016, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2018.3/BOARD/zcu111-reva.dtsi b/device_tree/data/kernel_dtsi/2018.3/BOARD/zcu111-reva.dtsi index 5ff23c27..37fd518b 100644 --- a/device_tree/data/kernel_dtsi/2018.3/BOARD/zcu111-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2018.3/BOARD/zcu111-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU111 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2018.3/zynq/zynq-7000.dtsi b/device_tree/data/kernel_dtsi/2018.3/zynq/zynq-7000.dtsi index bebae215..d35f16e6 100644 --- a/device_tree/data/kernel_dtsi/2018.3/zynq/zynq-7000.dtsi +++ b/device_tree/data/kernel_dtsi/2018.3/zynq/zynq-7000.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2011 - 2015 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and diff --git a/device_tree/data/kernel_dtsi/2018.3/zynqmp/zynqmp-clk-ccf.dtsi b/device_tree/data/kernel_dtsi/2018.3/zynqmp/zynqmp-clk-ccf.dtsi index 6b2702b4..a4cbb82e 100644 --- a/device_tree/data/kernel_dtsi/2018.3/zynqmp/zynqmp-clk-ccf.dtsi +++ b/device_tree/data/kernel_dtsi/2018.3/zynqmp/zynqmp-clk-ccf.dtsi @@ -2,7 +2,8 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2017, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2018.3/zynqmp/zynqmp.dtsi b/device_tree/data/kernel_dtsi/2018.3/zynqmp/zynqmp.dtsi index 8b931cc9..7ad5bdb3 100644 --- a/device_tree/data/kernel_dtsi/2018.3/zynqmp/zynqmp.dtsi +++ b/device_tree/data/kernel_dtsi/2018.3/zynqmp/zynqmp.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP * - * (C) Copyright 2014 - 2015, Xilinx, Inc. + * (C) Copyright 2014-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/2019.1/BOARD/avnet-ultra96-rev1.dtsi b/device_tree/data/kernel_dtsi/2019.1/BOARD/avnet-ultra96-rev1.dtsi index 60d70fec..9fcaf106 100644 --- a/device_tree/data/kernel_dtsi/2019.1/BOARD/avnet-ultra96-rev1.dtsi +++ b/device_tree/data/kernel_dtsi/2019.1/BOARD/avnet-ultra96-rev1.dtsi @@ -2,7 +2,8 @@ /* * dts file for Avnet Ultra96 rev1 * - * (C) Copyright 2018, Xilinx, Inc. + * (C) Copyright 2018-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.1/BOARD/versal-a2197-sc-reva.dtsi b/device_tree/data/kernel_dtsi/2019.1/BOARD/versal-a2197-sc-reva.dtsi index ae6e9633..e83c5522 100644 --- a/device_tree/data/kernel_dtsi/2019.1/BOARD/versal-a2197-sc-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2019.1/BOARD/versal-a2197-sc-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.1/BOARD/zc1232-reva.dtsi b/device_tree/data/kernel_dtsi/2019.1/BOARD/zc1232-reva.dtsi index 17c480e4..7e6b24ff 100644 --- a/device_tree/data/kernel_dtsi/2019.1/BOARD/zc1232-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2019.1/BOARD/zc1232-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1232 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.1/BOARD/zc1254-reva.dtsi b/device_tree/data/kernel_dtsi/2019.1/BOARD/zc1254-reva.dtsi index 96225767..3ed797c6 100644 --- a/device_tree/data/kernel_dtsi/2019.1/BOARD/zc1254-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2019.1/BOARD/zc1254-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1254 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2019.1/BOARD/zc1275-reva.dtsi b/device_tree/data/kernel_dtsi/2019.1/BOARD/zc1275-reva.dtsi index 71ea5b64..cde8e42d 100644 --- a/device_tree/data/kernel_dtsi/2019.1/BOARD/zc1275-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2019.1/BOARD/zc1275-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1275 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2019.1/BOARD/zc1275-revb.dtsi b/device_tree/data/kernel_dtsi/2019.1/BOARD/zc1275-revb.dtsi index 8248bbd1..d90e5991 100644 --- a/device_tree/data/kernel_dtsi/2019.1/BOARD/zc1275-revb.dtsi +++ b/device_tree/data/kernel_dtsi/2019.1/BOARD/zc1275-revb.dtsi @@ -1,7 +1,8 @@ /* * dts file for Xilinx ZynqMP ZC1275 RevB * - * (C) Copyright 2018, Xilinx, Inc. + * (C) Copyright 2018-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2019.1/BOARD/zc1751-dc1.dtsi b/device_tree/data/kernel_dtsi/2019.1/BOARD/zc1751-dc1.dtsi index cdca255b..db1989de 100644 --- a/device_tree/data/kernel_dtsi/2019.1/BOARD/zc1751-dc1.dtsi +++ b/device_tree/data/kernel_dtsi/2019.1/BOARD/zc1751-dc1.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.1/BOARD/zc1751-dc2.dtsi b/device_tree/data/kernel_dtsi/2019.1/BOARD/zc1751-dc2.dtsi index 64cc644f..b38e7137 100644 --- a/device_tree/data/kernel_dtsi/2019.1/BOARD/zc1751-dc2.dtsi +++ b/device_tree/data/kernel_dtsi/2019.1/BOARD/zc1751-dc2.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.1/BOARD/zc702.dtsi b/device_tree/data/kernel_dtsi/2019.1/BOARD/zc702.dtsi index d30e5126..40f310b1 100644 --- a/device_tree/data/kernel_dtsi/2019.1/BOARD/zc702.dtsi +++ b/device_tree/data/kernel_dtsi/2019.1/BOARD/zc702.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2011 - 2015 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ diff --git a/device_tree/data/kernel_dtsi/2019.1/BOARD/zc706.dtsi b/device_tree/data/kernel_dtsi/2019.1/BOARD/zc706.dtsi index c1620418..18e76f8c 100644 --- a/device_tree/data/kernel_dtsi/2019.1/BOARD/zc706.dtsi +++ b/device_tree/data/kernel_dtsi/2019.1/BOARD/zc706.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2011 - 2015 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ diff --git a/device_tree/data/kernel_dtsi/2019.1/BOARD/zcu100-revc.dtsi b/device_tree/data/kernel_dtsi/2019.1/BOARD/zcu100-revc.dtsi index 7998eca0..fcc7797f 100644 --- a/device_tree/data/kernel_dtsi/2019.1/BOARD/zcu100-revc.dtsi +++ b/device_tree/data/kernel_dtsi/2019.1/BOARD/zcu100-revc.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU100 revC * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy diff --git a/device_tree/data/kernel_dtsi/2019.1/BOARD/zcu102-rev1.0.dtsi b/device_tree/data/kernel_dtsi/2019.1/BOARD/zcu102-rev1.0.dtsi index fde0623b..cf2d4c78 100644 --- a/device_tree/data/kernel_dtsi/2019.1/BOARD/zcu102-rev1.0.dtsi +++ b/device_tree/data/kernel_dtsi/2019.1/BOARD/zcu102-rev1.0.dtsi @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.1/BOARD/zcu102-reva.dtsi b/device_tree/data/kernel_dtsi/2019.1/BOARD/zcu102-reva.dtsi index 9e41c8fa..d0a7c46f 100644 --- a/device_tree/data/kernel_dtsi/2019.1/BOARD/zcu102-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2019.1/BOARD/zcu102-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevA * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.1/BOARD/zcu102-revb.dtsi b/device_tree/data/kernel_dtsi/2019.1/BOARD/zcu102-revb.dtsi index fb68e39b..689cb938 100644 --- a/device_tree/data/kernel_dtsi/2019.1/BOARD/zcu102-revb.dtsi +++ b/device_tree/data/kernel_dtsi/2019.1/BOARD/zcu102-revb.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevB * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.1/BOARD/zcu104-reva.dtsi b/device_tree/data/kernel_dtsi/2019.1/BOARD/zcu104-reva.dtsi index 29a9ae1f..61ebce39 100644 --- a/device_tree/data/kernel_dtsi/2019.1/BOARD/zcu104-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2019.1/BOARD/zcu104-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.1/BOARD/zcu104-revc.dtsi b/device_tree/data/kernel_dtsi/2019.1/BOARD/zcu104-revc.dtsi index e047d6e6..263576f1 100644 --- a/device_tree/data/kernel_dtsi/2019.1/BOARD/zcu104-revc.dtsi +++ b/device_tree/data/kernel_dtsi/2019.1/BOARD/zcu104-revc.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.1/BOARD/zcu106-reva.dtsi b/device_tree/data/kernel_dtsi/2019.1/BOARD/zcu106-reva.dtsi index 1ed93daa..9e3b8793 100644 --- a/device_tree/data/kernel_dtsi/2019.1/BOARD/zcu106-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2019.1/BOARD/zcu106-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU106 * - * (C) Copyright 2016, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.1/BOARD/zcu111-reva.dtsi b/device_tree/data/kernel_dtsi/2019.1/BOARD/zcu111-reva.dtsi index 82fab4a6..ee340be6 100644 --- a/device_tree/data/kernel_dtsi/2019.1/BOARD/zcu111-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2019.1/BOARD/zcu111-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU111 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.1/BOARD/zcu1285-reva.dtsi b/device_tree/data/kernel_dtsi/2019.1/BOARD/zcu1285-reva.dtsi index bf7ffb6b..6015b1b5 100644 --- a/device_tree/data/kernel_dtsi/2019.1/BOARD/zcu1285-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2019.1/BOARD/zcu1285-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU1285 RevA * - * (C) Copyright 2018 - 2019, Xilinx, Inc. + * (C) Copyright 2018-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2019.1/BOARD/zynqmp-a2197-g-reva.dtsi b/device_tree/data/kernel_dtsi/2019.1/BOARD/zynqmp-a2197-g-reva.dtsi index 4f895f1e..73454224 100644 --- a/device_tree/data/kernel_dtsi/2019.1/BOARD/zynqmp-a2197-g-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2019.1/BOARD/zynqmp-a2197-g-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller on MGT * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.1/BOARD/zynqmp-a2197-m-reva.dtsi b/device_tree/data/kernel_dtsi/2019.1/BOARD/zynqmp-a2197-m-reva.dtsi index 66b4da4b..ac561d0b 100644 --- a/device_tree/data/kernel_dtsi/2019.1/BOARD/zynqmp-a2197-m-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2019.1/BOARD/zynqmp-a2197-m-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.1/BOARD/zynqmp-a2197-p-reva.dtsi b/device_tree/data/kernel_dtsi/2019.1/BOARD/zynqmp-a2197-p-reva.dtsi index 2874b4ae..f8a0e6ca 100644 --- a/device_tree/data/kernel_dtsi/2019.1/BOARD/zynqmp-a2197-p-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2019.1/BOARD/zynqmp-a2197-p-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.1/BOARD/zynqmp-a2197-reva.dtsi b/device_tree/data/kernel_dtsi/2019.1/BOARD/zynqmp-a2197-reva.dtsi index 468d37ae..c908fe74 100644 --- a/device_tree/data/kernel_dtsi/2019.1/BOARD/zynqmp-a2197-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2019.1/BOARD/zynqmp-a2197-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller on MGT * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.1/include/dt-bindings/pinctrl/pinctrl-zynqmp.h b/device_tree/data/kernel_dtsi/2019.1/include/dt-bindings/pinctrl/pinctrl-zynqmp.h index 65522a1f..6a052e31 100644 --- a/device_tree/data/kernel_dtsi/2019.1/include/dt-bindings/pinctrl/pinctrl-zynqmp.h +++ b/device_tree/data/kernel_dtsi/2019.1/include/dt-bindings/pinctrl/pinctrl-zynqmp.h @@ -1,7 +1,8 @@ /* * MIO pin configuration defines for Xilinx ZynqMP * - * Copyright (C) 2017 Xilinx, Inc. + * Copyright (C) 2017-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Author: Chirag Parekh * * This program is free software; you can redistribute it and/or diff --git a/device_tree/data/kernel_dtsi/2019.1/zynq/zynq-7000.dtsi b/device_tree/data/kernel_dtsi/2019.1/zynq/zynq-7000.dtsi index 32b0c55e..e5dbe8c3 100644 --- a/device_tree/data/kernel_dtsi/2019.1/zynq/zynq-7000.dtsi +++ b/device_tree/data/kernel_dtsi/2019.1/zynq/zynq-7000.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2011 - 2015 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and diff --git a/device_tree/data/kernel_dtsi/2019.1/zynqmp/zynqmp-clk-ccf.dtsi b/device_tree/data/kernel_dtsi/2019.1/zynqmp/zynqmp-clk-ccf.dtsi index 2f71bd3b..247808c7 100644 --- a/device_tree/data/kernel_dtsi/2019.1/zynqmp/zynqmp-clk-ccf.dtsi +++ b/device_tree/data/kernel_dtsi/2019.1/zynqmp/zynqmp-clk-ccf.dtsi @@ -2,7 +2,8 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2017, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.1/zynqmp/zynqmp.dtsi b/device_tree/data/kernel_dtsi/2019.1/zynqmp/zynqmp.dtsi index c287a5fa..c6c581b0 100644 --- a/device_tree/data/kernel_dtsi/2019.1/zynqmp/zynqmp.dtsi +++ b/device_tree/data/kernel_dtsi/2019.1/zynqmp/zynqmp.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP * - * (C) Copyright 2014 - 2015, Xilinx, Inc. + * (C) Copyright 2014-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/2019.2/BOARD/avnet-ultra96-rev1.dtsi b/device_tree/data/kernel_dtsi/2019.2/BOARD/avnet-ultra96-rev1.dtsi index 60d70fec..9fcaf106 100644 --- a/device_tree/data/kernel_dtsi/2019.2/BOARD/avnet-ultra96-rev1.dtsi +++ b/device_tree/data/kernel_dtsi/2019.2/BOARD/avnet-ultra96-rev1.dtsi @@ -2,7 +2,8 @@ /* * dts file for Avnet Ultra96 rev1 * - * (C) Copyright 2018, Xilinx, Inc. + * (C) Copyright 2018-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-v350-reva.dtsi b/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-v350-reva.dtsi index f8c9c8f9..c126c2a0 100644 --- a/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-v350-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-v350-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal v350 revA * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi b/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi index fcd70f4e..7ed76ef6 100644 --- a/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi +++ b/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-01 revA (SE1) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi b/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi index cfea3680..b8ff53f0 100644 --- a/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi +++ b/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi b/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi index d3b67bf8..1fccc61c 100644 --- a/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi b/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi index 76a47ade..ffda4d51 100644 --- a/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-02 revA (SE2) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi b/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi index 888df4ec..d9b3ec1e 100644 --- a/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-03 revA (SE3) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi b/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi index d9935a02..c88599dc 100644 --- a/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi +++ b/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-04 revA (SE4) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi b/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi index 9165220e..73645d0d 100644 --- a/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-04 revA (SE4) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi b/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi index ac2e7086..67eea3c9 100644 --- a/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-05 revA (SE5) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva.dtsi b/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva.dtsi index 5472a169..5f25d559 100644 --- a/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi b/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi index 12a70203..235ab024 100644 --- a/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vck190 revA with X-EBM-01-revA module * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vck190-reva.dtsi b/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vck190-reva.dtsi index 32e48384..d9feb544 100644 --- a/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vck190-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vck190-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal VCK190 revA * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi b/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi index 5bb2ea3f..cbe4e8ec 100644 --- a/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vmk180 revA with X-EBM-01-revA module * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vmk180-reva.dtsi b/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vmk180-reva.dtsi index 88025fb2..fa34ae5a 100644 --- a/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vmk180-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vmk180-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal VMK180 revA * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.2/BOARD/zc1232-reva.dtsi b/device_tree/data/kernel_dtsi/2019.2/BOARD/zc1232-reva.dtsi index 275e8c97..2f8dffab 100644 --- a/device_tree/data/kernel_dtsi/2019.2/BOARD/zc1232-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2019.2/BOARD/zc1232-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1232 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.2/BOARD/zc1254-reva.dtsi b/device_tree/data/kernel_dtsi/2019.2/BOARD/zc1254-reva.dtsi index 70323db4..199a57c1 100644 --- a/device_tree/data/kernel_dtsi/2019.2/BOARD/zc1254-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2019.2/BOARD/zc1254-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1254 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2019.2/BOARD/zc1751-dc1.dtsi b/device_tree/data/kernel_dtsi/2019.2/BOARD/zc1751-dc1.dtsi index 9c090e13..bb6f3578 100644 --- a/device_tree/data/kernel_dtsi/2019.2/BOARD/zc1751-dc1.dtsi +++ b/device_tree/data/kernel_dtsi/2019.2/BOARD/zc1751-dc1.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.2/BOARD/zc1751-dc2.dtsi b/device_tree/data/kernel_dtsi/2019.2/BOARD/zc1751-dc2.dtsi index 46a47af1..95e1b82c 100644 --- a/device_tree/data/kernel_dtsi/2019.2/BOARD/zc1751-dc2.dtsi +++ b/device_tree/data/kernel_dtsi/2019.2/BOARD/zc1751-dc2.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.2/BOARD/zc702.dtsi b/device_tree/data/kernel_dtsi/2019.2/BOARD/zc702.dtsi index d30e5126..40f310b1 100644 --- a/device_tree/data/kernel_dtsi/2019.2/BOARD/zc702.dtsi +++ b/device_tree/data/kernel_dtsi/2019.2/BOARD/zc702.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2011 - 2015 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ diff --git a/device_tree/data/kernel_dtsi/2019.2/BOARD/zc706.dtsi b/device_tree/data/kernel_dtsi/2019.2/BOARD/zc706.dtsi index c1620418..18e76f8c 100644 --- a/device_tree/data/kernel_dtsi/2019.2/BOARD/zc706.dtsi +++ b/device_tree/data/kernel_dtsi/2019.2/BOARD/zc706.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2011 - 2015 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ diff --git a/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu100-revc.dtsi b/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu100-revc.dtsi index 8234bb2a..1fcec16c 100644 --- a/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu100-revc.dtsi +++ b/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu100-revc.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU100 revC * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy diff --git a/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu102-rev1.0.dtsi b/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu102-rev1.0.dtsi index b0b64c8d..ebd72e4d 100644 --- a/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu102-rev1.0.dtsi +++ b/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu102-rev1.0.dtsi @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu102-reva.dtsi b/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu102-reva.dtsi index 457d56e7..41b284e4 100644 --- a/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu102-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu102-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevA * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu102-revb.dtsi b/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu102-revb.dtsi index d08f79f2..6b5f11d9 100644 --- a/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu102-revb.dtsi +++ b/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu102-revb.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevB * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu104-reva.dtsi b/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu104-reva.dtsi index 74919271..9cee2c32 100644 --- a/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu104-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu104-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu104-revc.dtsi b/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu104-revc.dtsi index 2e65bac9..75110dfe 100644 --- a/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu104-revc.dtsi +++ b/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu104-revc.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu106-reva.dtsi b/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu106-reva.dtsi index fbdcc0e4..f09062b3 100644 --- a/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu106-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu106-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU106 * - * (C) Copyright 2016, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu111-reva.dtsi b/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu111-reva.dtsi index e48c5a91..e07881cf 100644 --- a/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu111-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu111-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU111 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu1275-reva.dtsi b/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu1275-reva.dtsi index 0d4d7f2b..7c344e42 100644 --- a/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu1275-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu1275-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU1275 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu1275-revb.dtsi b/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu1275-revb.dtsi index e7b03931..c492b05b 100644 --- a/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu1275-revb.dtsi +++ b/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu1275-revb.dtsi @@ -1,7 +1,8 @@ /* * dts file for Xilinx ZynqMP ZCU1275 RevB * - * (C) Copyright 2018, Xilinx, Inc. + * (C) Copyright 2018-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu1285-reva.dtsi b/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu1285-reva.dtsi index 0f9dc2ad..efffd86c 100644 --- a/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu1285-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu1285-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU1285 RevA * - * (C) Copyright 2018 - 2019, Xilinx, Inc. + * (C) Copyright 2018-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu216-reva.dtsi b/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu216-reva.dtsi index 1dbfb6ff..785b123e 100644 --- a/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu216-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2019.2/BOARD/zcu216-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU216 * - * (C) Copyright 2017 - 2019, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.2/BOARD/zynqmp-a2197-reva.dtsi b/device_tree/data/kernel_dtsi/2019.2/BOARD/zynqmp-a2197-reva.dtsi index 468d37ae..c908fe74 100644 --- a/device_tree/data/kernel_dtsi/2019.2/BOARD/zynqmp-a2197-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2019.2/BOARD/zynqmp-a2197-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller on MGT * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.2/BOARD/zynqmp-e-a2197-00-reva.dtsi b/device_tree/data/kernel_dtsi/2019.2/BOARD/zynqmp-e-a2197-00-reva.dtsi index fa72e958..01064e64 100644 --- a/device_tree/data/kernel_dtsi/2019.2/BOARD/zynqmp-e-a2197-00-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2019.2/BOARD/zynqmp-e-a2197-00-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.2/include/dt-bindings/pinctrl/pinctrl-zynqmp.h b/device_tree/data/kernel_dtsi/2019.2/include/dt-bindings/pinctrl/pinctrl-zynqmp.h index 65522a1f..6a052e31 100644 --- a/device_tree/data/kernel_dtsi/2019.2/include/dt-bindings/pinctrl/pinctrl-zynqmp.h +++ b/device_tree/data/kernel_dtsi/2019.2/include/dt-bindings/pinctrl/pinctrl-zynqmp.h @@ -1,7 +1,8 @@ /* * MIO pin configuration defines for Xilinx ZynqMP * - * Copyright (C) 2017 Xilinx, Inc. + * Copyright (C) 2017-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Author: Chirag Parekh * * This program is free software; you can redistribute it and/or diff --git a/device_tree/data/kernel_dtsi/2019.2/versal/versal-clk.dtsi b/device_tree/data/kernel_dtsi/2019.2/versal/versal-clk.dtsi index d5bd6ad1..2f5ed48f 100644 --- a/device_tree/data/kernel_dtsi/2019.2/versal/versal-clk.dtsi +++ b/device_tree/data/kernel_dtsi/2019.2/versal/versal-clk.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal with PM * - * (C) Copyright 2017 - 2019, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.2/versal/versal.dtsi b/device_tree/data/kernel_dtsi/2019.2/versal/versal.dtsi index c2fd5999..d88099fb 100644 --- a/device_tree/data/kernel_dtsi/2019.2/versal/versal.dtsi +++ b/device_tree/data/kernel_dtsi/2019.2/versal/versal.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal * - * (C) Copyright 2017 - 2019, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.2/zynq/zynq-7000.dtsi b/device_tree/data/kernel_dtsi/2019.2/zynq/zynq-7000.dtsi index 32b0c55e..e5dbe8c3 100644 --- a/device_tree/data/kernel_dtsi/2019.2/zynq/zynq-7000.dtsi +++ b/device_tree/data/kernel_dtsi/2019.2/zynq/zynq-7000.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2011 - 2015 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and diff --git a/device_tree/data/kernel_dtsi/2019.2/zynqmp/zynqmp-clk-ccf.dtsi b/device_tree/data/kernel_dtsi/2019.2/zynqmp/zynqmp-clk-ccf.dtsi index 2f71bd3b..247808c7 100644 --- a/device_tree/data/kernel_dtsi/2019.2/zynqmp/zynqmp-clk-ccf.dtsi +++ b/device_tree/data/kernel_dtsi/2019.2/zynqmp/zynqmp-clk-ccf.dtsi @@ -2,7 +2,8 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2017, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2019.2/zynqmp/zynqmp.dtsi b/device_tree/data/kernel_dtsi/2019.2/zynqmp/zynqmp.dtsi index 0a9b83e6..255e6430 100644 --- a/device_tree/data/kernel_dtsi/2019.2/zynqmp/zynqmp.dtsi +++ b/device_tree/data/kernel_dtsi/2019.2/zynqmp/zynqmp.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP * - * (C) Copyright 2014 - 2015, Xilinx, Inc. + * (C) Copyright 2014-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/avnet-ultra96-rev1.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/avnet-ultra96-rev1.dtsi index 19814e6f..81276cb6 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/avnet-ultra96-rev1.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/avnet-ultra96-rev1.dtsi @@ -2,7 +2,8 @@ /* * dts file for Avnet Ultra96 rev1 * - * (C) Copyright 2018, Xilinx, Inc. + * (C) Copyright 2018-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-a2197-sc-reva.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-a2197-sc-reva.dtsi index ae6e9633..e83c5522 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-a2197-sc-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-a2197-sc-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-spp-itr8-cn13940875.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-spp-itr8-cn13940875.dtsi index 77cd0c57..f1d9e69d 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-spp-itr8-cn13940875.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-spp-itr8-cn13940875.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal * - * (C) Copyright 2017 - 2019, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-v350-reva.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-v350-reva.dtsi index c0cb332e..4705452f 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-v350-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-v350-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal v350 revA * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi index 266a0c29..d888182b 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-01 revA (SE1) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi index cfea3680..b8ff53f0 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi index 5b23dd56..7917f427 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi index ed341f5e..832dfbb8 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-02 revA (SE2) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi index 9a8f3070..53bed0db 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-03 revA (SE3) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi index 4bf7dcc5..c886175d 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-04 revA (SE4) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi index 21cfddfe..87aa87fe 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-04 revA (SE4) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi index 3c5c3fc2..2109edc4 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-05 revA (SE5) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva.dtsi index cff1d330..e8fc0c50 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi index 5c65cf9e..5c11b972 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vck190 revA with X-EBM-01-revA module * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi index a183d67a..2dc23b18 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vck190 revA with X-EBM-02-revA module * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi index d0ac7e14..b0053817 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vck190 revA with X-EBM-03-revA module * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vck190-reva.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vck190-reva.dtsi index 2f1e3abd..2cb23d12 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vck190-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vck190-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal VCK190 revA * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi index 06743776..781b3138 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vmk180 revA with X-EBM-01-revA module * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi index cb8f79bd..1bf4e0c7 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vmk180 revA with X-EBM-02-revA module * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi index 2eeb6c92..2608fa40 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vmk180 revA with X-EBM-03-revA module * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vmk180-reva.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vmk180-reva.dtsi index 4a40bd80..e9012707 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vmk180-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vmk180-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal VMK180 revA * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/zc1232-reva.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/zc1232-reva.dtsi index f6d2f1e7..21c6893f 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/zc1232-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/zc1232-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1232 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/zc1254-reva.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/zc1254-reva.dtsi index 0e4004de..39f313a6 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/zc1254-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/zc1254-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1254 * - * (C) Copyright 2015 - 2020, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/zc1751-dc1.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/zc1751-dc1.dtsi index 61643486..d41fde9a 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/zc1751-dc1.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/zc1751-dc1.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * - * (C) Copyright 2015 - 2020, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/zc1751-dc2.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/zc1751-dc2.dtsi index f4adb613..9fe968d2 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/zc1751-dc2.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/zc1751-dc2.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/zc702.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/zc702.dtsi index 29349cc2..d3ac03bc 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/zc702.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/zc702.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2011 - 2015 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/zc706.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/zc706.dtsi index cb240a9b..9450fa12 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/zc706.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/zc706.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2011 - 2015 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu100-revc.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu100-revc.dtsi index 1e73e89c..5fc1193a 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu100-revc.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu100-revc.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU100 revC * - * (C) Copyright 2016 - 2020, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu102-rev1.0.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu102-rev1.0.dtsi index 8887eab6..d844dfa3 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu102-rev1.0.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu102-rev1.0.dtsi @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 - * (C) Copyright 2016 - 2020, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu102-reva.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu102-reva.dtsi index e62ae3c4..e3aaa157 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu102-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu102-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevA * - * (C) Copyright 2015 - 2020, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu102-revb.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu102-revb.dtsi index 37a89b0d..4c613d16 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu102-revb.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu102-revb.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevB * - * (C) Copyright 2016 - 2020, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu104-reva.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu104-reva.dtsi index 1e2a81fd..1173704e 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu104-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu104-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu104-revc.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu104-revc.dtsi index 1f1d419d..0bab7567 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu104-revc.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu104-revc.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu106-reva.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu106-reva.dtsi index c465b682..4d3c7e22 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu106-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu106-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU106 * - * (C) Copyright 2016 - 2020, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu111-reva.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu111-reva.dtsi index e3ef221f..95762c94 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu111-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu111-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU111 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu1275-reva.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu1275-reva.dtsi index 55b83d13..a2b317c2 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu1275-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu1275-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU1275 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu1275-revb.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu1275-revb.dtsi index b72b2d66..4f99a752 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu1275-revb.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu1275-revb.dtsi @@ -1,7 +1,8 @@ /* * dts file for Xilinx ZynqMP ZCU1275 RevB * - * (C) Copyright 2018 - 2020, Xilinx, Inc. + * (C) Copyright 2018-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu1285-reva.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu1285-reva.dtsi index d5d7e07f..e7a700ee 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu1285-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu1285-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU1285 RevA * - * (C) Copyright 2018 - 2020, Xilinx, Inc. + * (C) Copyright 2018-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu208-reva.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu208-reva.dtsi index 5c67748f..09439b84 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu208-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu208-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU208 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu216-reva.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu216-reva.dtsi index fa0c34e1..2721e3af 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu216-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/zcu216-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU216 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-a2197-reva.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-a2197-reva.dtsi index 468d37ae..c908fe74 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-a2197-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-a2197-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller on MGT * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-e-a2197-00-reva.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-e-a2197-00-reva.dtsi index dc943b1f..dff0cdf8 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-e-a2197-00-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-e-a2197-00-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-g-a2197-00-reva.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-g-a2197-00-reva.dtsi index 1187d07b..d7cf46cc 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-g-a2197-00-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-g-a2197-00-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller on MGT * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-m-a2197-01-reva.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-m-a2197-01-reva.dtsi index 4a5962c3..1feffcf8 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-m-a2197-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-m-a2197-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-m-a2197-02-reva.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-m-a2197-02-reva.dtsi index 364f226e..cb5b5120 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-m-a2197-02-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-m-a2197-02-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-m-a2197-03-reva.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-m-a2197-03-reva.dtsi index 3cc2beba..30be31a8 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-m-a2197-03-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-m-a2197-03-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi index a927e184..60571e59 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi index fa028935..0ecd794b 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP System Controller X-PRC-02 revA (SE2) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi index 94e87cb9..c2c0d79b 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP System Controller X-PRC-03 revA (SE3) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi index 0c9956eb..c075a391 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP System Controller X-PRC-04 revA (SE4) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi index 1b9ab3bc..da4c20d6 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP System Controller X-PRC-05 revA (SE5) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-p-a2197-00-reva.dtsi b/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-p-a2197-00-reva.dtsi index 6621fc52..0b960464 100644 --- a/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-p-a2197-00-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-p-a2197-00-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/clock/xlnx-versal-clk.h b/device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/clock/xlnx-versal-clk.h index 264d634d..162361bb 100644 --- a/device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/clock/xlnx-versal-clk.h +++ b/device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/clock/xlnx-versal-clk.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2019 Xilinx Inc. + * Copyright (C) 2019-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * */ diff --git a/device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/clock/xlnx-zynqmp-clk.h b/device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/clock/xlnx-zynqmp-clk.h index cbdf80bc..52d5554b 100644 --- a/device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/clock/xlnx-zynqmp-clk.h +++ b/device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/clock/xlnx-zynqmp-clk.h @@ -2,7 +2,8 @@ /* * Xilinx Zynq MPSoC Firmware layer * - * Copyright (C) 2014-2018 Xilinx, Inc. + * Copyright (C) 2014-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * */ diff --git a/device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/pinctrl/pinctrl-zynqmp.h b/device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/pinctrl/pinctrl-zynqmp.h index 65522a1f..6a052e31 100644 --- a/device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/pinctrl/pinctrl-zynqmp.h +++ b/device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/pinctrl/pinctrl-zynqmp.h @@ -1,7 +1,8 @@ /* * MIO pin configuration defines for Xilinx ZynqMP * - * Copyright (C) 2017 Xilinx, Inc. + * Copyright (C) 2017-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Author: Chirag Parekh * * This program is free software; you can redistribute it and/or diff --git a/device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/power/xlnx-versal-power.h b/device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/power/xlnx-versal-power.h index 06bf914f..36e6d9a1 100644 --- a/device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/power/xlnx-versal-power.h +++ b/device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/power/xlnx-versal-power.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2019 Xilinx, Inc. + * Copyright (C) 2019-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_VERSAL_POWER_H diff --git a/device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/power/xlnx-zynqmp-power.h b/device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/power/xlnx-zynqmp-power.h index e7af0c41..80378265 100644 --- a/device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/power/xlnx-zynqmp-power.h +++ b/device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/power/xlnx-zynqmp-power.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2018 Xilinx, Inc. + * Copyright (C) 2018-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_ZYNQMP_POWER_H diff --git a/device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/reset/xlnx-zynqmp-resets.h b/device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/reset/xlnx-zynqmp-resets.h index 8b4859ce..f4305b22 100644 --- a/device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/reset/xlnx-zynqmp-resets.h +++ b/device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/reset/xlnx-zynqmp-resets.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2018 Xilinx, Inc. + * Copyright (C) 2018-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_ZYNQMP_RESETS_H diff --git a/device_tree/data/kernel_dtsi/2020.1/versal/versal-clk.dtsi b/device_tree/data/kernel_dtsi/2020.1/versal/versal-clk.dtsi index 208ff5c2..303267b4 100644 --- a/device_tree/data/kernel_dtsi/2020.1/versal/versal-clk.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/versal/versal-clk.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal with PM * - * (C) Copyright 2017 - 2019, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/versal/versal-spp-pm.dtsi b/device_tree/data/kernel_dtsi/2020.1/versal/versal-spp-pm.dtsi index f80796a6..33549439 100644 --- a/device_tree/data/kernel_dtsi/2020.1/versal/versal-spp-pm.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/versal/versal-spp-pm.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal with PM * - * (C) Copyright 2017 - 2019, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/versal/versal.dtsi b/device_tree/data/kernel_dtsi/2020.1/versal/versal.dtsi index 99481d69..857b79e8 100644 --- a/device_tree/data/kernel_dtsi/2020.1/versal/versal.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/versal/versal.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal * - * (C) Copyright 2017 - 2019, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/zynq/zynq-7000.dtsi b/device_tree/data/kernel_dtsi/2020.1/zynq/zynq-7000.dtsi index 9cefdf1a..c8cd4d86 100644 --- a/device_tree/data/kernel_dtsi/2020.1/zynq/zynq-7000.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/zynq/zynq-7000.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2011 - 2015 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and diff --git a/device_tree/data/kernel_dtsi/2020.1/zynqmp/zynqmp-clk-ccf.dtsi b/device_tree/data/kernel_dtsi/2020.1/zynqmp/zynqmp-clk-ccf.dtsi index 92ebeff3..716f0ff5 100644 --- a/device_tree/data/kernel_dtsi/2020.1/zynqmp/zynqmp-clk-ccf.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/zynqmp/zynqmp-clk-ccf.dtsi @@ -2,7 +2,8 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.1/zynqmp/zynqmp.dtsi b/device_tree/data/kernel_dtsi/2020.1/zynqmp/zynqmp.dtsi index f01bc776..60638455 100644 --- a/device_tree/data/kernel_dtsi/2020.1/zynqmp/zynqmp.dtsi +++ b/device_tree/data/kernel_dtsi/2020.1/zynqmp/zynqmp.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP * - * (C) Copyright 2014 - 2020, Xilinx, Inc. + * (C) Copyright 2014-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/avnet-ultra96-rev1.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/avnet-ultra96-rev1.dtsi index 19814e6f..81276cb6 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/avnet-ultra96-rev1.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/avnet-ultra96-rev1.dtsi @@ -2,7 +2,8 @@ /* * dts file for Avnet Ultra96 rev1 * - * (C) Copyright 2018, Xilinx, Inc. + * (C) Copyright 2018-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-a2197-sc-reva.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-a2197-sc-reva.dtsi index ae6e9633..e83c5522 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-a2197-sc-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-a2197-sc-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-spp-itr8-cn13940875.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-spp-itr8-cn13940875.dtsi index 77cd0c57..f1d9e69d 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-spp-itr8-cn13940875.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-spp-itr8-cn13940875.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal * - * (C) Copyright 2017 - 2019, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-v350-reva.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-v350-reva.dtsi index c0cb332e..4705452f 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-v350-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-v350-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal v350 revA * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi index 266a0c29..d888182b 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-01 revA (SE1) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi index cfea3680..b8ff53f0 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi index 5b23dd56..7917f427 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi index ed341f5e..832dfbb8 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-02 revA (SE2) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi index 9a8f3070..53bed0db 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-03 revA (SE3) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi index 4bf7dcc5..c886175d 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-04 revA (SE4) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi index 21cfddfe..87aa87fe 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-04 revA (SE4) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi index 07881762..0f7e52e1 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-05 revA (SE5) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva.dtsi index cff1d330..e8fc0c50 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi index cb6d0302..33074a04 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vck190 revA with X-EBM-01-revA module * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi index 98b355ae..f79f4583 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vck190 revA with X-EBM-02-revA module * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi index d0ac7e14..b0053817 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vck190 revA with X-EBM-03-revA module * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vck190-reva.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vck190-reva.dtsi index 2f1e3abd..2cb23d12 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vck190-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vck190-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal VCK190 revA * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vck5000-reva.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vck5000-reva.dtsi index 71fc960b..0c8d8bdc 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vck5000-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vck5000-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vck5000 revA * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi index cdc459c0..d9c0d117 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vmk180 revA with X-EBM-01-revA module * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi index a28d6e23..d9028ad3 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vmk180 revA with X-EBM-02-revA module * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi index 2eeb6c92..2608fa40 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vmk180 revA with X-EBM-03-revA module * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vmk180-reva.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vmk180-reva.dtsi index 4a40bd80..e9012707 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vmk180-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vmk180-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal VMK180 revA * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/zc1232-reva.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/zc1232-reva.dtsi index f6d2f1e7..21c6893f 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/zc1232-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/zc1232-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1232 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/zc1254-reva.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/zc1254-reva.dtsi index 0e4004de..39f313a6 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/zc1254-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/zc1254-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1254 * - * (C) Copyright 2015 - 2020, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/zc1751-dc1.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/zc1751-dc1.dtsi index 61643486..d41fde9a 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/zc1751-dc1.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/zc1751-dc1.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * - * (C) Copyright 2015 - 2020, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/zc1751-dc2.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/zc1751-dc2.dtsi index f4adb613..9fe968d2 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/zc1751-dc2.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/zc1751-dc2.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/zc702.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/zc702.dtsi index 29349cc2..d3ac03bc 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/zc702.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/zc702.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2011 - 2015 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/zc706.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/zc706.dtsi index cb240a9b..9450fa12 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/zc706.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/zc706.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2011 - 2015 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu100-revc.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu100-revc.dtsi index 1e73e89c..5fc1193a 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu100-revc.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu100-revc.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU100 revC * - * (C) Copyright 2016 - 2020, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu102-rev1.0.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu102-rev1.0.dtsi index 8887eab6..d844dfa3 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu102-rev1.0.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu102-rev1.0.dtsi @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 - * (C) Copyright 2016 - 2020, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu102-reva.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu102-reva.dtsi index e62ae3c4..e3aaa157 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu102-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu102-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevA * - * (C) Copyright 2015 - 2020, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu102-revb.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu102-revb.dtsi index 37a89b0d..4c613d16 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu102-revb.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu102-revb.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevB * - * (C) Copyright 2016 - 2020, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu104-reva.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu104-reva.dtsi index 1e2a81fd..1173704e 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu104-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu104-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu104-revc.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu104-revc.dtsi index 0ad901d4..41074390 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu104-revc.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu104-revc.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu106-reva.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu106-reva.dtsi index c465b682..4d3c7e22 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu106-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu106-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU106 * - * (C) Copyright 2016 - 2020, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu111-reva.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu111-reva.dtsi index 6be6ed17..4c20ffcc 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu111-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu111-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU111 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu1275-reva.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu1275-reva.dtsi index 55b83d13..a2b317c2 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu1275-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu1275-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU1275 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu1275-revb.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu1275-revb.dtsi index b49c800d..b6e30f0c 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu1275-revb.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu1275-revb.dtsi @@ -1,7 +1,8 @@ /* * dts file for Xilinx ZynqMP ZCU1275 RevB * - * (C) Copyright 2018 - 2020, Xilinx, Inc. + * (C) Copyright 2018-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu1285-reva.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu1285-reva.dtsi index d5d7e07f..e7a700ee 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu1285-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu1285-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU1285 RevA * - * (C) Copyright 2018 - 2020, Xilinx, Inc. + * (C) Copyright 2018-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu208-reva.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu208-reva.dtsi index d9f8290b..688142e3 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu208-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu208-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU208 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu216-reva.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu216-reva.dtsi index f2d1c3c1..e939e0f0 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu216-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/zcu216-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU216 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-a2197-reva.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-a2197-reva.dtsi index 468d37ae..c908fe74 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-a2197-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-a2197-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller on MGT * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-e-a2197-00-reva.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-e-a2197-00-reva.dtsi index e715a16b..5acd43b7 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-e-a2197-00-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-e-a2197-00-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-g-a2197-00-reva.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-g-a2197-00-reva.dtsi index 81025a19..97a16b76 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-g-a2197-00-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-g-a2197-00-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller on MGT * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-m-a2197-01-reva.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-m-a2197-01-reva.dtsi index 5825b50e..5374d126 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-m-a2197-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-m-a2197-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-m-a2197-02-reva.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-m-a2197-02-reva.dtsi index 565c57c2..9952b538 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-m-a2197-02-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-m-a2197-02-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-m-a2197-03-reva.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-m-a2197-03-reva.dtsi index 49101090..62027810 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-m-a2197-03-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-m-a2197-03-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi index 6e9ddf5e..8f27c252 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi index 6d6f116d..8d4daa85 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP System Controller X-PRC-02 revA (SE2) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi index c88edbda..23dc312e 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP System Controller X-PRC-03 revA (SE3) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi index 05b6fd28..cb1c8764 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP System Controller X-PRC-04 revA (SE4) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi index 5cc32c6d..b62db286 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP System Controller X-PRC-05 revA (SE5) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-p-a2197-00-reva.dtsi b/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-p-a2197-00-reva.dtsi index 67df5ad3..d1658202 100644 --- a/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-p-a2197-00-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-p-a2197-00-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/clock/xlnx-versal-clk.h b/device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/clock/xlnx-versal-clk.h index 264d634d..162361bb 100644 --- a/device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/clock/xlnx-versal-clk.h +++ b/device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/clock/xlnx-versal-clk.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2019 Xilinx Inc. + * Copyright (C) 2019-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * */ diff --git a/device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/clock/xlnx-zynqmp-clk.h b/device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/clock/xlnx-zynqmp-clk.h index cbdf80bc..52d5554b 100644 --- a/device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/clock/xlnx-zynqmp-clk.h +++ b/device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/clock/xlnx-zynqmp-clk.h @@ -2,7 +2,8 @@ /* * Xilinx Zynq MPSoC Firmware layer * - * Copyright (C) 2014-2018 Xilinx, Inc. + * Copyright (C) 2014-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * */ diff --git a/device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/pinctrl/pinctrl-zynqmp.h b/device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/pinctrl/pinctrl-zynqmp.h index 65522a1f..6a052e31 100644 --- a/device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/pinctrl/pinctrl-zynqmp.h +++ b/device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/pinctrl/pinctrl-zynqmp.h @@ -1,7 +1,8 @@ /* * MIO pin configuration defines for Xilinx ZynqMP * - * Copyright (C) 2017 Xilinx, Inc. + * Copyright (C) 2017-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Author: Chirag Parekh * * This program is free software; you can redistribute it and/or diff --git a/device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/power/xlnx-versal-power.h b/device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/power/xlnx-versal-power.h index 06bf914f..36e6d9a1 100644 --- a/device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/power/xlnx-versal-power.h +++ b/device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/power/xlnx-versal-power.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2019 Xilinx, Inc. + * Copyright (C) 2019-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_VERSAL_POWER_H diff --git a/device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/power/xlnx-zynqmp-power.h b/device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/power/xlnx-zynqmp-power.h index e7af0c41..80378265 100644 --- a/device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/power/xlnx-zynqmp-power.h +++ b/device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/power/xlnx-zynqmp-power.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2018 Xilinx, Inc. + * Copyright (C) 2018-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_ZYNQMP_POWER_H diff --git a/device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/reset/xlnx-zynqmp-resets.h b/device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/reset/xlnx-zynqmp-resets.h index 8b4859ce..f4305b22 100644 --- a/device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/reset/xlnx-zynqmp-resets.h +++ b/device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/reset/xlnx-zynqmp-resets.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2018 Xilinx, Inc. + * Copyright (C) 2018-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_ZYNQMP_RESETS_H diff --git a/device_tree/data/kernel_dtsi/2020.2/versal/versal-clk.dtsi b/device_tree/data/kernel_dtsi/2020.2/versal/versal-clk.dtsi index 208ff5c2..303267b4 100644 --- a/device_tree/data/kernel_dtsi/2020.2/versal/versal-clk.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/versal/versal-clk.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal with PM * - * (C) Copyright 2017 - 2019, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/versal/versal-spp-pm.dtsi b/device_tree/data/kernel_dtsi/2020.2/versal/versal-spp-pm.dtsi index f80796a6..33549439 100644 --- a/device_tree/data/kernel_dtsi/2020.2/versal/versal-spp-pm.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/versal/versal-spp-pm.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal with PM * - * (C) Copyright 2017 - 2019, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/versal/versal.dtsi b/device_tree/data/kernel_dtsi/2020.2/versal/versal.dtsi index 348c6fbb..7868946d 100644 --- a/device_tree/data/kernel_dtsi/2020.2/versal/versal.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/versal/versal.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal * - * (C) Copyright 2017 - 2019, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/zynq/zynq-7000.dtsi b/device_tree/data/kernel_dtsi/2020.2/zynq/zynq-7000.dtsi index 9cefdf1a..c8cd4d86 100644 --- a/device_tree/data/kernel_dtsi/2020.2/zynq/zynq-7000.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/zynq/zynq-7000.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2011 - 2015 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and diff --git a/device_tree/data/kernel_dtsi/2020.2/zynqmp/zynqmp-clk-ccf.dtsi b/device_tree/data/kernel_dtsi/2020.2/zynqmp/zynqmp-clk-ccf.dtsi index 92ebeff3..716f0ff5 100644 --- a/device_tree/data/kernel_dtsi/2020.2/zynqmp/zynqmp-clk-ccf.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/zynqmp/zynqmp-clk-ccf.dtsi @@ -2,7 +2,8 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2020.2/zynqmp/zynqmp.dtsi b/device_tree/data/kernel_dtsi/2020.2/zynqmp/zynqmp.dtsi index bd6b9cde..11aecb02 100644 --- a/device_tree/data/kernel_dtsi/2020.2/zynqmp/zynqmp.dtsi +++ b/device_tree/data/kernel_dtsi/2020.2/zynqmp/zynqmp.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP * - * (C) Copyright 2014 - 2020, Xilinx, Inc. + * (C) Copyright 2014-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/avnet-ultra96-rev1.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/avnet-ultra96-rev1.dtsi index 7bfbf841..58df7319 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/avnet-ultra96-rev1.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/avnet-ultra96-rev1.dtsi @@ -2,7 +2,8 @@ /* * dts file for Avnet Ultra96 rev1 * - * (C) Copyright 2018, Xilinx, Inc. + * (C) Copyright 2018-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-a2197-sc-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-a2197-sc-reva.dtsi index 1d90c010..8a406104 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-a2197-sc-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-a2197-sc-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-spp-itr8-cn13940875.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-spp-itr8-cn13940875.dtsi index 5f85588a..f2587000 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-spp-itr8-cn13940875.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-spp-itr8-cn13940875.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal * - * (C) Copyright 2017 - 2019, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-v350-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-v350-reva.dtsi index 0463aaa5..063c1e20 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-v350-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-v350-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal v350 revA * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi index 1990b196..0fa8c81f 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-01 revA (SE1) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi index 4df9dc1f..9135ece9 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi index fe96e7d1..aaf0b895 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi index 83ce3fda..185ce316 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-02 revA (SE2) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi index 81e6481e..c764f827 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-03 revA (SE3) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi index 632287b2..e048d86f 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-04 revA (SE4) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi index 47dcd386..4091c3c6 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-04 revA (SE4) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi index b0d63c37..7ee655ba 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-05 revA (SE5) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva.dtsi index cff1d330..e8fc0c50 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi index 39ccca8a..b23e1939 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vck190 revA with X-EBM-01-revA module * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi index f4076d7f..492e0fe8 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vck190 revA with X-EBM-02-revA module * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi index aa18175c..855e3bc2 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vck190 revA with X-EBM-03-revA module * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vck190-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vck190-reva.dtsi index 6e032780..6146bb4e 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vck190-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vck190-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal VCK190 revA * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vck5000-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vck5000-reva.dtsi index ea1ba904..365ede21 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vck5000-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vck5000-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vck5000 revA * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi index ae2ec0b5..8bcf140e 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vmk180 revA with X-EBM-01-revA module * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi index 7eabb183..0f2e6eae 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vmk180 revA with X-EBM-02-revA module * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi index 7072cc65..bb4b82fe 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vmk180 revA with X-EBM-03-revA module * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vmk180-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vmk180-reva.dtsi index 801bfa94..9109b7d9 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vmk180-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vmk180-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal VMK180 revA * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vp-x-a2785-00-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vp-x-a2785-00-reva.dtsi index 06dafda1..a00560f2 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vp-x-a2785-00-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vp-x-a2785-00-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vp-x-a2785-00 revA * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vpk120-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vpk120-reva.dtsi index 90867a18..43c14314 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vpk120-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vpk120-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vpk120 revA * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/zc1232-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/zc1232-reva.dtsi index 9beb1b42..a56b5a9e 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/zc1232-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/zc1232-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1232 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/zc1254-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/zc1254-reva.dtsi index 0e4004de..39f313a6 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/zc1254-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/zc1254-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1254 * - * (C) Copyright 2015 - 2020, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/zc1751-dc1.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/zc1751-dc1.dtsi index 6249635b..8eb91c52 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/zc1751-dc1.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/zc1751-dc1.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * - * (C) Copyright 2015 - 2020, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/zc1751-dc2.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/zc1751-dc2.dtsi index f635ceaf..1a288c1e 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/zc1751-dc2.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/zc1751-dc2.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/zc702.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/zc702.dtsi index 37e233f3..a214ddcc 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/zc702.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/zc702.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2011 - 2015 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/zc706.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/zc706.dtsi index cb240a9b..9450fa12 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/zc706.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/zc706.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2011 - 2015 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu100-revc.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu100-revc.dtsi index b9d09628..5993e047 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu100-revc.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu100-revc.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU100 revC * - * (C) Copyright 2016 - 2020, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu102-rev1.0.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu102-rev1.0.dtsi index 42355e34..903fea55 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu102-rev1.0.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu102-rev1.0.dtsi @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 - * (C) Copyright 2016 - 2020, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu102-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu102-reva.dtsi index c7041d6b..b3de96a9 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu102-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu102-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevA * - * (C) Copyright 2015 - 2020, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu102-revb.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu102-revb.dtsi index 3ecd82d5..7833f00e 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu102-revb.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu102-revb.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevB * - * (C) Copyright 2016 - 2020, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu104-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu104-reva.dtsi index 4a7c47ee..8c727c08 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu104-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu104-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu104-revc.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu104-revc.dtsi index b9f736aa..9a71d413 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu104-revc.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu104-revc.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu106-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu106-reva.dtsi index 94889bcd..f4804678 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu106-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu106-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU106 * - * (C) Copyright 2016 - 2020, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu111-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu111-reva.dtsi index 73c0ebcd..af2f46f7 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu111-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu111-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU111 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu1275-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu1275-reva.dtsi index 55b83d13..a2b317c2 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu1275-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu1275-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU1275 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu1275-revb.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu1275-revb.dtsi index b49c800d..b6e30f0c 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu1275-revb.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu1275-revb.dtsi @@ -1,7 +1,8 @@ /* * dts file for Xilinx ZynqMP ZCU1275 RevB * - * (C) Copyright 2018 - 2020, Xilinx, Inc. + * (C) Copyright 2018-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu1285-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu1285-reva.dtsi index fb40a3a0..5578d6fa 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu1285-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu1285-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU1285 RevA * - * (C) Copyright 2018 - 2020, Xilinx, Inc. + * (C) Copyright 2018-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu208-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu208-reva.dtsi index 5ef95fbf..127c5919 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu208-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu208-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU208 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu216-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu216-reva.dtsi index a2e8684b..d9a8801e 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu216-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu216-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU216 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu670-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu670-reva.dtsi index cb5cdafb..0a301bfe 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu670-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/zcu670-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU670 (67DR), ZCU670-LD (57DR) * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-a2197-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-a2197-reva.dtsi index e55ff80a..609facc0 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-a2197-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-a2197-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller on MGT * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-e-a2197-00-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-e-a2197-00-reva.dtsi index 5e8e22de..c02f041a 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-e-a2197-00-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-e-a2197-00-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-g-a2197-00-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-g-a2197-00-reva.dtsi index 346981b2..59de8fc3 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-g-a2197-00-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-g-a2197-00-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller on MGT * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-m-a2197-01-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-m-a2197-01-reva.dtsi index 35666988..4544d3c6 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-m-a2197-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-m-a2197-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-m-a2197-02-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-m-a2197-02-reva.dtsi index ce9d4614..849bbd5e 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-m-a2197-02-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-m-a2197-02-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-m-a2197-03-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-m-a2197-03-reva.dtsi index 4b90692f..386e766f 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-m-a2197-03-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-m-a2197-03-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi index 39e91f7c..eacd94b3 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi index 168d917d..07f01372 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP System Controller X-PRC-02 revA (SE2) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi index 0d7f6aed..58fb74a9 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP System Controller X-PRC-03 revA (SE3) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi index 31d406e3..407cb56f 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP System Controller X-PRC-04 revA (SE4) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi index 425c01a0..5d35eb50 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP System Controller X-PRC-05 revA (SE5) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-p-a2197-00-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-p-a2197-00-reva.dtsi index f00d3535..5309f043 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-p-a2197-00-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-p-a2197-00-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-reva-mlcc.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-reva-mlcc.dtsi index a9eab528..5f9a4570 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-reva-mlcc.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-reva-mlcc.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP K26 revA * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-reva.dtsi index 15fb12df..fcbd4d5b 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP SM-K26 rev1/B/A * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-reva01-mlcc.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-reva01-mlcc.dtsi index 029a2006..5898510c 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-reva01-mlcc.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-reva01-mlcc.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP K26 revA * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-reva01.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-reva01.dtsi index 41647281..ac515ed2 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-reva01.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-reva01.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP K26 revA * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-revb-mlcc.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-revb-mlcc.dtsi index d62532fb..b4a83801 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-revb-mlcc.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-revb-mlcc.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP K26 revB * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-revb.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-revb.dtsi index 2b567b44..ad893656 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-revb.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-revb.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP K26 revB * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-revb01-mlcc.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-revb01-mlcc.dtsi index d62532fb..b4a83801 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-revb01-mlcc.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-revb01-mlcc.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP K26 revB * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-revb01.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-revb01.dtsi index 5b47382a..4bd46007 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-revb01.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-revb01.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP K26 revB * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-smk-k26-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-smk-k26-reva.dtsi index 0fd465ec..2ed1ec99 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-smk-k26-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-smk-k26-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-vp-x-a2785-00-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-vp-x-a2785-00-reva.dtsi index 60921e23..945c60db 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-vp-x-a2785-00-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-vp-x-a2785-00-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP vp-x-a2785-00 RevA System Controller * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-vpk120-reva.dtsi b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-vpk120-reva.dtsi index 9b154fa0..9de51047 100644 --- a/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-vpk120-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-vpk120-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP VPK120 RevA System Controller * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/clock/xlnx-versal-clk.h b/device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/clock/xlnx-versal-clk.h index 264d634d..162361bb 100644 --- a/device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/clock/xlnx-versal-clk.h +++ b/device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/clock/xlnx-versal-clk.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2019 Xilinx Inc. + * Copyright (C) 2019-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * */ diff --git a/device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/clock/xlnx-zynqmp-clk.h b/device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/clock/xlnx-zynqmp-clk.h index cbdf80bc..52d5554b 100644 --- a/device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/clock/xlnx-zynqmp-clk.h +++ b/device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/clock/xlnx-zynqmp-clk.h @@ -2,7 +2,8 @@ /* * Xilinx Zynq MPSoC Firmware layer * - * Copyright (C) 2014-2018 Xilinx, Inc. + * Copyright (C) 2014-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * */ diff --git a/device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/pinctrl/pinctrl-zynqmp.h b/device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/pinctrl/pinctrl-zynqmp.h index 65522a1f..6a052e31 100644 --- a/device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/pinctrl/pinctrl-zynqmp.h +++ b/device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/pinctrl/pinctrl-zynqmp.h @@ -1,7 +1,8 @@ /* * MIO pin configuration defines for Xilinx ZynqMP * - * Copyright (C) 2017 Xilinx, Inc. + * Copyright (C) 2017-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Author: Chirag Parekh * * This program is free software; you can redistribute it and/or diff --git a/device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/power/xlnx-versal-power.h b/device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/power/xlnx-versal-power.h index 06bf914f..36e6d9a1 100644 --- a/device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/power/xlnx-versal-power.h +++ b/device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/power/xlnx-versal-power.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2019 Xilinx, Inc. + * Copyright (C) 2019-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_VERSAL_POWER_H diff --git a/device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/power/xlnx-zynqmp-power.h b/device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/power/xlnx-zynqmp-power.h index e7af0c41..80378265 100644 --- a/device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/power/xlnx-zynqmp-power.h +++ b/device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/power/xlnx-zynqmp-power.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2018 Xilinx, Inc. + * Copyright (C) 2018-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_ZYNQMP_POWER_H diff --git a/device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/reset/xlnx-zynqmp-resets.h b/device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/reset/xlnx-zynqmp-resets.h index 8b4859ce..f4305b22 100644 --- a/device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/reset/xlnx-zynqmp-resets.h +++ b/device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/reset/xlnx-zynqmp-resets.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2018 Xilinx, Inc. + * Copyright (C) 2018-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_ZYNQMP_RESETS_H diff --git a/device_tree/data/kernel_dtsi/2021.1/versal/versal-clk.dtsi b/device_tree/data/kernel_dtsi/2021.1/versal/versal-clk.dtsi index bf86d21e..b0ef11d9 100644 --- a/device_tree/data/kernel_dtsi/2021.1/versal/versal-clk.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/versal/versal-clk.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal with PM * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/versal/versal-spp-pm.dtsi b/device_tree/data/kernel_dtsi/2021.1/versal/versal-spp-pm.dtsi index f80796a6..33549439 100644 --- a/device_tree/data/kernel_dtsi/2021.1/versal/versal-spp-pm.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/versal/versal-spp-pm.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal with PM * - * (C) Copyright 2017 - 2019, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/versal/versal.dtsi b/device_tree/data/kernel_dtsi/2021.1/versal/versal.dtsi index cad9c37b..a98ac60a 100644 --- a/device_tree/data/kernel_dtsi/2021.1/versal/versal.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/versal/versal.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal * - * (C) Copyright 2017 - 2019, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/zynq/zynq-7000.dtsi b/device_tree/data/kernel_dtsi/2021.1/zynq/zynq-7000.dtsi index 11ba2b90..81440667 100644 --- a/device_tree/data/kernel_dtsi/2021.1/zynq/zynq-7000.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/zynq/zynq-7000.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2011 - 2015 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and diff --git a/device_tree/data/kernel_dtsi/2021.1/zynqmp/zynqmp-clk-ccf.dtsi b/device_tree/data/kernel_dtsi/2021.1/zynqmp/zynqmp-clk-ccf.dtsi index d9aa4273..5ff2e1ae 100644 --- a/device_tree/data/kernel_dtsi/2021.1/zynqmp/zynqmp-clk-ccf.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/zynqmp/zynqmp-clk-ccf.dtsi @@ -2,7 +2,8 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.1/zynqmp/zynqmp.dtsi b/device_tree/data/kernel_dtsi/2021.1/zynqmp/zynqmp.dtsi index 939e0288..054a9987 100644 --- a/device_tree/data/kernel_dtsi/2021.1/zynqmp/zynqmp.dtsi +++ b/device_tree/data/kernel_dtsi/2021.1/zynqmp/zynqmp.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP * - * (C) Copyright 2014 - 2020, Xilinx, Inc. + * (C) Copyright 2014-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/avnet-ultra96-rev1.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/avnet-ultra96-rev1.dtsi index 343267d1..dd453eb1 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/avnet-ultra96-rev1.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/avnet-ultra96-rev1.dtsi @@ -2,7 +2,8 @@ /* * dts file for Avnet Ultra96 rev1 * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-a2197-sc-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-a2197-sc-reva.dtsi index 23c1e9a8..b797c448 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-a2197-sc-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-a2197-sc-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-spp-itr8-cn13940875.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-spp-itr8-cn13940875.dtsi index 5f85588a..f2587000 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-spp-itr8-cn13940875.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-spp-itr8-cn13940875.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal * - * (C) Copyright 2017 - 2019, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-v350-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-v350-reva.dtsi index 0463aaa5..063c1e20 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-v350-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-v350-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal v350 revA * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi index 1990b196..0fa8c81f 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-01 revA (SE1) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi index 4df9dc1f..9135ece9 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi index fe96e7d1..aaf0b895 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi index 83ce3fda..185ce316 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-02 revA (SE2) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi index 81e6481e..c764f827 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-03 revA (SE3) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi index 632287b2..e048d86f 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-04 revA (SE4) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi index 47dcd386..4091c3c6 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-04 revA (SE4) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi index b0d63c37..7ee655ba 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-05 revA (SE5) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva.dtsi index cff1d330..e8fc0c50 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi index e6231f31..11639160 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vck190 revA with X-EBM-01-revA module * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi index 0f88ed13..a3dcf7d4 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vck190 revA with X-EBM-02-revA module * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi index 24b949e5..ede50d26 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vck190 revA with X-EBM-03-revA module * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vck190-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vck190-reva.dtsi index 7be252b8..b709f4a4 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vck190-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vck190-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal VCK190 revA * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vck5000-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vck5000-reva.dtsi index ea1ba904..365ede21 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vck5000-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vck5000-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vck5000 revA * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi index 710346ec..614d4520 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vmk180 revA with X-EBM-01-revA module * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi index da4edc4c..19340edc 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vmk180 revA with X-EBM-02-revA module * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi index 98f11406..0a71d59c 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vmk180 revA with X-EBM-03-revA module * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vmk180-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vmk180-reva.dtsi index 5cdee4ff..99d53fdc 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vmk180-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vmk180-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal VMK180 revA * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vp-x-a2785-00-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vp-x-a2785-00-reva.dtsi index 06dafda1..a00560f2 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vp-x-a2785-00-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vp-x-a2785-00-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vp-x-a2785-00 revA * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vpk120-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vpk120-reva.dtsi index 90867a18..43c14314 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vpk120-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vpk120-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vpk120 revA * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vpk120-revb.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vpk120-revb.dtsi index 19c1941e..67e16eee 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vpk120-revb.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vpk120-revb.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vpk120 revB * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/zc1232-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/zc1232-reva.dtsi index 3162a7cc..6b1fca5d 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/zc1232-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/zc1232-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1232 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/zc1254-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/zc1254-reva.dtsi index 0e4004de..39f313a6 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/zc1254-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/zc1254-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1254 * - * (C) Copyright 2015 - 2020, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/zc1751-dc1.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/zc1751-dc1.dtsi index 6c106069..7e455a17 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/zc1751-dc1.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/zc1751-dc1.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * - * (C) Copyright 2015 - 2020, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/zc1751-dc2.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/zc1751-dc2.dtsi index 9160088d..b854bb6c 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/zc1751-dc2.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/zc1751-dc2.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/zc702.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/zc702.dtsi index 4d2f4358..209e8219 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/zc702.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/zc702.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2011 - 2015 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/zc706.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/zc706.dtsi index cab05c7f..294f7adb 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/zc706.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/zc706.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2011 - 2015 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu100-revc.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu100-revc.dtsi index be7f7336..94542d3f 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu100-revc.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu100-revc.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU100 revC * - * (C) Copyright 2016 - 2021, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu102-rev1.0.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu102-rev1.0.dtsi index dc582cdd..7634be25 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu102-rev1.0.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu102-rev1.0.dtsi @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 - * (C) Copyright 2016 - 2020, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu102-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu102-reva.dtsi index ec7081b6..c6f1e86b 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu102-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu102-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevA * - * (C) Copyright 2015 - 2020, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu102-revb.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu102-revb.dtsi index e447fda7..65129266 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu102-revb.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu102-revb.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevB * - * (C) Copyright 2016 - 2020, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu104-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu104-reva.dtsi index 468dd9e3..00f99337 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu104-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu104-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu104-revc.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu104-revc.dtsi index ecd0f75c..d65ef575 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu104-revc.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu104-revc.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu106-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu106-reva.dtsi index 2605799b..529dc883 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu106-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu106-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU106 * - * (C) Copyright 2016 - 2021, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu111-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu111-reva.dtsi index 16504086..1f7813a8 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu111-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu111-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU111 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu1275-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu1275-reva.dtsi index 7760649b..a2b317c2 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu1275-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu1275-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU1275 * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu1275-revb.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu1275-revb.dtsi index db46bf69..b6e30f0c 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu1275-revb.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu1275-revb.dtsi @@ -1,7 +1,8 @@ /* * dts file for Xilinx ZynqMP ZCU1275 RevB * - * (C) Copyright 2018 - 2021, Xilinx, Inc. + * (C) Copyright 2018-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu1285-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu1285-reva.dtsi index e2f92276..5578d6fa 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu1285-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu1285-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU1285 RevA * - * (C) Copyright 2018 - 2021, Xilinx, Inc. + * (C) Copyright 2018-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu208-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu208-reva.dtsi index 03af8ab3..2622c2bd 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu208-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu208-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU208 * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu216-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu216-reva.dtsi index d4f8aa30..ac0843c5 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu216-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu216-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU216 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu670-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu670-reva.dtsi index a8e95f75..0650e857 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu670-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu670-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU670 (67DR), ZCU670-LD (57DR) * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu670-revb.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu670-revb.dtsi index 0deef8de..6f3b4de8 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu670-revb.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/zcu670-revb.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU670 (67DR) revB * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-a2197-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-a2197-reva.dtsi index 17334814..2680dd94 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-a2197-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-a2197-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller on MGT * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-e-a2197-00-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-e-a2197-00-reva.dtsi index 7c45aca4..ce567ed1 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-e-a2197-00-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-e-a2197-00-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-g-a2197-00-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-g-a2197-00-reva.dtsi index 19393872..439c91f1 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-g-a2197-00-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-g-a2197-00-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller on MGT * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-m-a2197-01-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-m-a2197-01-reva.dtsi index daf60885..bf5bb885 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-m-a2197-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-m-a2197-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-m-a2197-02-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-m-a2197-02-reva.dtsi index 4f6f0bbd..0be2873f 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-m-a2197-02-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-m-a2197-02-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-m-a2197-03-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-m-a2197-03-reva.dtsi index 901f6997..28555894 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-m-a2197-03-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-m-a2197-03-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi index 37d307b7..c152e3fe 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi index ed01bbc2..0a0e59d5 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP System Controller X-PRC-02 revA (SE2) * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi index b7d9f19f..5b3186dd 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP System Controller X-PRC-03 revA (SE3) * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi index 64f44fcd..9b915b87 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP System Controller X-PRC-04 revA (SE4) * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi index 8aeb63fb..183ad1ae 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP System Controller X-PRC-05 revA (SE5) * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-p-a2197-00-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-p-a2197-00-reva.dtsi index 501e73f3..dd6c3137 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-p-a2197-00-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-p-a2197-00-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-sc-revb.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-sc-revb.dtsi index 132f6b50..98a3ef79 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-sc-revb.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-sc-revb.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP Generic System Controller * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-sm-k26-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-sm-k26-reva.dtsi index 409a61a2..b4d393e1 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-sm-k26-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-sm-k26-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP SM-K26 rev1/B/A * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-smk-k26-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-smk-k26-reva.dtsi index 29dd896e..caff30ac 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-smk-k26-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-smk-k26-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-vp-x-a2785-00-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-vp-x-a2785-00-reva.dtsi index 65f3f6e6..02316542 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-vp-x-a2785-00-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-vp-x-a2785-00-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP vp-x-a2785-00 RevA System Controller * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-vpk120-reva.dtsi b/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-vpk120-reva.dtsi index 945b5142..005688cd 100644 --- a/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-vpk120-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-vpk120-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP VPK120 RevA System Controller * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/clock/xlnx-versal-clk.h b/device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/clock/xlnx-versal-clk.h index 264d634d..162361bb 100644 --- a/device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/clock/xlnx-versal-clk.h +++ b/device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/clock/xlnx-versal-clk.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2019 Xilinx Inc. + * Copyright (C) 2019-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * */ diff --git a/device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/clock/xlnx-zynqmp-clk.h b/device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/clock/xlnx-zynqmp-clk.h index cbdf80bc..52d5554b 100644 --- a/device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/clock/xlnx-zynqmp-clk.h +++ b/device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/clock/xlnx-zynqmp-clk.h @@ -2,7 +2,8 @@ /* * Xilinx Zynq MPSoC Firmware layer * - * Copyright (C) 2014-2018 Xilinx, Inc. + * Copyright (C) 2014-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * */ diff --git a/device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/pinctrl/pinctrl-zynqmp.h b/device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/pinctrl/pinctrl-zynqmp.h index 65522a1f..6a052e31 100644 --- a/device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/pinctrl/pinctrl-zynqmp.h +++ b/device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/pinctrl/pinctrl-zynqmp.h @@ -1,7 +1,8 @@ /* * MIO pin configuration defines for Xilinx ZynqMP * - * Copyright (C) 2017 Xilinx, Inc. + * Copyright (C) 2017-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Author: Chirag Parekh * * This program is free software; you can redistribute it and/or diff --git a/device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/power/xlnx-versal-power.h b/device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/power/xlnx-versal-power.h index 73a04b37..5b881d65 100644 --- a/device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/power/xlnx-versal-power.h +++ b/device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/power/xlnx-versal-power.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2019 Xilinx, Inc. + * Copyright (C) 2019-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_VERSAL_POWER_H diff --git a/device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/power/xlnx-zynqmp-power.h b/device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/power/xlnx-zynqmp-power.h index 90aa27ab..2143f079 100644 --- a/device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/power/xlnx-zynqmp-power.h +++ b/device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/power/xlnx-zynqmp-power.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2018 Xilinx, Inc. + * Copyright (C) 2018-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_ZYNQMP_POWER_H diff --git a/device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/reset/xlnx-zynqmp-resets.h b/device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/reset/xlnx-zynqmp-resets.h index 8b4859ce..f4305b22 100644 --- a/device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/reset/xlnx-zynqmp-resets.h +++ b/device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/reset/xlnx-zynqmp-resets.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2018 Xilinx, Inc. + * Copyright (C) 2018-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_ZYNQMP_RESETS_H diff --git a/device_tree/data/kernel_dtsi/2021.2/versal/versal-clk.dtsi b/device_tree/data/kernel_dtsi/2021.2/versal/versal-clk.dtsi index bf86d21e..b0ef11d9 100644 --- a/device_tree/data/kernel_dtsi/2021.2/versal/versal-clk.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/versal/versal-clk.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal with PM * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/versal/versal-spp-pm.dtsi b/device_tree/data/kernel_dtsi/2021.2/versal/versal-spp-pm.dtsi index f80796a6..33549439 100644 --- a/device_tree/data/kernel_dtsi/2021.2/versal/versal-spp-pm.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/versal/versal-spp-pm.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal with PM * - * (C) Copyright 2017 - 2019, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/versal/versal.dtsi b/device_tree/data/kernel_dtsi/2021.2/versal/versal.dtsi index 134eb939..91f982f3 100644 --- a/device_tree/data/kernel_dtsi/2021.2/versal/versal.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/versal/versal.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal * - * (C) Copyright 2017 - 2019, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/zynq/zynq-7000.dtsi b/device_tree/data/kernel_dtsi/2021.2/zynq/zynq-7000.dtsi index 11ba2b90..81440667 100644 --- a/device_tree/data/kernel_dtsi/2021.2/zynq/zynq-7000.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/zynq/zynq-7000.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2011 - 2015 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and diff --git a/device_tree/data/kernel_dtsi/2021.2/zynqmp/zynqmp-clk-ccf.dtsi b/device_tree/data/kernel_dtsi/2021.2/zynqmp/zynqmp-clk-ccf.dtsi index 57cc953a..5ff2e1ae 100644 --- a/device_tree/data/kernel_dtsi/2021.2/zynqmp/zynqmp-clk-ccf.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/zynqmp/zynqmp-clk-ccf.dtsi @@ -2,7 +2,8 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2021.2/zynqmp/zynqmp.dtsi b/device_tree/data/kernel_dtsi/2021.2/zynqmp/zynqmp.dtsi index 97f572fb..30a4cfff 100644 --- a/device_tree/data/kernel_dtsi/2021.2/zynqmp/zynqmp.dtsi +++ b/device_tree/data/kernel_dtsi/2021.2/zynqmp/zynqmp.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP * - * (C) Copyright 2014 - 2021, Xilinx, Inc. + * (C) Copyright 2014-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/avnet-ultra96-rev1.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/avnet-ultra96-rev1.dtsi index 343267d1..dd453eb1 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/avnet-ultra96-rev1.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/avnet-ultra96-rev1.dtsi @@ -2,7 +2,8 @@ /* * dts file for Avnet Ultra96 rev1 * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-a2197-sc-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-a2197-sc-reva.dtsi index 23c1e9a8..b797c448 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-a2197-sc-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-a2197-sc-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-spp-itr8-cn13940875.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-spp-itr8-cn13940875.dtsi index affbdd9b..5e27001a 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-spp-itr8-cn13940875.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-spp-itr8-cn13940875.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal * - * (C) Copyright 2017 - 2019, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-v350-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-v350-reva.dtsi index 0463aaa5..063c1e20 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-v350-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-v350-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal v350 revA * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi index f9cfa571..2cf73994 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-01 revA (SE1) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi index eaa1967b..e7e32a73 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi index 77112e7d..8332f481 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-01 revA (SE1) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi index c588d87a..db53dc16 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-02 revA (SE2) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi index 02710a85..530db348 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-03 revA (SE3) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi index 632287b2..e048d86f 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-04 revA (SE4) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi index 98dc9e9f..07154ade 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-04 revA (SE4) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi index e2e14ec9..0fd6acd0 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-05 revA (SE5) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva.dtsi index cff1d330..e8fc0c50 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-rev1.1-x-ebm-01-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-rev1.1-x-ebm-01-reva.dtsi index 4f6a006f..eb0c7d0c 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-rev1.1-x-ebm-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-rev1.1-x-ebm-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-01-revA module * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-rev1.1-x-ebm-02-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-rev1.1-x-ebm-02-reva.dtsi index 8196780d..b47f8524 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-rev1.1-x-ebm-02-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-rev1.1-x-ebm-02-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-02-revA module * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-rev1.1-x-ebm-03-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-rev1.1-x-ebm-03-reva.dtsi index 4ac71fba..33196049 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-rev1.1-x-ebm-03-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-rev1.1-x-ebm-03-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-03-revA module * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-rev1.1.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-rev1.1.dtsi index a2d6b7ae..0ae6a01e 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-rev1.1.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-rev1.1.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal VCK190 rev1.1 * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi index 1ef73e3f..434a9278 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vck190 revA with X-EBM-01-revA module * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi index ffa89868..f157e6d4 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vck190 revA with X-EBM-02-revA module * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi index 704fe4ec..7541fc21 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vck190 revA with X-EBM-03-revA module * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-reva.dtsi index 6b987899..2e480850 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal VCK190 revA * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck5000-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck5000-reva.dtsi index ea1ba904..365ede21 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck5000-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck5000-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vck5000 revA * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vhk158-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vhk158-reva.dtsi index e7e279aa..67affa16 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vhk158-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vhk158-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal VHK158 revA * - * (C) Copyright 2022, Xilinx, Inc. + * (C) Copyright 2022-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-rev1.1-x-ebm-01-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-rev1.1-x-ebm-01-reva.dtsi index d125cd64..cbb8c967 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-rev1.1-x-ebm-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-rev1.1-x-ebm-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-01-revA module * - * (C) Copyright 2019 - 2021, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-rev1.1-x-ebm-02-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-rev1.1-x-ebm-02-reva.dtsi index 14974572..a1b8d1eb 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-rev1.1-x-ebm-02-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-rev1.1-x-ebm-02-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-02-revA module * - * (C) Copyright 2020 - 2021, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-rev1.1-x-ebm-03-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-rev1.1-x-ebm-03-reva.dtsi index 0c8f98ce..f4c0fefe 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-rev1.1-x-ebm-03-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-rev1.1-x-ebm-03-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal VMK180 rev1.1 with X-EBM-03-revA module * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-rev1.1.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-rev1.1.dtsi index b055e1f3..51228a87 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-rev1.1.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-rev1.1.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vmk180 rev1.1 * - * (C) Copyright 2019 - 2021, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi index dbd1bc87..ed2cf4cb 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vmk180 revA with X-EBM-01-revA module * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi index 1e392095..b9565380 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vmk180 revA with X-EBM-02-revA module * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi index 82c2e506..9bcdcac6 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vmk180 revA with X-EBM-03-revA module * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-reva.dtsi index 801bfa94..9109b7d9 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal VMK180 revA * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vp-x-a2785-00-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vp-x-a2785-00-reva.dtsi index 06438b05..7bebc1e4 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vp-x-a2785-00-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vp-x-a2785-00-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vp-x-a2785-00 revA * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vpk120-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vpk120-reva.dtsi index c3790102..265890fd 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vpk120-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vpk120-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vpk120 revA * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vpk120-revb.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vpk120-revb.dtsi index 915609ab..0f553c28 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vpk120-revb.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vpk120-revb.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vpk120 revB * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vpk180-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vpk180-reva.dtsi index 663a98ad..44e7968e 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vpk180-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vpk180-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vpk180 revA * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-x-ebm-01-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-x-ebm-01-reva.dtsi index e0d1105d..0036c8b8 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-x-ebm-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-x-ebm-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx X-EBM-01 revA for vck190/vmk180 * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-x-ebm-02-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-x-ebm-02-reva.dtsi index a4e8cd71..68ef323d 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-x-ebm-02-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-x-ebm-02-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx X-EBM-02 revA for vck190/vmk180 * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-x-ebm-03-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-x-ebm-03-reva.dtsi index e5c52361..bff5d39e 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-x-ebm-03-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/versal-x-ebm-03-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx X-EBM-03 revA for vck190/vmk180 * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/zc1232-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/zc1232-reva.dtsi index 24b101f1..0fc2fb34 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/zc1232-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/zc1232-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1232 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/zc1254-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/zc1254-reva.dtsi index 0832c65e..0ea0ad99 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/zc1254-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/zc1254-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1254 * - * (C) Copyright 2015 - 2020, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/zc1751-dc1.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/zc1751-dc1.dtsi index 22f19ccc..1b83f54c 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/zc1751-dc1.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/zc1751-dc1.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * - * (C) Copyright 2015 - 2020, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/zc1751-dc2.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/zc1751-dc2.dtsi index 9160088d..b854bb6c 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/zc1751-dc2.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/zc1751-dc2.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/zc702.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/zc702.dtsi index 4d2f4358..209e8219 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/zc702.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/zc702.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2011 - 2015 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/zc706.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/zc706.dtsi index cab05c7f..294f7adb 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/zc706.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/zc706.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2011 - 2015 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu100-revc.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu100-revc.dtsi index be7f7336..94542d3f 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu100-revc.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu100-revc.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU100 revC * - * (C) Copyright 2016 - 2021, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu102-rev1.0.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu102-rev1.0.dtsi index 0fadcdb0..09e1ac7f 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu102-rev1.0.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu102-rev1.0.dtsi @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 - * (C) Copyright 2016 - 2020, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu102-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu102-reva.dtsi index 832686c2..47012cdd 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu102-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu102-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevA * - * (C) Copyright 2015 - 2020, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu102-revb.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu102-revb.dtsi index db6747c5..9630ff10 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu102-revb.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu102-revb.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevB * - * (C) Copyright 2016 - 2020, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu104-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu104-reva.dtsi index b3e23f77..f0b65d96 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu104-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu104-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu104-revc.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu104-revc.dtsi index e329a2ae..3d1d4ad6 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu104-revc.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu104-revc.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu106-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu106-reva.dtsi index 97c79781..6c30ba18 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu106-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu106-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU106 * - * (C) Copyright 2016 - 2021, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu111-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu111-reva.dtsi index 8aee022e..996692f8 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu111-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu111-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU111 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu1275-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu1275-reva.dtsi index f38b5913..8e8e87cd 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu1275-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu1275-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU1275 * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu1275-revb.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu1275-revb.dtsi index db46bf69..b6e30f0c 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu1275-revb.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu1275-revb.dtsi @@ -1,7 +1,8 @@ /* * dts file for Xilinx ZynqMP ZCU1275 RevB * - * (C) Copyright 2018 - 2021, Xilinx, Inc. + * (C) Copyright 2018-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu1285-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu1285-reva.dtsi index e2f92276..5578d6fa 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu1285-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu1285-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU1285 RevA * - * (C) Copyright 2018 - 2021, Xilinx, Inc. + * (C) Copyright 2018-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu208-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu208-reva.dtsi index a4ea4c89..169c6df0 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu208-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu208-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU208 * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu216-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu216-reva.dtsi index 28353d2b..28964724 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu216-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu216-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU216 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu670-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu670-reva.dtsi index c493dae6..7f58d781 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu670-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu670-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU670 (67DR), ZCU670-LD (57DR) * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu670-revb.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu670-revb.dtsi index a9abfa94..0e457825 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu670-revb.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/zcu670-revb.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU670 (67DR) revB * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-a2197-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-a2197-reva.dtsi index 17334814..2680dd94 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-a2197-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-a2197-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller on MGT * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-e-a2197-00-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-e-a2197-00-reva.dtsi index 84fd2d06..a93b629b 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-e-a2197-00-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-e-a2197-00-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-g-a2197-00-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-g-a2197-00-reva.dtsi index 19393872..439c91f1 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-g-a2197-00-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-g-a2197-00-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller on MGT * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-m-a2197-01-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-m-a2197-01-reva.dtsi index 433d0c82..291fdf04 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-m-a2197-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-m-a2197-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-m-a2197-02-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-m-a2197-02-reva.dtsi index 54c2a682..b5b4a619 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-m-a2197-02-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-m-a2197-02-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-m-a2197-03-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-m-a2197-03-reva.dtsi index 04263b7e..5e9a53df 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-m-a2197-03-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-m-a2197-03-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi index 37d307b7..c152e3fe 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi index ed01bbc2..0a0e59d5 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP System Controller X-PRC-02 revA (SE2) * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi index b7d9f19f..5b3186dd 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP System Controller X-PRC-03 revA (SE3) * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi index 64f44fcd..9b915b87 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP System Controller X-PRC-04 revA (SE4) * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi index 8aeb63fb..183ad1ae 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP System Controller X-PRC-05 revA (SE5) * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-p-a2197-00-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-p-a2197-00-reva.dtsi index 9643b4a7..c85c3f5f 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-p-a2197-00-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-p-a2197-00-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-sc-revb.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-sc-revb.dtsi index 3374510c..aefe631f 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-sc-revb.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-sc-revb.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP Generic System Controller * - * (C) Copyright 2021-2022, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-sm-k26-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-sm-k26-reva.dtsi index ed388116..9fed8d1d 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-sm-k26-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-sm-k26-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP SM-K26 rev1/B/A * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-smk-k26-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-smk-k26-reva.dtsi index e263f529..12a6630b 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-smk-k26-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-smk-k26-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-vp-x-a2785-00-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-vp-x-a2785-00-reva.dtsi index 7a0d4f55..84eae89b 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-vp-x-a2785-00-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-vp-x-a2785-00-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP vp-x-a2785-00 RevA System Controller * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-vpk120-reva.dtsi b/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-vpk120-reva.dtsi index 8b46d807..f22e3d4b 100644 --- a/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-vpk120-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-vpk120-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP VPK120 RevA System Controller * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/clock/xlnx-versal-clk.h b/device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/clock/xlnx-versal-clk.h index 264d634d..162361bb 100644 --- a/device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/clock/xlnx-versal-clk.h +++ b/device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/clock/xlnx-versal-clk.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2019 Xilinx Inc. + * Copyright (C) 2019-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * */ diff --git a/device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/clock/xlnx-zynqmp-clk.h b/device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/clock/xlnx-zynqmp-clk.h index cbdf80bc..52d5554b 100644 --- a/device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/clock/xlnx-zynqmp-clk.h +++ b/device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/clock/xlnx-zynqmp-clk.h @@ -2,7 +2,8 @@ /* * Xilinx Zynq MPSoC Firmware layer * - * Copyright (C) 2014-2018 Xilinx, Inc. + * Copyright (C) 2014-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * */ diff --git a/device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/pinctrl/pinctrl-zynqmp.h b/device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/pinctrl/pinctrl-zynqmp.h index 5910b428..dd7312e6 100644 --- a/device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/pinctrl/pinctrl-zynqmp.h +++ b/device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/pinctrl/pinctrl-zynqmp.h @@ -2,7 +2,8 @@ /* * MIO pin configuration defines for Xilinx ZynqMP * - * Copyright (C) 2020 Xilinx, Inc. + * Copyright (C) 2020-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H diff --git a/device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/power/xlnx-versal-power.h b/device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/power/xlnx-versal-power.h index 09cfb02b..efc4c1f6 100644 --- a/device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/power/xlnx-versal-power.h +++ b/device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/power/xlnx-versal-power.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2019 - 2021 Xilinx, Inc. + * Copyright (C) 2019-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_VERSAL_POWER_H diff --git a/device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/power/xlnx-zynqmp-power.h b/device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/power/xlnx-zynqmp-power.h index 639fe18c..44ac524d 100644 --- a/device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/power/xlnx-zynqmp-power.h +++ b/device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/power/xlnx-zynqmp-power.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2018 Xilinx, Inc. + * Copyright (C) 2018-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_ZYNQMP_POWER_H diff --git a/device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/reset/xlnx-zynqmp-resets.h b/device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/reset/xlnx-zynqmp-resets.h index 8b4859ce..f4305b22 100644 --- a/device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/reset/xlnx-zynqmp-resets.h +++ b/device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/reset/xlnx-zynqmp-resets.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2018 Xilinx, Inc. + * Copyright (C) 2018-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_ZYNQMP_RESETS_H diff --git a/device_tree/data/kernel_dtsi/2022.1/versal/versal-clk.dtsi b/device_tree/data/kernel_dtsi/2022.1/versal/versal-clk.dtsi index 0ae8a6c5..1903cb99 100644 --- a/device_tree/data/kernel_dtsi/2022.1/versal/versal-clk.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/versal/versal-clk.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal with PM * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/versal/versal-spp-pm.dtsi b/device_tree/data/kernel_dtsi/2022.1/versal/versal-spp-pm.dtsi index f80796a6..33549439 100644 --- a/device_tree/data/kernel_dtsi/2022.1/versal/versal-spp-pm.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/versal/versal-spp-pm.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal with PM * - * (C) Copyright 2017 - 2019, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/versal/versal.dtsi b/device_tree/data/kernel_dtsi/2022.1/versal/versal.dtsi index 6679a65e..55f6a167 100644 --- a/device_tree/data/kernel_dtsi/2022.1/versal/versal.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/versal/versal.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/zynq/zynq-7000.dtsi b/device_tree/data/kernel_dtsi/2022.1/zynq/zynq-7000.dtsi index 18f08c24..fd61b4e5 100644 --- a/device_tree/data/kernel_dtsi/2022.1/zynq/zynq-7000.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/zynq/zynq-7000.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2011 - 2015 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and diff --git a/device_tree/data/kernel_dtsi/2022.1/zynqmp/zynqmp-clk-ccf.dtsi b/device_tree/data/kernel_dtsi/2022.1/zynqmp/zynqmp-clk-ccf.dtsi index f523e897..83ba56f1 100644 --- a/device_tree/data/kernel_dtsi/2022.1/zynqmp/zynqmp-clk-ccf.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/zynqmp/zynqmp-clk-ccf.dtsi @@ -2,7 +2,8 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.1/zynqmp/zynqmp.dtsi b/device_tree/data/kernel_dtsi/2022.1/zynqmp/zynqmp.dtsi index d07c6298..bea53f0c 100644 --- a/device_tree/data/kernel_dtsi/2022.1/zynqmp/zynqmp.dtsi +++ b/device_tree/data/kernel_dtsi/2022.1/zynqmp/zynqmp.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP * - * (C) Copyright 2014 - 2021, Xilinx, Inc. + * (C) Copyright 2014-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/avnet-ultra96-rev1.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/avnet-ultra96-rev1.dtsi index 9b638a81..b0d8e703 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/avnet-ultra96-rev1.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/avnet-ultra96-rev1.dtsi @@ -2,7 +2,8 @@ /* * dts file for Avnet Ultra96 rev1 * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-a2197-sc-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-a2197-sc-reva.dtsi index 9d08ac2d..348c1160 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-a2197-sc-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-a2197-sc-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-net-emu-rev1.9.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-net-emu-rev1.9.dtsi index dba01a6a..0afb252f 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-net-emu-rev1.9.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-net-emu-rev1.9.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal NET * - * (C) Copyright 2021 - 2022, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-net-ipp-rev1.9-ospi.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-net-ipp-rev1.9-ospi.dtsi index 29d07718..f4664848 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-net-ipp-rev1.9-ospi.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-net-ipp-rev1.9-ospi.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal NET IPP/SPP OSPI * - * (C) Copyright 2021 - 2022, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-net-ipp-rev1.9.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-net-ipp-rev1.9.dtsi index e303d1fb..0aabcc01 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-net-ipp-rev1.9.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-net-ipp-rev1.9.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal NET * - * (C) Copyright 2021 - 2022, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-spp-itr8-cn13940875.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-spp-itr8-cn13940875.dtsi index 3eea7d8c..940b94ff 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-spp-itr8-cn13940875.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-spp-itr8-cn13940875.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal * - * (C) Copyright 2017 - 2019, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-v350-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-v350-reva.dtsi index 63824784..b734db79 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-v350-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-v350-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal v350 revA * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi index 2e6ef636..95eb9f31 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-01 revA (SE1) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi index eaa1967b..e7e32a73 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi index 77112e7d..8332f481 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-01 revA (SE1) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi index c588d87a..db53dc16 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-02 revA (SE2) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi index 02710a85..530db348 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-03 revA (SE3) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi index a620e918..20181edf 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-04 revA (SE4) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi index 98dc9e9f..07154ade 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-04 revA (SE4) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi index e2e14ec9..0fd6acd0 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-05 revA (SE5) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva.dtsi index cff1d330..e8fc0c50 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-rev1.1-x-ebm-01-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-rev1.1-x-ebm-01-reva.dtsi index d460279e..e73c3488 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-rev1.1-x-ebm-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-rev1.1-x-ebm-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-01-revA module * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-rev1.1-x-ebm-02-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-rev1.1-x-ebm-02-reva.dtsi index 8196780d..b47f8524 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-rev1.1-x-ebm-02-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-rev1.1-x-ebm-02-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-02-revA module * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-rev1.1-x-ebm-03-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-rev1.1-x-ebm-03-reva.dtsi index 4ac71fba..33196049 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-rev1.1-x-ebm-03-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-rev1.1-x-ebm-03-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-03-revA module * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-rev1.1.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-rev1.1.dtsi index a2d6b7ae..0ae6a01e 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-rev1.1.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-rev1.1.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal VCK190 rev1.1 * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi index 1ef73e3f..434a9278 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vck190 revA with X-EBM-01-revA module * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi index ffa89868..f157e6d4 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vck190 revA with X-EBM-02-revA module * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi index 704fe4ec..7541fc21 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vck190 revA with X-EBM-03-revA module * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-reva.dtsi index 6b987899..2e480850 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal VCK190 revA * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck5000-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck5000-reva.dtsi index db1635fb..4cdde4d8 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck5000-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck5000-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vck5000 revA * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vhk158-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vhk158-reva.dtsi index 1471490d..10e9a83b 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vhk158-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vhk158-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal VHK158 revA * - * (C) Copyright 2022, Xilinx, Inc. + * (C) Copyright 2022-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-rev1.1-x-ebm-01-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-rev1.1-x-ebm-01-reva.dtsi index d125cd64..cbb8c967 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-rev1.1-x-ebm-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-rev1.1-x-ebm-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-01-revA module * - * (C) Copyright 2019 - 2021, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-rev1.1-x-ebm-02-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-rev1.1-x-ebm-02-reva.dtsi index 14974572..a1b8d1eb 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-rev1.1-x-ebm-02-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-rev1.1-x-ebm-02-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-02-revA module * - * (C) Copyright 2020 - 2021, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-rev1.1-x-ebm-03-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-rev1.1-x-ebm-03-reva.dtsi index 0c8f98ce..f4c0fefe 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-rev1.1-x-ebm-03-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-rev1.1-x-ebm-03-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal VMK180 rev1.1 with X-EBM-03-revA module * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-rev1.1.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-rev1.1.dtsi index b055e1f3..51228a87 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-rev1.1.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-rev1.1.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vmk180 rev1.1 * - * (C) Copyright 2019 - 2021, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi index dbd1bc87..ed2cf4cb 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vmk180 revA with X-EBM-01-revA module * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi index 1e392095..b9565380 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vmk180 revA with X-EBM-02-revA module * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi index 82c2e506..9bcdcac6 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vmk180 revA with X-EBM-03-revA module * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-reva.dtsi index 9e22d90e..beeb6599 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal VMK180 revA * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vp-x-a2785-00-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vp-x-a2785-00-reva.dtsi index 06438b05..7bebc1e4 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vp-x-a2785-00-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vp-x-a2785-00-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vp-x-a2785-00 revA * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vpk120-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vpk120-reva.dtsi index c3790102..265890fd 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vpk120-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vpk120-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vpk120 revA * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vpk120-revb.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vpk120-revb.dtsi index 915609ab..0f553c28 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vpk120-revb.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vpk120-revb.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vpk120 revB * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vpk180-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vpk180-reva.dtsi index 663a98ad..44e7968e 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vpk180-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vpk180-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vpk180 revA * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-x-ebm-01-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-x-ebm-01-reva.dtsi index e0d1105d..0036c8b8 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-x-ebm-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-x-ebm-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx X-EBM-01 revA for vck190/vmk180 * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-x-ebm-02-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-x-ebm-02-reva.dtsi index a4e8cd71..68ef323d 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-x-ebm-02-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-x-ebm-02-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx X-EBM-02 revA for vck190/vmk180 * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-x-ebm-03-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-x-ebm-03-reva.dtsi index c8cca160..0448dc06 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-x-ebm-03-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/versal-x-ebm-03-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx X-EBM-03 revA for vck190/vmk180 * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/zc1232-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/zc1232-reva.dtsi index ae586171..7163ea6e 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/zc1232-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/zc1232-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1232 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/zc1254-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/zc1254-reva.dtsi index 0e254b87..9ed2594e 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/zc1254-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/zc1254-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1254 * - * (C) Copyright 2015 - 2020, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/zc1751-dc1.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/zc1751-dc1.dtsi index 2b7fadbb..ad2436ba 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/zc1751-dc1.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/zc1751-dc1.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * - * (C) Copyright 2015 - 2020, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/zc1751-dc2.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/zc1751-dc2.dtsi index 1984db9f..269db190 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/zc1751-dc2.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/zc1751-dc2.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/zc702.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/zc702.dtsi index 6863e33d..aa870550 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/zc702.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/zc702.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2011 - 2015 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/zc706.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/zc706.dtsi index 6c20353b..5d039c9e 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/zc706.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/zc706.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2011 - 2015 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu100-revc.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu100-revc.dtsi index 08fbf175..e8bb0f39 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu100-revc.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu100-revc.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU100 revC * - * (C) Copyright 2016 - 2021, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu102-rev1.0.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu102-rev1.0.dtsi index 0fadcdb0..09e1ac7f 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu102-rev1.0.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu102-rev1.0.dtsi @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 - * (C) Copyright 2016 - 2020, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu102-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu102-reva.dtsi index 20f3b075..16eb8815 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu102-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu102-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevA * - * (C) Copyright 2015 - 2020, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu102-revb.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu102-revb.dtsi index 8dfb0e41..bfaf36c0 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu102-revb.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu102-revb.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevB * - * (C) Copyright 2016 - 2020, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu104-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu104-reva.dtsi index c5ea2166..2b6a4f35 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu104-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu104-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu104-revc.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu104-revc.dtsi index 24cdda7c..637f86c0 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu104-revc.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu104-revc.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu106-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu106-reva.dtsi index b48852ff..b2b1810a 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu106-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu106-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU106 * - * (C) Copyright 2016 - 2021, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu111-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu111-reva.dtsi index c3a252e9..74cea6a2 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu111-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu111-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU111 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu1275-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu1275-reva.dtsi index d2b5d66a..df7cf17b 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu1275-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu1275-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU1275 * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu1275-revb.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu1275-revb.dtsi index 0268212c..42fbb36e 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu1275-revb.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu1275-revb.dtsi @@ -1,7 +1,8 @@ /* * dts file for Xilinx ZynqMP ZCU1275 RevB * - * (C) Copyright 2018 - 2021, Xilinx, Inc. + * (C) Copyright 2018-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu1285-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu1285-reva.dtsi index afa6b331..3c952e27 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu1285-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu1285-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU1285 RevA * - * (C) Copyright 2018 - 2021, Xilinx, Inc. + * (C) Copyright 2018-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu208-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu208-reva.dtsi index a55031e0..36072711 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu208-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu208-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU208 * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu216-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu216-reva.dtsi index 763ae45b..d08a3add 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu216-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu216-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU216 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu670-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu670-reva.dtsi index f277ccf3..a64d6ce7 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu670-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu670-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU670 (67DR), ZCU670-LD (57DR) * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu670-revb.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu670-revb.dtsi index c0bb478c..4284f509 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu670-revb.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu670-revb.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU670 (67DR) revB * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-a2197-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-a2197-reva.dtsi index cc45a897..6c23725e 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-a2197-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-a2197-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller on MGT * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-e-a2197-00-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-e-a2197-00-reva.dtsi index a4e1702d..f71979d4 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-e-a2197-00-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-e-a2197-00-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-e-a2197-00-revb.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-e-a2197-00-revb.dtsi index 5d68893c..6d004dd3 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-e-a2197-00-revb.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-e-a2197-00-revb.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevB System Controller * - * (C) Copyright 2019 - 2021, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-g-a2197-00-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-g-a2197-00-reva.dtsi index cfb888f7..7eab0f9a 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-g-a2197-00-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-g-a2197-00-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller on MGT * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-m-a2197-01-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-m-a2197-01-reva.dtsi index 8d6cdefa..c699c2a3 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-m-a2197-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-m-a2197-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-m-a2197-02-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-m-a2197-02-reva.dtsi index 60e28bfe..e18ac42e 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-m-a2197-02-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-m-a2197-02-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-m-a2197-03-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-m-a2197-03-reva.dtsi index b5df331e..24c6d9cb 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-m-a2197-03-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-m-a2197-03-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi index ed8a9ac6..79712df2 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi index ed01bbc2..0a0e59d5 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP System Controller X-PRC-02 revA (SE2) * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi index 592536d9..a770c565 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP System Controller X-PRC-03 revA (SE3) * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi index 64f44fcd..9b915b87 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP System Controller X-PRC-04 revA (SE4) * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi index 8aeb63fb..183ad1ae 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP System Controller X-PRC-05 revA (SE5) * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-p-a2197-00-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-p-a2197-00-reva.dtsi index 5d3c3c41..c8ccd41c 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-p-a2197-00-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-p-a2197-00-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-sc-revb.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-sc-revb.dtsi index 31408e96..eede2412 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-sc-revb.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-sc-revb.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP Generic System Controller * - * (C) Copyright 2021-2022, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-sm-k26-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-sm-k26-reva.dtsi index 8b6b4ca0..b3b4dfbc 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-sm-k26-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-sm-k26-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP SM-K26 rev1/B/A * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-smk-k26-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-smk-k26-reva.dtsi index e263f529..12a6630b 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-smk-k26-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-smk-k26-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-vp-x-a2785-00-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-vp-x-a2785-00-reva.dtsi index 48662c05..97d49ccb 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-vp-x-a2785-00-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-vp-x-a2785-00-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP vp-x-a2785-00 RevA System Controller * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-vpk120-reva.dtsi b/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-vpk120-reva.dtsi index 05222225..c22d191d 100644 --- a/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-vpk120-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-vpk120-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP VPK120 RevA System Controller * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/clock/xlnx-versal-clk.h b/device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/clock/xlnx-versal-clk.h index 264d634d..162361bb 100644 --- a/device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/clock/xlnx-versal-clk.h +++ b/device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/clock/xlnx-versal-clk.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2019 Xilinx Inc. + * Copyright (C) 2019-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * */ diff --git a/device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/clock/xlnx-zynqmp-clk.h b/device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/clock/xlnx-zynqmp-clk.h index cbdf80bc..52d5554b 100644 --- a/device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/clock/xlnx-zynqmp-clk.h +++ b/device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/clock/xlnx-zynqmp-clk.h @@ -2,7 +2,8 @@ /* * Xilinx Zynq MPSoC Firmware layer * - * Copyright (C) 2014-2018 Xilinx, Inc. + * Copyright (C) 2014-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * */ diff --git a/device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/pinctrl/pinctrl-zynqmp.h b/device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/pinctrl/pinctrl-zynqmp.h index 5910b428..dd7312e6 100644 --- a/device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/pinctrl/pinctrl-zynqmp.h +++ b/device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/pinctrl/pinctrl-zynqmp.h @@ -2,7 +2,8 @@ /* * MIO pin configuration defines for Xilinx ZynqMP * - * Copyright (C) 2020 Xilinx, Inc. + * Copyright (C) 2020-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H diff --git a/device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/power/xlnx-versal-net-power.h b/device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/power/xlnx-versal-net-power.h index 9bd7d64f..0c8ac0ee 100644 --- a/device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/power/xlnx-versal-net-power.h +++ b/device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/power/xlnx-versal-net-power.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2022 Xilinx, Inc. + * Copyright (C) 2022-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_VERSAL_NET_POWER_H diff --git a/device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/power/xlnx-versal-power.h b/device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/power/xlnx-versal-power.h index 09cfb02b..efc4c1f6 100644 --- a/device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/power/xlnx-versal-power.h +++ b/device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/power/xlnx-versal-power.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2019 - 2021 Xilinx, Inc. + * Copyright (C) 2019-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_VERSAL_POWER_H diff --git a/device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/power/xlnx-versal-regnode.h b/device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/power/xlnx-versal-regnode.h index 8d9eaff5..b419498e 100644 --- a/device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/power/xlnx-versal-regnode.h +++ b/device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/power/xlnx-versal-regnode.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2022 Xilinx, Inc. + * Copyright (C) 2022-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_VERSAL_REGNODE_H diff --git a/device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/power/xlnx-zynqmp-power.h b/device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/power/xlnx-zynqmp-power.h index 639fe18c..44ac524d 100644 --- a/device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/power/xlnx-zynqmp-power.h +++ b/device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/power/xlnx-zynqmp-power.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2018 Xilinx, Inc. + * Copyright (C) 2018-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_ZYNQMP_POWER_H diff --git a/device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/reset/xlnx-versal-net-resets.h b/device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/reset/xlnx-versal-net-resets.h index 71388da0..06f3c32d 100644 --- a/device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/reset/xlnx-versal-net-resets.h +++ b/device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/reset/xlnx-versal-net-resets.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2020 Xilinx, Inc. + * Copyright (C) 2020-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_VERSAL_NET_RESETS_H diff --git a/device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/reset/xlnx-versal-resets.h b/device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/reset/xlnx-versal-resets.h index 895424e9..28d3c6bb 100644 --- a/device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/reset/xlnx-versal-resets.h +++ b/device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/reset/xlnx-versal-resets.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2020 Xilinx, Inc. + * Copyright (C) 2020-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_VERSAL_RESETS_H diff --git a/device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/reset/xlnx-zynqmp-resets.h b/device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/reset/xlnx-zynqmp-resets.h index 8b4859ce..f4305b22 100644 --- a/device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/reset/xlnx-zynqmp-resets.h +++ b/device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/reset/xlnx-zynqmp-resets.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2018 Xilinx, Inc. + * Copyright (C) 2018-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_ZYNQMP_RESETS_H diff --git a/device_tree/data/kernel_dtsi/2022.2/versal-net/versal-net-ipp-rev1.9.dtsi b/device_tree/data/kernel_dtsi/2022.2/versal-net/versal-net-ipp-rev1.9.dtsi index 740e4749..d04fdff9 100644 --- a/device_tree/data/kernel_dtsi/2022.2/versal-net/versal-net-ipp-rev1.9.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/versal-net/versal-net-ipp-rev1.9.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal NET * - * (C) Copyright 2021 - 2022, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/versal/versal-clk.dtsi b/device_tree/data/kernel_dtsi/2022.2/versal/versal-clk.dtsi index 9e822b35..6257aa19 100644 --- a/device_tree/data/kernel_dtsi/2022.2/versal/versal-clk.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/versal/versal-clk.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal with PM * - * (C) Copyright 2017 - 2022, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/versal/versal-spp-pm.dtsi b/device_tree/data/kernel_dtsi/2022.2/versal/versal-spp-pm.dtsi index f80796a6..33549439 100644 --- a/device_tree/data/kernel_dtsi/2022.2/versal/versal-spp-pm.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/versal/versal-spp-pm.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal with PM * - * (C) Copyright 2017 - 2019, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/versal/versal.dtsi b/device_tree/data/kernel_dtsi/2022.2/versal/versal.dtsi index 9ef47459..db8085ad 100644 --- a/device_tree/data/kernel_dtsi/2022.2/versal/versal.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/versal/versal.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/zynq/zynq-7000.dtsi b/device_tree/data/kernel_dtsi/2022.2/zynq/zynq-7000.dtsi index ae7954af..b9f178f1 100644 --- a/device_tree/data/kernel_dtsi/2022.2/zynq/zynq-7000.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/zynq/zynq-7000.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2011 - 2015 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and diff --git a/device_tree/data/kernel_dtsi/2022.2/zynqmp/zynqmp-clk-ccf.dtsi b/device_tree/data/kernel_dtsi/2022.2/zynqmp/zynqmp-clk-ccf.dtsi index f60f3464..8df7a849 100644 --- a/device_tree/data/kernel_dtsi/2022.2/zynqmp/zynqmp-clk-ccf.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/zynqmp/zynqmp-clk-ccf.dtsi @@ -2,7 +2,8 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2022.2/zynqmp/zynqmp.dtsi b/device_tree/data/kernel_dtsi/2022.2/zynqmp/zynqmp.dtsi index cadbd885..82c76479 100644 --- a/device_tree/data/kernel_dtsi/2022.2/zynqmp/zynqmp.dtsi +++ b/device_tree/data/kernel_dtsi/2022.2/zynqmp/zynqmp.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP * - * (C) Copyright 2014 - 2021, Xilinx, Inc. + * (C) Copyright 2014-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/avnet-ultra96-rev1.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/avnet-ultra96-rev1.dtsi index 9b638a81..b0d8e703 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/avnet-ultra96-rev1.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/avnet-ultra96-rev1.dtsi @@ -2,7 +2,8 @@ /* * dts file for Avnet Ultra96 rev1 * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-a2197-sc-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-a2197-sc-reva.dtsi index 67eb87c9..d84aa56a 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-a2197-sc-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-a2197-sc-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-net-emu-rev1.9.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-net-emu-rev1.9.dtsi index 445eb082..7d120960 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-net-emu-rev1.9.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-net-emu-rev1.9.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal NET * - * (C) Copyright 2021 - 2022, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-net-ipp-rev1.9-ospi.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-net-ipp-rev1.9-ospi.dtsi index 29d07718..f4664848 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-net-ipp-rev1.9-ospi.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-net-ipp-rev1.9-ospi.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal NET IPP/SPP OSPI * - * (C) Copyright 2021 - 2022, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-net-ipp-rev1.9.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-net-ipp-rev1.9.dtsi index e984b51c..59c50af5 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-net-ipp-rev1.9.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-net-ipp-rev1.9.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal NET * - * (C) Copyright 2021 - 2022, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-spp-itr8-cn13940875.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-spp-itr8-cn13940875.dtsi index baf5e13c..6eb274ef 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-spp-itr8-cn13940875.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-spp-itr8-cn13940875.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal * - * (C) Copyright 2017 - 2019, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-v350-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-v350-reva.dtsi index 63824784..b734db79 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-v350-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-v350-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal v350 revA * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi index 2e6ef636..95eb9f31 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-01 revA (SE1) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi index f3a3ee80..22554e64 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi index 011e033f..6b7ea268 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-01 revA (SE1) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi index 0d9e23c0..6a9c608a 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-02 revA (SE2) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi index 02710a85..530db348 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-03 revA (SE3) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi index e29c7d78..209d17b7 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-04 revA (SE4) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi index 50f117cf..349566be 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-04 revA (SE4) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi index f0124921..60018a39 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal X-PRC-05 revA (SE5) * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva.dtsi index cff1d330..e8fc0c50 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-rev1.1-x-ebm-01-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-rev1.1-x-ebm-01-reva.dtsi index d460279e..e73c3488 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-rev1.1-x-ebm-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-rev1.1-x-ebm-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-01-revA module * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-rev1.1-x-ebm-02-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-rev1.1-x-ebm-02-reva.dtsi index 8196780d..b47f8524 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-rev1.1-x-ebm-02-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-rev1.1-x-ebm-02-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-02-revA module * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-rev1.1-x-ebm-03-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-rev1.1-x-ebm-03-reva.dtsi index 4ac71fba..33196049 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-rev1.1-x-ebm-03-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-rev1.1-x-ebm-03-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-03-revA module * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-rev1.1.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-rev1.1.dtsi index a2d6b7ae..0ae6a01e 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-rev1.1.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-rev1.1.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal VCK190 rev1.1 * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi index 1ef73e3f..434a9278 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vck190 revA with X-EBM-01-revA module * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi index ffa89868..f157e6d4 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vck190 revA with X-EBM-02-revA module * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi index 704fe4ec..7541fc21 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vck190 revA with X-EBM-03-revA module * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-reva.dtsi index 6b987899..2e480850 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal VCK190 revA * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck5000-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck5000-reva.dtsi index db1635fb..4cdde4d8 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck5000-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck5000-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vck5000 revA * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vhk158-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vhk158-reva.dtsi index 85fa7583..c2963e23 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vhk158-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vhk158-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal VHK158 revA * - * (C) Copyright 2022, Xilinx, Inc. + * (C) Copyright 2022-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-rev1.1-x-ebm-01-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-rev1.1-x-ebm-01-reva.dtsi index d125cd64..cbb8c967 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-rev1.1-x-ebm-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-rev1.1-x-ebm-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-01-revA module * - * (C) Copyright 2019 - 2021, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-rev1.1-x-ebm-02-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-rev1.1-x-ebm-02-reva.dtsi index 14974572..a1b8d1eb 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-rev1.1-x-ebm-02-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-rev1.1-x-ebm-02-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-02-revA module * - * (C) Copyright 2020 - 2021, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-rev1.1-x-ebm-03-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-rev1.1-x-ebm-03-reva.dtsi index 0c8f98ce..f4c0fefe 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-rev1.1-x-ebm-03-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-rev1.1-x-ebm-03-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal VMK180 rev1.1 with X-EBM-03-revA module * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-rev1.1.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-rev1.1.dtsi index b055e1f3..51228a87 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-rev1.1.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-rev1.1.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vmk180 rev1.1 * - * (C) Copyright 2019 - 2021, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi index dbd1bc87..ed2cf4cb 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vmk180 revA with X-EBM-01-revA module * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi index 1e392095..b9565380 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vmk180 revA with X-EBM-02-revA module * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi index 82c2e506..9bcdcac6 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vmk180 revA with X-EBM-03-revA module * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-reva.dtsi index dd04cfe9..6df98b0a 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal VMK180 revA * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vp-x-a2785-00-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vp-x-a2785-00-reva.dtsi index d6102a68..d2c0dc0a 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vp-x-a2785-00-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vp-x-a2785-00-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vp-x-a2785-00 revA * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vpk120-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vpk120-reva.dtsi index 2e4d0317..22b76b6a 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vpk120-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vpk120-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vpk120 revA * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vpk120-revb.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vpk120-revb.dtsi index 5a1c6ea2..589349cc 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vpk120-revb.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vpk120-revb.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vpk120 revB * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vpk180-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vpk180-reva.dtsi index 554cdf58..c079f465 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vpk180-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vpk180-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal vpk180 revA * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-x-ebm-01-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-x-ebm-01-reva.dtsi index e0d1105d..0036c8b8 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-x-ebm-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-x-ebm-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx X-EBM-01 revA for vck190/vmk180 * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-x-ebm-02-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-x-ebm-02-reva.dtsi index a4e8cd71..68ef323d 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-x-ebm-02-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-x-ebm-02-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx X-EBM-02 revA for vck190/vmk180 * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-x-ebm-03-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-x-ebm-03-reva.dtsi index c8cca160..0448dc06 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-x-ebm-03-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/versal-x-ebm-03-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx X-EBM-03 revA for vck190/vmk180 * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/zc1232-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/zc1232-reva.dtsi index ae586171..7163ea6e 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/zc1232-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/zc1232-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1232 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/zc1254-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/zc1254-reva.dtsi index 0e254b87..9ed2594e 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/zc1254-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/zc1254-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1254 * - * (C) Copyright 2015 - 2020, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/zc1751-dc1.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/zc1751-dc1.dtsi index 2b7fadbb..ad2436ba 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/zc1751-dc1.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/zc1751-dc1.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * - * (C) Copyright 2015 - 2020, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/zc1751-dc2.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/zc1751-dc2.dtsi index 1984db9f..269db190 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/zc1751-dc2.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/zc1751-dc2.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/zc702.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/zc702.dtsi index 6863e33d..aa870550 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/zc702.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/zc702.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2011 - 2015 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/zc706.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/zc706.dtsi index 6c20353b..5d039c9e 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/zc706.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/zc706.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2011 - 2015 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu100-revc.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu100-revc.dtsi index 08fbf175..e8bb0f39 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu100-revc.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu100-revc.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU100 revC * - * (C) Copyright 2016 - 2021, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu102-rev1.0.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu102-rev1.0.dtsi index 0fadcdb0..09e1ac7f 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu102-rev1.0.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu102-rev1.0.dtsi @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 - * (C) Copyright 2016 - 2020, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu102-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu102-reva.dtsi index ccfbb21a..ded6ab54 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu102-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu102-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevA * - * (C) Copyright 2015 - 2020, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu102-revb.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu102-revb.dtsi index a6a2ac06..23148899 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu102-revb.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu102-revb.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevB * - * (C) Copyright 2016 - 2020, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu104-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu104-reva.dtsi index d0ef662d..2cba586a 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu104-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu104-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu104-revc.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu104-revc.dtsi index a809594a..3a6b4864 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu104-revc.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu104-revc.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu106-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu106-reva.dtsi index be5c5ad7..42914ff2 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu106-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu106-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU106 * - * (C) Copyright 2016 - 2021, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu111-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu111-reva.dtsi index a276c2e2..61f72856 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu111-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu111-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU111 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu1275-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu1275-reva.dtsi index d2b5d66a..df7cf17b 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu1275-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu1275-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU1275 * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu1275-revb.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu1275-revb.dtsi index 0268212c..42fbb36e 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu1275-revb.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu1275-revb.dtsi @@ -1,7 +1,8 @@ /* * dts file for Xilinx ZynqMP ZCU1275 RevB * - * (C) Copyright 2018 - 2021, Xilinx, Inc. + * (C) Copyright 2018-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu1285-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu1285-reva.dtsi index afa6b331..3c952e27 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu1285-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu1285-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU1285 RevA * - * (C) Copyright 2018 - 2021, Xilinx, Inc. + * (C) Copyright 2018-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu208-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu208-reva.dtsi index 2a93f176..4e9dee49 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu208-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu208-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU208 * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu216-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu216-reva.dtsi index 15ffeab1..cc4a7a91 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu216-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu216-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU216 * - * (C) Copyright 2017 - 2020, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu670-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu670-reva.dtsi index 5eb64f3d..f4727aed 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu670-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu670-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU670 (67DR), ZCU670-LD (57DR) * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu670-revb.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu670-revb.dtsi index fbef44d4..23048c7c 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu670-revb.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/zcu670-revb.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU670 (67DR) revB * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-a2197-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-a2197-reva.dtsi index 58c639c0..3fde185e 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-a2197-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-a2197-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller on MGT * - * (C) Copyright 2019, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-e-a2197-00-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-e-a2197-00-reva.dtsi index da9128ac..6fff7184 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-e-a2197-00-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-e-a2197-00-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-e-a2197-00-revb.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-e-a2197-00-revb.dtsi index 5d68893c..6d004dd3 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-e-a2197-00-revb.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-e-a2197-00-revb.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevB System Controller * - * (C) Copyright 2019 - 2021, Xilinx, Inc. + * (C) Copyright 2019-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-g-a2197-00-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-g-a2197-00-reva.dtsi index 37cfa0da..37e68956 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-g-a2197-00-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-g-a2197-00-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller on MGT * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-m-a2197-01-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-m-a2197-01-reva.dtsi index 598e6266..bccc9c92 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-m-a2197-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-m-a2197-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-m-a2197-02-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-m-a2197-02-reva.dtsi index a4ccbe53..112bbf4e 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-m-a2197-02-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-m-a2197-02-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-m-a2197-03-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-m-a2197-03-reva.dtsi index deaea90a..3d6c206b 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-m-a2197-03-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-m-a2197-03-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi index 35732191..1d07f11d 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi index 7e4f78af..d800b914 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP System Controller X-PRC-02 revA (SE2) * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi index e5dba81d..933f471a 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP System Controller X-PRC-03 revA (SE3) * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi index 4a629b71..76a94d57 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP System Controller X-PRC-04 revA (SE4) * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi index 69db9510..45b031f1 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP System Controller X-PRC-05 revA (SE5) * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-p-a2197-00-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-p-a2197-00-reva.dtsi index 252e90cc..b8712a07 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-p-a2197-00-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-p-a2197-00-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-sc-revb.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-sc-revb.dtsi index 30ac9e32..c6f0a491 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-sc-revb.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-sc-revb.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP Generic System Controller * - * (C) Copyright 2021-2022, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-sc-revc.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-sc-revc.dtsi index b13d8826..6f9f3aab 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-sc-revc.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-sc-revc.dtsi @@ -2,8 +2,8 @@ /* * dts file for Xilinx ZynqMP Generic System Controller * - * Copyright (C) 2021 - 2022, Xilinx, Inc. - * Copyright (C) 2022, Advanced Micro Devices, Inc. + * Copyright (C) 2021-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-sm-k26-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-sm-k26-reva.dtsi index 8b6b4ca0..b3b4dfbc 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-sm-k26-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-sm-k26-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP SM-K26 rev1/B/A * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-smk-k26-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-smk-k26-reva.dtsi index e263f529..12a6630b 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-smk-k26-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-smk-k26-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-vp-x-a2785-00-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-vp-x-a2785-00-reva.dtsi index ac0bc94e..a25e746c 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-vp-x-a2785-00-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-vp-x-a2785-00-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP vp-x-a2785-00 RevA System Controller * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-vpk120-reva.dtsi b/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-vpk120-reva.dtsi index b988069e..05250ac7 100644 --- a/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-vpk120-reva.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-vpk120-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP VPK120 RevA System Controller * - * (C) Copyright 2021, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/clock/xlnx-versal-clk.h b/device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/clock/xlnx-versal-clk.h index 264d634d..162361bb 100644 --- a/device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/clock/xlnx-versal-clk.h +++ b/device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/clock/xlnx-versal-clk.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2019 Xilinx Inc. + * Copyright (C) 2019-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * */ diff --git a/device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/clock/xlnx-versal-net-clk.h b/device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/clock/xlnx-versal-net-clk.h index 04ae468b..8ce0d25e 100644 --- a/device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/clock/xlnx-versal-net-clk.h +++ b/device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/clock/xlnx-versal-net-clk.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2022 Xilinx Inc. + * Copyright (C) 2022-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * */ diff --git a/device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/clock/xlnx-zynqmp-clk.h b/device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/clock/xlnx-zynqmp-clk.h index cbdf80bc..52d5554b 100644 --- a/device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/clock/xlnx-zynqmp-clk.h +++ b/device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/clock/xlnx-zynqmp-clk.h @@ -2,7 +2,8 @@ /* * Xilinx Zynq MPSoC Firmware layer * - * Copyright (C) 2014-2018 Xilinx, Inc. + * Copyright (C) 2014-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * */ diff --git a/device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/pinctrl/pinctrl-zynqmp.h b/device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/pinctrl/pinctrl-zynqmp.h index 5910b428..dd7312e6 100644 --- a/device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/pinctrl/pinctrl-zynqmp.h +++ b/device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/pinctrl/pinctrl-zynqmp.h @@ -2,7 +2,8 @@ /* * MIO pin configuration defines for Xilinx ZynqMP * - * Copyright (C) 2020 Xilinx, Inc. + * Copyright (C) 2020-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H diff --git a/device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/power/xlnx-versal-net-power.h b/device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/power/xlnx-versal-net-power.h index 55eedc9c..e11b94b6 100644 --- a/device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/power/xlnx-versal-net-power.h +++ b/device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/power/xlnx-versal-net-power.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2022 Xilinx, Inc. + * Copyright (C) 2022-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_VERSAL_NET_POWER_H diff --git a/device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/power/xlnx-versal-power.h b/device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/power/xlnx-versal-power.h index 09cfb02b..efc4c1f6 100644 --- a/device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/power/xlnx-versal-power.h +++ b/device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/power/xlnx-versal-power.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2019 - 2021 Xilinx, Inc. + * Copyright (C) 2019-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_VERSAL_POWER_H diff --git a/device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/power/xlnx-versal-regnode.h b/device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/power/xlnx-versal-regnode.h index 8d9eaff5..b419498e 100644 --- a/device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/power/xlnx-versal-regnode.h +++ b/device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/power/xlnx-versal-regnode.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2022 Xilinx, Inc. + * Copyright (C) 2022-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_VERSAL_REGNODE_H diff --git a/device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/power/xlnx-zynqmp-power.h b/device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/power/xlnx-zynqmp-power.h index 639fe18c..44ac524d 100644 --- a/device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/power/xlnx-zynqmp-power.h +++ b/device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/power/xlnx-zynqmp-power.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2018 Xilinx, Inc. + * Copyright (C) 2018-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_ZYNQMP_POWER_H diff --git a/device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/reset/xlnx-versal-net-resets.h b/device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/reset/xlnx-versal-net-resets.h index 71388da0..06f3c32d 100644 --- a/device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/reset/xlnx-versal-net-resets.h +++ b/device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/reset/xlnx-versal-net-resets.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2020 Xilinx, Inc. + * Copyright (C) 2020-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_VERSAL_NET_RESETS_H diff --git a/device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/reset/xlnx-versal-resets.h b/device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/reset/xlnx-versal-resets.h index 895424e9..28d3c6bb 100644 --- a/device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/reset/xlnx-versal-resets.h +++ b/device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/reset/xlnx-versal-resets.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2020 Xilinx, Inc. + * Copyright (C) 2020-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_VERSAL_RESETS_H diff --git a/device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/reset/xlnx-zynqmp-resets.h b/device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/reset/xlnx-zynqmp-resets.h index 8b4859ce..f4305b22 100644 --- a/device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/reset/xlnx-zynqmp-resets.h +++ b/device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/reset/xlnx-zynqmp-resets.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2018 Xilinx, Inc. + * Copyright (C) 2018-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_ZYNQMP_RESETS_H diff --git a/device_tree/data/kernel_dtsi/2023.1/versal-net/versal-net-ipp-rev1.9.dtsi b/device_tree/data/kernel_dtsi/2023.1/versal-net/versal-net-ipp-rev1.9.dtsi index e984b51c..59c50af5 100644 --- a/device_tree/data/kernel_dtsi/2023.1/versal-net/versal-net-ipp-rev1.9.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/versal-net/versal-net-ipp-rev1.9.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal NET * - * (C) Copyright 2021 - 2022, Xilinx, Inc. + * (C) Copyright 2021-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/versal/versal-clk.dtsi b/device_tree/data/kernel_dtsi/2023.1/versal/versal-clk.dtsi index 9e822b35..6257aa19 100644 --- a/device_tree/data/kernel_dtsi/2023.1/versal/versal-clk.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/versal/versal-clk.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal with PM * - * (C) Copyright 2017 - 2022, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/versal/versal-spp-pm.dtsi b/device_tree/data/kernel_dtsi/2023.1/versal/versal-spp-pm.dtsi index f80796a6..33549439 100644 --- a/device_tree/data/kernel_dtsi/2023.1/versal/versal-spp-pm.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/versal/versal-spp-pm.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal with PM * - * (C) Copyright 2017 - 2019, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/versal/versal.dtsi b/device_tree/data/kernel_dtsi/2023.1/versal/versal.dtsi index 2a880d6b..577090e3 100644 --- a/device_tree/data/kernel_dtsi/2023.1/versal/versal.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/versal/versal.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/zynq/zynq-7000.dtsi b/device_tree/data/kernel_dtsi/2023.1/zynq/zynq-7000.dtsi index a414d7e5..c6430ccf 100644 --- a/device_tree/data/kernel_dtsi/2023.1/zynq/zynq-7000.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/zynq/zynq-7000.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2011 - 2015 Xilinx + * Copyright (C) 2011-2022 Xilinx, Inc. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and diff --git a/device_tree/data/kernel_dtsi/2023.1/zynqmp/zynqmp-clk-ccf.dtsi b/device_tree/data/kernel_dtsi/2023.1/zynqmp/zynqmp-clk-ccf.dtsi index cf3f33da..d1074c7e 100644 --- a/device_tree/data/kernel_dtsi/2023.1/zynqmp/zynqmp-clk-ccf.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/zynqmp/zynqmp-clk-ccf.dtsi @@ -2,7 +2,8 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/2023.1/zynqmp/zynqmp.dtsi b/device_tree/data/kernel_dtsi/2023.1/zynqmp/zynqmp.dtsi index 5f980dfe..49c8fa5e 100644 --- a/device_tree/data/kernel_dtsi/2023.1/zynqmp/zynqmp.dtsi +++ b/device_tree/data/kernel_dtsi/2023.1/zynqmp/zynqmp.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP * - * (C) Copyright 2014 - 2021, Xilinx, Inc. + * (C) Copyright 2014-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/v4.17/board/zc1232-reva.dtsi b/device_tree/data/kernel_dtsi/v4.17/board/zc1232-reva.dtsi index 11d3533b..9086e8a5 100644 --- a/device_tree/data/kernel_dtsi/v4.17/board/zc1232-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v4.17/board/zc1232-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1232 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.17/board/zc1254-reva.dtsi b/device_tree/data/kernel_dtsi/v4.17/board/zc1254-reva.dtsi index b038b578..033a5678 100644 --- a/device_tree/data/kernel_dtsi/v4.17/board/zc1254-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v4.17/board/zc1254-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1254 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/v4.17/board/zc1275-reva.dtsi b/device_tree/data/kernel_dtsi/v4.17/board/zc1275-reva.dtsi index a01dccfb..8bfdc132 100644 --- a/device_tree/data/kernel_dtsi/v4.17/board/zc1275-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v4.17/board/zc1275-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1275 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/v4.17/board/zc1751-dc1.dtsi b/device_tree/data/kernel_dtsi/v4.17/board/zc1751-dc1.dtsi index ad67ab8e..34315632 100644 --- a/device_tree/data/kernel_dtsi/v4.17/board/zc1751-dc1.dtsi +++ b/device_tree/data/kernel_dtsi/v4.17/board/zc1751-dc1.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.17/board/zc1751-dc2.dtsi b/device_tree/data/kernel_dtsi/v4.17/board/zc1751-dc2.dtsi index c0c65029..e72e7d7e 100644 --- a/device_tree/data/kernel_dtsi/v4.17/board/zc1751-dc2.dtsi +++ b/device_tree/data/kernel_dtsi/v4.17/board/zc1751-dc2.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.17/board/zc1751-dc3.dtsi b/device_tree/data/kernel_dtsi/v4.17/board/zc1751-dc3.dtsi index 60e7b42c..71f00495 100644 --- a/device_tree/data/kernel_dtsi/v4.17/board/zc1751-dc3.dtsi +++ b/device_tree/data/kernel_dtsi/v4.17/board/zc1751-dc3.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm017-dc3 * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.17/board/zc1751-dc4.dtsi b/device_tree/data/kernel_dtsi/v4.17/board/zc1751-dc4.dtsi index 816fba97..ad817a70 100644 --- a/device_tree/data/kernel_dtsi/v4.17/board/zc1751-dc4.dtsi +++ b/device_tree/data/kernel_dtsi/v4.17/board/zc1751-dc4.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm018-dc4 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.17/board/zc1751-dc5.dtsi b/device_tree/data/kernel_dtsi/v4.17/board/zc1751-dc5.dtsi index 1822d09f..abb12d5e 100644 --- a/device_tree/data/kernel_dtsi/v4.17/board/zc1751-dc5.dtsi +++ b/device_tree/data/kernel_dtsi/v4.17/board/zc1751-dc5.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm019-dc5 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Siva Durga Prasad * Michal Simek diff --git a/device_tree/data/kernel_dtsi/v4.17/board/zcep108.dtsi b/device_tree/data/kernel_dtsi/v4.17/board/zcep108.dtsi index 8751506a..c2f815f1 100644 --- a/device_tree/data/kernel_dtsi/v4.17/board/zcep108.dtsi +++ b/device_tree/data/kernel_dtsi/v4.17/board/zcep108.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ep108 development board * - * (C) Copyright 2014 - 2015, Xilinx, Inc. + * (C) Copyright 2014-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/v4.17/board/zcu100-revc.dtsi b/device_tree/data/kernel_dtsi/v4.17/board/zcu100-revc.dtsi index cee8fced..04790677 100644 --- a/device_tree/data/kernel_dtsi/v4.17/board/zcu100-revc.dtsi +++ b/device_tree/data/kernel_dtsi/v4.17/board/zcu100-revc.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU100 revC * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy diff --git a/device_tree/data/kernel_dtsi/v4.17/board/zcu102-rev1.0.dtsi b/device_tree/data/kernel_dtsi/v4.17/board/zcu102-rev1.0.dtsi index ee6814d2..b64ef5e7 100644 --- a/device_tree/data/kernel_dtsi/v4.17/board/zcu102-rev1.0.dtsi +++ b/device_tree/data/kernel_dtsi/v4.17/board/zcu102-rev1.0.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.17/board/zcu102-reva.dtsi b/device_tree/data/kernel_dtsi/v4.17/board/zcu102-reva.dtsi index 68012bbf..73502f7b 100644 --- a/device_tree/data/kernel_dtsi/v4.17/board/zcu102-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v4.17/board/zcu102-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevA * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.17/board/zcu102-revb.dtsi b/device_tree/data/kernel_dtsi/v4.17/board/zcu102-revb.dtsi index f8883b7b..cb2d1674 100644 --- a/device_tree/data/kernel_dtsi/v4.17/board/zcu102-revb.dtsi +++ b/device_tree/data/kernel_dtsi/v4.17/board/zcu102-revb.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevB * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.17/board/zcu104-reva.dtsi b/device_tree/data/kernel_dtsi/v4.17/board/zcu104-reva.dtsi index 33622c7d..17adc329 100644 --- a/device_tree/data/kernel_dtsi/v4.17/board/zcu104-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v4.17/board/zcu104-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.17/board/zcu106-reva.dtsi b/device_tree/data/kernel_dtsi/v4.17/board/zcu106-reva.dtsi index be4e9c94..33c18109 100644 --- a/device_tree/data/kernel_dtsi/v4.17/board/zcu106-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v4.17/board/zcu106-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU106 * - * (C) Copyright 2016, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.17/board/zcu111-reva.dtsi b/device_tree/data/kernel_dtsi/v4.17/board/zcu111-reva.dtsi index d73801bd..ec50c145 100644 --- a/device_tree/data/kernel_dtsi/v4.17/board/zcu111-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v4.17/board/zcu111-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU111 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.17/zynqmp/zynqmp-clk.dtsi b/device_tree/data/kernel_dtsi/v4.17/zynqmp/zynqmp-clk.dtsi index 9c09baca..c9c7a762 100644 --- a/device_tree/data/kernel_dtsi/v4.17/zynqmp/zynqmp-clk.dtsi +++ b/device_tree/data/kernel_dtsi/v4.17/zynqmp/zynqmp-clk.dtsi @@ -2,7 +2,8 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.17/zynqmp/zynqmp.dtsi b/device_tree/data/kernel_dtsi/v4.17/zynqmp/zynqmp.dtsi index a091e6f0..84425c0f 100644 --- a/device_tree/data/kernel_dtsi/v4.17/zynqmp/zynqmp.dtsi +++ b/device_tree/data/kernel_dtsi/v4.17/zynqmp/zynqmp.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP * - * (C) Copyright 2014 - 2015, Xilinx, Inc. + * (C) Copyright 2014-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/v4.18/board/zc1232-reva.dtsi b/device_tree/data/kernel_dtsi/v4.18/board/zc1232-reva.dtsi index 26f546e0..2c07462f 100644 --- a/device_tree/data/kernel_dtsi/v4.18/board/zc1232-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v4.18/board/zc1232-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1232 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.18/board/zc1254-reva.dtsi b/device_tree/data/kernel_dtsi/v4.18/board/zc1254-reva.dtsi index 692c4257..0a493b44 100644 --- a/device_tree/data/kernel_dtsi/v4.18/board/zc1254-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v4.18/board/zc1254-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1254 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/v4.18/board/zc1275-reva.dtsi b/device_tree/data/kernel_dtsi/v4.18/board/zc1275-reva.dtsi index 5aca1e9f..beaf4cc8 100644 --- a/device_tree/data/kernel_dtsi/v4.18/board/zc1275-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v4.18/board/zc1275-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1275 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/v4.18/board/zc1751-dc1.dtsi b/device_tree/data/kernel_dtsi/v4.18/board/zc1751-dc1.dtsi index 072e3f55..ccea0cd5 100644 --- a/device_tree/data/kernel_dtsi/v4.18/board/zc1751-dc1.dtsi +++ b/device_tree/data/kernel_dtsi/v4.18/board/zc1751-dc1.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.18/board/zc1751-dc2.dtsi b/device_tree/data/kernel_dtsi/v4.18/board/zc1751-dc2.dtsi index dd2810a0..e3688d43 100644 --- a/device_tree/data/kernel_dtsi/v4.18/board/zc1751-dc2.dtsi +++ b/device_tree/data/kernel_dtsi/v4.18/board/zc1751-dc2.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.18/board/zc1751-dc3.dtsi b/device_tree/data/kernel_dtsi/v4.18/board/zc1751-dc3.dtsi index 5c807289..0646457d 100644 --- a/device_tree/data/kernel_dtsi/v4.18/board/zc1751-dc3.dtsi +++ b/device_tree/data/kernel_dtsi/v4.18/board/zc1751-dc3.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm017-dc3 * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.18/board/zc1751-dc4.dtsi b/device_tree/data/kernel_dtsi/v4.18/board/zc1751-dc4.dtsi index c8b6bdf9..84e8f502 100644 --- a/device_tree/data/kernel_dtsi/v4.18/board/zc1751-dc4.dtsi +++ b/device_tree/data/kernel_dtsi/v4.18/board/zc1751-dc4.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm018-dc4 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.18/board/zc1751-dc5.dtsi b/device_tree/data/kernel_dtsi/v4.18/board/zc1751-dc5.dtsi index afd450c3..55fb782b 100644 --- a/device_tree/data/kernel_dtsi/v4.18/board/zc1751-dc5.dtsi +++ b/device_tree/data/kernel_dtsi/v4.18/board/zc1751-dc5.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm019-dc5 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Siva Durga Prasad * Michal Simek diff --git a/device_tree/data/kernel_dtsi/v4.18/board/zcu100-revc.dtsi b/device_tree/data/kernel_dtsi/v4.18/board/zcu100-revc.dtsi index 0bb8d1cf..d791d2d5 100644 --- a/device_tree/data/kernel_dtsi/v4.18/board/zcu100-revc.dtsi +++ b/device_tree/data/kernel_dtsi/v4.18/board/zcu100-revc.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU100 revC * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy diff --git a/device_tree/data/kernel_dtsi/v4.18/board/zcu102-rev1.0.dtsi b/device_tree/data/kernel_dtsi/v4.18/board/zcu102-rev1.0.dtsi index ee6814d2..b64ef5e7 100644 --- a/device_tree/data/kernel_dtsi/v4.18/board/zcu102-rev1.0.dtsi +++ b/device_tree/data/kernel_dtsi/v4.18/board/zcu102-rev1.0.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.18/board/zcu102-reva.dtsi b/device_tree/data/kernel_dtsi/v4.18/board/zcu102-reva.dtsi index d65c2642..8530a388 100644 --- a/device_tree/data/kernel_dtsi/v4.18/board/zcu102-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v4.18/board/zcu102-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevA * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.18/board/zcu102-revb.dtsi b/device_tree/data/kernel_dtsi/v4.18/board/zcu102-revb.dtsi index f8883b7b..cb2d1674 100644 --- a/device_tree/data/kernel_dtsi/v4.18/board/zcu102-revb.dtsi +++ b/device_tree/data/kernel_dtsi/v4.18/board/zcu102-revb.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevB * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.18/board/zcu104-reva.dtsi b/device_tree/data/kernel_dtsi/v4.18/board/zcu104-reva.dtsi index c87376d3..247ea762 100644 --- a/device_tree/data/kernel_dtsi/v4.18/board/zcu104-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v4.18/board/zcu104-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.18/board/zcu106-reva.dtsi b/device_tree/data/kernel_dtsi/v4.18/board/zcu106-reva.dtsi index 5cdad46e..ba4ed799 100644 --- a/device_tree/data/kernel_dtsi/v4.18/board/zcu106-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v4.18/board/zcu106-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU106 * - * (C) Copyright 2016, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.18/board/zcu111-reva.dtsi b/device_tree/data/kernel_dtsi/v4.18/board/zcu111-reva.dtsi index 2db0a5ff..435bdf81 100644 --- a/device_tree/data/kernel_dtsi/v4.18/board/zcu111-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v4.18/board/zcu111-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU111 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.18/zynqmp/zynqmp-clk.dtsi b/device_tree/data/kernel_dtsi/v4.18/zynqmp/zynqmp-clk.dtsi index 9c09baca..c9c7a762 100644 --- a/device_tree/data/kernel_dtsi/v4.18/zynqmp/zynqmp-clk.dtsi +++ b/device_tree/data/kernel_dtsi/v4.18/zynqmp/zynqmp-clk.dtsi @@ -2,7 +2,8 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.18/zynqmp/zynqmp.dtsi b/device_tree/data/kernel_dtsi/v4.18/zynqmp/zynqmp.dtsi index a091e6f0..84425c0f 100644 --- a/device_tree/data/kernel_dtsi/v4.18/zynqmp/zynqmp.dtsi +++ b/device_tree/data/kernel_dtsi/v4.18/zynqmp/zynqmp.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP * - * (C) Copyright 2014 - 2015, Xilinx, Inc. + * (C) Copyright 2014-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/v4.19/board/avnet-ultra96-rev1.dtsi b/device_tree/data/kernel_dtsi/v4.19/board/avnet-ultra96-rev1.dtsi index 79e2db27..e50f6ec9 100644 --- a/device_tree/data/kernel_dtsi/v4.19/board/avnet-ultra96-rev1.dtsi +++ b/device_tree/data/kernel_dtsi/v4.19/board/avnet-ultra96-rev1.dtsi @@ -2,7 +2,8 @@ /* * dts file for Avnet Ultra96 rev1 * - * (C) Copyright 2018, Xilinx, Inc. + * (C) Copyright 2018-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.19/board/zc1232-reva.dtsi b/device_tree/data/kernel_dtsi/v4.19/board/zc1232-reva.dtsi index 26f546e0..2c07462f 100644 --- a/device_tree/data/kernel_dtsi/v4.19/board/zc1232-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v4.19/board/zc1232-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1232 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.19/board/zc1254-reva.dtsi b/device_tree/data/kernel_dtsi/v4.19/board/zc1254-reva.dtsi index 692c4257..0a493b44 100644 --- a/device_tree/data/kernel_dtsi/v4.19/board/zc1254-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v4.19/board/zc1254-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1254 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/v4.19/board/zc1275-reva.dtsi b/device_tree/data/kernel_dtsi/v4.19/board/zc1275-reva.dtsi index 5aca1e9f..beaf4cc8 100644 --- a/device_tree/data/kernel_dtsi/v4.19/board/zc1275-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v4.19/board/zc1275-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1275 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/v4.19/board/zc1751-dc1.dtsi b/device_tree/data/kernel_dtsi/v4.19/board/zc1751-dc1.dtsi index 072e3f55..ccea0cd5 100644 --- a/device_tree/data/kernel_dtsi/v4.19/board/zc1751-dc1.dtsi +++ b/device_tree/data/kernel_dtsi/v4.19/board/zc1751-dc1.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.19/board/zc1751-dc2.dtsi b/device_tree/data/kernel_dtsi/v4.19/board/zc1751-dc2.dtsi index dd2810a0..e3688d43 100644 --- a/device_tree/data/kernel_dtsi/v4.19/board/zc1751-dc2.dtsi +++ b/device_tree/data/kernel_dtsi/v4.19/board/zc1751-dc2.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.19/board/zc1751-dc3.dtsi b/device_tree/data/kernel_dtsi/v4.19/board/zc1751-dc3.dtsi index 5c807289..0646457d 100644 --- a/device_tree/data/kernel_dtsi/v4.19/board/zc1751-dc3.dtsi +++ b/device_tree/data/kernel_dtsi/v4.19/board/zc1751-dc3.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm017-dc3 * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.19/board/zc1751-dc4.dtsi b/device_tree/data/kernel_dtsi/v4.19/board/zc1751-dc4.dtsi index c8b6bdf9..84e8f502 100644 --- a/device_tree/data/kernel_dtsi/v4.19/board/zc1751-dc4.dtsi +++ b/device_tree/data/kernel_dtsi/v4.19/board/zc1751-dc4.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm018-dc4 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.19/board/zc1751-dc5.dtsi b/device_tree/data/kernel_dtsi/v4.19/board/zc1751-dc5.dtsi index afd450c3..55fb782b 100644 --- a/device_tree/data/kernel_dtsi/v4.19/board/zc1751-dc5.dtsi +++ b/device_tree/data/kernel_dtsi/v4.19/board/zc1751-dc5.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm019-dc5 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Siva Durga Prasad * Michal Simek diff --git a/device_tree/data/kernel_dtsi/v4.19/board/zcu100-revc.dtsi b/device_tree/data/kernel_dtsi/v4.19/board/zcu100-revc.dtsi index 0bb8d1cf..d791d2d5 100644 --- a/device_tree/data/kernel_dtsi/v4.19/board/zcu100-revc.dtsi +++ b/device_tree/data/kernel_dtsi/v4.19/board/zcu100-revc.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU100 revC * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy diff --git a/device_tree/data/kernel_dtsi/v4.19/board/zcu102-rev1.0.dtsi b/device_tree/data/kernel_dtsi/v4.19/board/zcu102-rev1.0.dtsi index ee6814d2..b64ef5e7 100644 --- a/device_tree/data/kernel_dtsi/v4.19/board/zcu102-rev1.0.dtsi +++ b/device_tree/data/kernel_dtsi/v4.19/board/zcu102-rev1.0.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.19/board/zcu102-reva.dtsi b/device_tree/data/kernel_dtsi/v4.19/board/zcu102-reva.dtsi index d65c2642..8530a388 100644 --- a/device_tree/data/kernel_dtsi/v4.19/board/zcu102-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v4.19/board/zcu102-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevA * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.19/board/zcu102-revb.dtsi b/device_tree/data/kernel_dtsi/v4.19/board/zcu102-revb.dtsi index f8883b7b..cb2d1674 100644 --- a/device_tree/data/kernel_dtsi/v4.19/board/zcu102-revb.dtsi +++ b/device_tree/data/kernel_dtsi/v4.19/board/zcu102-revb.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevB * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.19/board/zcu104-reva.dtsi b/device_tree/data/kernel_dtsi/v4.19/board/zcu104-reva.dtsi index c87376d3..247ea762 100644 --- a/device_tree/data/kernel_dtsi/v4.19/board/zcu104-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v4.19/board/zcu104-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.19/board/zcu106-reva.dtsi b/device_tree/data/kernel_dtsi/v4.19/board/zcu106-reva.dtsi index 5cdad46e..ba4ed799 100644 --- a/device_tree/data/kernel_dtsi/v4.19/board/zcu106-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v4.19/board/zcu106-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU106 * - * (C) Copyright 2016, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.19/board/zcu111-reva.dtsi b/device_tree/data/kernel_dtsi/v4.19/board/zcu111-reva.dtsi index 2db0a5ff..435bdf81 100644 --- a/device_tree/data/kernel_dtsi/v4.19/board/zcu111-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v4.19/board/zcu111-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU111 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.19/zynqmp/zynqmp-clk.dtsi b/device_tree/data/kernel_dtsi/v4.19/zynqmp/zynqmp-clk.dtsi index 306ad215..f3bd24bb 100644 --- a/device_tree/data/kernel_dtsi/v4.19/zynqmp/zynqmp-clk.dtsi +++ b/device_tree/data/kernel_dtsi/v4.19/zynqmp/zynqmp-clk.dtsi @@ -2,7 +2,8 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.19/zynqmp/zynqmp.dtsi b/device_tree/data/kernel_dtsi/v4.19/zynqmp/zynqmp.dtsi index a516c0e0..00086ea4 100644 --- a/device_tree/data/kernel_dtsi/v4.19/zynqmp/zynqmp.dtsi +++ b/device_tree/data/kernel_dtsi/v4.19/zynqmp/zynqmp.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP * - * (C) Copyright 2014 - 2015, Xilinx, Inc. + * (C) Copyright 2014-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/v4.20/board/avnet-ultra96-rev1.dtsi b/device_tree/data/kernel_dtsi/v4.20/board/avnet-ultra96-rev1.dtsi index 79e2db27..e50f6ec9 100644 --- a/device_tree/data/kernel_dtsi/v4.20/board/avnet-ultra96-rev1.dtsi +++ b/device_tree/data/kernel_dtsi/v4.20/board/avnet-ultra96-rev1.dtsi @@ -2,7 +2,8 @@ /* * dts file for Avnet Ultra96 rev1 * - * (C) Copyright 2018, Xilinx, Inc. + * (C) Copyright 2018-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.20/board/zc1232-reva.dtsi b/device_tree/data/kernel_dtsi/v4.20/board/zc1232-reva.dtsi index 26f546e0..2c07462f 100644 --- a/device_tree/data/kernel_dtsi/v4.20/board/zc1232-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v4.20/board/zc1232-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1232 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.20/board/zc1254-reva.dtsi b/device_tree/data/kernel_dtsi/v4.20/board/zc1254-reva.dtsi index 692c4257..0a493b44 100644 --- a/device_tree/data/kernel_dtsi/v4.20/board/zc1254-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v4.20/board/zc1254-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1254 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/v4.20/board/zc1275-reva.dtsi b/device_tree/data/kernel_dtsi/v4.20/board/zc1275-reva.dtsi index 5aca1e9f..beaf4cc8 100644 --- a/device_tree/data/kernel_dtsi/v4.20/board/zc1275-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v4.20/board/zc1275-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1275 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/v4.20/board/zc1751-dc1.dtsi b/device_tree/data/kernel_dtsi/v4.20/board/zc1751-dc1.dtsi index 072e3f55..ccea0cd5 100644 --- a/device_tree/data/kernel_dtsi/v4.20/board/zc1751-dc1.dtsi +++ b/device_tree/data/kernel_dtsi/v4.20/board/zc1751-dc1.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.20/board/zc1751-dc2.dtsi b/device_tree/data/kernel_dtsi/v4.20/board/zc1751-dc2.dtsi index dd2810a0..e3688d43 100644 --- a/device_tree/data/kernel_dtsi/v4.20/board/zc1751-dc2.dtsi +++ b/device_tree/data/kernel_dtsi/v4.20/board/zc1751-dc2.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.20/board/zc1751-dc3.dtsi b/device_tree/data/kernel_dtsi/v4.20/board/zc1751-dc3.dtsi index 5c807289..0646457d 100644 --- a/device_tree/data/kernel_dtsi/v4.20/board/zc1751-dc3.dtsi +++ b/device_tree/data/kernel_dtsi/v4.20/board/zc1751-dc3.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm017-dc3 * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.20/board/zc1751-dc4.dtsi b/device_tree/data/kernel_dtsi/v4.20/board/zc1751-dc4.dtsi index c8b6bdf9..84e8f502 100644 --- a/device_tree/data/kernel_dtsi/v4.20/board/zc1751-dc4.dtsi +++ b/device_tree/data/kernel_dtsi/v4.20/board/zc1751-dc4.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm018-dc4 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.20/board/zc1751-dc5.dtsi b/device_tree/data/kernel_dtsi/v4.20/board/zc1751-dc5.dtsi index afd450c3..55fb782b 100644 --- a/device_tree/data/kernel_dtsi/v4.20/board/zc1751-dc5.dtsi +++ b/device_tree/data/kernel_dtsi/v4.20/board/zc1751-dc5.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm019-dc5 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Siva Durga Prasad * Michal Simek diff --git a/device_tree/data/kernel_dtsi/v4.20/board/zcu100-revc.dtsi b/device_tree/data/kernel_dtsi/v4.20/board/zcu100-revc.dtsi index 0bb8d1cf..d791d2d5 100644 --- a/device_tree/data/kernel_dtsi/v4.20/board/zcu100-revc.dtsi +++ b/device_tree/data/kernel_dtsi/v4.20/board/zcu100-revc.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU100 revC * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy diff --git a/device_tree/data/kernel_dtsi/v4.20/board/zcu102-rev1.0.dtsi b/device_tree/data/kernel_dtsi/v4.20/board/zcu102-rev1.0.dtsi index ee6814d2..b64ef5e7 100644 --- a/device_tree/data/kernel_dtsi/v4.20/board/zcu102-rev1.0.dtsi +++ b/device_tree/data/kernel_dtsi/v4.20/board/zcu102-rev1.0.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.20/board/zcu102-reva.dtsi b/device_tree/data/kernel_dtsi/v4.20/board/zcu102-reva.dtsi index d65c2642..8530a388 100644 --- a/device_tree/data/kernel_dtsi/v4.20/board/zcu102-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v4.20/board/zcu102-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevA * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.20/board/zcu102-revb.dtsi b/device_tree/data/kernel_dtsi/v4.20/board/zcu102-revb.dtsi index f8883b7b..cb2d1674 100644 --- a/device_tree/data/kernel_dtsi/v4.20/board/zcu102-revb.dtsi +++ b/device_tree/data/kernel_dtsi/v4.20/board/zcu102-revb.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevB * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.20/board/zcu104-reva.dtsi b/device_tree/data/kernel_dtsi/v4.20/board/zcu104-reva.dtsi index c87376d3..247ea762 100644 --- a/device_tree/data/kernel_dtsi/v4.20/board/zcu104-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v4.20/board/zcu104-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.20/board/zcu106-reva.dtsi b/device_tree/data/kernel_dtsi/v4.20/board/zcu106-reva.dtsi index 5cdad46e..ba4ed799 100644 --- a/device_tree/data/kernel_dtsi/v4.20/board/zcu106-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v4.20/board/zcu106-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU106 * - * (C) Copyright 2016, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.20/board/zcu111-reva.dtsi b/device_tree/data/kernel_dtsi/v4.20/board/zcu111-reva.dtsi index 2db0a5ff..435bdf81 100644 --- a/device_tree/data/kernel_dtsi/v4.20/board/zcu111-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v4.20/board/zcu111-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU111 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.20/zynqmp/zynqmp-clk.dtsi b/device_tree/data/kernel_dtsi/v4.20/zynqmp/zynqmp-clk.dtsi index 9c09baca..c9c7a762 100644 --- a/device_tree/data/kernel_dtsi/v4.20/zynqmp/zynqmp-clk.dtsi +++ b/device_tree/data/kernel_dtsi/v4.20/zynqmp/zynqmp-clk.dtsi @@ -2,7 +2,8 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v4.20/zynqmp/zynqmp.dtsi b/device_tree/data/kernel_dtsi/v4.20/zynqmp/zynqmp.dtsi index 29ce2342..ad06ca5e 100644 --- a/device_tree/data/kernel_dtsi/v4.20/zynqmp/zynqmp.dtsi +++ b/device_tree/data/kernel_dtsi/v4.20/zynqmp/zynqmp.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP * - * (C) Copyright 2014 - 2015, Xilinx, Inc. + * (C) Copyright 2014-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/v5.0/board/avnet-ultra96-rev1.dtsi b/device_tree/data/kernel_dtsi/v5.0/board/avnet-ultra96-rev1.dtsi index 79e2db27..e50f6ec9 100644 --- a/device_tree/data/kernel_dtsi/v5.0/board/avnet-ultra96-rev1.dtsi +++ b/device_tree/data/kernel_dtsi/v5.0/board/avnet-ultra96-rev1.dtsi @@ -2,7 +2,8 @@ /* * dts file for Avnet Ultra96 rev1 * - * (C) Copyright 2018, Xilinx, Inc. + * (C) Copyright 2018-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.0/board/zc1232-reva.dtsi b/device_tree/data/kernel_dtsi/v5.0/board/zc1232-reva.dtsi index 26f546e0..2c07462f 100644 --- a/device_tree/data/kernel_dtsi/v5.0/board/zc1232-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v5.0/board/zc1232-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1232 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.0/board/zc1254-reva.dtsi b/device_tree/data/kernel_dtsi/v5.0/board/zc1254-reva.dtsi index 45b5b7d9..739a7637 100644 --- a/device_tree/data/kernel_dtsi/v5.0/board/zc1254-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v5.0/board/zc1254-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1254 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/v5.0/board/zc1275-reva.dtsi b/device_tree/data/kernel_dtsi/v5.0/board/zc1275-reva.dtsi index 382e99bb..fdf11993 100644 --- a/device_tree/data/kernel_dtsi/v5.0/board/zc1275-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v5.0/board/zc1275-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1275 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/v5.0/board/zc1751-dc1.dtsi b/device_tree/data/kernel_dtsi/v5.0/board/zc1751-dc1.dtsi index 9133ca6b..33c3efe4 100644 --- a/device_tree/data/kernel_dtsi/v5.0/board/zc1751-dc1.dtsi +++ b/device_tree/data/kernel_dtsi/v5.0/board/zc1751-dc1.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.0/board/zc1751-dc2.dtsi b/device_tree/data/kernel_dtsi/v5.0/board/zc1751-dc2.dtsi index 9c2aab85..dbaba2e2 100644 --- a/device_tree/data/kernel_dtsi/v5.0/board/zc1751-dc2.dtsi +++ b/device_tree/data/kernel_dtsi/v5.0/board/zc1751-dc2.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.0/board/zc1751-dc3.dtsi b/device_tree/data/kernel_dtsi/v5.0/board/zc1751-dc3.dtsi index 5c807289..0646457d 100644 --- a/device_tree/data/kernel_dtsi/v5.0/board/zc1751-dc3.dtsi +++ b/device_tree/data/kernel_dtsi/v5.0/board/zc1751-dc3.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm017-dc3 * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.0/board/zc1751-dc4.dtsi b/device_tree/data/kernel_dtsi/v5.0/board/zc1751-dc4.dtsi index cee76d7b..acd864c6 100644 --- a/device_tree/data/kernel_dtsi/v5.0/board/zc1751-dc4.dtsi +++ b/device_tree/data/kernel_dtsi/v5.0/board/zc1751-dc4.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm018-dc4 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.0/board/zc1751-dc5.dtsi b/device_tree/data/kernel_dtsi/v5.0/board/zc1751-dc5.dtsi index a4731142..ab02dfda 100644 --- a/device_tree/data/kernel_dtsi/v5.0/board/zc1751-dc5.dtsi +++ b/device_tree/data/kernel_dtsi/v5.0/board/zc1751-dc5.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm019-dc5 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Siva Durga Prasad * Michal Simek diff --git a/device_tree/data/kernel_dtsi/v5.0/board/zcu100-revc.dtsi b/device_tree/data/kernel_dtsi/v5.0/board/zcu100-revc.dtsi index 24e8a96d..c47ba043 100644 --- a/device_tree/data/kernel_dtsi/v5.0/board/zcu100-revc.dtsi +++ b/device_tree/data/kernel_dtsi/v5.0/board/zcu100-revc.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU100 revC * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy diff --git a/device_tree/data/kernel_dtsi/v5.0/board/zcu102-rev1.0.dtsi b/device_tree/data/kernel_dtsi/v5.0/board/zcu102-rev1.0.dtsi index ee6814d2..b64ef5e7 100644 --- a/device_tree/data/kernel_dtsi/v5.0/board/zcu102-rev1.0.dtsi +++ b/device_tree/data/kernel_dtsi/v5.0/board/zcu102-rev1.0.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.0/board/zcu102-reva.dtsi b/device_tree/data/kernel_dtsi/v5.0/board/zcu102-reva.dtsi index 68012bbf..73502f7b 100644 --- a/device_tree/data/kernel_dtsi/v5.0/board/zcu102-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v5.0/board/zcu102-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevA * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.0/board/zcu102-revb.dtsi b/device_tree/data/kernel_dtsi/v5.0/board/zcu102-revb.dtsi index f8883b7b..cb2d1674 100644 --- a/device_tree/data/kernel_dtsi/v5.0/board/zcu102-revb.dtsi +++ b/device_tree/data/kernel_dtsi/v5.0/board/zcu102-revb.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevB * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.0/board/zcu104-reva.dtsi b/device_tree/data/kernel_dtsi/v5.0/board/zcu104-reva.dtsi index b3025f66..6b702459 100644 --- a/device_tree/data/kernel_dtsi/v5.0/board/zcu104-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v5.0/board/zcu104-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.0/board/zcu106-reva.dtsi b/device_tree/data/kernel_dtsi/v5.0/board/zcu106-reva.dtsi index c15452ce..515264ce 100644 --- a/device_tree/data/kernel_dtsi/v5.0/board/zcu106-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v5.0/board/zcu106-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU106 * - * (C) Copyright 2016, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.0/board/zcu111-reva.dtsi b/device_tree/data/kernel_dtsi/v5.0/board/zcu111-reva.dtsi index 58b2063c..810e44b3 100644 --- a/device_tree/data/kernel_dtsi/v5.0/board/zcu111-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v5.0/board/zcu111-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU111 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.0/zynqmp/zynqmp-clk.dtsi b/device_tree/data/kernel_dtsi/v5.0/zynqmp/zynqmp-clk.dtsi index 306ad215..f3bd24bb 100644 --- a/device_tree/data/kernel_dtsi/v5.0/zynqmp/zynqmp-clk.dtsi +++ b/device_tree/data/kernel_dtsi/v5.0/zynqmp/zynqmp-clk.dtsi @@ -2,7 +2,8 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.0/zynqmp/zynqmp.dtsi b/device_tree/data/kernel_dtsi/v5.0/zynqmp/zynqmp.dtsi index fa4fd777..6595c66b 100644 --- a/device_tree/data/kernel_dtsi/v5.0/zynqmp/zynqmp.dtsi +++ b/device_tree/data/kernel_dtsi/v5.0/zynqmp/zynqmp.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP * - * (C) Copyright 2014 - 2015, Xilinx, Inc. + * (C) Copyright 2014-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/v5.1/board/avnet-ultra96-rev1.dtsi b/device_tree/data/kernel_dtsi/v5.1/board/avnet-ultra96-rev1.dtsi index 79e2db27..e50f6ec9 100644 --- a/device_tree/data/kernel_dtsi/v5.1/board/avnet-ultra96-rev1.dtsi +++ b/device_tree/data/kernel_dtsi/v5.1/board/avnet-ultra96-rev1.dtsi @@ -2,7 +2,8 @@ /* * dts file for Avnet Ultra96 rev1 * - * (C) Copyright 2018, Xilinx, Inc. + * (C) Copyright 2018-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.1/board/zc1232-reva.dtsi b/device_tree/data/kernel_dtsi/v5.1/board/zc1232-reva.dtsi index 26f546e0..2c07462f 100644 --- a/device_tree/data/kernel_dtsi/v5.1/board/zc1232-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v5.1/board/zc1232-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1232 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.1/board/zc1254-reva.dtsi b/device_tree/data/kernel_dtsi/v5.1/board/zc1254-reva.dtsi index 692c4257..0a493b44 100644 --- a/device_tree/data/kernel_dtsi/v5.1/board/zc1254-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v5.1/board/zc1254-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1254 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/v5.1/board/zc1275-reva.dtsi b/device_tree/data/kernel_dtsi/v5.1/board/zc1275-reva.dtsi index 2395442d..360a7bc5 100644 --- a/device_tree/data/kernel_dtsi/v5.1/board/zc1275-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v5.1/board/zc1275-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1275 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/v5.1/board/zc1751-dc1.dtsi b/device_tree/data/kernel_dtsi/v5.1/board/zc1751-dc1.dtsi index 9133ca6b..33c3efe4 100644 --- a/device_tree/data/kernel_dtsi/v5.1/board/zc1751-dc1.dtsi +++ b/device_tree/data/kernel_dtsi/v5.1/board/zc1751-dc1.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.1/board/zc1751-dc2.dtsi b/device_tree/data/kernel_dtsi/v5.1/board/zc1751-dc2.dtsi index 9c2aab85..dbaba2e2 100644 --- a/device_tree/data/kernel_dtsi/v5.1/board/zc1751-dc2.dtsi +++ b/device_tree/data/kernel_dtsi/v5.1/board/zc1751-dc2.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.1/board/zc1751-dc3.dtsi b/device_tree/data/kernel_dtsi/v5.1/board/zc1751-dc3.dtsi index 5c807289..0646457d 100644 --- a/device_tree/data/kernel_dtsi/v5.1/board/zc1751-dc3.dtsi +++ b/device_tree/data/kernel_dtsi/v5.1/board/zc1751-dc3.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm017-dc3 * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.1/board/zc1751-dc4.dtsi b/device_tree/data/kernel_dtsi/v5.1/board/zc1751-dc4.dtsi index 221ec1ef..54774d94 100644 --- a/device_tree/data/kernel_dtsi/v5.1/board/zc1751-dc4.dtsi +++ b/device_tree/data/kernel_dtsi/v5.1/board/zc1751-dc4.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm018-dc4 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.1/board/zc1751-dc5.dtsi b/device_tree/data/kernel_dtsi/v5.1/board/zc1751-dc5.dtsi index 125c96a5..5d83a24d 100644 --- a/device_tree/data/kernel_dtsi/v5.1/board/zc1751-dc5.dtsi +++ b/device_tree/data/kernel_dtsi/v5.1/board/zc1751-dc5.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm019-dc5 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Siva Durga Prasad * Michal Simek diff --git a/device_tree/data/kernel_dtsi/v5.1/board/zcu100-revc.dtsi b/device_tree/data/kernel_dtsi/v5.1/board/zcu100-revc.dtsi index a6827dc1..94be7d2a 100644 --- a/device_tree/data/kernel_dtsi/v5.1/board/zcu100-revc.dtsi +++ b/device_tree/data/kernel_dtsi/v5.1/board/zcu100-revc.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU100 revC * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy diff --git a/device_tree/data/kernel_dtsi/v5.1/board/zcu102-rev1.0.dtsi b/device_tree/data/kernel_dtsi/v5.1/board/zcu102-rev1.0.dtsi index ee6814d2..b64ef5e7 100644 --- a/device_tree/data/kernel_dtsi/v5.1/board/zcu102-rev1.0.dtsi +++ b/device_tree/data/kernel_dtsi/v5.1/board/zcu102-rev1.0.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.1/board/zcu102-reva.dtsi b/device_tree/data/kernel_dtsi/v5.1/board/zcu102-reva.dtsi index d65c2642..8530a388 100644 --- a/device_tree/data/kernel_dtsi/v5.1/board/zcu102-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v5.1/board/zcu102-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevA * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.1/board/zcu102-revb.dtsi b/device_tree/data/kernel_dtsi/v5.1/board/zcu102-revb.dtsi index f8883b7b..cb2d1674 100644 --- a/device_tree/data/kernel_dtsi/v5.1/board/zcu102-revb.dtsi +++ b/device_tree/data/kernel_dtsi/v5.1/board/zcu102-revb.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevB * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.1/board/zcu104-reva.dtsi b/device_tree/data/kernel_dtsi/v5.1/board/zcu104-reva.dtsi index ba74005f..ca6f4069 100644 --- a/device_tree/data/kernel_dtsi/v5.1/board/zcu104-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v5.1/board/zcu104-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.1/board/zcu106-reva.dtsi b/device_tree/data/kernel_dtsi/v5.1/board/zcu106-reva.dtsi index 5ddc224b..573084c9 100644 --- a/device_tree/data/kernel_dtsi/v5.1/board/zcu106-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v5.1/board/zcu106-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU106 * - * (C) Copyright 2016, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.1/board/zcu111-reva.dtsi b/device_tree/data/kernel_dtsi/v5.1/board/zcu111-reva.dtsi index 3cb93d5a..afbe56c6 100644 --- a/device_tree/data/kernel_dtsi/v5.1/board/zcu111-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v5.1/board/zcu111-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU111 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.1/zynqmp/zynqmp-clk.dtsi b/device_tree/data/kernel_dtsi/v5.1/zynqmp/zynqmp-clk.dtsi index 306ad215..f3bd24bb 100644 --- a/device_tree/data/kernel_dtsi/v5.1/zynqmp/zynqmp-clk.dtsi +++ b/device_tree/data/kernel_dtsi/v5.1/zynqmp/zynqmp-clk.dtsi @@ -2,7 +2,8 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.1/zynqmp/zynqmp.dtsi b/device_tree/data/kernel_dtsi/v5.1/zynqmp/zynqmp.dtsi index 9aa67340..740c8e80 100644 --- a/device_tree/data/kernel_dtsi/v5.1/zynqmp/zynqmp.dtsi +++ b/device_tree/data/kernel_dtsi/v5.1/zynqmp/zynqmp.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP * - * (C) Copyright 2014 - 2015, Xilinx, Inc. + * (C) Copyright 2014-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/v5.2/board/avnet-ultra96-rev1.dtsi b/device_tree/data/kernel_dtsi/v5.2/board/avnet-ultra96-rev1.dtsi index 79e2db27..e50f6ec9 100644 --- a/device_tree/data/kernel_dtsi/v5.2/board/avnet-ultra96-rev1.dtsi +++ b/device_tree/data/kernel_dtsi/v5.2/board/avnet-ultra96-rev1.dtsi @@ -2,7 +2,8 @@ /* * dts file for Avnet Ultra96 rev1 * - * (C) Copyright 2018, Xilinx, Inc. + * (C) Copyright 2018-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.2/board/zc1232-reva.dtsi b/device_tree/data/kernel_dtsi/v5.2/board/zc1232-reva.dtsi index 0aa682db..84711542 100644 --- a/device_tree/data/kernel_dtsi/v5.2/board/zc1232-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v5.2/board/zc1232-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1232 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.2/board/zc1254-reva.dtsi b/device_tree/data/kernel_dtsi/v5.2/board/zc1254-reva.dtsi index 692c4257..0a493b44 100644 --- a/device_tree/data/kernel_dtsi/v5.2/board/zc1254-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v5.2/board/zc1254-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1254 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/v5.2/board/zc1275-reva.dtsi b/device_tree/data/kernel_dtsi/v5.2/board/zc1275-reva.dtsi index 5aca1e9f..beaf4cc8 100644 --- a/device_tree/data/kernel_dtsi/v5.2/board/zc1275-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v5.2/board/zc1275-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1275 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/v5.2/board/zc1751-dc1.dtsi b/device_tree/data/kernel_dtsi/v5.2/board/zc1751-dc1.dtsi index cab1d6f7..330b0ab0 100644 --- a/device_tree/data/kernel_dtsi/v5.2/board/zc1751-dc1.dtsi +++ b/device_tree/data/kernel_dtsi/v5.2/board/zc1751-dc1.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.2/board/zc1751-dc2.dtsi b/device_tree/data/kernel_dtsi/v5.2/board/zc1751-dc2.dtsi index 875f32d3..ddfa9825 100644 --- a/device_tree/data/kernel_dtsi/v5.2/board/zc1751-dc2.dtsi +++ b/device_tree/data/kernel_dtsi/v5.2/board/zc1751-dc2.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.2/board/zc1751-dc3.dtsi b/device_tree/data/kernel_dtsi/v5.2/board/zc1751-dc3.dtsi index 5c807289..0646457d 100644 --- a/device_tree/data/kernel_dtsi/v5.2/board/zc1751-dc3.dtsi +++ b/device_tree/data/kernel_dtsi/v5.2/board/zc1751-dc3.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm017-dc3 * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.2/board/zc1751-dc4.dtsi b/device_tree/data/kernel_dtsi/v5.2/board/zc1751-dc4.dtsi index c8b6bdf9..84e8f502 100644 --- a/device_tree/data/kernel_dtsi/v5.2/board/zc1751-dc4.dtsi +++ b/device_tree/data/kernel_dtsi/v5.2/board/zc1751-dc4.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm018-dc4 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.2/board/zc1751-dc5.dtsi b/device_tree/data/kernel_dtsi/v5.2/board/zc1751-dc5.dtsi index afd450c3..55fb782b 100644 --- a/device_tree/data/kernel_dtsi/v5.2/board/zc1751-dc5.dtsi +++ b/device_tree/data/kernel_dtsi/v5.2/board/zc1751-dc5.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm019-dc5 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Siva Durga Prasad * Michal Simek diff --git a/device_tree/data/kernel_dtsi/v5.2/board/zcu100-revc.dtsi b/device_tree/data/kernel_dtsi/v5.2/board/zcu100-revc.dtsi index abfc3ed8..a7e5987f 100644 --- a/device_tree/data/kernel_dtsi/v5.2/board/zcu100-revc.dtsi +++ b/device_tree/data/kernel_dtsi/v5.2/board/zcu100-revc.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU100 revC * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy diff --git a/device_tree/data/kernel_dtsi/v5.2/board/zcu102-rev1.0.dtsi b/device_tree/data/kernel_dtsi/v5.2/board/zcu102-rev1.0.dtsi index ee6814d2..b64ef5e7 100644 --- a/device_tree/data/kernel_dtsi/v5.2/board/zcu102-rev1.0.dtsi +++ b/device_tree/data/kernel_dtsi/v5.2/board/zcu102-rev1.0.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.2/board/zcu102-reva.dtsi b/device_tree/data/kernel_dtsi/v5.2/board/zcu102-reva.dtsi index 68012bbf..73502f7b 100644 --- a/device_tree/data/kernel_dtsi/v5.2/board/zcu102-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v5.2/board/zcu102-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevA * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.2/board/zcu102-revb.dtsi b/device_tree/data/kernel_dtsi/v5.2/board/zcu102-revb.dtsi index f8883b7b..cb2d1674 100644 --- a/device_tree/data/kernel_dtsi/v5.2/board/zcu102-revb.dtsi +++ b/device_tree/data/kernel_dtsi/v5.2/board/zcu102-revb.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevB * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.2/board/zcu104-reva.dtsi b/device_tree/data/kernel_dtsi/v5.2/board/zcu104-reva.dtsi index 2fc9bee1..129329a0 100644 --- a/device_tree/data/kernel_dtsi/v5.2/board/zcu104-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v5.2/board/zcu104-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.2/board/zcu106-reva.dtsi b/device_tree/data/kernel_dtsi/v5.2/board/zcu106-reva.dtsi index 2a5774ce..b1bbca75 100644 --- a/device_tree/data/kernel_dtsi/v5.2/board/zcu106-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v5.2/board/zcu106-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU106 * - * (C) Copyright 2016, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.2/board/zcu111-reva.dtsi b/device_tree/data/kernel_dtsi/v5.2/board/zcu111-reva.dtsi index eb6fe203..25bbea49 100644 --- a/device_tree/data/kernel_dtsi/v5.2/board/zcu111-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v5.2/board/zcu111-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU111 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.2/zynqmp/zynqmp-clk.dtsi b/device_tree/data/kernel_dtsi/v5.2/zynqmp/zynqmp-clk.dtsi index 306ad215..f3bd24bb 100644 --- a/device_tree/data/kernel_dtsi/v5.2/zynqmp/zynqmp-clk.dtsi +++ b/device_tree/data/kernel_dtsi/v5.2/zynqmp/zynqmp-clk.dtsi @@ -2,7 +2,8 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.2/zynqmp/zynqmp.dtsi b/device_tree/data/kernel_dtsi/v5.2/zynqmp/zynqmp.dtsi index 9aa67340..740c8e80 100644 --- a/device_tree/data/kernel_dtsi/v5.2/zynqmp/zynqmp.dtsi +++ b/device_tree/data/kernel_dtsi/v5.2/zynqmp/zynqmp.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP * - * (C) Copyright 2014 - 2015, Xilinx, Inc. + * (C) Copyright 2014-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/v5.3/board/avnet-ultra96-rev1.dtsi b/device_tree/data/kernel_dtsi/v5.3/board/avnet-ultra96-rev1.dtsi index 79e2db27..e50f6ec9 100644 --- a/device_tree/data/kernel_dtsi/v5.3/board/avnet-ultra96-rev1.dtsi +++ b/device_tree/data/kernel_dtsi/v5.3/board/avnet-ultra96-rev1.dtsi @@ -2,7 +2,8 @@ /* * dts file for Avnet Ultra96 rev1 * - * (C) Copyright 2018, Xilinx, Inc. + * (C) Copyright 2018-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.3/board/zc1232-reva.dtsi b/device_tree/data/kernel_dtsi/v5.3/board/zc1232-reva.dtsi index 26f546e0..2c07462f 100644 --- a/device_tree/data/kernel_dtsi/v5.3/board/zc1232-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v5.3/board/zc1232-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1232 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.3/board/zc1254-reva.dtsi b/device_tree/data/kernel_dtsi/v5.3/board/zc1254-reva.dtsi index 45b5b7d9..739a7637 100644 --- a/device_tree/data/kernel_dtsi/v5.3/board/zc1254-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v5.3/board/zc1254-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1254 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/v5.3/board/zc1275-reva.dtsi b/device_tree/data/kernel_dtsi/v5.3/board/zc1275-reva.dtsi index 382e99bb..fdf11993 100644 --- a/device_tree/data/kernel_dtsi/v5.3/board/zc1275-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v5.3/board/zc1275-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1275 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/v5.3/board/zc1751-dc1.dtsi b/device_tree/data/kernel_dtsi/v5.3/board/zc1751-dc1.dtsi index 9133ca6b..33c3efe4 100644 --- a/device_tree/data/kernel_dtsi/v5.3/board/zc1751-dc1.dtsi +++ b/device_tree/data/kernel_dtsi/v5.3/board/zc1751-dc1.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.3/board/zc1751-dc2.dtsi b/device_tree/data/kernel_dtsi/v5.3/board/zc1751-dc2.dtsi index 9c2aab85..dbaba2e2 100644 --- a/device_tree/data/kernel_dtsi/v5.3/board/zc1751-dc2.dtsi +++ b/device_tree/data/kernel_dtsi/v5.3/board/zc1751-dc2.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.3/board/zc1751-dc3.dtsi b/device_tree/data/kernel_dtsi/v5.3/board/zc1751-dc3.dtsi index 5c807289..0646457d 100644 --- a/device_tree/data/kernel_dtsi/v5.3/board/zc1751-dc3.dtsi +++ b/device_tree/data/kernel_dtsi/v5.3/board/zc1751-dc3.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm017-dc3 * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.3/board/zc1751-dc4.dtsi b/device_tree/data/kernel_dtsi/v5.3/board/zc1751-dc4.dtsi index cee76d7b..acd864c6 100644 --- a/device_tree/data/kernel_dtsi/v5.3/board/zc1751-dc4.dtsi +++ b/device_tree/data/kernel_dtsi/v5.3/board/zc1751-dc4.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm018-dc4 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.3/board/zc1751-dc5.dtsi b/device_tree/data/kernel_dtsi/v5.3/board/zc1751-dc5.dtsi index a4731142..ab02dfda 100644 --- a/device_tree/data/kernel_dtsi/v5.3/board/zc1751-dc5.dtsi +++ b/device_tree/data/kernel_dtsi/v5.3/board/zc1751-dc5.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm019-dc5 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Siva Durga Prasad * Michal Simek diff --git a/device_tree/data/kernel_dtsi/v5.3/board/zcu100-revc.dtsi b/device_tree/data/kernel_dtsi/v5.3/board/zcu100-revc.dtsi index 24e8a96d..c47ba043 100644 --- a/device_tree/data/kernel_dtsi/v5.3/board/zcu100-revc.dtsi +++ b/device_tree/data/kernel_dtsi/v5.3/board/zcu100-revc.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU100 revC * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy diff --git a/device_tree/data/kernel_dtsi/v5.3/board/zcu102-rev1.0.dtsi b/device_tree/data/kernel_dtsi/v5.3/board/zcu102-rev1.0.dtsi index ee6814d2..b64ef5e7 100644 --- a/device_tree/data/kernel_dtsi/v5.3/board/zcu102-rev1.0.dtsi +++ b/device_tree/data/kernel_dtsi/v5.3/board/zcu102-rev1.0.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.3/board/zcu102-reva.dtsi b/device_tree/data/kernel_dtsi/v5.3/board/zcu102-reva.dtsi index 68012bbf..73502f7b 100644 --- a/device_tree/data/kernel_dtsi/v5.3/board/zcu102-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v5.3/board/zcu102-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevA * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.3/board/zcu102-revb.dtsi b/device_tree/data/kernel_dtsi/v5.3/board/zcu102-revb.dtsi index f8883b7b..cb2d1674 100644 --- a/device_tree/data/kernel_dtsi/v5.3/board/zcu102-revb.dtsi +++ b/device_tree/data/kernel_dtsi/v5.3/board/zcu102-revb.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevB * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.3/board/zcu104-reva.dtsi b/device_tree/data/kernel_dtsi/v5.3/board/zcu104-reva.dtsi index b3025f66..6b702459 100644 --- a/device_tree/data/kernel_dtsi/v5.3/board/zcu104-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v5.3/board/zcu104-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.3/board/zcu106-reva.dtsi b/device_tree/data/kernel_dtsi/v5.3/board/zcu106-reva.dtsi index c15452ce..515264ce 100644 --- a/device_tree/data/kernel_dtsi/v5.3/board/zcu106-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v5.3/board/zcu106-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU106 * - * (C) Copyright 2016, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.3/board/zcu111-reva.dtsi b/device_tree/data/kernel_dtsi/v5.3/board/zcu111-reva.dtsi index 58b2063c..810e44b3 100644 --- a/device_tree/data/kernel_dtsi/v5.3/board/zcu111-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v5.3/board/zcu111-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU111 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.3/zynqmp/zynqmp-clk.dtsi b/device_tree/data/kernel_dtsi/v5.3/zynqmp/zynqmp-clk.dtsi index 306ad215..f3bd24bb 100644 --- a/device_tree/data/kernel_dtsi/v5.3/zynqmp/zynqmp-clk.dtsi +++ b/device_tree/data/kernel_dtsi/v5.3/zynqmp/zynqmp-clk.dtsi @@ -2,7 +2,8 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.3/zynqmp/zynqmp.dtsi b/device_tree/data/kernel_dtsi/v5.3/zynqmp/zynqmp.dtsi index 9aa67340..740c8e80 100644 --- a/device_tree/data/kernel_dtsi/v5.3/zynqmp/zynqmp.dtsi +++ b/device_tree/data/kernel_dtsi/v5.3/zynqmp/zynqmp.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP * - * (C) Copyright 2014 - 2015, Xilinx, Inc. + * (C) Copyright 2014-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/device_tree/data/kernel_dtsi/v5.4/board/avnet-ultra96-rev1.dtsi b/device_tree/data/kernel_dtsi/v5.4/board/avnet-ultra96-rev1.dtsi index 79e2db27..e50f6ec9 100644 --- a/device_tree/data/kernel_dtsi/v5.4/board/avnet-ultra96-rev1.dtsi +++ b/device_tree/data/kernel_dtsi/v5.4/board/avnet-ultra96-rev1.dtsi @@ -2,7 +2,8 @@ /* * dts file for Avnet Ultra96 rev1 * - * (C) Copyright 2018, Xilinx, Inc. + * (C) Copyright 2018-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.4/board/zc1232-reva.dtsi b/device_tree/data/kernel_dtsi/v5.4/board/zc1232-reva.dtsi index 0aa682db..84711542 100644 --- a/device_tree/data/kernel_dtsi/v5.4/board/zc1232-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v5.4/board/zc1232-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1232 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.4/board/zc1254-reva.dtsi b/device_tree/data/kernel_dtsi/v5.4/board/zc1254-reva.dtsi index 692c4257..0a493b44 100644 --- a/device_tree/data/kernel_dtsi/v5.4/board/zc1254-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v5.4/board/zc1254-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1254 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/v5.4/board/zc1275-reva.dtsi b/device_tree/data/kernel_dtsi/v5.4/board/zc1275-reva.dtsi index 5aca1e9f..beaf4cc8 100644 --- a/device_tree/data/kernel_dtsi/v5.4/board/zc1275-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v5.4/board/zc1275-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZC1275 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu diff --git a/device_tree/data/kernel_dtsi/v5.4/board/zc1751-dc1.dtsi b/device_tree/data/kernel_dtsi/v5.4/board/zc1751-dc1.dtsi index cab1d6f7..330b0ab0 100644 --- a/device_tree/data/kernel_dtsi/v5.4/board/zc1751-dc1.dtsi +++ b/device_tree/data/kernel_dtsi/v5.4/board/zc1751-dc1.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.4/board/zc1751-dc2.dtsi b/device_tree/data/kernel_dtsi/v5.4/board/zc1751-dc2.dtsi index 875f32d3..ddfa9825 100644 --- a/device_tree/data/kernel_dtsi/v5.4/board/zc1751-dc2.dtsi +++ b/device_tree/data/kernel_dtsi/v5.4/board/zc1751-dc2.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.4/board/zc1751-dc3.dtsi b/device_tree/data/kernel_dtsi/v5.4/board/zc1751-dc3.dtsi index 5c807289..0646457d 100644 --- a/device_tree/data/kernel_dtsi/v5.4/board/zc1751-dc3.dtsi +++ b/device_tree/data/kernel_dtsi/v5.4/board/zc1751-dc3.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm017-dc3 * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.4/board/zc1751-dc4.dtsi b/device_tree/data/kernel_dtsi/v5.4/board/zc1751-dc4.dtsi index c8b6bdf9..84e8f502 100644 --- a/device_tree/data/kernel_dtsi/v5.4/board/zc1751-dc4.dtsi +++ b/device_tree/data/kernel_dtsi/v5.4/board/zc1751-dc4.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm018-dc4 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.4/board/zc1751-dc5.dtsi b/device_tree/data/kernel_dtsi/v5.4/board/zc1751-dc5.dtsi index afd450c3..55fb782b 100644 --- a/device_tree/data/kernel_dtsi/v5.4/board/zc1751-dc5.dtsi +++ b/device_tree/data/kernel_dtsi/v5.4/board/zc1751-dc5.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm019-dc5 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Siva Durga Prasad * Michal Simek diff --git a/device_tree/data/kernel_dtsi/v5.4/board/zcu100-revc.dtsi b/device_tree/data/kernel_dtsi/v5.4/board/zcu100-revc.dtsi index abfc3ed8..a7e5987f 100644 --- a/device_tree/data/kernel_dtsi/v5.4/board/zcu100-revc.dtsi +++ b/device_tree/data/kernel_dtsi/v5.4/board/zcu100-revc.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU100 revC * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy diff --git a/device_tree/data/kernel_dtsi/v5.4/board/zcu102-rev1.0.dtsi b/device_tree/data/kernel_dtsi/v5.4/board/zcu102-rev1.0.dtsi index ee6814d2..b64ef5e7 100644 --- a/device_tree/data/kernel_dtsi/v5.4/board/zcu102-rev1.0.dtsi +++ b/device_tree/data/kernel_dtsi/v5.4/board/zcu102-rev1.0.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.4/board/zcu102-reva.dtsi b/device_tree/data/kernel_dtsi/v5.4/board/zcu102-reva.dtsi index 68012bbf..73502f7b 100644 --- a/device_tree/data/kernel_dtsi/v5.4/board/zcu102-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v5.4/board/zcu102-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevA * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.4/board/zcu102-revb.dtsi b/device_tree/data/kernel_dtsi/v5.4/board/zcu102-revb.dtsi index f8883b7b..cb2d1674 100644 --- a/device_tree/data/kernel_dtsi/v5.4/board/zcu102-revb.dtsi +++ b/device_tree/data/kernel_dtsi/v5.4/board/zcu102-revb.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevB * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.4/board/zcu104-reva.dtsi b/device_tree/data/kernel_dtsi/v5.4/board/zcu104-reva.dtsi index 2fc9bee1..129329a0 100644 --- a/device_tree/data/kernel_dtsi/v5.4/board/zcu104-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v5.4/board/zcu104-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.4/board/zcu106-reva.dtsi b/device_tree/data/kernel_dtsi/v5.4/board/zcu106-reva.dtsi index 2a5774ce..b1bbca75 100644 --- a/device_tree/data/kernel_dtsi/v5.4/board/zcu106-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v5.4/board/zcu106-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU106 * - * (C) Copyright 2016, Xilinx, Inc. + * (C) Copyright 2016-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.4/board/zcu111-reva.dtsi b/device_tree/data/kernel_dtsi/v5.4/board/zcu111-reva.dtsi index eb6fe203..25bbea49 100644 --- a/device_tree/data/kernel_dtsi/v5.4/board/zcu111-reva.dtsi +++ b/device_tree/data/kernel_dtsi/v5.4/board/zcu111-reva.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU111 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.4/zynqmp/zynqmp-clk.dtsi b/device_tree/data/kernel_dtsi/v5.4/zynqmp/zynqmp-clk.dtsi index 306ad215..f3bd24bb 100644 --- a/device_tree/data/kernel_dtsi/v5.4/zynqmp/zynqmp-clk.dtsi +++ b/device_tree/data/kernel_dtsi/v5.4/zynqmp/zynqmp-clk.dtsi @@ -2,7 +2,8 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ diff --git a/device_tree/data/kernel_dtsi/v5.4/zynqmp/zynqmp.dtsi b/device_tree/data/kernel_dtsi/v5.4/zynqmp/zynqmp.dtsi index 9aa67340..740c8e80 100644 --- a/device_tree/data/kernel_dtsi/v5.4/zynqmp/zynqmp.dtsi +++ b/device_tree/data/kernel_dtsi/v5.4/zynqmp/zynqmp.dtsi @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP * - * (C) Copyright 2014 - 2015, Xilinx, Inc. + * (C) Copyright 2014-2022 Xilinx, Inc. + * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * diff --git a/dmaps/data/dmaps.mdd b/dmaps/data/dmaps.mdd index 2831e9b7..6ce961fa 100644 --- a/dmaps/data/dmaps.mdd +++ b/dmaps/data/dmaps.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/dmaps/data/dmaps.tcl b/dmaps/data/dmaps.tcl index 0b878516..688ecba9 100644 --- a/dmaps/data/dmaps.tcl +++ b/dmaps/data/dmaps.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/dp/data/dp.mdd b/dp/data/dp.mdd index 5bda7cf1..e5188292 100644 --- a/dp/data/dp.mdd +++ b/dp/data/dp.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/dp/data/dp.tcl b/dp/data/dp.tcl index 112847fb..81441d94 100644 --- a/dp/data/dp.tcl +++ b/dp/data/dp.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/dp_rx/data/dp_rx.mdd b/dp_rx/data/dp_rx.mdd index 7a28d07c..18e9fb9a 100644 --- a/dp_rx/data/dp_rx.mdd +++ b/dp_rx/data/dp_rx.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2020-2021 Xilinx, Inc. +# (C) Copyright 2020-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/dp_rx/data/dp_rx.tcl b/dp_rx/data/dp_rx.tcl index 4dceaff6..80f254e2 100644 --- a/dp_rx/data/dp_rx.tcl +++ b/dp_rx/data/dp_rx.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2020-2021 Xilinx, Inc. +# (C) Copyright 2020-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/dp_tx/data/dp_tx.mdd b/dp_tx/data/dp_tx.mdd index ca345ffb..29c06e88 100644 --- a/dp_tx/data/dp_tx.mdd +++ b/dp_tx/data/dp_tx.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2020-2021 Xilinx, Inc. +# (C) Copyright 2020-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/dp_tx/data/dp_tx.tcl b/dp_tx/data/dp_tx.tcl index 0a84f0b9..3ddda882 100644 --- a/dp_tx/data/dp_tx.tcl +++ b/dp_tx/data/dp_tx.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2020-2021 Xilinx, Inc. +# (C) Copyright 2020-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/dpu_eu/data/dpu_eu.mdd b/dpu_eu/data/dpu_eu.mdd index 264a8924..ae4a27bd 100644 --- a/dpu_eu/data/dpu_eu.mdd +++ b/dpu_eu/data/dpu_eu.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2019 Xilinx, Inc. +# (C) Copyright 2019-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/dpu_eu/data/dpu_eu.tcl b/dpu_eu/data/dpu_eu.tcl index d2905990..8af50b7e 100644 --- a/dpu_eu/data/dpu_eu.tcl +++ b/dpu_eu/data/dpu_eu.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2019 Xilinx, Inc. +# (C) Copyright 2019-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/emaclite/data/emaclite.mdd b/emaclite/data/emaclite.mdd index 0ec81c5a..a31945f9 100644 --- a/emaclite/data/emaclite.mdd +++ b/emaclite/data/emaclite.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/emaclite/data/emaclite.tcl b/emaclite/data/emaclite.tcl index 5538e734..d60cb8bd 100644 --- a/emaclite/data/emaclite.tcl +++ b/emaclite/data/emaclite.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/emacps/data/emacps.mdd b/emacps/data/emacps.mdd index ddeefd63..479a2208 100644 --- a/emacps/data/emacps.mdd +++ b/emacps/data/emacps.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/emacps/data/emacps.tcl b/emacps/data/emacps.tcl index 7475ac35..00ac495b 100644 --- a/emacps/data/emacps.tcl +++ b/emacps/data/emacps.tcl @@ -1,8 +1,9 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd # Based on original code: # (C) Copyright 2007-2014 Michal Simek -# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # Michal SIMEK # diff --git a/ernic/data/ernic.mdd b/ernic/data/ernic.mdd index 3bafb3a0..79d97a7b 100644 --- a/ernic/data/ernic.mdd +++ b/ernic/data/ernic.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2019 Xilinx, Inc. +# (C) Copyright 2019-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/ernic/data/ernic.tcl b/ernic/data/ernic.tcl index 5277f94b..0a590596 100644 --- a/ernic/data/ernic.tcl +++ b/ernic/data/ernic.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2019 Xilinx, Inc. +# (C) Copyright 2019-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/framebuf_rd/data/framebuf_rd.mdd b/framebuf_rd/data/framebuf_rd.mdd index e87e32d4..d39ec4a8 100644 --- a/framebuf_rd/data/framebuf_rd.mdd +++ b/framebuf_rd/data/framebuf_rd.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/framebuf_rd/data/framebuf_rd.tcl b/framebuf_rd/data/framebuf_rd.tcl index bc481dc9..9b89f702 100644 --- a/framebuf_rd/data/framebuf_rd.tcl +++ b/framebuf_rd/data/framebuf_rd.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/framebuf_wr/data/framebuf_wr.mdd b/framebuf_wr/data/framebuf_wr.mdd index f94928be..4bd8d750 100644 --- a/framebuf_wr/data/framebuf_wr.mdd +++ b/framebuf_wr/data/framebuf_wr.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/framebuf_wr/data/framebuf_wr.tcl b/framebuf_wr/data/framebuf_wr.tcl index 083f323a..e91a823c 100644 --- a/framebuf_wr/data/framebuf_wr.tcl +++ b/framebuf_wr/data/framebuf_wr.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/gamma_lut/data/gamma_lut.mdd b/gamma_lut/data/gamma_lut.mdd index 76c25764..0048d69f 100644 --- a/gamma_lut/data/gamma_lut.mdd +++ b/gamma_lut/data/gamma_lut.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/gamma_lut/data/gamma_lut.tcl b/gamma_lut/data/gamma_lut.tcl index 702ba805..ff76257f 100644 --- a/gamma_lut/data/gamma_lut.tcl +++ b/gamma_lut/data/gamma_lut.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/generic/data/generic.mdd b/generic/data/generic.mdd index f9ad31a3..ef38902c 100644 --- a/generic/data/generic.mdd +++ b/generic/data/generic.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/generic/data/generic.tcl b/generic/data/generic.tcl index dc72ab09..14039798 100644 --- a/generic/data/generic.tcl +++ b/generic/data/generic.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/globaltimerps/data/globaltimerps.mdd b/globaltimerps/data/globaltimerps.mdd index a4b5559e..64836425 100644 --- a/globaltimerps/data/globaltimerps.mdd +++ b/globaltimerps/data/globaltimerps.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/globaltimerps/data/globaltimerps.tcl b/globaltimerps/data/globaltimerps.tcl index 304b3bcd..734ec2b0 100644 --- a/globaltimerps/data/globaltimerps.tcl +++ b/globaltimerps/data/globaltimerps.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/gpiops/data/gpiops.mdd b/gpiops/data/gpiops.mdd index 586338ec..28f052c7 100644 --- a/gpiops/data/gpiops.mdd +++ b/gpiops/data/gpiops.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/gpiops/data/gpiops.tcl b/gpiops/data/gpiops.tcl index 9d6db5f8..33bceb69 100644 --- a/gpiops/data/gpiops.tcl +++ b/gpiops/data/gpiops.tcl @@ -1,8 +1,9 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd # Based on original code: # (C) Copyright 2007-2014 Michal Simek -# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # Michal SIMEK # diff --git a/hdmi_ctrl/data/hdmi_ctrl.mdd b/hdmi_ctrl/data/hdmi_ctrl.mdd index c35489a2..0dc63dd6 100644 --- a/hdmi_ctrl/data/hdmi_ctrl.mdd +++ b/hdmi_ctrl/data/hdmi_ctrl.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/hdmi_ctrl/data/hdmi_ctrl.tcl b/hdmi_ctrl/data/hdmi_ctrl.tcl index 9a247c29..11189b60 100644 --- a/hdmi_ctrl/data/hdmi_ctrl.tcl +++ b/hdmi_ctrl/data/hdmi_ctrl.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/hdmi_gt_ctrl/data/hdmi_gt_ctrl.mdd b/hdmi_gt_ctrl/data/hdmi_gt_ctrl.mdd index 13ebcad4..c13b0ff6 100644 --- a/hdmi_gt_ctrl/data/hdmi_gt_ctrl.mdd +++ b/hdmi_gt_ctrl/data/hdmi_gt_ctrl.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2019 Xilinx, Inc. +# (C) Copyright 2019-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/hdmi_gt_ctrl/data/hdmi_gt_ctrl.tcl b/hdmi_gt_ctrl/data/hdmi_gt_ctrl.tcl index ad8c435b..6dbde6ed 100644 --- a/hdmi_gt_ctrl/data/hdmi_gt_ctrl.tcl +++ b/hdmi_gt_ctrl/data/hdmi_gt_ctrl.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/hdmi_rx_ss/data/hdmi_rx_ss.mdd b/hdmi_rx_ss/data/hdmi_rx_ss.mdd index f68465b4..586cae9e 100644 --- a/hdmi_rx_ss/data/hdmi_rx_ss.mdd +++ b/hdmi_rx_ss/data/hdmi_rx_ss.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/hdmi_rx_ss/data/hdmi_rx_ss.tcl b/hdmi_rx_ss/data/hdmi_rx_ss.tcl index e7a48a20..1ca33276 100644 --- a/hdmi_rx_ss/data/hdmi_rx_ss.tcl +++ b/hdmi_rx_ss/data/hdmi_rx_ss.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/hdmi_tx_ss/data/hdmi_tx_ss.mdd b/hdmi_tx_ss/data/hdmi_tx_ss.mdd index e44c1516..cd08a2c3 100644 --- a/hdmi_tx_ss/data/hdmi_tx_ss.mdd +++ b/hdmi_tx_ss/data/hdmi_tx_ss.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/hdmi_tx_ss/data/hdmi_tx_ss.tcl b/hdmi_tx_ss/data/hdmi_tx_ss.tcl index 744d112f..993396aa 100644 --- a/hdmi_tx_ss/data/hdmi_tx_ss.tcl +++ b/hdmi_tx_ss/data/hdmi_tx_ss.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/i2s_receiver/data/i2s_receiver.mdd b/i2s_receiver/data/i2s_receiver.mdd index 44c6e13d..ab2055c8 100644 --- a/i2s_receiver/data/i2s_receiver.mdd +++ b/i2s_receiver/data/i2s_receiver.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/i2s_receiver/data/i2s_receiver.tcl b/i2s_receiver/data/i2s_receiver.tcl index a31950f2..f8f14cbb 100644 --- a/i2s_receiver/data/i2s_receiver.tcl +++ b/i2s_receiver/data/i2s_receiver.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/i2s_transmitter/data/i2s_transmitter.mdd b/i2s_transmitter/data/i2s_transmitter.mdd index e8c2f493..0f529ca1 100644 --- a/i2s_transmitter/data/i2s_transmitter.mdd +++ b/i2s_transmitter/data/i2s_transmitter.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/i2s_transmitter/data/i2s_transmitter.tcl b/i2s_transmitter/data/i2s_transmitter.tcl index 33e92567..aa45565a 100644 --- a/i2s_transmitter/data/i2s_transmitter.tcl +++ b/i2s_transmitter/data/i2s_transmitter.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/i3cpsx/data/i3cpsx.mdd b/i3cpsx/data/i3cpsx.mdd index 73d9d90a..3c17f55f 100644 --- a/i3cpsx/data/i3cpsx.mdd +++ b/i3cpsx/data/i3cpsx.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/i3cpsx/data/i3cpsx.tcl b/i3cpsx/data/i3cpsx.tcl index 4e6f8db4..b1c82fb6 100644 --- a/i3cpsx/data/i3cpsx.tcl +++ b/i3cpsx/data/i3cpsx.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/iicps/data/iicps.mdd b/iicps/data/iicps.mdd index d517054c..88f765ba 100644 --- a/iicps/data/iicps.mdd +++ b/iicps/data/iicps.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/iicps/data/iicps.tcl b/iicps/data/iicps.tcl index 368373f6..e49b25da 100644 --- a/iicps/data/iicps.tcl +++ b/iicps/data/iicps.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/intc/data/intc.mdd b/intc/data/intc.mdd index e1e358de..8a527cd4 100644 --- a/intc/data/intc.mdd +++ b/intc/data/intc.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/intc/data/intc.tcl b/intc/data/intc.tcl index 262a2efc..25bb38bd 100644 --- a/intc/data/intc.tcl +++ b/intc/data/intc.tcl @@ -1,8 +1,9 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd # Based on original code: # (C) Copyright 2007-2014 Michal Simek -# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # Michal SIMEK # diff --git a/mig_7series/data/mig_7series.mdd b/mig_7series/data/mig_7series.mdd index 0d7929a0..2991ecb2 100644 --- a/mig_7series/data/mig_7series.mdd +++ b/mig_7series/data/mig_7series.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/mig_7series/data/mig_7series.tcl b/mig_7series/data/mig_7series.tcl index 6024ad3c..470c3c2a 100644 --- a/mig_7series/data/mig_7series.tcl +++ b/mig_7series/data/mig_7series.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/mipi_csi2_rx/data/mipi_csi2_rx.mdd b/mipi_csi2_rx/data/mipi_csi2_rx.mdd index 999acf5d..e68003e9 100644 --- a/mipi_csi2_rx/data/mipi_csi2_rx.mdd +++ b/mipi_csi2_rx/data/mipi_csi2_rx.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/mipi_csi2_rx/data/mipi_csi2_rx.tcl b/mipi_csi2_rx/data/mipi_csi2_rx.tcl index 457c3165..787dc766 100644 --- a/mipi_csi2_rx/data/mipi_csi2_rx.tcl +++ b/mipi_csi2_rx/data/mipi_csi2_rx.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/mipi_dsi_tx/data/mipi_dsi_tx.mdd b/mipi_dsi_tx/data/mipi_dsi_tx.mdd index 8847d9ac..551bf128 100644 --- a/mipi_dsi_tx/data/mipi_dsi_tx.mdd +++ b/mipi_dsi_tx/data/mipi_dsi_tx.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/mipi_dsi_tx/data/mipi_dsi_tx.tcl b/mipi_dsi_tx/data/mipi_dsi_tx.tcl index cdbd3d53..ad2d89b5 100644 --- a/mipi_dsi_tx/data/mipi_dsi_tx.tcl +++ b/mipi_dsi_tx/data/mipi_dsi_tx.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/mixer/data/mixer.mdd b/mixer/data/mixer.mdd index 97d5e62f..4f924b29 100644 --- a/mixer/data/mixer.mdd +++ b/mixer/data/mixer.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/mixer/data/mixer.tcl b/mixer/data/mixer.tcl index 629dffe6..e84a4750 100644 --- a/mixer/data/mixer.tcl +++ b/mixer/data/mixer.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/mrmac/data/mrmac.mdd b/mrmac/data/mrmac.mdd index 93e975c1..e1475d6d 100644 --- a/mrmac/data/mrmac.mdd +++ b/mrmac/data/mrmac.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2020 Xilinx, Inc. +# (C) Copyright 2020-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/mrmac/data/mrmac.tcl b/mrmac/data/mrmac.tcl index 36df951c..d5562d6d 100644 --- a/mrmac/data/mrmac.tcl +++ b/mrmac/data/mrmac.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2019-2020 Xilinx, Inc. +# (C) Copyright 2019-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # # This program is free software; you can redistribute it and/or diff --git a/multi_scaler/data/multi_scaler.mdd b/multi_scaler/data/multi_scaler.mdd index e31d7381..23cf7380 100644 --- a/multi_scaler/data/multi_scaler.mdd +++ b/multi_scaler/data/multi_scaler.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/multi_scaler/data/multi_scaler.tcl b/multi_scaler/data/multi_scaler.tcl index 81be0edc..5427f326 100644 --- a/multi_scaler/data/multi_scaler.tcl +++ b/multi_scaler/data/multi_scaler.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/nandps/data/nandps.mdd b/nandps/data/nandps.mdd index 000b4042..1d56d80b 100644 --- a/nandps/data/nandps.mdd +++ b/nandps/data/nandps.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/nandps/data/nandps.tcl b/nandps/data/nandps.tcl index 7f038567..94e240ec 100644 --- a/nandps/data/nandps.tcl +++ b/nandps/data/nandps.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/norps/data/norps.mdd b/norps/data/norps.mdd index daeb5b3a..25cec91d 100644 --- a/norps/data/norps.mdd +++ b/norps/data/norps.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/norps/data/norps.tcl b/norps/data/norps.tcl index c675f0bd..974a1748 100644 --- a/norps/data/norps.tcl +++ b/norps/data/norps.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/nvme_aggr/data/nvme_aggr.mdd b/nvme_aggr/data/nvme_aggr.mdd index 5d16ea13..fc6422f2 100644 --- a/nvme_aggr/data/nvme_aggr.mdd +++ b/nvme_aggr/data/nvme_aggr.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/nvme_aggr/data/nvme_aggr.tcl b/nvme_aggr/data/nvme_aggr.tcl index dbab1181..da868ff4 100644 --- a/nvme_aggr/data/nvme_aggr.tcl +++ b/nvme_aggr/data/nvme_aggr.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/ocmcps/data/ocmcps.mdd b/ocmcps/data/ocmcps.mdd index 867882d0..9c6a175a 100644 --- a/ocmcps/data/ocmcps.mdd +++ b/ocmcps/data/ocmcps.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/ocmcps/data/ocmcps.tcl b/ocmcps/data/ocmcps.tcl index 304b3bcd..734ec2b0 100644 --- a/ocmcps/data/ocmcps.tcl +++ b/ocmcps/data/ocmcps.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/ospips/data/ospips.mdd b/ospips/data/ospips.mdd index 6e50a912..ad5a804f 100644 --- a/ospips/data/ospips.mdd +++ b/ospips/data/ospips.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2019 Xilinx, Inc. +# (C) Copyright 2019-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/ospips/data/ospips.tcl b/ospips/data/ospips.tcl index 19169a88..0acd7aae 100644 --- a/ospips/data/ospips.tcl +++ b/ospips/data/ospips.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2019 Xilinx, Inc. +# (C) Copyright 2019-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/pl310ps/data/pl310ps.mdd b/pl310ps/data/pl310ps.mdd index d6e1591c..c8ea7144 100644 --- a/pl310ps/data/pl310ps.mdd +++ b/pl310ps/data/pl310ps.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/pl310ps/data/pl310ps.tcl b/pl310ps/data/pl310ps.tcl index 304b3bcd..734ec2b0 100644 --- a/pl310ps/data/pl310ps.tcl +++ b/pl310ps/data/pl310ps.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/pmups/data/pmups.mdd b/pmups/data/pmups.mdd index 6b7c8d97..b4daf4dc 100644 --- a/pmups/data/pmups.mdd +++ b/pmups/data/pmups.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/pmups/data/pmups.tcl b/pmups/data/pmups.tcl index 304b3bcd..734ec2b0 100644 --- a/pmups/data/pmups.tcl +++ b/pmups/data/pmups.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/pr_decoupler/data/pr_decoupler.mdd b/pr_decoupler/data/pr_decoupler.mdd index 9184f544..b4b1f53c 100644 --- a/pr_decoupler/data/pr_decoupler.mdd +++ b/pr_decoupler/data/pr_decoupler.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2017 Xilinx, Inc. +# (C) Copyright 2017-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/pr_decoupler/data/pr_decoupler.tcl b/pr_decoupler/data/pr_decoupler.tcl index c6a6eded..afe5faf6 100644 --- a/pr_decoupler/data/pr_decoupler.tcl +++ b/pr_decoupler/data/pr_decoupler.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2017 Xilinx, Inc. +# (C) Copyright 2017-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/ptp_1588_timer_syncer/data/ptp_1588_timer_syncer.mdd b/ptp_1588_timer_syncer/data/ptp_1588_timer_syncer.mdd index e37069e1..d7beba0a 100644 --- a/ptp_1588_timer_syncer/data/ptp_1588_timer_syncer.mdd +++ b/ptp_1588_timer_syncer/data/ptp_1588_timer_syncer.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2021 Xilinx, Inc. +# (C) Copyright 2021-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/ptp_1588_timer_syncer/data/ptp_1588_timer_syncer.tcl b/ptp_1588_timer_syncer/data/ptp_1588_timer_syncer.tcl index 481d55f1..11250d9c 100644 --- a/ptp_1588_timer_syncer/data/ptp_1588_timer_syncer.tcl +++ b/ptp_1588_timer_syncer/data/ptp_1588_timer_syncer.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2021 Xilinx, Inc. +# (C) Copyright 2021-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/qspips/data/qspips.mdd b/qspips/data/qspips.mdd index 5016b716..27a45862 100644 --- a/qspips/data/qspips.mdd +++ b/qspips/data/qspips.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/qspips/data/qspips.tcl b/qspips/data/qspips.tcl index 7954335f..b4e99bf3 100644 --- a/qspips/data/qspips.tcl +++ b/qspips/data/qspips.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/ramps/data/ramps.mdd b/ramps/data/ramps.mdd index 227e8e5b..57f20b9d 100644 --- a/ramps/data/ramps.mdd +++ b/ramps/data/ramps.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/ramps/data/ramps.tcl b/ramps/data/ramps.tcl index 2f3b7ce9..72676cfa 100644 --- a/ramps/data/ramps.tcl +++ b/ramps/data/ramps.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/rfdc/data/rfdc.mdd b/rfdc/data/rfdc.mdd index 533e6efc..f29baa41 100644 --- a/rfdc/data/rfdc.mdd +++ b/rfdc/data/rfdc.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2017-2020 Xilinx, Inc. +# (C) Copyright 2017-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/rfdc/data/rfdc.tcl b/rfdc/data/rfdc.tcl index dcd608f5..aa300e30 100644 --- a/rfdc/data/rfdc.tcl +++ b/rfdc/data/rfdc.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2017-2021 Xilinx, Inc. +# (C) Copyright 2017-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/scene_change_detector/data/scene_change_detector.mdd b/scene_change_detector/data/scene_change_detector.mdd index 1ade6bd5..ae2848f6 100644 --- a/scene_change_detector/data/scene_change_detector.mdd +++ b/scene_change_detector/data/scene_change_detector.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/scene_change_detector/data/scene_change_detector.tcl b/scene_change_detector/data/scene_change_detector.tcl index 557cca26..1f448ee6 100644 --- a/scene_change_detector/data/scene_change_detector.tcl +++ b/scene_change_detector/data/scene_change_detector.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/scugic/data/scugic.mdd b/scugic/data/scugic.mdd index 56782420..37f90188 100644 --- a/scugic/data/scugic.mdd +++ b/scugic/data/scugic.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/scugic/data/scugic.tcl b/scugic/data/scugic.tcl index cfee3fcf..646484cb 100644 --- a/scugic/data/scugic.tcl +++ b/scugic/data/scugic.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/scutimer/data/scutimer.mdd b/scutimer/data/scutimer.mdd index 48707ab4..ad7d7380 100644 --- a/scutimer/data/scutimer.mdd +++ b/scutimer/data/scutimer.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/scutimer/data/scutimer.tcl b/scutimer/data/scutimer.tcl index 304b3bcd..734ec2b0 100644 --- a/scutimer/data/scutimer.tcl +++ b/scutimer/data/scutimer.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/scuwdt/data/scuwdt.mdd b/scuwdt/data/scuwdt.mdd index bcf38a7b..8ae5a292 100644 --- a/scuwdt/data/scuwdt.mdd +++ b/scuwdt/data/scuwdt.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/scuwdt/data/scuwdt.tcl b/scuwdt/data/scuwdt.tcl index 304b3bcd..734ec2b0 100644 --- a/scuwdt/data/scuwdt.tcl +++ b/scuwdt/data/scuwdt.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/sdfec/data/sdfec.mdd b/sdfec/data/sdfec.mdd index 1001b90c..721b2723 100644 --- a/sdfec/data/sdfec.mdd +++ b/sdfec/data/sdfec.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2017 Xilinx, Inc. +# (C) Copyright 2017-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/sdfec/data/sdfec.tcl b/sdfec/data/sdfec.tcl index 4f6182f1..fdff6dd7 100644 --- a/sdfec/data/sdfec.tcl +++ b/sdfec/data/sdfec.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2017 Xilinx, Inc. +# (C) Copyright 2017-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/sdi_rx/data/sdi_rx.mdd b/sdi_rx/data/sdi_rx.mdd index 51ded9aa..0f13166b 100644 --- a/sdi_rx/data/sdi_rx.mdd +++ b/sdi_rx/data/sdi_rx.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/sdi_rx/data/sdi_rx.tcl b/sdi_rx/data/sdi_rx.tcl index 3abc9712..bba21cdf 100644 --- a/sdi_rx/data/sdi_rx.tcl +++ b/sdi_rx/data/sdi_rx.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/sdi_tx/data/sdi_tx.mdd b/sdi_tx/data/sdi_tx.mdd index 2c60883d..e3801dc3 100644 --- a/sdi_tx/data/sdi_tx.mdd +++ b/sdi_tx/data/sdi_tx.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/sdi_tx/data/sdi_tx.tcl b/sdi_tx/data/sdi_tx.tcl index b9b60fb0..ca941571 100644 --- a/sdi_tx/data/sdi_tx.tcl +++ b/sdi_tx/data/sdi_tx.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/sdps/data/sdps.mdd b/sdps/data/sdps.mdd index 029b4f7a..5945b317 100644 --- a/sdps/data/sdps.mdd +++ b/sdps/data/sdps.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/sdps/data/sdps.tcl b/sdps/data/sdps.tcl index 601325d6..870cef4b 100644 --- a/sdps/data/sdps.tcl +++ b/sdps/data/sdps.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/slcrps/data/slcrps.mdd b/slcrps/data/slcrps.mdd index d8b1e80a..2f9aef9a 100644 --- a/slcrps/data/slcrps.mdd +++ b/slcrps/data/slcrps.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/slcrps/data/slcrps.tcl b/slcrps/data/slcrps.tcl index 0d32bd90..a43667cf 100644 --- a/slcrps/data/slcrps.tcl +++ b/slcrps/data/slcrps.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/smccps/data/smccps.mdd b/smccps/data/smccps.mdd index 19585156..3e9419e4 100644 --- a/smccps/data/smccps.mdd +++ b/smccps/data/smccps.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/smccps/data/smccps.tcl b/smccps/data/smccps.tcl index 304b3bcd..734ec2b0 100644 --- a/smccps/data/smccps.tcl +++ b/smccps/data/smccps.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/spips/data/spips.mdd b/spips/data/spips.mdd index 3db585ce..31d69c49 100644 --- a/spips/data/spips.mdd +++ b/spips/data/spips.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/spips/data/spips.tcl b/spips/data/spips.tcl index 1236c7d1..618ba750 100644 --- a/spips/data/spips.tcl +++ b/spips/data/spips.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/sync_ip/data/sync_ip.mdd b/sync_ip/data/sync_ip.mdd index 04f2e514..0fa8dfa7 100644 --- a/sync_ip/data/sync_ip.mdd +++ b/sync_ip/data/sync_ip.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2019 Xilinx, Inc. +# (C) Copyright 2019-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/sync_ip/data/sync_ip.tcl b/sync_ip/data/sync_ip.tcl index f007fc17..ec095671 100644 --- a/sync_ip/data/sync_ip.tcl +++ b/sync_ip/data/sync_ip.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2019 Xilinx, Inc. +# (C) Copyright 2019-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/sysmonpsv/data/sysmonpsv.mdd b/sysmonpsv/data/sysmonpsv.mdd index 381340e8..2d0da6da 100644 --- a/sysmonpsv/data/sysmonpsv.mdd +++ b/sysmonpsv/data/sysmonpsv.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2020 Xilinx, Inc. +# (C) Copyright 2020-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/sysmonpsv/data/sysmonpsv.tcl b/sysmonpsv/data/sysmonpsv.tcl index 7e9de961..2c0740e5 100644 --- a/sysmonpsv/data/sysmonpsv.tcl +++ b/sysmonpsv/data/sysmonpsv.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2020 Xilinx, Inc. +# (C) Copyright 2020-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/tmrctr/data/tmrctr.mdd b/tmrctr/data/tmrctr.mdd index acd54852..717834ac 100644 --- a/tmrctr/data/tmrctr.mdd +++ b/tmrctr/data/tmrctr.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/tmrctr/data/tmrctr.tcl b/tmrctr/data/tmrctr.tcl index 2fb17386..50db1876 100644 --- a/tmrctr/data/tmrctr.tcl +++ b/tmrctr/data/tmrctr.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/tpg/data/tpg.mdd b/tpg/data/tpg.mdd index 40e5c61b..623e14da 100644 --- a/tpg/data/tpg.mdd +++ b/tpg/data/tpg.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/tpg/data/tpg.tcl b/tpg/data/tpg.tcl index 0793ae2e..9f151d6a 100644 --- a/tpg/data/tpg.tcl +++ b/tpg/data/tpg.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/tsn/data/tsn.mdd b/tsn/data/tsn.mdd index ca56a620..f1161bad 100644 --- a/tsn/data/tsn.mdd +++ b/tsn/data/tsn.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/tsn/data/tsn.tcl b/tsn/data/tsn.tcl index 91dfc89e..6f79343c 100644 --- a/tsn/data/tsn.tcl +++ b/tsn/data/tsn.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/ttcps/data/ttcps.mdd b/ttcps/data/ttcps.mdd index be65b9e3..41393dd7 100644 --- a/ttcps/data/ttcps.mdd +++ b/ttcps/data/ttcps.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/ttcps/data/ttcps.tcl b/ttcps/data/ttcps.tcl index 304b3bcd..734ec2b0 100644 --- a/ttcps/data/ttcps.tcl +++ b/ttcps/data/ttcps.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/uartlite/data/uartlite.mdd b/uartlite/data/uartlite.mdd index 738f30f8..9854cf99 100644 --- a/uartlite/data/uartlite.mdd +++ b/uartlite/data/uartlite.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/uartlite/data/uartlite.tcl b/uartlite/data/uartlite.tcl index 0887c1e3..bf998de4 100644 --- a/uartlite/data/uartlite.tcl +++ b/uartlite/data/uartlite.tcl @@ -1,8 +1,9 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd # Based on original code: # (C) Copyright 2007-2014 Michal Simek -# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # Michal SIMEK # diff --git a/uartns/data/uartns.mdd b/uartns/data/uartns.mdd index 164038eb..015b4025 100644 --- a/uartns/data/uartns.mdd +++ b/uartns/data/uartns.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/uartns/data/uartns.tcl b/uartns/data/uartns.tcl index 1ac1f715..ebeed943 100644 --- a/uartns/data/uartns.tcl +++ b/uartns/data/uartns.tcl @@ -1,8 +1,9 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd # Based on original code: # (C) Copyright 2007-2014 Michal Simek -# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # Michal SIMEK # diff --git a/uartps/data/uartps.mdd b/uartps/data/uartps.mdd index f66b8ad4..203c0491 100644 --- a/uartps/data/uartps.mdd +++ b/uartps/data/uartps.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/uartps/data/uartps.tcl b/uartps/data/uartps.tcl index f9f0e403..b1f27a38 100644 --- a/uartps/data/uartps.tcl +++ b/uartps/data/uartps.tcl @@ -1,8 +1,9 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd # Based on original code: # (C) Copyright 2007-2014 Michal Simek -# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # Michal SIMEK # diff --git a/usbps/data/usbps.mdd b/usbps/data/usbps.mdd index 5a76e374..388b070d 100644 --- a/usbps/data/usbps.mdd +++ b/usbps/data/usbps.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/usbps/data/usbps.tcl b/usbps/data/usbps.tcl index 7d9eefdf..5fa87c0d 100644 --- a/usbps/data/usbps.tcl +++ b/usbps/data/usbps.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/vid_phy_ctrl/data/vid_phy_ctrl.mdd b/vid_phy_ctrl/data/vid_phy_ctrl.mdd index 2f772cf1..9ae00193 100644 --- a/vid_phy_ctrl/data/vid_phy_ctrl.mdd +++ b/vid_phy_ctrl/data/vid_phy_ctrl.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/vid_phy_ctrl/data/vid_phy_ctrl.tcl b/vid_phy_ctrl/data/vid_phy_ctrl.tcl index 0a3fb8e6..8834fb18 100644 --- a/vid_phy_ctrl/data/vid_phy_ctrl.tcl +++ b/vid_phy_ctrl/data/vid_phy_ctrl.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/vproc_ss/data/vproc_ss.mdd b/vproc_ss/data/vproc_ss.mdd index 336d9758..dbdba2ca 100644 --- a/vproc_ss/data/vproc_ss.mdd +++ b/vproc_ss/data/vproc_ss.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/vproc_ss/data/vproc_ss.tcl b/vproc_ss/data/vproc_ss.tcl index 81e406b1..607047f3 100644 --- a/vproc_ss/data/vproc_ss.tcl +++ b/vproc_ss/data/vproc_ss.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/vtc/data/vtc.mdd b/vtc/data/vtc.mdd index 3d003c32..83286905 100644 --- a/vtc/data/vtc.mdd +++ b/vtc/data/vtc.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/vtc/data/vtc.tcl b/vtc/data/vtc.tcl index 3eb28ea9..7a738da7 100644 --- a/vtc/data/vtc.tcl +++ b/vtc/data/vtc.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2018 Xilinx, Inc. +# (C) Copyright 2018-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/wdtps/data/wdtps.mdd b/wdtps/data/wdtps.mdd index 4532d04f..034f76db 100644 --- a/wdtps/data/wdtps.mdd +++ b/wdtps/data/wdtps.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/wdtps/data/wdtps.tcl b/wdtps/data/wdtps.tcl index 304b3bcd..734ec2b0 100644 --- a/wdtps/data/wdtps.tcl +++ b/wdtps/data/wdtps.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/xadcps/data/xadcps.mdd b/xadcps/data/xadcps.mdd index e3d3c26e..29640a3b 100644 --- a/xadcps/data/xadcps.mdd +++ b/xadcps/data/xadcps.mdd @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/xadcps/data/xadcps.tcl b/xadcps/data/xadcps.tcl index 304b3bcd..734ec2b0 100644 --- a/xadcps/data/xadcps.tcl +++ b/xadcps/data/xadcps.tcl @@ -1,5 +1,6 @@ # -# (C) Copyright 2014-2015 Xilinx, Inc. +# (C) Copyright 2014-2022 Xilinx, Inc. +# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as