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Is the hardware design configurable? #176

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gitosu67 opened this issue May 2, 2020 · 0 comments
Open

Is the hardware design configurable? #176

gitosu67 opened this issue May 2, 2020 · 0 comments

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@gitosu67
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gitosu67 commented May 2, 2020

Can we generate all the IPs using the code provided or create custom IPs? For example, the files https://github.com/Xilinx/CHaiDNN/tree/master/design/ can they be modified and recompiled then run on FPGA?

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