You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
Currently the clock frequency is only partially modifiable. By partially I mean that it can be specified in the Makefile when linking the designing, which directly affects PnR. However, the frequency is hard-coded for most kernels (e.g. vadd_put) in the .tcl script.
While this has no impact on PnR, it can affect HLS synthesis - The HLS compiler uses the clock frequency to schedule the design, and, with a higher frequency the design can take more clock cycles. So if performing HLS compilation with e.g. 250 MHz but PnR with 200 MHz, there can be a performance drop due to added clock cycles.
I will try to open a PR for this, so that the operating frequency can be set for each part of ACCL and is propagated from the top-level Makefile.
The text was updated successfully, but these errors were encountered:
Currently the clock frequency is only partially modifiable. By partially I mean that it can be specified in the Makefile when linking the designing, which directly affects PnR. However, the frequency is hard-coded for most kernels (e.g. vadd_put) in the .tcl script.
While this has no impact on PnR, it can affect HLS synthesis - The HLS compiler uses the clock frequency to schedule the design, and, with a higher frequency the design can take more clock cycles. So if performing HLS compilation with e.g. 250 MHz but PnR with 200 MHz, there can be a performance drop due to added clock cycles.
I will try to open a PR for this, so that the operating frequency can be set for each part of ACCL and is propagated from the top-level Makefile.
The text was updated successfully, but these errors were encountered: