Are TCP/UDP depacketizers still directly connected to a DMA?

[Apfelvater]

In the original ACCL Paper "ACCL: FPGA-Accelerated Collectives over 100Gbps TCP-IP", you wrote, that each Depacketizer is directly connected one DMA's write-channel. Is that still up-to-date, or in other words, is Figure 2 (Data Plane) still up-to-date?
The file "/kernels/cclo/tcl/rebuild_bd.tcl" suggests, that the Depacketizer is now only connected to the AXIS Switch 0, but i have to say, i am not very familiar with tcl syntax.
Thanks in advance!