Add dblclockfft pipelined FFT #31
Description
Design: dblclockfft
Repository: https://github.com/ZipCPU/dblclockfft
License: LGPLv3 (commercial licenses available from Gisselquist Technology)
Language: Verilog (generated by C++ configurator)
Stars: ~180
Description
A configurable, pipelined FFT/IFFT core generator that produces synthesizable Verilog. Supports arbitrary power-of-2 transform sizes with configurable bit widths, and processes two samples per clock cycle using a radix-2 butterfly architecture.
Why it's a good benchmark candidate
- New architecture: DSP/signal processing is not represented in the suite. Pipelined FFT butterflies with twiddle factor ROMs create a distinctive datapath pattern — deep pipelines, heavy use of multipliers, and regular but complex interconnect.
- Industry-relevant: FFT is a fundamental building block in communications (OFDM, radar), audio processing, and scientific computing. Common in real ASIC designs.
- Formal verification: Verified with SymbiYosys formal proofs (yices + boolector engines) in addition to Verilator simulation and Octave golden model comparison — a unique verification approach not yet in the suite.
Estimated complexity
- Gate count: Medium (configurable — scales with FFT size and bit width; a 1024-point FFT is a substantial design)
- Memories: Twiddle factor ROMs and internal pipeline registers. ROMs may need FakeRAM for larger configurations.
- IO count: Low to medium (streaming input/output with handshaking)
Verification
Formal verification with SymbiYosys (yices + boolector). Verilator-based C++ testbenches with Octave golden model comparison. Comprehensive bench tests covering individual butterflies and full FFT.
Conversion notes
A C++ generator produces the Verilog RTL files. Run the generator once to produce a specific FFT configuration, then use the output Verilog directly. Generated code is clean Verilog 2001.
Target platforms
- asap7
- nangate45
- sky130hd