Add core_jpeg JPEG decoder #30
Description
Design: core_jpeg
Repository: https://github.com/ultraembedded/core_jpeg
License: Check LICENSE file (ultraembedded projects typically Apache 2.0)
Language: Verilog
Stars: ~1,100
Description
A high-throughput baseline JPEG decoder in Verilog with 24-bit RGB output. Supports monochrome, 4:4:4, and 4:2:0 chroma subsampling with both fixed and dynamic Huffman table modes.
Why it's a good benchmark candidate
- New architecture: Image/video processing is not represented in the suite. The JPEG decoder has a complex multi-stage pipeline (Huffman decode → inverse quantization → IDCT → color conversion → reorder) that stresses synthesis differently than processors or network controllers.
- Industry-relevant: JPEG decode is a common peripheral in display controllers, camera pipelines, and SoC media subsystems.
- Active development: 1.1k stars, well-documented, actively maintained by ultraembedded.
Estimated complexity
- Gate count: Medium (pipelined architecture with DSP multipliers, Huffman tables, IDCT butterfly)
- Memories: Yes — uses block RAMs for Huffman tables, quantization tables, and line buffers. Will need FakeRAM or mapping to standard cells.
- IO count: Medium (AXI-style streaming input, RGB pixel output with block coordinates)
Verification
Co-simulation against a C reference model, tested on FPGA with thousands of images. Verilator-friendly synthesizable Verilog 2001. The companion core_jpeg_decoder repo adds an AXI-4 DMA wrapper with additional test infrastructure.
Conversion notes
Pure synthesizable Verilog 2001 — no conversion needed. Multipliers and tables map to DSP48/blockRAM on FPGA but will synthesize to standard cells for ASIC.
Target platforms
- asap7
- nangate45
- sky130hd