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Martin Zabel
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Memtest for Nexys4DDR
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‎projects/mem/ddr2/memtest_Nexys4DDR/Nexys4DDR.ucf

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# Schematic name: CLK100MHZ
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NET "sys_clk_i" TNM_NET = TNM_sys_clk | LOC = E3 | IOSTANDARD = LVCMOS33;
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TIMESPEC "TS_sys_clk" = PERIOD "TNM_sys_clk" 10 ns;
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NET "led<7>" LOC = "U16" | IOSTANDARD = LVCMOS33;
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NET "led<6>" LOC = "U17" | IOSTANDARD = LVCMOS33;
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NET "led<5>" LOC = "V17" | IOSTANDARD = LVCMOS33;
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NET "led<4>" LOC = "R18" | IOSTANDARD = LVCMOS33;
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NET "led<3>" LOC = "N14" | IOSTANDARD = LVCMOS33;
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NET "led<2>" LOC = "J13" | IOSTANDARD = LVCMOS33;
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NET "led<1>" LOC = "K15" | IOSTANDARD = LVCMOS33;
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NET "led<0>" LOC = "H17" | IOSTANDARD = LVCMOS33;

‎projects/mem/ddr2/memtest_Nexys4DDR/ipcore_dir/mig_Nexys4DDR.xco

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##############################################################
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#
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# Xilinx Core Generator version 14.7
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# Date: Tue Jul 03 20:28:42 2018
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#
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##############################################################
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#
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# This file contains the customisation parameters for a
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# Xilinx CORE Generator IP GUI. It is strongly recommended
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# that you do not manually alter this file as it may cause
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# unexpected and unsupported behavior.
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#
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##############################################################
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#
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# Generated from component: xilinx.com:ip:mig_7series:1.9
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#
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##############################################################
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#
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# BEGIN Project Options
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SET addpads = false
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SET asysymbol = true
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = false
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SET designentry = VHDL
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SET device = xc7a100t
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SET devicefamily = artix7
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SET flowvendor = Other
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SET formalverification = false
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SET foundationsym = false
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SET implementationfiletype = Ngc
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SET package = csg324
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SET removerpms = false
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SET simulationfiles = Behavioral
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SET speedgrade = -1
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SET verilogsim = false
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SET vhdlsim = true
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# END Project Options
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# BEGIN Select
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SELECT MIG_7_Series family Xilinx,_Inc. 1.9
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# END Select
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# BEGIN Parameters
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CSET component_name=mig_Nexys4DDR
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CSET xml_input_file=./mig_Nexys4DDR/mig.prj
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# END Parameters
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# BEGIN Extra information
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MISC pkg_timestamp=2013-10-13T18:46:09Z
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# END Extra information
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GENERATE
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# CRC: c215c63b

‎projects/mem/ddr2/memtest_Nexys4DDR/ipcore_dir/mig_Nexys4DDR.xise

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‎projects/mem/ddr2/memtest_Nexys4DDR/ipcore_dir/mig_Nexys4DDR/datasheet.txt

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CORE Generator Options:
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Target Device : xc7a100t-csg324
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Speed Grade : -1
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HDL : vhdl
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Synthesis Tool : Foundation_ISE
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MIG Output Options:
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Module Name : mig_Nexys4DDR
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No of Controllers : 1
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Selected Compatible Device(s) : --
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FPGA Options:
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System Clock Type : No Buffer
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Reference Clock Type : No Buffer
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Debug Port : OFF
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Internal Vref : enabled
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IO Power Reduction : ON
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XADC instantiation in MIG : Enabled
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Extended FPGA Options:
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DCI for DQ,DQS/DQS#,DM : enabled
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Internal Termination (HR Banks) : 50 Ohms
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/*******************************************************/
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/* Controller 0 */
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/*******************************************************/
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Controller Options :
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Memory : DDR2_SDRAM
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Interface : NATIVE
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Design Clock Frequency : 3077 ps (324.99 MHz)
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Phy to Controller Clock Ratio : 4:1
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Input Clock Period : 10000 ps
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CLKFBOUT_MULT (PLL) : 13
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DIVCLK_DIVIDE (PLL) : 1
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VCC_AUX IO : 1.8V
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Memory Type : Components
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Memory Part : MT47H64M16HR-25E
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Equivalent Part(s) : --
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Data Width : 16
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ECC : Disabled
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Data Mask : enabled
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ORDERING : Normal
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AXI Parameters :
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Data Width : 128
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Arbitration Scheme : RD_PRI_REG
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Narrow Burst Support : 1
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ID Width : 4
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Memory Options:
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Burst Length (MR0[1:0]) : 8
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CAS Latency (MR0[6:4]) : 5
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Output Drive Strength (MR1[5,1]) : Fullstrength
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Controller CS option : Enable
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Rtt_NOM - ODT (MR1[9,6,2]) : 50ohms
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Memory Address Mapping : ROW_BANK_COLUMN
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Bank Selections:
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System_Control:
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SignalName: sys_rst
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PadLocation: No connect Bank: Select Bank
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SignalName: init_calib_complete
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PadLocation: No connect Bank: Select Bank
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SignalName: tg_compare_error
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PadLocation: No connect Bank: Select Bank
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‎projects/mem/ddr2/memtest_Nexys4DDR/ipcore_dir/mig_Nexys4DDR/mig.prj

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<?xml version='1.0' encoding='UTF-8'?>
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<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
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<Project NoOfControllers="1" >
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<ModuleName>mig_Nexys4DDR</ModuleName>
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<dci_inouts_inputs>1</dci_inouts_inputs>
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<dci_inputs>1</dci_inputs>
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<Debug_En>OFF</Debug_En>
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<DataDepth_En>1024</DataDepth_En>
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<LowPower_En>ON</LowPower_En>
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<XADC_En>Enabled</XADC_En>
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<TargetFPGA>xc7a100t-csg324/-1</TargetFPGA>
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<Version>1.9</Version>
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<SystemClock>No Buffer</SystemClock>
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<ReferenceClock>No Buffer</ReferenceClock>
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<SysResetPolarity>ACTIVE LOW</SysResetPolarity>
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<BankSelectionFlag>FALSE</BankSelectionFlag>
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<InternalVref>1</InternalVref>
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<dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
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<dci_cascade>0</dci_cascade>
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<Controller number="0" >
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<MemoryDevice>DDR2_SDRAM/Components/MT47H64M16HR-25E</MemoryDevice>
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<TimePeriod>3077</TimePeriod>
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<VccAuxIO>1.8V</VccAuxIO>
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<PHYRatio>4:1</PHYRatio>
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<InputClkFreq>99.997</InputClkFreq>
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<UIExtraClocks>0</UIExtraClocks>
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<MMCMClkOut0> 1.000</MMCMClkOut0>
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<MMCMClkOut1>1</MMCMClkOut1>
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<MMCMClkOut2>1</MMCMClkOut2>
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<MMCMClkOut3>1</MMCMClkOut3>
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<MMCMClkOut4>1</MMCMClkOut4>
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<DataWidth>16</DataWidth>
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<DeepMemory>1</DeepMemory>
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<DataMask>1</DataMask>
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<ECC>Disabled</ECC>
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<Ordering>Normal</Ordering>
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<CustomPart>FALSE</CustomPart>
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<NewPartName></NewPartName>
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<RowAddress>13</RowAddress>
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<ColAddress>10</ColAddress>
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<BankAddress>3</BankAddress>
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<UserMemoryAddressMap>ROW_BANK_COLUMN</UserMemoryAddressMap>
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<PinSelection>
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="M4" SLEW="FAST" name="ddr2_addr[0]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="R2" SLEW="FAST" name="ddr2_addr[10]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="K5" SLEW="FAST" name="ddr2_addr[11]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="N6" SLEW="FAST" name="ddr2_addr[12]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="P4" SLEW="FAST" name="ddr2_addr[1]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="M6" SLEW="FAST" name="ddr2_addr[2]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="T1" SLEW="FAST" name="ddr2_addr[3]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="L3" SLEW="FAST" name="ddr2_addr[4]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="P5" SLEW="FAST" name="ddr2_addr[5]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="M2" SLEW="FAST" name="ddr2_addr[6]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="N1" SLEW="FAST" name="ddr2_addr[7]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="L4" SLEW="FAST" name="ddr2_addr[8]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="N5" SLEW="FAST" name="ddr2_addr[9]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="P2" SLEW="FAST" name="ddr2_ba[0]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="P3" SLEW="FAST" name="ddr2_ba[1]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="R1" SLEW="FAST" name="ddr2_ba[2]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="L1" SLEW="FAST" name="ddr2_cas_n" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL18_II" PADName="L5" SLEW="FAST" name="ddr2_ck_n[0]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL18_II" PADName="L6" SLEW="FAST" name="ddr2_ck_p[0]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="M1" SLEW="FAST" name="ddr2_cke[0]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="K6" SLEW="FAST" name="ddr2_cs_n[0]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="T6" SLEW="FAST" name="ddr2_dm[0]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="U1" SLEW="FAST" name="ddr2_dm[1]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="R7" SLEW="FAST" name="ddr2_dq[0]" IN_TERM="UNTUNED_SPLIT_50" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="V5" SLEW="FAST" name="ddr2_dq[10]" IN_TERM="UNTUNED_SPLIT_50" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="U4" SLEW="FAST" name="ddr2_dq[11]" IN_TERM="UNTUNED_SPLIT_50" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="V4" SLEW="FAST" name="ddr2_dq[12]" IN_TERM="UNTUNED_SPLIT_50" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="T4" SLEW="FAST" name="ddr2_dq[13]" IN_TERM="UNTUNED_SPLIT_50" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="V1" SLEW="FAST" name="ddr2_dq[14]" IN_TERM="UNTUNED_SPLIT_50" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="T3" SLEW="FAST" name="ddr2_dq[15]" IN_TERM="UNTUNED_SPLIT_50" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="V6" SLEW="FAST" name="ddr2_dq[1]" IN_TERM="UNTUNED_SPLIT_50" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="R8" SLEW="FAST" name="ddr2_dq[2]" IN_TERM="UNTUNED_SPLIT_50" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="U7" SLEW="FAST" name="ddr2_dq[3]" IN_TERM="UNTUNED_SPLIT_50" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="V7" SLEW="FAST" name="ddr2_dq[4]" IN_TERM="UNTUNED_SPLIT_50" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="R6" SLEW="FAST" name="ddr2_dq[5]" IN_TERM="UNTUNED_SPLIT_50" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="U6" SLEW="FAST" name="ddr2_dq[6]" IN_TERM="UNTUNED_SPLIT_50" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="R5" SLEW="FAST" name="ddr2_dq[7]" IN_TERM="UNTUNED_SPLIT_50" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="T5" SLEW="FAST" name="ddr2_dq[8]" IN_TERM="UNTUNED_SPLIT_50" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="U3" SLEW="FAST" name="ddr2_dq[9]" IN_TERM="UNTUNED_SPLIT_50" />
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<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL18_II" PADName="V9" SLEW="FAST" name="ddr2_dqs_n[0]" IN_TERM="UNTUNED_SPLIT_50" />
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<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL18_II" PADName="V2" SLEW="FAST" name="ddr2_dqs_n[1]" IN_TERM="UNTUNED_SPLIT_50" />
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<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL18_II" PADName="U9" SLEW="FAST" name="ddr2_dqs_p[0]" IN_TERM="UNTUNED_SPLIT_50" />
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<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL18_II" PADName="U2" SLEW="FAST" name="ddr2_dqs_p[1]" IN_TERM="UNTUNED_SPLIT_50" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="M3" SLEW="FAST" name="ddr2_odt[0]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="N4" SLEW="FAST" name="ddr2_ras_n" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="N2" SLEW="FAST" name="ddr2_we_n" IN_TERM="" />
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</PinSelection>
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<System_Control>
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<Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
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<Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
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<Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
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</System_Control>
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<TimingParameters>
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<Parameters twtr="7.5" trrd="10" trefi="7.8" tfaw="45" trtp="7.5" trfc="127.5" trp="12.5" tras="40" trcd="15" />
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</TimingParameters>
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<mrBurstLength name="Burst Length" >8</mrBurstLength>
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<mrBurstType name="Burst Type" >Sequential</mrBurstType>
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<mrCasLatency name="CAS Latency" >5</mrCasLatency>
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<mrMode name="Mode" >Normal</mrMode>
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<mrDllReset name="DLL Reset" >No</mrDllReset>
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<mrPdMode name="PD Mode" >Fast exit</mrPdMode>
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<mrWriteRecovery name="Write Recovery" >5</mrWriteRecovery>
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<emrDllEnable name="DLL Enable" >Enable-Normal</emrDllEnable>
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<emrOutputDriveStrength name="Output Drive Strength" >Fullstrength</emrOutputDriveStrength>
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<emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>
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<emrCKSelection name="Memory Clock Selection" >1</emrCKSelection>
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<emrRTT name="RTT (nominal) - ODT" >50ohms</emrRTT>
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<emrPosted name="Additive Latency (AL)" >0</emrPosted>
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<emrOCD name="OCD Operation" >OCD Exit</emrOCD>
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<emrDQS name="DQS# Enable" >Enable</emrDQS>
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<emrRDQS name="RDQS Enable" >Disable</emrRDQS>
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<emrOutputs name="Outputs" >Enable</emrOutputs>
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<PortInterface>NATIVE</PortInterface>
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</Controller>
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</Project>

‎projects/mem/ddr2/memtest_Nexys4DDR/ipcore_dir/mig_Nexys4DDR/mig_Nexys4DDR.csv

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#Generated by MIG Version 1.9
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#Coregen 14.5 - Build Number P.20131013 on Di 3. Jul 22:28:39 2018
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#FPGA Part xc7a100t-csg324-1
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IO Bank,Pin Number,Signal Name,IO Standard,Direction,Slew Rate,DiffPair Type,DiffPair Signal
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34,R7,ddr2_dq[0],SSTL18_II,INOUT,FAST,,
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34,V6,ddr2_dq[1],SSTL18_II,INOUT,FAST,,
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34,R8,ddr2_dq[2],SSTL18_II,INOUT,FAST,,
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34,U7,ddr2_dq[3],SSTL18_II,INOUT,FAST,,
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34,V7,ddr2_dq[4],SSTL18_II,INOUT,FAST,,
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34,R6,ddr2_dq[5],SSTL18_II,INOUT,FAST,,
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34,U6,ddr2_dq[6],SSTL18_II,INOUT,FAST,,
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34,R5,ddr2_dq[7],SSTL18_II,INOUT,FAST,,
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34,T5,ddr2_dq[8],SSTL18_II,INOUT,FAST,,
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34,U3,ddr2_dq[9],SSTL18_II,INOUT,FAST,,
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34,V5,ddr2_dq[10],SSTL18_II,INOUT,FAST,,
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34,U4,ddr2_dq[11],SSTL18_II,INOUT,FAST,,
19+
34,V4,ddr2_dq[12],SSTL18_II,INOUT,FAST,,
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34,T4,ddr2_dq[13],SSTL18_II,INOUT,FAST,,
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34,V1,ddr2_dq[14],SSTL18_II,INOUT,FAST,,
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34,T3,ddr2_dq[15],SSTL18_II,INOUT,FAST,,
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34,N6,ddr2_addr[12],SSTL18_II,OUT,FAST,,
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34,K5,ddr2_addr[11],SSTL18_II,OUT,FAST,,
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34,R2,ddr2_addr[10],SSTL18_II,OUT,FAST,,
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34,N5,ddr2_addr[9],SSTL18_II,OUT,FAST,,
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34,L4,ddr2_addr[8],SSTL18_II,OUT,FAST,,
28+
34,N1,ddr2_addr[7],SSTL18_II,OUT,FAST,,
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34,M2,ddr2_addr[6],SSTL18_II,OUT,FAST,,
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34,P5,ddr2_addr[5],SSTL18_II,OUT,FAST,,
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34,L3,ddr2_addr[4],SSTL18_II,OUT,FAST,,
32+
34,T1,ddr2_addr[3],SSTL18_II,OUT,FAST,,
33+
34,M6,ddr2_addr[2],SSTL18_II,OUT,FAST,,
34+
34,P4,ddr2_addr[1],SSTL18_II,OUT,FAST,,
35+
34,M4,ddr2_addr[0],SSTL18_II,OUT,FAST,,
36+
34,R1,ddr2_ba[2],SSTL18_II,OUT,FAST,,
37+
34,P3,ddr2_ba[1],SSTL18_II,OUT,FAST,,
38+
34,P2,ddr2_ba[0],SSTL18_II,OUT,FAST,,
39+
34,N4,ddr2_ras_n,SSTL18_II,OUT,FAST,,
40+
34,L1,ddr2_cas_n,SSTL18_II,OUT,FAST,,
41+
34,N2,ddr2_we_n,SSTL18_II,OUT,FAST,,
42+
34,M1,ddr2_cke[0],SSTL18_II,OUT,FAST,,
43+
34,M3,ddr2_odt[0],SSTL18_II,OUT,FAST,,
44+
34,K6,ddr2_cs_n[0],SSTL18_II,OUT,FAST,,
45+
34,T6,ddr2_dm[0],SSTL18_II,OUT,FAST,,
46+
34,U1,ddr2_dm[1],SSTL18_II,OUT,FAST,,
47+
34,U9,ddr2_dqs_p[0],DIFF_SSTL18_II,INOUT,FAST,P,ddr2_dqs_n[0]
48+
34,V9,ddr2_dqs_n[0],DIFF_SSTL18_II,INOUT,FAST,N,ddr2_dqs_p[0]
49+
34,U2,ddr2_dqs_p[1],DIFF_SSTL18_II,INOUT,FAST,P,ddr2_dqs_n[1]
50+
34,V2,ddr2_dqs_n[1],DIFF_SSTL18_II,INOUT,FAST,N,ddr2_dqs_p[1]
51+
34,L6,ddr2_ck_p[0],DIFF_SSTL18_II,OUT,FAST,P,ddr2_ck_n[0]
52+
34,L5,ddr2_ck_n[0],DIFF_SSTL18_II,OUT,FAST,N,ddr2_ck_p[0]

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