diff --git a/.nojekyll b/.nojekyll new file mode 100644 index 000000000..e69de29bb diff --git a/Analyze/index.html b/Analyze/index.html new file mode 100644 index 000000000..58627b57c --- /dev/null +++ b/Analyze/index.html @@ -0,0 +1,276 @@ + + + + + + + Analyze — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

Analyze

+
    +

  1. Dependency analysis

    2. +
+
+

Dependency Analysis

+
+

1. Create Dependency Graph

+

Create unconnected vertices in the design’s dependency graph for every VHDL library object and every design unit.

+

The vertex’s ID field is set to a unique identifying string.
+The following patterns are used:

+
+
Libraries

The normalized library name: library.

+
+
Contexts

The normalized library and context name: library.context.

+
+
Entities

The normalized library and entity name: library.entity.

+
+
Architectures

The normalized library, entity and architecture name in parenthesis: library.entity(architecture).

+
+
Packages

The normalized library and package name: library.package.

+
+
Package Bodies

The normalized library and package name: library.package(body).

+
+
+

The vertex’s Value field references to the library or design unit object respectively.

+

Each vertex has two attributes:

+
+
"kind"

A kind attribute is set to an enumeration value of DependencyGraphVertexKind representing +vertex kind (type).

+
+
"predefined"

A predefined attribute is set to True, if the library or design unit is a VHDL predefined language entity from +e.g. from std or ieee.

+
+
+

Lastly, every vertex is assigned to a :py:attr:~pyVHDLModel.DesignUnit.DesignUnit._dependencyVertex field. Thus, +there is a double reference from graph’s vertex via Value to the DOM object as well as in reverse via +_dependencyVertex to the representing vertex.

+
predefinedLibraries = ("std", "ieee")
+
+for libraryIdentifier, library in self._libraries.items():
+  dependencyVertex = Vertex(vertexID=f"{libraryIdentifier}", value=library, graph=self._dependencyGraph)
+  dependencyVertex["kind"] = DependencyGraphVertexKind.Library
+  dependencyVertex["predefined"] = libraryIdentifier in predefinedLibraries
+  library._dependencyVertex = dependencyVertex
+
+  for contextIdentifier, context in library._contexts.items():
+    dependencyVertex = Vertex(vertexID=f"{libraryIdentifier}.{contextIdentifier}", value=context, graph=self._dependencyGraph)
+    dependencyVertex["kind"] = DependencyGraphVertexKind.Context
+    dependencyVertex["predefined"] = context._library._normalizedIdentifier in predefinedLibraries
+    context._dependencyVertex = dependencyVertex
+
+
+
+
+

2. Create Compile Order Graph

+
+
+

3. Index Packages

+
+
+

4. Index Architectures

+
+ + + + + + + + +
+

13. Create Hierarchy Graph

+
+
+

14. Compute Compile Order

+
+
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/ChangeLog/index.html b/ChangeLog/index.html new file mode 100644 index 000000000..a847f9f07 --- /dev/null +++ b/ChangeLog/index.html @@ -0,0 +1,178 @@ + + + + + + + ChangeLog — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

ChangeLog

+
+

Upcoming Release

+
    +

  • tbd

    • +
+
+
+

26.12.2020

+

pyVHDLModel was split from pyVHDLParser (v0.6.0) as an independent Python package.

+
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/DataStructure/CompileOrderGraph.html b/DataStructure/CompileOrderGraph.html new file mode 100644 index 000000000..7219dd14b --- /dev/null +++ b/DataStructure/CompileOrderGraph.html @@ -0,0 +1,178 @@ + + + + + + + Compile Order Graph — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

Compile Order Graph

+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/DataStructure/DependencyGraph.html b/DataStructure/DependencyGraph.html new file mode 100644 index 000000000..d855ce146 --- /dev/null +++ b/DataStructure/DependencyGraph.html @@ -0,0 +1,178 @@ + + + + + + + Dependency Graph — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

Dependency Graph

+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/DataStructure/HierarchyGraph.html b/DataStructure/HierarchyGraph.html new file mode 100644 index 000000000..28ac535c0 --- /dev/null +++ b/DataStructure/HierarchyGraph.html @@ -0,0 +1,178 @@ + + + + + + + Hierarchy Graph — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

Hierarchy Graph

+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/DataStructure/index.html b/DataStructure/index.html new file mode 100644 index 000000000..db3d7c1b5 --- /dev/null +++ b/DataStructure/index.html @@ -0,0 +1,232 @@ + + + + + + + Data Structures — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

Data Structures

+

Besides the document object model as a tree-like structure, pyVHDLModel has either lists, lookup dictionaries, direct +cross-references or dedicated data structure (tree, graph, …) for connecting multiple objects together.

+
+

Graphs

+

pyVHDLModel uses the graph implementation from :pyTool:mod:`pyTooling.Graph` as it provides an object oriented programming +interface to vertices and edges.

+
+

Dependency Graph

+

The dependency graph describes dependencies between:

+
    +

  • Sourcecode files

    • +

  • VHDL libraries

    • +

  • Contexts

    • +

  • Packages

    • +

  • Entities

    • +

  • Architectures

    • +

  • Packages

    • +

  • Package Bodies

    • +

  • Configurations

    • +
+

The relation can be:

+
    +

  • Defined in source file

    • +

  • references

    • +

  • implements

    • +

  • instantiates

    • +

  • needs to be analyzed before

    • +
+
+
+

Hierarchy Graph

+

The hierarchy graph can be derived from dependency graph by:

+
    +

  1. copying all entity and architecture vertices

    2. +

  2. copying all implements dependency edges

    3. +

  3. copying all instantiates edges in reverse direction

    4. +
+

The graph can then be scanned for a root vertices (no inbound edges). If only a single root vertex exists, this vertex +references the toplevel of the design.

+
+
+

Compile Order Graph

+

The compile order can be derived from dependency graph by:

+
    +

  1. copying all document vertices

    2. +

  2. iterating all edges in the dependency graph. +1. resolve the source and the destination to the referenced design units +2. resolved further to the documents these design units are declared in +3. resolve further which vertices correspond in the compile order graph +4. if edges does not yet exist, add an edge between two documents in the compile order graph

    3. +
+
+
+
+
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/Dependency.html b/Dependency.html new file mode 100644 index 000000000..6ff7a1901 --- /dev/null +++ b/Dependency.html @@ -0,0 +1,380 @@ + + + + + + + Dependency — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

Dependency

+ + + + + + + + + + + +

Libraries.io

Requires.io

Libraries.io status for latest release

Service was shutdown

+
+

pyVHDLModel Package

+ + + + + + + + + + + + + + + +

Package

Version

License

Dependencies

pyTooling

≥6.6

Apache License, 2.0

None

+
+
+

Unit Testing / Coverage / Type Checking (Optional)

+

Additional Python packages needed for testing, code coverage collection and static type checking. These packages are +only needed for developers or on a CI server, thus sub-dependencies are not evaluated further.

+

Manually Installing Test Requirements

+

Use the tests/requirements.txt file to install all dependencies via pip3. The file will recursively install +the mandatory dependencies too.

+
pip3 install -U -r tests/requirements.txt
+
+
+

Dependency List

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Package

Version

License

Dependencies

pytest

≥8.3

MIT

Not yet evaluated.

pytest-cov

≥5.0

MIT

Not yet evaluated.

Coverage

≥7.6

Apache License, 2.0

Not yet evaluated.

mypy

≥1.11

MIT

Not yet evaluated.

typing-extensions

≥4.12

PSF-2.0

Not yet evaluated.

lxml

≥5.3

BSD 3-Clause

Not yet evaluated.

+
+
+

Sphinx Documentation (Optional)

+

Additional Python packages needed for documentation generation. These packages are only needed for developers or on a +CI server, thus sub-dependencies are not evaluated further.

+

Manually Installing Documentation Requirements

+

Use the doc/requirements.txt file to install all dependencies via pip3. The file will recursively install +the mandatory dependencies too.

+
pip3 install -U -r doc/requirements.txt
+
+
+

Dependency List

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Package

Version

License

Dependencies

pyTooling

≥6.6

Apache License, 2.0

None

Sphinx

≥7.4

BSD 3-Clause

Not yet evaluated.

sphinxcontrib-mermaid

≥0.9.2

BSD

Not yet evaluated.

autoapi

≥2.0.1

Apache License, 2.0

Not yet evaluated.

sphinx_btd_theme

MIT

Not yet evaluated.

!! sphinx_fontawesome

≥0.0.6

GPL 2.0

Not yet evaluated.

sphinx_autodoc_typehints

≥2.3

MIT

Not yet evaluated.

+
+
+

Packaging (Optional)

+

Additional Python packages needed for installation package generation. These packages are only needed for developers or +on a CI server, thus sub-dependencies are not evaluated further.

+

Manually Installing Packaging Requirements

+

Use the build/requirements.txt file to install all dependencies via pip3. The file will recursively +install the mandatory dependencies too.

+
pip3 install -U -r build/requirements.txt
+
+
+

Dependency List

+ + + + + + + + + + + + + + + + + + + + +

Package

Version

License

Dependencies

pyTooling

≥6.6

Apache License, 2.0

None

wheel

≥0.44

MIT

Not yet evaluated.

+
+
+

Publishing (CI-Server only)

+

Additional Python packages needed for publishing the generated installation package to e.g, PyPI or any equivalent +services. These packages are only needed for maintainers or on a CI server, thus sub-dependencies are not evaluated +further.

+

Manually Installing Publishing Requirements

+

Use the dist/requirements.txt file to install all dependencies via pip3. The file will recursively +install the mandatory dependencies too.

+
pip3 install -U -r dist/requirements.txt
+
+
+

Dependency List

+ + + + + + + + + + + + + + + + + + + + +

Package

Version

License

Dependencies

wheel

≥0.44

MIT

Not yet evaluated.

Twine

≥5.1

Apache License, 2.0

Not yet evaluated.

+
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/Doc-License.html b/Doc-License.html new file mode 100644 index 000000000..b4629ff84 --- /dev/null +++ b/Doc-License.html @@ -0,0 +1,508 @@ + + + + + + + Creative Commons Attribution 4.0 International — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ + +
+

Attention

+

This CC BY 4.0 license applies only to the documentation of this project.

+
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Creative Commons Attribution 4.0 International

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+
+
+ + + + \ No newline at end of file diff --git a/DocCoverage.html b/DocCoverage.html new file mode 100644 index 000000000..43f3fa716 --- /dev/null +++ b/DocCoverage.html @@ -0,0 +1,348 @@ + + + + + + + Documentation Coverage — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

Documentation Coverage

+

Documentation coverage generated by docstr-coverage.

+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Filename

Total

Covered

Missing

Coverage in %

📦pyVHDLModel

108

89

19

82.4%

   Association

9

5

4

55.6%

   Base

54

36

18

66.7%

   Common

14

5

9

35.7%

   Concurrent

91

18

73

19.8%

   Declaration

13

5

8

38.5%

   DesignUnit

68

26

42

38.2%

   Exception

41

23

18

56.1%

   Expression

153

13

140

8.5%

   IEEE

43

26

17

60.5%

   Instantiation

13

1

12

7.7%

   Interface

31

6

25

19.4%

   Name

31

11

20

35.5%

   Namespace

10

1

9

10.0%

   Object

21

11

10

52.4%

   PSLModel

11

1

10

9.1%

   Predefined

11

5

6

45.5%

   Regions

14

2

12

14.3%

   STD

11

8

3

72.7%

   Sequential

79

12

67

15.2%

   Subprogram

20

2

18

10.0%

   Symbol

57

14

43

24.6%

   Type

64

8

56

12.5%

Overall (23 files):

967

328

639

33.9%

+

Legend

+ + + + + + + + + + + + + + + + + + + + + + + +

%

Coverage Level

≤30%

almost undocumented

≤50%

poorly documented

≤80%

roughly documented

≤90%

well documented

≤100%

excellent documented

+
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/GettingStarted.html b/GettingStarted.html new file mode 100644 index 000000000..1aa8d9974 --- /dev/null +++ b/GettingStarted.html @@ -0,0 +1,407 @@ + + + + + + + Getting Started — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

Getting Started

+

pyVHDLModel is a VHDL language model without any parser. There are currently two parsers available that can serve as a +frontend to pyVHDLModel. These parsers can generate a VHDL language model instance from VHDL source files:

+
    +

  • pyVHDLParser (currently broken)

    • +

  • GHDL

    • +
+
+

pyVHDLParser

+

The pyVHDLParser is a token-stream based parser creating a code document object model (CodeDOM) derived from +pyVHDLModel. Actually, pyVHDlModel was originally part of that parser, until it got refactored into this standalone +package so multiple frontends (parsers) and backends (analysis tools) can use this VHDL language model as a common API.

+
+

Warning

+

Currently, pyVHDLParser is not aligned with latest updates in pyVHDLModel.

+
+
+
+

GHDL as Parser

+

The free and open-source VHDL-2008 simulator GHDL offers a Python binding, so Python code can access libghdl. +This binding layer is exposed in the pyGHDL.libghdl package. In addition, GHDL offers a pyGHDL.dom package +implementing derived classes of pyVHDLModel. Each derived class adds translation methods (.parse(iirNode)) from +GHDL’s internal data structure IIR to the code document object model (CodeDOM) of pyVHDLModel.

+
+

Installation and Setup

+

To use pyVHDLModel a tool offering a parser like GHDL is required. GHDL itself offers multiple options for installation. +In addition it has multiple backends. For the usage with pyVHDLModel, an mcode backend is preferred, as it’s faster +and doesn’t write *.o files to the disk. As most Python installation are nowadays 64-bit, an mcode 64-bit +variant of GHDL would be best.

+
+

On Windows - Native

+

Assuming a 64-bit Windows installation and a 64-bit CPython (python.org) +installation, it’s suggested to install:

+ +

As development of Python packages pyGHDL.dom and pyVHDLModel are under quick development cycles, a GHDL +nightly build is suggested compared to the stable releases (once a year). These nightly builds are provided as ZIP +files on GitHub: https://github.com/ghdl/ghdl/releases/tag/nightly (or use links from above).

+

At next, unpack the ZIP files content to e.g. C:\Tools\GHDL\3.0.0-dev (GHDL installation directory). This ZIP +file brings the GHDL synthesis and simulation tool as well as libghdl-3_0_0_dev.dll needed as a parser frontend.

+
+
+

On Windows - MSYS2

+

Assuming a 64-bit Windows installation and an MSYS2 installation in C:msys64.

+

MSYS2 Prepartions and GHDL/libghdl Installation

+

Start either the MinGW64 or UCRT64 environment and then use pacman to install GHDL. The following steps are +explained for UCRT64, but can be applied to MinGW64 similarly.

+
+

Bash

+
# Update MSYS2 to latest package releases
+pacman -Suyy
+
+# If the core system was updated, a second run might be required.
+pacman -Suyy
+
+# Search for available GHDL packages
+pacman -Ss ghdl
+# mingw32/mingw-w64-i686-ghdl-mcode 2.0.0.r870.g1cc85c578-1 (mingw-w64-i686-eda) [Installiert]
+#     GHDL: the open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL (mcode backend) (mingw-w64)
+# mingw64/mingw-w64-x86_64-ghdl-llvm 2.0.0.r870.g1cc85c578-1 (mingw-w64-x86_64-eda) [Installiert]
+#     GHDL: the open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL (LLVM backend) (mingw-w64)
+# ucrt64/mingw-w64-ucrt-x86_64-ghdl-llvm 2.0.0.r870.g1cc85c578-1 (mingw-w64-ucrt-x86_64-eda) [Installiert]
+#     GHDL: the open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL (LLVM backend) (mingw-w64)
+
+# Note: The GHDL version is 870 commits after 2.0.0 release and has Git hash "1cc85c578" (without prefix 'g')
+
+# Install GHDL for UCRT64
+pacman -S ucrt64/mingw-w64-ucrt-x86_64-ghdl-llvm
+
+
+
+

Installing pyGHDL

+

At next, pyGHDL matching the currently installed GHDL version must be installed. At best, pyGHDL matches the exact Git +hash of GHDL, so there is no discrepancy between the libghdl binary and the DLL binding layer in pyGHDL.libghdl.

+

Assuming Git for Windows is installed and available in PowerShell, the following command will install pyGHDL via PIP:

+
+

PowerShell

+
# Install pyGHDL
+pip install git+https://github.com/ghdl/ghdl.git@$(ghdl version hash).
+
+
+
+
+
+

On Windows from Sources

+

Assuming a 64-bit Windows installation, a 64-bit CPython (python.org) +installation as well as an MSYS2 installation in C:msys64.

+

MSYS2 Prepartions

+

Start either the MinGW64 or UCRT64 environment and then use pacman to install build dependencies. The +following steps are explained for UCRT64, but can be applied to MinGW64 similarly.

+
+

Bash

+
# Update MSYS2 to latest package releases
+pacman -Suyy
+
+# If the core system was updated, a second run might be required.
+pacman -Suyy
+
+# Install system dependencies
+pacman -S git
+pacman -S make
+pacman -S diffutils
+
+# Install GHDL build dependencies (GCC with Ada support)
+pacman -S ucrt64/mingw-w64-ucrt-x86_64-gcc-ada
+
+
+
+

Building GHDL and libghdl

+

The next steps will clone GHDL from GitHub, configure the software, build the binaries, run the testsuite and install +all needed result files into the installation directory.

+
+

Bash

+
# Clone GHDL repository
+mkdir -p /c/Tools/GHDL
+cd /c/Tools/GHDL
+git clone https://github.com/ghdl/ghdl.git sources
+
+# Create build directory and configure GHDL
+mkdir -p sources/build
+cd sources/build
+../configure --prefix=/c/Tools/GHDL/3.0.0-dev
+
+# Build GHDL, run testsuite and install to ``prefix``
+make
+make install
+
+
+
+

The directory structure will look like this:

+
├── Tools
+│   ├── GHDL
+│   │   ├── 3.0.0-dev
+│   │   │   ├── bin
+│   │   │   ├── include
+│   │   │   ├── lib
+│   │   │   │   ├── ghdl
+│   │   ├── sources
+│   │   │   ├── ...
+│   │   │   ├── pyGHDL
+│   │   │   ├── src
+│   │   │   ├── ...
+
+
+

In the next steps, some files from MSYS2/UCRT64 need to be copied into the installation directory, so +libghdl-3_0_0_dev.dll can be used independently from MSYS2 environments.

+

Installing pyGHDL

+

As a final setup step, pyGHDL needs to be installed via PIP by executing some commands in PowerShell. The dependencies +of pyGHDL will take care of installing all necessary requirements like pyVHDLModel.

+
+

PowerShell

+
cd C:\Tools\GHDL\sources
+pip install .
+
+
+
+

Updating GHDL and libghdl

+

If GHDL gets updated through new commits, start the UCRT64 console and execute these instructions to build a latest +libghdl-3_0_0_dev.dll:

+
+

Bash

+
# Update Git reository
+cd /c/Tools/GHDL/sources/build
+git pull
+
+# Recompile GHDL
+make
+
+# Overwrite file in installation directory
+make install
+
+
+
+

Updating pyGHDL

+

TBD

+
+
+

On Linux

+
+

Todo

+

Write how to get started on Linux with libghdl.

+
+
+
+

On Mac

+
+

Todo

+

Write how to get started on Mac with libghdl.

+
+
+
+
+

Using libghdl with Python

+

An environment variable GHDL_PREFIX=C:\Tools\GHDL\3.0.0-dev\lib\ghdl is needed for libghdl. The path is +constructed from installation path plus lib\\ghdl.

+
+

GettingStarted.py

+
from pathlib import Path
+from pyGHDL.dom.NonStandard import Design, Document
+
+fileList = (
+  ("libStopWatch", Path("Counter.vhdl")),  # a list of 2-element tuples; library name and pat to the VHDL file
+  ...                                      # just for this example to simply loop all files
+)
+
+design = Design()
+design.LoadDefaultLibraries()    # loads std.* and ieee.* (dummies for now to calculate dependencies)
+for libName, file in fileList:
+  library = design.GetLibrary(libName)
+  document = Document(file)
+  design.AddDocument(document, library)
+
+# Analyzing dependencies and computing graphs
+design.Analyze()
+
+# Accessing the TopLevel
+design.TopLevel
+
+# Accessing graphs
+design.DependencyGraph
+design.HierarchyGraph
+design.CompileOrderGraph
+
+
+
+
+
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/Glossary.html b/Glossary.html new file mode 100644 index 000000000..668368f6b --- /dev/null +++ b/Glossary.html @@ -0,0 +1,175 @@ + + + + + + + Glossary — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

Glossary

+
+
LRM

IEEE Standard for VHDL Language Reference Manual

+ +

See VHDL Standards for further details.

+
+
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/Installation.html b/Installation.html new file mode 100644 index 000000000..619d3a631 --- /dev/null +++ b/Installation.html @@ -0,0 +1,372 @@ + + + + + + + Installation/Updates — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

Installation/Updates

+
+

Using PIP to Install from PyPI

+

The following instruction are using PIP (Package Installer for Python) as a package manager and PyPI (Python Package +Index) as a source of Python packages.

+
+

Installing a Wheel Package from PyPI using PIP

+

Users of pyTooling can select if the want to install a basic variant of pyTooling. See Dependencies for more +details.

+
+ +
+
# Basic sphinx-reports package
+pip3 install pyVHDLModel
+
+
+
+ +
+
# Basic sphinx-reports package
+pip install pyVHDLModel
+
+
+
+
+

Developers can install further dependencies for documentation generation (doc) or running unit tests (test) or +just all (all) dependencies.

+
+ +
+
+ +
+
+
# Install with dependencies to generate documentation
+pip3 install pyVHDLModel[doc]
+
+
+
+
+ +
+
+
# Install with dependencies to run unit tests
+pip3 install pyVHDLModel[test]
+
+
+
+
+ +
+
+
# Install with all developer dependencies
+pip install pyVHDLModel[all]
+
+
+
+
+
+
+ +
+
+ +
+
+
# Install with dependencies to generate documentation
+pip install pyVHDLModel[doc]
+
+
+
+
+ +
+
+
# Install with dependencies to run unit tests
+pip install pyVHDLModel[test]
+
+
+
+
+ +
+
+
# Install with all developer dependencies
+pip install pyVHDLModel[all]
+
+
+
+
+
+
+
+
+
+

Updating from PyPI using PIP

+
+ +
+
pip install -U pyVHDLModel
+
+
+
+ +
+
pip3 install -U pyVHDLModel
+
+
+
+
+
+
+

Uninstallation using PIP

+
+ +
+
pip uninstall pyVHDLModel
+
+
+
+ +
+
pip3 uninstall pyVHDLModel
+
+
+
+
+
+
+
+

Using setup.py (legacy)

+

See sections above on how to use PIP.

+
+

Installation using setup.py

+
setup.py install
+
+
+
+
+
+

Local Packaging and Installation via PIP

+

For development and bug fixing it might be handy to create a local wheel package and also install it locally on the +development machine. The following instructions will create a local wheel package (*.whl) and then use PIP to +install it. As a user might have a sphinx-reports installation from PyPI, it’s recommended to uninstall any previous +sphinx-reports packages. (This step is also needed if installing an updated local wheel file with same version number. PIP +will not detect a new version and thus not overwrite/reinstall the updated package contents.)

+

Ensure packaging requirements are installed.

+
+ +
+
cd <sphinx-reports>
+
+# Package the code in a wheel (*.whl)
+python -m build --wheel
+
+# Uninstall the old package
+python -m pip uninstall -y pyVHDLModel
+
+# Install from wheel
+python -m pip install ./dist/pyVHDLModel-0.28.0-py3-none-any.whl
+
+
+
+ +
+
cd <sphinx-reports>
+
+# Package the code in a wheel (*.whl)
+py -m build --wheel
+
+# Uninstall the old package
+py -m pip uninstall -y pyVHDLModel
+
+# Install from wheel
+py -m pip install .\dist\pyVHDLModel-0.28.0-py3-none-any.whl
+
+
+
+
+
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/LanguageModel/ConcurrentStatements.html b/LanguageModel/ConcurrentStatements.html new file mode 100644 index 000000000..27ce218a2 --- /dev/null +++ b/LanguageModel/ConcurrentStatements.html @@ -0,0 +1,454 @@ + + + + + + + Concurrent Statements — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

Concurrent Statements

+ +

Class Hierarchy

+
+

Assert Statement

+
+

Todo

+

Write documentation.

+
+

Condensed definition of class ConcurrentSignalAssignment:

+
@export
+class ConcurrentAssertStatement(ConcurrentStatement, MixinAssertStatement):
+  # inherited from ModelEntity
+  @property
+  def Parent(self) -> ModelEntity:
+
+  # inherited from LabeledEntity
+  @property
+  def Label(self) -> str:
+
+  # inherited from MixinReportStatement
+  @property
+  def Message(self) -> BaseExpression:
+
+  @property
+  def Severity(self) -> BaseExpression:
+
+  # inherited from MixinAssertStatement
+  @property
+  def Condition(self) -> BaseExpression:
+
+
+
+
+

Signal Assignment

+
+

Todo

+

Write documentation.

+
+

Condensed definition of class ConcurrentSignalAssignment:

+
@export
+class ConcurrentSignalAssignment(ConcurrentStatement, SignalAssignment):
+  # inherited from ModelEntity
+  @property
+  def Parent(self) -> ModelEntity:
+
+  # inherited from LabeledEntity
+  @property
+  def Label(self) -> str:
+
+  # inherited from Assignment
+  @property
+  def Target(self) -> Object:
+
+  @property
+  def BaseExpression(self) -> BaseExpression:
+
+
+
+
+

Concurrent Block Statement

+
+

Todo

+

Write documentation.

+
+

Condensed definition of class ConcurrentBlockStatement:

+
@export
+class ConcurrentBlockStatement(ConcurrentStatement, BlockStatement, ConcurrentDeclarations, ConcurrentStatements):
+  # inherited from ModelEntity
+  @property
+  def Parent(self) -> ModelEntity:
+
+  # inherited from LabeledEntity
+  @property
+  def Label(self) -> str:
+
+  # inherited from ConcurrentDeclarations
+  @property
+  def DeclaredItems(self) -> List:
+
+  # inherited from ConcurrentStatements
+  @property
+  def Statements(self) -> List[ConcurrentStatement]:
+
+  # from ConcurrentBlockStatement
+  @property
+  def PortItems(self) -> List[PortInterfaceItem]:
+
+
+
+
+

Instantiations

+
+

Todo

+

Write documentation.

+
+
+

Entity Instantiation

+
+
+

Component Instantiation

+
+
+

Configuration Instantiation

+
+
+
+

Generate Statements

+
+

If Generate

+
+

Todo

+

Write documentation.

+
+

Condensed definition of class IfGenerateStatement:

+
@export
+class IfGenerateStatement(GenerateStatement):
+  # inherited from ModelEntity
+  @property
+  def Parent(self) -> ModelEntity:
+
+  # inherited from LabeledEntity
+  @property
+  def Label(self) -> str:
+
+  # from IfGenerateStatement
+  @property
+  def IfBranch(self) -> IfGenerateBranch:
+
+  @property
+  def ElsifBranches(self) -> List[ElsifGenerateBranch]:
+
+  @property
+  def ElseBranch(self) -> ElseGenerateBranch:
+
+
+
+
+

Case Generate

+
+

Todo

+

Write documentation.

+
+

Condensed definition of class CaseGenerateStatement:

+
@export
+class CaseGenerateStatement(GenerateStatement):
+  # inherited from ModelEntity
+  @property
+  def Parent(self) -> ModelEntity:
+
+  # inherited from LabeledEntity
+  @property
+  def Label(self) -> str:
+
+  # from CaseGenerateStatement
+  @property
+  def SelectExpression(self) -> BaseExpression:
+
+  @property
+  def Cases(self) -> List[GenerateCase]:
+
+
+
+
+

For Generate

+
+

Todo

+

Write documentation.

+
+

Condensed definition of class ForGenerateStatement:

+
@export
+class ForGenerateStatement(GenerateStatement):
+  # inherited from ModelEntity
+  @property
+  def Parent(self) -> ModelEntity:
+
+  # inherited from LabeledEntity
+  @property
+  def Label(self) -> str:
+
+  # inherited from ConcurrentDeclarations
+  @property
+  def DeclaredItems(self) -> List:
+
+  # inherited from ConcurrentStatements
+  @property
+  def Statements(self) -> List[ConcurrentStatement]:
+
+  # from ForGenerateStatement
+  @property
+  def LoopIndex(self) -> Constant:
+
+  @property
+  def Range(self) -> Range:
+
+
+
+
+
+

Procedure Call

+
+

Todo

+

Write documentation.

+
+
+
+

Process

+
+

Todo

+

Write documentation.

+
+

Condensed definition of class ForGenerateStatement:

+
class ProcessStatement(ConcurrentStatement, SequentialDeclarations, SequentialStatements):
+  # inherited from ModelEntity
+  @property
+  def Parent(self) -> ModelEntity:
+
+  # inherited from LabeledEntity
+  @property
+  def Label(self) -> str:
+
+  # inherited from SequentialDeclarations
+  @property
+  def DeclaredItems(self) -> List:
+
+  # inherited from SequentialStatements
+  @property
+  def Statements(self) -> List[SequentialStatement]:
+
+  # from ProcessStatement
+  @property
+  def SensitivityList(self) -> List[Signal]:
+
+
+
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/LanguageModel/DesignUnits.html b/LanguageModel/DesignUnits.html new file mode 100644 index 000000000..4001795fc --- /dev/null +++ b/LanguageModel/DesignUnits.html @@ -0,0 +1,388 @@ + + + + + + + Design Units — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

Design Units

+

A VHDL design (see Design) is assembled from design units. VHDL distinguishes +between primary and secondary design units.

+ +

Class Hierarchy

+
+

Primary Units

+
+

Context

+
+

Todo

+

Write documentation.

+
+
+
+

Configuration

+
+

Todo

+

Write documentation.

+
+
+
+

Entity

+

An Entity represents a VHDL entity declaration. Libraries and package +references declared ahead an entity are consumed by that entity and made +available as lists. An entities also provides lists of generic and port items. +The list of declared items (e.g. objects) also contains defined items (e.g. +types). An entity’s list of statements is called body items.

+

Condensed definition of class Entity:

+
@export
+class Entity(PrimaryUnit, MixinDesignUnitWithContext):
+  # inherited from ModelEntity
+  @property
+  def Parent(self) -> ModelEntity:
+
+  # inherited from NamedEntity
+  @property
+  def Name(self) -> str:
+
+  # inherited from MixinDesignUnitWithContext
+  @property
+  def LibraryReferences(self) -> List[LibraryClause]:
+
+  @property
+  def PackageReferences(self) -> List[UseClause]:
+
+  @property
+  def ContextReferences(self) -> List[Context]:
+
+  # from Entity
+  @property
+  def GenericItems(self) -> List[GenericInterfaceItem]:
+
+  @property
+  def PortItems(self) -> List[PortInterfaceItem]:
+
+  @property
+  def DeclaredItems(self) -> List:
+
+  @property
+  def BodyItems(self) -> List[ConcurrentStatement]:
+
+
+
+
+

Package

+
+

Todo

+

Write documentation.

+
+

Condensed definition of class Package:

+
@export
+class Package(PrimaryUnit, MixinDesignUnitWithContext):
+  # inherited from ModelEntity
+  @property
+  def Parent(self) -> ModelEntity:
+
+  # inherited from NamedEntity
+  @property
+  def Name(self) -> str:
+
+  # inherited from MixinDesignUnitWithContext
+  @property
+  def LibraryReferences(self) -> List[LibraryClause]:
+
+  @property
+  def PackageReferences(self) -> List[UseClause]:
+
+  @property
+  def ContextReferences(self) -> List[Context]:
+
+  # from Package
+  @property
+  def GenericItems(self) -> List[GenericInterfaceItem]:
+
+  @property
+  def DeclaredItems(self) -> List:
+
+
+
+
+
+

Secondary Units

+
+

Architeture

+
+

Todo

+

Write documentation.

+
+

Condensed definition of class Architecture:

+
@export
+class Architecture(SecondaryUnit, MixinDesignUnitWithContext):
+  # inherited from ModelEntity
+  @property
+  def Parent(self) -> ModelEntity:
+
+  # inherited from NamedEntity
+  @property
+  def Name(self) -> str:
+
+  # inherited from MixinDesignUnitWithContext
+  @property
+  def LibraryReferences(self) -> List[LibraryClause]:
+
+  @property
+  def PackageReferences(self) -> List[UseClause]:
+
+  @property
+  def ContextReferences(self) -> List[Context]:
+
+  # from Architecture
+  @property
+  def Entity(self) -> Entity:
+
+  @property
+  def DeclaredItems(self) -> List:
+
+  @property
+  def BodyItems(self) -> List[ConcurrentStatement]:
+
+
+
+
+

Package Body

+
+

Todo

+

Write documentation.

+
+

Condensed definition of class PackageBody:

+
@export
+class PackageBody(SecondaryUnit, MixinDesignUnitWithContext):
+  # inherited from ModelEntity
+  @property
+  def Parent(self) -> ModelEntity:
+
+  # inherited from NamedEntity
+  @property
+  def Name(self) -> str:
+
+  # inherited from MixinDesignUnitWithContext
+  @property
+  def LibraryReferences(self) -> List[LibraryClause]:
+
+  @property
+  def PackageReferences(self) -> List[UseClause]:
+
+  @property
+  def ContextReferences(self) -> List[Context]:
+
+  # from Package Body
+  @property
+  def Package(self) -> Package:
+
+  @property
+  def DeclaredItems(self) -> List:
+
+
+
+
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/LanguageModel/Enumerations.html b/LanguageModel/Enumerations.html new file mode 100644 index 000000000..561ac7267 --- /dev/null +++ b/LanguageModel/Enumerations.html @@ -0,0 +1,239 @@ + + + + + + + Enumerations — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

Enumerations

+

The language model contains some enumerations to express a kind of a models +entity. These are not enumerated types defined by VHDL itself, like boolean.

+ +
+

Direction

+

Ranges and slices have an ascending (To) or descending (DownTo) direction.

+

Condensed definition of class Direction:

+
@export
+class Direction(Enum):
+  To =      0
+  DownTo =  1
+
+
+
+
+

Mode

+

A mode describes the direction of data exchange e.g. for entity ports or subprogram parameters. +In addition to the modes defined by VHDL (In, Out, InOut, Buffer and Linkage), Default +is a placeholder for omitted modes. The mode is then determined from the context.

+

Condensed definition of class Mode:

+
@export
+class Mode(Enum):
+  Default = 0
+  In =      1
+  Out =     2
+  InOut =   3
+  Buffer =  4
+  Linkage = 5
+
+
+
+
+

Object ObjectClass

+

In addition to the 4 object classes defined by VHDL (Constant, Variable, +Signal and File), Default is used when no object class is defined. In +such a case, the object class is determined from the context.

+

Condensed definition of class ObjectClass:

+
@export
+class ObjectClass(Enum):
+  Default =    0
+  Constant =   1
+  Variable =   2
+  Signal =     3
+  File =       4
+  Type =       5
+  Subprogram = 6
+
+
+
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/LanguageModel/Expressions.html b/LanguageModel/Expressions.html new file mode 100644 index 000000000..b6a63fda0 --- /dev/null +++ b/LanguageModel/Expressions.html @@ -0,0 +1,331 @@ + + + + + + + Literals and Expressions — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

Literals and Expressions

+ +

Class Hierarchy

+
+

Literals

+
+

Enumeration Literal

+
+

Todo

+

Write documentation.

+
+
+
+

Integer Literal

+
+

Todo

+

Write documentation.

+
+
+
+

Floating Point Literal

+
+

Todo

+

Write documentation.

+
+
+
+

Physical Literal

+
+

Todo

+

Write documentation.

+
+
+
+
+

Expressions

+

Class Hierarchy

+
+

Todo

+

Write documentation.

+
+
+

Unary Expressions

+

Class Hierarchy

+
+

Todo

+

Write documentation.

+
+
+
+

Binary Expressions

+

Class Hierarchy

+
+

Todo

+

Write documentation.

+
+
+

Adding Expressions

+

Class Hierarchy

+
+

Todo

+

Write documentation.

+
+
+
+

Multiplying Expressions

+

Class Hierarchy

+
+

Todo

+

Write documentation.

+
+
+
+

Logical Expressions

+

Class Hierarchy

+
+

Todo

+

Write documentation.

+
+
+
+

Relational Expressions

+

Class Hierarchy

+
+

Todo

+

Write documentation.

+
+
+
+

Shifting Expressions

+

Class Hierarchy

+
+

Todo

+

Write documentation.

+
+
+
+
+

Ternary Expressions

+
+

Todo

+

Write documentation.

+
+
+
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/LanguageModel/InterfaceItems.html b/LanguageModel/InterfaceItems.html new file mode 100644 index 000000000..447a55e8b --- /dev/null +++ b/LanguageModel/InterfaceItems.html @@ -0,0 +1,452 @@ + + + + + + + Interface Items — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

Interface Items

+

Interface items are used in generic, port and parameter declarations.

+ +

Class Hierarchy

+
+

Generic Interface Items

+
+

GenericConstantInterfaceItem

+
+

Todo

+

Write documentation.

+
+

Condensed definition of class GenericConstantInterfaceItem:

+
@export
+class GenericConstantInterfaceItem(Constant, GenericInterfaceItem):
+  # inherited from ModelEntity
+  @property
+  def Parent(self) -> ModelEntity:
+
+  # inherited from NamedEntity
+  @property
+  def Name(self) -> str:
+
+  # inherited from Object
+  @property
+  def Subtype(self) -> Subtype:
+
+  # inherited from WithDefaultExpressionMixin
+  @property
+  def DefaultExpression(self) -> BaseExpression:
+
+  # inherited from InterfaceItem
+  @property
+  def Mode(self) -> Mode:
+
+
+
+
+

GenericTypeInterfaceItem

+
+

Todo

+

Write documentation.

+
+

Condensed definition of class GenericTypeInterfaceItem:

+
@Export
+class GenericTypeInterfaceItem(GenericInterfaceItem):
+
+
+
+
+

GenericProcedureInterfaceItem

+
+

Todo

+

Write documentation.

+
+

Condensed definition of class GenericProcedureInterfaceItem:

+
@Export
+class GenericProcedureInterfaceItem(GenericSubprogramInterfaceItem):
+
+
+
+
+

GenericFunctionInterfaceItem

+
+

Todo

+

Write documentation.

+
+

Condensed definition of class GenericFunctionInterfaceItem:

+
@Export
+class GenericFunctionInterfaceItem(GenericSubprogramInterfaceItem):
+
+
+
+
+

GenericPackageInterfaceItem

+
+

Todo

+

Write documentation.

+
+

Condensed definition of class GenericPackageInterfaceItem:

+
@Export
+class GenericPackageInterfaceItem(GenericInterfaceItem):
+
+
+
+
+
+

Port Interface Item

+
+

PortSignalInterfaceItem

+
+

Todo

+

Write documentation.

+
+

Condensed definition of class PortSignalInterfaceItem:

+
@export
+class PortSignalInterfaceItem(Signal, PortInterfaceItem):
+  # inherited from ModelEntity
+  @property
+  def Parent(self) -> ModelEntity:
+
+  # inherited from NamedEntity
+  @property
+  def Name(self) -> str:
+
+  # inherited from Object
+  @property
+  def Subtype(self) -> Subtype:
+
+  # inherited from WithDefaultExpressionMixin
+  @property
+  def DefaultExpression(self) -> BaseExpression:
+
+  # inherited from InterfaceItem
+  @property
+  def Mode(self) -> Mode:
+
+
+
+
+
+

Parameter Interface Item

+
+

ParameterConstantInterfaceItem

+
+

Todo

+

Write documentation.

+
+

Condensed definition of class ParameterConstantInterfaceItem:

+
@export
+class ParameterConstantInterfaceItem(Constant, ParameterInterfaceItem):
+  # inherited from ModelEntity
+  @property
+  def Parent(self) -> ModelEntity:
+
+  # inherited from NamedEntity
+  @property
+  def Name(self) -> str:
+
+  # inherited from Object
+  @property
+  def Subtype(self) -> Subtype:
+
+  # inherited from WithDefaultExpressionMixin
+  @property
+  def DefaultExpression(self) -> BaseExpression:
+
+  # inherited from InterfaceItem
+  @property
+  def Mode(self) -> Mode:
+
+
+
+
+

ParameterVariableInterfaceItem

+
+

Todo

+

Write documentation.

+
+

Condensed definition of class ParameterVariableInterfaceItem:

+
@export
+class ParameterVariableInterfaceItem(Variable, ParameterInterfaceItem):
+  # inherited from ModelEntity
+  @property
+  def Parent(self) -> ModelEntity:
+
+  # inherited from NamedEntity
+  @property
+  def Name(self) -> str:
+
+  # inherited from Object
+  @property
+  def Subtype(self) -> Subtype:
+
+  # inherited from WithDefaultExpressionMixin
+  @property
+  def DefaultExpression(self) -> BaseExpression:
+
+  # inherited from InterfaceItem
+  @property
+  def Mode(self) -> Mode:
+
+
+
+
+

ParameterSignalInterfaceItem

+
+

Todo

+

Write documentation.

+
+

Condensed definition of class ParameterSignalInterfaceItem:

+
@export
+class ParameterSignalInterfaceItem(Signal, ParameterInterfaceItem):
+  # inherited from ModelEntity
+  @property
+  def Parent(self) -> ModelEntity:
+
+  # inherited from NamedEntity
+  @property
+  def Name(self) -> str:
+
+  # inherited from Object
+  @property
+  def Subtype(self) -> Subtype:
+
+  # inherited from WithDefaultExpressionMixin
+  @property
+  def DefaultExpression(self) -> BaseExpression:
+
+  # inherited from InterfaceItem
+  @property
+  def Mode(self) -> Mode:
+
+
+
+
+

ParameterFileInterfaceItem

+
+

Todo

+

Write documentation.

+
+

Condensed definition of class ParameterFileInterfaceItem:

+
@Export
+class ParameterFileInterfaceItem(ParameterInterfaceItem):
+
+
+
+
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/LanguageModel/Miscellaneous.html b/LanguageModel/Miscellaneous.html new file mode 100644 index 000000000..40433834f --- /dev/null +++ b/LanguageModel/Miscellaneous.html @@ -0,0 +1,290 @@ + + + + + + + Concepts not defined by VHDL — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

Concepts not defined by VHDL

+

Some features required for a holistic language model are not defined in the VHDL +LRM (IEEE Std. 1076). Other features are made explicitly implementation +specific to the implementer. This chapter will cover these parts.

+ +
+

Design

+

The root element in the language model is a design made out of multiple +sourcecode files (documents). Sourcecode files are compiled into libraries. Thus +a design has the two child nodes: Libraries +and Documents. Each is a list.

+

Condensed definition of class Design:

+
@export
+class Design(ModelEntity):
+  # inherited from ModelEntity
+  @property
+  def Parent(self) -> ModelEntity:
+
+  # from Design
+  @property
+  def Libraries(self) -> Dict[str, Library]:
+
+  @property
+  def Documents(self) -> List[Document]:
+
+  def GetLibrary(self, libraryName: str) -> Library:
+
+  def AddDocument(self, document: Document, library: Library):
+
+
+
+
+

Library

+

A library contains multiple design units. Each design unit listed in a library +is a primary design unit like: Configuration, +Entity, Package or +Context.

+

Condensed definition of class Library:

+
@export
+class Library(ModelEntity):
+  # inherited from ModelEntity
+  @property
+  def Parent(self) -> ModelEntity:
+
+  # from Library
+  @property
+  def Contexts(self) -> List[Context]:
+
+  @property
+  def Configurations(self) -> List[Configuration]:
+
+  @property
+  def Entities(self) -> List[Entity]:
+
+  @property
+  def Packages(self) -> List[Package]:
+
+
+
+
+

Document

+

A source file (document) contains multiple design units. Each design unit +listed in a sourcecode file is a primary or secondary design unit like: +configuration, entity, architecture, package, package body +or context.

+

Design unit may be preceded by a context made of library, use and +context statements. These statements are not directly visible in the +Document object, because design unit contexts are consumed by the design +units. See the Libraries and Uses fields of each design unit to +investigate the consumed contexts.

+

Condensed definition of class Document:

+
@export
+class Document(ModelEntity):
+  # inherited from ModelEntity
+  @property
+  def Parent(self) -> ModelEntity:
+
+  # from Document
+  @property
+  def Path(self) -> Path:
+
+  @property
+  def Contexts(self) -> List[Context]:
+
+  @property
+  def Configurations(self) -> List[Configuration]:
+
+  @property
+  def Entities(self) -> List[Entity]:
+
+  @property
+  def Architectures(self) -> List[Architecture]:
+
+  @property
+  def Packages(self) -> List[Package]:
+
+  @property
+  def PackageBodies(self) -> List[PackageBody]:
+
+
+
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/LanguageModel/ObjectDeclarations.html b/LanguageModel/ObjectDeclarations.html new file mode 100644 index 000000000..e7c6190b7 --- /dev/null +++ b/LanguageModel/ObjectDeclarations.html @@ -0,0 +1,416 @@ + + + + + + + Object Declarations — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

Object Declarations

+ +
+

Constants

+

VHDL defines regular constants as an object. In addition, deferred constants are +supported in package declarations. Often generics to e.g. packages or entities +are constants. Also most in parameters to subprograms are constants.

+
+

Constant

+

A constant represents immutable data. This data (value) must be assigned via a +default expression. If a constant’s value is delayed in calculation, it’s called +a deferred constant. See Deferred Constant in next section.

+

Condensed definition of class Constant:

+
@export
+class Constant(BaseConstant):
+  # inherited from ModelEntity
+  @property
+  def Parent(self) -> ModelEntity:
+
+  # inherited from NamedEntity
+  @property
+  def Name(self) -> str:
+
+  # inherited from Object
+  @property
+  def Subtype(self) -> Subtype:
+
+  @property
+  def DefaultExpression(self) -> BaseExpression:
+
+
+
+
+

Deferred Constant

+

If a constant’s value is delayed in calculation, it’s a deferred constant. Such +a deferred constant has a reference to the regular constant of the same name.

+

Condensed definition of class DeferredConstant:

+
@export
+class DeferredConstant(BaseConstant):
+  # inherited from ModelEntity
+  @property
+  def Parent(self) -> ModelEntity:
+
+  # inherited from NamedEntity
+  @property
+  def Name(self) -> str:
+
+  # inherited from Object
+  @property
+  def Subtype(self) -> Subtype:
+
+  # inherited from WithDefaultExpressionMixin
+  @property
+  def ConstantReference(self) -> Constant:
+
+
+
+
+

Generic Constant

+

A generic without object class or a generic constant is a regular constant.

+
+

See also

+

See GenericConstantInterfaceItem for details.

+
+
+
+

Constant as Parameter

+

A subprogram parameter without object class of mode in or a parameter constant is a regular constant.

+
+

See also

+

See ParameterConstantInterfaceItem for details.

+
+
+
+
+

Variables

+
+

Variable

+

A variable represents mutable data in sequential regions. Assignments to +variables have no delay. The initial value can be assigned via a default +expression.

+

Condensed definition of class Variable:

+
@export
+class Variable(Object):
+  # inherited from ModelEntity
+  @property
+  def Parent(self) -> ModelEntity:
+
+  # inherited from NamedEntity
+  @property
+  def Name(self) -> str:
+
+  # inherited from Object
+  @property
+  def Subtype(self) -> Subtype:
+
+  # inherited from WithDefaultExpressionMixin
+  @property
+  def DefaultExpression(self) -> BaseExpression:
+
+
+
+
+

Variable as Parameter

+

A subprogram parameter without object class of mode out or a parameter variable is a regular variable.

+
+

See also

+

See ParameterVariableInterfaceItem for details.

+
+
+
+
+

Shared Variable

+
+

Todo

+

Write documentation.

+
+
+
+

Signals

+
+

Signal

+

A signal represents mutable data in concurrent regions. Assignments to signals +are delayed until next wait statement is executed. The initial value can be +assigned via a default expression.

+

Condensed definition of class Signal:

+
@export
+class Signal(Object):
+  # inherited from ModelEntity
+  @property
+  def Parent(self) -> ModelEntity:
+
+  # inherited from NamedEntity
+  @property
+  def Name(self) -> str:
+
+  # inherited from Object
+  @property
+  def Subtype(self) -> Subtype:
+
+  # inherited from WithDefaultExpressionMixin
+  @property
+  def DefaultExpression(self) -> BaseExpression:
+
+
+
+
+

Signal as Port

+

A port signal is a regular signal.

+
+

See also

+

See PortSignalInterfaceItem for details.

+
+
+
+

Signal as Parameter

+

A parameter signal is a regular signal.

+
+

See also

+

See ParameterSignalInterfaceItem for details.

+
+
+
+
+

Files

+
+

File

+
+

Todo

+

Write documentation.

+
+
+
+

File as Parameter

+

A parameter file is a regular file.

+
+

See also

+

See ParameterFileInterfaceItem for details.

+
+
+
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/LanguageModel/SequentialStatements.html b/LanguageModel/SequentialStatements.html new file mode 100644 index 000000000..650c4d3b4 --- /dev/null +++ b/LanguageModel/SequentialStatements.html @@ -0,0 +1,593 @@ + + + + + + + Sequential Statements — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

Sequential Statements

+ +

Class Hierarchy

+
+

Assignments

+
+

Signal Assignment

+
+

Todo

+

Write documentation.

+
+

Condensed definition of class SequentialSignalAssignment:

+
@export
+class SequentialSignalAssignment(SequentialStatement, SignalAssignment):
+  # inherited from ModelEntity
+  @property
+  def Parent(self) -> ModelEntity:
+
+  # inherited from LabeledEntity
+  @property
+  def Label(self) -> str:
+
+  # inherited from Assignment
+  @property
+  def Target(self) -> Object:
+
+  @property
+  def BaseExpression(self) -> BaseExpression:
+
+
+
+
+

Variable Assignment

+
+

Todo

+

Write documentation.

+
+

Condensed definition of class SequentialVariableAssignment:

+
@export
+class SequentialVariableAssignment(SequentialStatement, VariableAssignment):
+  # inherited from ModelEntity
+  @property
+  def Parent(self) -> ModelEntity:
+
+  # inherited from LabeledEntity
+  @property
+  def Label(self) -> str:
+
+  # inherited from Assignment
+  @property
+  def Target(self) -> Object:
+
+  @property
+  def BaseExpression(self) -> BaseExpression:
+
+
+
+
+
+

Branching

+
+

If Statement

+
+

Todo

+

Write documentation.

+
+
+
+

Case Statement

+
+

Todo

+

Write documentation.

+
+

Condensed definition of class CaseStatement:

+
@export
+class CaseStatement(CompoundStatement):
+  # inherited from ModelEntity
+  @property
+  def Parent(self) -> ModelEntity:
+
+  # inherited from LabeledEntity
+  @property
+  def Label(self) -> str:
+
+  # from CaseGenerateStatement
+  @property
+  def SelectExpression(self) -> BaseExpression:
+
+  @property
+  def Cases(self) -> List[SequentialCase]:
+
+
+
+
+
+

Loops

+
+

Endless Loop

+
+

Todo

+

Write documentation.

+
+

Condensed definition of class EndlessLoopStatement:

+
@export
+class EndlessLoopStatement(LoopStatement):
+  # inherited from ModelEntity
+  @property
+  def Parent(self) -> ModelEntity:
+
+  # inherited from LabeledEntity
+  @property
+  def Label(self) -> str:
+
+  # inherited from SequentialStatements
+  @property
+  def Statements(self) -> List[SequentialStatement]:
+
+
+
+
+

For Loop

+
+

Todo

+

Write documentation.

+
+

Condensed definition of class ForLoopStatement:

+
@export
+class ForLoopStatement(LoopStatement):
+  # inherited from ModelEntity
+  @property
+  def Parent(self) -> ModelEntity:
+
+  # inherited from LabeledEntity
+  @property
+  def Label(self) -> str:
+
+  # inherited from SequentialStatements
+  @property
+  def Statements(self) -> List[SequentialStatement]:
+
+  # from ForLoopStatement
+  @property
+  def LoopIndex(self) -> Constant:
+
+  @property
+  def Range(self) -> Range:
+
+
+
+
+

While Loop

+
+

Todo

+

Write documentation.

+
+

Condensed definition of class WhileLoopStatement:

+
@export
+class WhileLoopStatement(LoopStatement, BaseConditional):
+  # inherited from ModelEntity
+  @property
+  def Parent(self) -> ModelEntity:
+
+  # inherited from LabeledEntity
+  @property
+  def Label(self) -> str:
+
+  # inherited from SequentialStatements
+  @property
+  def Statements(self) -> List[SequentialStatement]:
+
+  # inherited from BaseConditional
+  @property
+  def Condition(self) -> BaseExpression:
+
+
+
+
+

Next Statement

+
+

Todo

+

Write documentation.

+
+

Condensed definition of class NextStatement:

+
@export
+class NextStatement(SequentialStatement, BaseConditional):
+  # inherited from ModelEntity
+  @property
+  def Parent(self) -> ModelEntity:
+
+  # inherited from LabeledEntity
+  @property
+  def Label(self) -> str:
+
+  # inherited from BaseCondition
+  @property
+  def Condition(self) -> BaseExpression:
+
+  # inherited from LoopControlStatement
+  @property
+  def LoopReference(self) -> LoopStatement:
+
+
+
+
+

Exit Statement

+
+

Todo

+

Write documentation.

+
+

Condensed definition of class ExitStatement:

+
@export
+class ExitStatement(SequentialStatement, BaseConditional):
+  # inherited from ModelEntity
+  @property
+  def Parent(self) -> ModelEntity:
+
+  # inherited from LabeledEntity
+  @property
+  def Label(self) -> str:
+
+  # inherited from BaseCondition
+  @property
+  def Condition(self) -> BaseExpression:
+
+  # inherited from LoopControlStatement
+  @property
+  def LoopReference(self) -> LoopStatement:
+
+
+
+
+
+

Reporting

+
+

Report Statement

+
+

Todo

+

Write documentation.

+
+

Condensed definition of class SequentialReportStatement:

+
@export
+class SequentialReportStatement(SequentialStatement, MixinReportStatement):
+  # inherited from ModelEntity
+  @property
+  def Parent(self) -> ModelEntity:
+
+  # inherited from LabeledEntity
+  @property
+  def Label(self) -> str:
+
+  # inherited from MixinReportStatement
+  @property
+  def Message(self) -> BaseExpression:
+
+  @property
+  def Severity(self) -> BaseExpression:
+
+
+
+
+

Assert Statement

+
+

Todo

+

Write documentation.

+
+

Condensed definition of class SequentialAssertStatement:

+
@export
+class SequentialAssertStatement(SequentialStatement, MixinAssertStatement):
+  # inherited from ModelEntity
+  @property
+  def Parent(self) -> ModelEntity:
+
+  # inherited from LabeledEntity
+  @property
+  def Label(self) -> str:
+
+  # inherited from MixinReportStatement
+  @property
+  def Message(self) -> BaseExpression:
+
+  @property
+  def Severity(self) -> BaseExpression:
+
+  # inherited from MixinAssertStatement
+  @property
+  def Condition(self) -> BaseExpression:
+
+
+
+
+
+

Procedure Call

+
+

Todo

+

Write documentation.

+
+
+
+

Wait Statement

+
+

Todo

+

Write documentation.

+
+

Condensed definition of class WaitStatement:

+
@export
+class WaitStatement(SequentialStatement, BaseConditional):
+  # inherited from ModelEntity
+  @property
+  def Parent(self) -> ModelEntity:
+
+  # inherited from LabeledEntity
+  @property
+  def Label(self) -> str:
+
+  # inherited from BaseCondition
+  @property
+  def Condition(self) -> BaseExpression:
+
+  # from WaitStatement
+  @property
+  def SensitivityList(self) -> List[Signal]:
+
+  @property
+  def Timeout(self) -> BaseExpression:
+
+
+
+
+

Return Statement

+
+

Todo

+

Write documentation.

+
+

Condensed definition of class ReturnStatement:

+
@export
+class ReturnStatement(SequentialStatement, BaseConditional):
+  # inherited from ModelEntity
+  @property
+  def Parent(self) -> ModelEntity:
+
+  # inherited from LabeledEntity
+  @property
+  def Label(self) -> str:
+
+  # inherited from BaseCondition
+  @property
+  def Condition(self) -> BaseExpression:
+
+  # from ReturnStatement
+  @property
+  def ReturnValue(self) -> BaseExpression:
+
+
+
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/LanguageModel/SubprogramDefinitions.html b/LanguageModel/SubprogramDefinitions.html new file mode 100644 index 000000000..973510651 --- /dev/null +++ b/LanguageModel/SubprogramDefinitions.html @@ -0,0 +1,391 @@ + + + + + + + Subprogram Declarations — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

Subprogram Declarations

+ +
+

Procedures

+
+

Procedure

+

Condensed definition of class Procedure:

+
@export
+class Procedure(SubProgramm):
+  # inherited from ModelEntity
+  @property
+  def Parent(self) -> ModelEntity:
+
+  # inherited from NamedEntity
+  @property
+  def Name(self) -> str:
+
+  # inherited from Subprogram
+  @property
+  def GenericItems(self) -> List[GenericInterfaceItem]:
+
+  @property
+  def ParameterItems(self) -> List[ParameterInterfaceItem]:
+
+  @property
+  def DeclaredItems(self) -> List:
+
+  @property
+  def BodyItems(self) -> List[SequentialStatement]:
+
+  @property
+  def IsPure(self) -> bool:
+
+
+
+
+

Procedure Instantiation

+
+

Todo

+

Write documentation.

+
+
+
+

Procedure as Method

+

Condensed definition of class ProcedureMethod:

+
@export
+class ProcedureMethod(SubProgramm):
+  # inherited from ModelEntity
+  @property
+  def Parent(self) -> ModelEntity:
+
+  # inherited from NamedEntity
+  @property
+  def Name(self) -> str:
+
+  # inherited from Subprogram
+  @property
+  def GenericItems(self) -> List[GenericInterfaceItem]:
+
+  @property
+  def ParameterItems(self) -> List[ParameterInterfaceItem]:
+
+  @property
+  def DeclaredItems(self) -> List:
+
+  @property
+  def BodyItems(self) -> List[SequentialStatement]:
+
+  @property
+  def IsPure(self) -> bool:
+
+  # inherited from Method
+  @property
+  def ProtectedType(self) -> ProtectedType:
+
+
+
+
+

Generic Procedure

+

A generic procedure is a regular procedure.

+
+

See also

+

See GenericProcedureInterfaceItem for details.

+
+
+
+
+

Functions

+
+

Function

+

Condensed definition of class Function:

+
@export
+class Function(SubProgramm):
+  # inherited from ModelEntity
+  @property
+  def Parent(self) -> ModelEntity:
+
+  # inherited from NamedEntity
+  @property
+  def Name(self) -> str:
+
+  # inherited from Subprogram
+  @property
+  def GenericItems(self) -> List[GenericInterfaceItem]:
+
+  @property
+  def ParameterItems(self) -> List[ParameterInterfaceItem]:
+
+  @property
+  def DeclaredItems(self) -> List:
+
+  @property
+  def BodyItems(self) -> List[SequentialStatement]:
+
+  @property
+  def IsPure(self) -> bool:
+
+  # from Function
+  @property
+  def ReturnType(self) -> Subtype:
+
+
+
+
+

Function Instantiation

+
+

Todo

+

Write documentation.

+
+
+
+

Function as Method

+

Condensed definition of class FunctionMethod:

+
@export
+class Function(SubProgramm):
+  # inherited from ModelEntity
+  @property
+  def Parent(self) -> ModelEntity:
+
+  # inherited from NamedEntity
+  @property
+  def Name(self) -> str:
+
+  # inherited from Subprogram
+  @property
+  def GenericItems(self) -> List[GenericInterfaceItem]:
+
+  @property
+  def ParameterItems(self) -> List[ParameterInterfaceItem]:
+
+  @property
+  def DeclaredItems(self) -> List:
+
+  @property
+  def BodyItems(self) -> List[SequentialStatement]:
+
+  @property
+  def IsPure(self) -> bool:
+
+  # inherited from Function
+  @property
+  def ReturnType(self) -> Subtype:
+
+  # inherited from Method
+  @property
+  def ProtectedType(self) -> ProtectedType:
+
+
+
+
+

Generic Function

+

A generic function is a regular function.

+
+

See also

+

See GenericFunctionInterfaceItem for details.

+
+
+
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/LanguageModel/SubtypeDefinitions.html b/LanguageModel/SubtypeDefinitions.html new file mode 100644 index 000000000..6ddc5e25d --- /dev/null +++ b/LanguageModel/SubtypeDefinitions.html @@ -0,0 +1,184 @@ + + + + + + + Subtype Declarations — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

Subtype Declarations

+

VHDL has subtypes to constrain types.

+

Class Hierarchy

+
+

Todo

+

Write documentation.

+
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/LanguageModel/TypeDefinitions.html b/LanguageModel/TypeDefinitions.html new file mode 100644 index 000000000..9cdb2a466 --- /dev/null +++ b/LanguageModel/TypeDefinitions.html @@ -0,0 +1,403 @@ + + + + + + + Type Declarations — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

Type Declarations

+

VHDL has types (also called a base type) and subtypes. The following shows VHDL’s type hierarchy:

+ +

Class Hierarchy

+
+

Scalar Types

+
+

Enumeration

+
+

Todo

+

Write documentation.

+
+

Condensed definition of class EnumeratedType:

+
@export
+class EnumeratedType(ScalarType, DiscreteType):
+  # inherited from ModelEntity
+  @property
+  def Parent(self) -> ModelEntity:
+
+  # inherited from NamedEntity
+  @property
+  def Name(self) -> str:
+
+  # from EnumeratedType
+  @property
+  def Elements(self) -> List[str]:
+
+
+
+
+

Integer

+
+

Todo

+

Write documentation.

+
+

Condensed definition of class IntegerType:

+
@export
+class IntegerType(RangedScalarType, NumericType, DiscreteType):
+  # inherited from ModelEntity
+  @property
+  def Parent(self) -> ModelEntity:
+
+  # inherited from NamedEntity
+  @property
+  def Name(self) -> str:
+
+  # inherited from RangedScalarType
+  @property
+  def LeftBound(self) -> 'BaseExpression':
+
+  @property
+  def RightBound(self) -> 'BaseExpression':
+
+
+
+
+

Real

+
+

Todo

+

Write documentation.

+
+

Condensed definition of class RealType:

+
@export
+class RealType(RangedScalarType, NumericType):
+  # inherited from ModelEntity
+  @property
+  def Parent(self) -> ModelEntity:
+
+  # inherited from NamedEntity
+  @property
+  def Name(self) -> str:
+
+  # inherited from RangedScalarType
+  @property
+  def LeftBound(self) -> 'BaseExpression':
+
+  @property
+  def RightBound(self) -> 'BaseExpression':
+
+
+
+
+

Physical

+
+

Todo

+

Write documentation.

+
+

Condensed definition of class PhysicalType:

+
@export
+class PhysicalType(RangedScalarType, NumericType):
+  # inherited from ModelEntity
+  @property
+  def Parent(self) -> ModelEntity:
+
+  # inherited from NamedEntity
+  @property
+  def Name(self) -> str:
+
+  # inherited from RangedScalarType
+  @property
+  def LeftBound(self) -> 'BaseExpression':
+
+  @property
+  def RightBound(self) -> 'BaseExpression':
+
+  # from PhysicalType
+  @property
+  def PrimaryUnit(self) -> str:
+
+  @property
+  def SecondaryUnits(self) -> List[Tuple[int, str]]:
+
+
+
+
+
+

Composite Types

+
+

Array

+
+

Todo

+

Write documentation.

+
+

Condensed definition of class ArrayType:

+
@export
+class ArrayType(CompositeType):
+  # inherited from ModelEntity
+  @property
+  def Parent(self) -> ModelEntity:
+
+  # inherited from NamedEntity
+  @property
+  def Name(self) -> str:
+
+  # from ArrayType
+  @property
+  def Dimensions(self) -> List[Range]:
+
+  @property
+  def ElementType(self) -> Subtype:
+
+
+
+
+

Record

+
+

Todo

+

Write documentation.

+
+

Condensed definition of class RecordType:

+
@export
+class RecordType(CompositeType):
+  # inherited from ModelEntity
+  @property
+  def Parent(self) -> ModelEntity:
+
+  # inherited from NamedEntity
+  @property
+  def Name(self) -> str:
+
+  # from RecordType
+  @property
+  def Members(self) -> List[RecordTypeElement]:
+
+
+
+
+
+

Protected

+
+

Todo

+

Write documentation.

+
+
+
+

Access

+
+

Todo

+

Write documentation.

+
+
+
+

File

+
+

Todo

+

Write documentation.

+
+
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/LanguageModel/index.html b/LanguageModel/index.html new file mode 100644 index 000000000..df1ff1bfe --- /dev/null +++ b/LanguageModel/index.html @@ -0,0 +1,193 @@ + + + + + + + VHDL Language Model — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

VHDL Language Model

+

Elements of the Language Model

+
+ +
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/License.html b/License.html new file mode 100644 index 000000000..a593a6c0f --- /dev/null +++ b/License.html @@ -0,0 +1,299 @@ + + + + + + + Apache License 2.0 — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

Note

+

This is a local copy of the Apache License Version 2.0.

+
+
+

Attention

+

This Apache License, 2.0 applies to all source and configuration files of project, except documentation.

+
+
+

Apache License 2.0

+

Version 2.0, January 2004

+

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+
Copyright [yyyy] [name of copyright owner]
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
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+
+
+
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/TODO.html b/TODO.html new file mode 100644 index 000000000..94ed88ce1 --- /dev/null +++ b/TODO.html @@ -0,0 +1,525 @@ + + + + + + + TODOs — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

TODOs

+
+

Todo

+

Write how to get started on Linux with libghdl.

+
+

original entry

+
+

Todo

+

Write how to get started on Mac with libghdl.

+
+

original entry

+
+

Todo

+

Write documentation.

+
+

original entry

+
+

Todo

+

Write documentation.

+
+

original entry

+
+

Todo

+

Write documentation.

+
+

original entry

+
+

Todo

+

Write documentation.

+
+

original entry

+
+

Todo

+

Write documentation.

+
+

original entry

+
+

Todo

+

Write documentation.

+
+

original entry

+
+

Todo

+

Write documentation.

+
+

original entry

+
+

Todo

+

Write documentation.

+
+

original entry

+
+

Todo

+

Write documentation.

+
+

original entry

+
+

Todo

+

Write documentation.

+
+

original entry

+
+

Todo

+

Write documentation.

+
+

original entry

+
+

Todo

+

Write documentation.

+
+

original entry

+
+

Todo

+

Write documentation.

+
+

original entry

+
+

Todo

+

Write documentation.

+
+

original entry

+
+

Todo

+

Write documentation.

+
+

original entry

+
+

Todo

+

Write documentation.

+
+

original entry

+
+

Todo

+

Write documentation.

+
+

original entry

+
+

Todo

+

Write documentation.

+
+

original entry

+
+

Todo

+

Write documentation.

+
+

original entry

+
+

Todo

+

Write documentation.

+
+

original entry

+
+

Todo

+

Write documentation.

+
+

original entry

+
+

Todo

+

Write documentation.

+
+

original entry

+
+

Todo

+

Write documentation.

+
+

original entry

+
+

Todo

+

Write documentation.

+
+

original entry

+
+

Todo

+

Write documentation.

+
+

original entry

+
+

Todo

+

Write documentation.

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+ + + + \ No newline at end of file diff --git a/_images/inheritance-00fc5ca7c23ab6ce3c644be6978a1557936a6be3.svg b/_images/inheritance-00fc5ca7c23ab6ce3c644be6978a1557936a6be3.svg new file mode 100644 index 000000000..f8cb4b1bf --- /dev/null +++ b/_images/inheritance-00fc5ca7c23ab6ce3c644be6978a1557936a6be3.svg @@ -0,0 +1,74 @@ + + +inheritance97a76ea76b + + +BaseExpression + + +BaseExpression + + + + + +BinaryExpression + + +BinaryExpression + + + + + +BaseExpression->BinaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +RelationalExpression + + +RelationalExpression + + + + + +BinaryExpression->RelationalExpression + + + + + +UnequalExpression + + +UnequalExpression + + + + + +RelationalExpression->UnequalExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-01cb7efac51ca6d4c734256f0d0e059509be6dad.svg b/_images/inheritance-01cb7efac51ca6d4c734256f0d0e059509be6dad.svg new file mode 100644 index 000000000..e3a126b08 --- /dev/null +++ b/_images/inheritance-01cb7efac51ca6d4c734256f0d0e059509be6dad.svg @@ -0,0 +1,119 @@ + + +inheritance1e38608f2f + + +CompoundStatement + + +CompoundStatement + + + + + +LoopStatement + + +LoopStatement + + + + + +CompoundStatement->LoopStatement + + + + + +SequentialStatement + + +SequentialStatement + + + + + +SequentialStatement->CompoundStatement + + + + + +EndlessLoopStatement + + +EndlessLoopStatement + + + + + +LoopStatement->EndlessLoopStatement + + + + + +LabeledEntityMixin + + +LabeledEntityMixin + + + + + +Statement + + +Statement + + + + + +LabeledEntityMixin->Statement + + + + + +SequentialStatementsMixin + + +SequentialStatementsMixin + + + + + +SequentialStatementsMixin->LoopStatement + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Statement + + + + + +Statement->SequentialStatement + + + + + \ No newline at end of file diff --git a/_images/inheritance-02ecdd9e081258b7814325a65147ec990c904a78.svg b/_images/inheritance-02ecdd9e081258b7814325a65147ec990c904a78.svg new file mode 100644 index 000000000..a55e7b8e0 --- /dev/null +++ b/_images/inheritance-02ecdd9e081258b7814325a65147ec990c904a78.svg @@ -0,0 +1,164 @@ + + +inheritance21ac1cbe2f + + +ConcurrentDeclarationRegionMixin + + +ConcurrentDeclarationRegionMixin + + + + + +Package + + +Package + + + + + +ConcurrentDeclarationRegionMixin->Package + + + + + +DesignUnit + + +DesignUnit + + + + + +PrimaryUnit + + +PrimaryUnit + + + + + +DesignUnit->PrimaryUnit + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->DesignUnit + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->DesignUnit + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->DesignUnit + + + + + +DesignUnitWithContextMixin + + +DesignUnitWithContextMixin + + + + + +DesignUnitWithContextMixin->Package + + + + + +Math_Complex + + +Math_Complex + + + + + +PredefinedPackage + + +PredefinedPackage + + + + + +PredefinedPackage->Math_Complex + + + + + +Package->PredefinedPackage + + + + + +PrimaryUnit->Package + + + + + +PredefinedPackageMixin + + +PredefinedPackageMixin + + + + + +PredefinedPackageMixin->PredefinedPackage + + + + + \ No newline at end of file diff --git a/_images/inheritance-030ba4b047910fad5c58890598cbcf6840c0d629.svg b/_images/inheritance-030ba4b047910fad5c58890598cbcf6840c0d629.svg new file mode 100644 index 000000000..a9e027c72 --- /dev/null +++ b/_images/inheritance-030ba4b047910fad5c58890598cbcf6840c0d629.svg @@ -0,0 +1,74 @@ + + +inheritanced3f9e95351 + + +AddingExpression + + +AddingExpression + + + + + +ConcatenationExpression + + +ConcatenationExpression + + + + + +AddingExpression->ConcatenationExpression + + + + + +BinaryExpression + + +BinaryExpression + + + + + +BinaryExpression->AddingExpression + + + + + +BaseExpression + + +BaseExpression + + + + + +BaseExpression->BinaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-03dfc0ce6b6e17154d093d6b5d6e4f9e454da438.svg b/_images/inheritance-03dfc0ce6b6e17154d093d6b5d6e4f9e454da438.svg new file mode 100644 index 000000000..7a9022a32 --- /dev/null +++ b/_images/inheritance-03dfc0ce6b6e17154d093d6b5d6e4f9e454da438.svg @@ -0,0 +1,74 @@ + + +inheritance75ceb8d9b1 + + +BaseExpression + + +BaseExpression + + + + + +BinaryExpression + + +BinaryExpression + + + + + +BaseExpression->BinaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +MultiplyingExpression + + +MultiplyingExpression + + + + + +BinaryExpression->MultiplyingExpression + + + + + +ModuloExpression + + +ModuloExpression + + + + + +MultiplyingExpression->ModuloExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-04dcd2ab83d441551a4738760c8b7aa2091e105d.svg b/_images/inheritance-04dcd2ab83d441551a4738760c8b7aa2091e105d.svg new file mode 100644 index 000000000..7b6402da4 --- /dev/null +++ b/_images/inheritance-04dcd2ab83d441551a4738760c8b7aa2091e105d.svg @@ -0,0 +1,74 @@ + + +inheritancecb0e56e4c5 + + +BaseCase + + +BaseCase + + + + + +SequentialCase + + +SequentialCase + + + + + +BaseCase->SequentialCase + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseCase + + + + + +Case + + +Case + + + + + +SequentialCase->Case + + + + + +SequentialStatementsMixin + + +SequentialStatementsMixin + + + + + +SequentialStatementsMixin->SequentialCase + + + + + \ No newline at end of file diff --git a/_images/inheritance-062a295c7f8122175357cf4c846094b0d6375b04.svg b/_images/inheritance-062a295c7f8122175357cf4c846094b0d6375b04.svg new file mode 100644 index 000000000..e5e3ae484 --- /dev/null +++ b/_images/inheritance-062a295c7f8122175357cf4c846094b0d6375b04.svg @@ -0,0 +1,44 @@ + + +inheritancec5a3b8eb0e + + +BaseExpression + + +BaseExpression + + + + + +FunctionCall + + +FunctionCall + + + + + +BaseExpression->FunctionCall + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-077d2fccd44f3793945affb9ec14ca6e6b142830.svg b/_images/inheritance-077d2fccd44f3793945affb9ec14ca6e6b142830.svg new file mode 100644 index 000000000..848aa55b9 --- /dev/null +++ b/_images/inheritance-077d2fccd44f3793945affb9ec14ca6e6b142830.svg @@ -0,0 +1,29 @@ + + +inheritance6fc3f51034 + + +LibraryNotRegisteredError + + +LibraryNotRegisteredError + + + + + +VHDLModelException + + +VHDLModelException + + + + + +VHDLModelException->LibraryNotRegisteredError + + + + + \ No newline at end of file diff --git a/_images/inheritance-07b312165f08663c6ba82e75a11fe6de3649c657.svg b/_images/inheritance-07b312165f08663c6ba82e75a11fe6de3649c657.svg new file mode 100644 index 000000000..fd23e59d8 --- /dev/null +++ b/_images/inheritance-07b312165f08663c6ba82e75a11fe6de3649c657.svg @@ -0,0 +1,59 @@ + + +inheritance291a10a041 + + +BaseExpression + + +BaseExpression + + + + + +UnaryExpression + + +UnaryExpression + + + + + +BaseExpression->UnaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +TypeConversion + + +TypeConversion + + + + + +UnaryExpression->TypeConversion + + + + + \ No newline at end of file diff --git a/_images/inheritance-07e5dfcbd8d2fef0ff3075cb35e21badd6e03262.svg b/_images/inheritance-07e5dfcbd8d2fef0ff3075cb35e21badd6e03262.svg new file mode 100644 index 000000000..3f499a805 --- /dev/null +++ b/_images/inheritance-07e5dfcbd8d2fef0ff3075cb35e21badd6e03262.svg @@ -0,0 +1,104 @@ + + +inheritance31a0079c97 + + +ConditionalMixin + + +ConditionalMixin + + + + + +LoopControlStatement + + +LoopControlStatement + + + + + +ConditionalMixin->LoopControlStatement + + + + + +LabeledEntityMixin + + +LabeledEntityMixin + + + + + +Statement + + +Statement + + + + + +LabeledEntityMixin->Statement + + + + + +NextStatement + + +NextStatement + + + + + +LoopControlStatement->NextStatement + + + + + +SequentialStatement + + +SequentialStatement + + + + + +SequentialStatement->LoopControlStatement + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Statement + + + + + +Statement->SequentialStatement + + + + + \ No newline at end of file diff --git a/_images/inheritance-08063d2c9f2dd81cc502e129da03b7a538cd4932.svg b/_images/inheritance-08063d2c9f2dd81cc502e129da03b7a538cd4932.svg new file mode 100644 index 000000000..c3ae621ec --- /dev/null +++ b/_images/inheritance-08063d2c9f2dd81cc502e129da03b7a538cd4932.svg @@ -0,0 +1,74 @@ + + +inheritance35605eee8e + + +BaseExpression + + +BaseExpression + + + + + +BinaryExpression + + +BinaryExpression + + + + + +BaseExpression->BinaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +MultiplyingExpression + + +MultiplyingExpression + + + + + +BinaryExpression->MultiplyingExpression + + + + + +RemainderExpression + + +RemainderExpression + + + + + +MultiplyingExpression->RemainderExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-0840e80a49404c04863404d33af051610ccc2b5f.svg b/_images/inheritance-0840e80a49404c04863404d33af051610ccc2b5f.svg new file mode 100644 index 000000000..a59bfe1e4 --- /dev/null +++ b/_images/inheritance-0840e80a49404c04863404d33af051610ccc2b5f.svg @@ -0,0 +1,74 @@ + + +inheritancea5c7587250 + + +BaseExpression + + +BaseExpression + + + + + +BinaryExpression + + +BinaryExpression + + + + + +BaseExpression->BinaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +MultiplyingExpression + + +MultiplyingExpression + + + + + +BinaryExpression->MultiplyingExpression + + + + + +DivisionExpression + + +DivisionExpression + + + + + +MultiplyingExpression->DivisionExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-0867625f93f85ad18664e22f566dd4af3fceab11.svg b/_images/inheritance-0867625f93f85ad18664e22f566dd4af3fceab11.svg new file mode 100644 index 000000000..4572415b8 --- /dev/null +++ b/_images/inheritance-0867625f93f85ad18664e22f566dd4af3fceab11.svg @@ -0,0 +1,74 @@ + + +inheritance45d9bdd109 + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +Subprogram + + +Subprogram + + + + + +DocumentedEntityMixin->Subprogram + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Subprogram + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->Subprogram + + + + + +Procedure + + +Procedure + + + + + +Subprogram->Procedure + + + + + \ No newline at end of file diff --git a/_images/inheritance-087a63d2551454cffdd9e15e59f3c2e036fedb97.svg b/_images/inheritance-087a63d2551454cffdd9e15e59f3c2e036fedb97.svg new file mode 100644 index 000000000..37dc45ebf --- /dev/null +++ b/_images/inheritance-087a63d2551454cffdd9e15e59f3c2e036fedb97.svg @@ -0,0 +1,89 @@ + + +inheritanced279002b8c + + +BaseType + + +BaseType + + + + + +FullType + + +FullType + + + + + +BaseType->FullType + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseType + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->BaseType + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->BaseType + + + + + +CompositeType + + +CompositeType + + + + + +FullType->CompositeType + + + + + \ No newline at end of file diff --git a/_images/inheritance-0893b00135b154d3f0571c3b21cdddba031a02cc.svg b/_images/inheritance-0893b00135b154d3f0571c3b21cdddba031a02cc.svg new file mode 100644 index 000000000..913682032 --- /dev/null +++ b/_images/inheritance-0893b00135b154d3f0571c3b21cdddba031a02cc.svg @@ -0,0 +1,59 @@ + + +inheritance502f648504 + + +BaseExpression + + +BaseExpression + + + + + +QualifiedExpression + + +QualifiedExpression + + + + + +BaseExpression->QualifiedExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +ParenthesisExpression + + +ParenthesisExpression + + + + + +ParenthesisExpression->QualifiedExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-096d308fc56be774a6d69fc83723b12eb7c8ab69.svg b/_images/inheritance-096d308fc56be774a6d69fc83723b12eb7c8ab69.svg new file mode 100644 index 000000000..c663b1855 --- /dev/null +++ b/_images/inheritance-096d308fc56be774a6d69fc83723b12eb7c8ab69.svg @@ -0,0 +1,74 @@ + + +inheritanceec5907b79d + + +LabeledEntityMixin + + +LabeledEntityMixin + + + + + +Statement + + +Statement + + + + + +LabeledEntityMixin->Statement + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Statement + + + + + +NullStatement + + +NullStatement + + + + + +SequentialStatement + + +SequentialStatement + + + + + +SequentialStatement->NullStatement + + + + + +Statement->SequentialStatement + + + + + \ No newline at end of file diff --git a/_images/inheritance-0999820bdb6f60460ad5c20b24ec755acb744e45.svg b/_images/inheritance-0999820bdb6f60460ad5c20b24ec755acb744e45.svg new file mode 100644 index 000000000..b8efadbef --- /dev/null +++ b/_images/inheritance-0999820bdb6f60460ad5c20b24ec755acb744e45.svg @@ -0,0 +1,29 @@ + + +inheritance6f60f6a5e1 + + +BaseCase + + +BaseCase + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseCase + + + + + \ No newline at end of file diff --git a/_images/inheritance-0a0ff1726dc1620d5ce59e6df51579e66d3a5ea4.svg b/_images/inheritance-0a0ff1726dc1620d5ce59e6df51579e66d3a5ea4.svg new file mode 100644 index 000000000..2bd3e75f5 --- /dev/null +++ b/_images/inheritance-0a0ff1726dc1620d5ce59e6df51579e66d3a5ea4.svg @@ -0,0 +1,59 @@ + + +inheritancefeea002840 + + +BaseExpression + + +BaseExpression + + + + + +UnaryExpression + + +UnaryExpression + + + + + +BaseExpression->UnaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +InverseExpression + + +InverseExpression + + + + + +UnaryExpression->InverseExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-0a4324bb301d394eb304a5a29a1ba2ae2046cbc6.svg b/_images/inheritance-0a4324bb301d394eb304a5a29a1ba2ae2046cbc6.svg new file mode 100644 index 000000000..67ca81716 --- /dev/null +++ b/_images/inheritance-0a4324bb301d394eb304a5a29a1ba2ae2046cbc6.svg @@ -0,0 +1,59 @@ + + +inheritance7bee0b37ea + + +Library + + +Library + + + + + +PredefinedLibrary + + +PredefinedLibrary + + + + + +Library->PredefinedLibrary + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Library + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->Library + + + + + \ No newline at end of file diff --git a/_images/inheritance-0a75307247c30d88be7386368fea87f09383c49e.svg b/_images/inheritance-0a75307247c30d88be7386368fea87f09383c49e.svg new file mode 100644 index 000000000..a5dd55ac3 --- /dev/null +++ b/_images/inheritance-0a75307247c30d88be7386368fea87f09383c49e.svg @@ -0,0 +1,29 @@ + + +inheritance78c29ac60b + + +ModelEntity + + +ModelEntity + + + + + +Name + + +Name + + + + + +ModelEntity->Name + + + + + \ No newline at end of file diff --git a/_images/inheritance-0b0e4f4d974f7dd43f7e689b18e1b82be82f3997.svg b/_images/inheritance-0b0e4f4d974f7dd43f7e689b18e1b82be82f3997.svg new file mode 100644 index 000000000..903bee935 --- /dev/null +++ b/_images/inheritance-0b0e4f4d974f7dd43f7e689b18e1b82be82f3997.svg @@ -0,0 +1,74 @@ + + +inheritancefc4f5bd18c + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +Obj + + +Obj + + + + + +DocumentedEntityMixin->Obj + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Obj + + + + + +MultipleNamedEntityMixin + + +MultipleNamedEntityMixin + + + + + +MultipleNamedEntityMixin->Obj + + + + + +SharedVariable + + +SharedVariable + + + + + +Obj->SharedVariable + + + + + \ No newline at end of file diff --git a/_images/inheritance-0c2c6d79181fab15deedb06542f1e109eb3bdcc1.svg b/_images/inheritance-0c2c6d79181fab15deedb06542f1e109eb3bdcc1.svg new file mode 100644 index 000000000..26b93f5a9 --- /dev/null +++ b/_images/inheritance-0c2c6d79181fab15deedb06542f1e109eb3bdcc1.svg @@ -0,0 +1,74 @@ + + +inheritance11ec8a2b36 + + +BaseCase + + +BaseCase + + + + + +SequentialCase + + +SequentialCase + + + + + +BaseCase->SequentialCase + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseCase + + + + + +OthersCase + + +OthersCase + + + + + +SequentialCase->OthersCase + + + + + +SequentialStatementsMixin + + +SequentialStatementsMixin + + + + + +SequentialStatementsMixin->SequentialCase + + + + + \ No newline at end of file diff --git a/_images/inheritance-0c8833ead8d4b27533251231dba9022558ea07e9.svg b/_images/inheritance-0c8833ead8d4b27533251231dba9022558ea07e9.svg new file mode 100644 index 000000000..25ac4aeae --- /dev/null +++ b/_images/inheritance-0c8833ead8d4b27533251231dba9022558ea07e9.svg @@ -0,0 +1,44 @@ + + +inheritanced80b3cd419 + + +ModelEntity + + +ModelEntity + + + + + +Name + + +Name + + + + + +ModelEntity->Name + + + + + +OpenName + + +OpenName + + + + + +Name->OpenName + + + + + \ No newline at end of file diff --git a/_images/inheritance-0c9d89c29afeb27c6a075be42635d3f804bc9fd8.svg b/_images/inheritance-0c9d89c29afeb27c6a075be42635d3f804bc9fd8.svg new file mode 100644 index 000000000..1f3ff9625 --- /dev/null +++ b/_images/inheritance-0c9d89c29afeb27c6a075be42635d3f804bc9fd8.svg @@ -0,0 +1,74 @@ + + +inheritance5070b1170e + + +BaseExpression + + +BaseExpression + + + + + +BinaryExpression + + +BinaryExpression + + + + + +BaseExpression->BinaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +ShiftExpression + + +ShiftExpression + + + + + +BinaryExpression->ShiftExpression + + + + + +ShiftLogicExpression + + +ShiftLogicExpression + + + + + +ShiftExpression->ShiftLogicExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-0d39846c2b8fe1fe779b3420a677ed382589703b.svg b/_images/inheritance-0d39846c2b8fe1fe779b3420a677ed382589703b.svg new file mode 100644 index 000000000..9ecda2c49 --- /dev/null +++ b/_images/inheritance-0d39846c2b8fe1fe779b3420a677ed382589703b.svg @@ -0,0 +1,59 @@ + + +inheritance876a801865 + + +BranchMixin + + +BranchMixin + + + + + +ConditionalBranchMixin + + +ConditionalBranchMixin + + + + + +BranchMixin->ConditionalBranchMixin + + + + + +ElsifBranchMixin + + +ElsifBranchMixin + + + + + +ConditionalBranchMixin->ElsifBranchMixin + + + + + +ConditionalMixin + + +ConditionalMixin + + + + + +ConditionalMixin->ConditionalBranchMixin + + + + + \ No newline at end of file diff --git a/_images/inheritance-0d3e476d38ee0b82c2e04bc03d4f54ea251081d8.svg b/_images/inheritance-0d3e476d38ee0b82c2e04bc03d4f54ea251081d8.svg new file mode 100644 index 000000000..ff77032cf --- /dev/null +++ b/_images/inheritance-0d3e476d38ee0b82c2e04bc03d4f54ea251081d8.svg @@ -0,0 +1,44 @@ + + +inheritance1f21125056 + + +BaseExpression + + +BaseExpression + + + + + +BinaryExpression + + +BinaryExpression + + + + + +BaseExpression->BinaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-0d47a136982ce86a14814872cbbf083b82a935c8.svg b/_images/inheritance-0d47a136982ce86a14814872cbbf083b82a935c8.svg new file mode 100644 index 000000000..cc2765801 --- /dev/null +++ b/_images/inheritance-0d47a136982ce86a14814872cbbf083b82a935c8.svg @@ -0,0 +1,164 @@ + + +inheritance89b3d15da2 + + +ConcurrentDeclarationRegionMixin + + +ConcurrentDeclarationRegionMixin + + + + + +PackageBody + + +PackageBody + + + + + +ConcurrentDeclarationRegionMixin->PackageBody + + + + + +DesignUnit + + +DesignUnit + + + + + +SecondaryUnit + + +SecondaryUnit + + + + + +DesignUnit->SecondaryUnit + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->DesignUnit + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->DesignUnit + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->DesignUnit + + + + + +DesignUnitWithContextMixin + + +DesignUnitWithContextMixin + + + + + +DesignUnitWithContextMixin->PackageBody + + + + + +Numeric_Std_Unsigned_Body + + +Numeric_Std_Unsigned_Body + + + + + +PredefinedPackageBody + + +PredefinedPackageBody + + + + + +PredefinedPackageBody->Numeric_Std_Unsigned_Body + + + + + +PackageBody->PredefinedPackageBody + + + + + +SecondaryUnit->PackageBody + + + + + +PredefinedPackageMixin + + +PredefinedPackageMixin + + + + + +PredefinedPackageMixin->PredefinedPackageBody + + + + + \ No newline at end of file diff --git a/_images/inheritance-1010aa19c3495a18a2a99b4898ca9c594b1d75cf.svg b/_images/inheritance-1010aa19c3495a18a2a99b4898ca9c594b1d75cf.svg new file mode 100644 index 000000000..349dde3ae --- /dev/null +++ b/_images/inheritance-1010aa19c3495a18a2a99b4898ca9c594b1d75cf.svg @@ -0,0 +1,104 @@ + + +inheritance3649c7a88a + + +ConditionalMixin + + +ConditionalMixin + + + + + +LoopControlStatement + + +LoopControlStatement + + + + + +ConditionalMixin->LoopControlStatement + + + + + +ExitStatement + + +ExitStatement + + + + + +LoopControlStatement->ExitStatement + + + + + +LabeledEntityMixin + + +LabeledEntityMixin + + + + + +Statement + + +Statement + + + + + +LabeledEntityMixin->Statement + + + + + +SequentialStatement + + +SequentialStatement + + + + + +SequentialStatement->LoopControlStatement + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Statement + + + + + +Statement->SequentialStatement + + + + + \ No newline at end of file diff --git a/_images/inheritance-113b49db802df87a047e2a20160cbbf8ba8967b4.svg b/_images/inheritance-113b49db802df87a047e2a20160cbbf8ba8967b4.svg new file mode 100644 index 000000000..b459fd660 --- /dev/null +++ b/_images/inheritance-113b49db802df87a047e2a20160cbbf8ba8967b4.svg @@ -0,0 +1,104 @@ + + +inheritanceb6d84a57c3 + + +DesignUnit + + +DesignUnit + + + + + +PrimaryUnit + + +PrimaryUnit + + + + + +DesignUnit->PrimaryUnit + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->DesignUnit + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->DesignUnit + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->DesignUnit + + + + + +PSLPrimaryUnit + + +PSLPrimaryUnit + + + + + +VerificationUnit + + +VerificationUnit + + + + + +PSLPrimaryUnit->VerificationUnit + + + + + +PrimaryUnit->PSLPrimaryUnit + + + + + \ No newline at end of file diff --git a/_images/inheritance-11a9f06d57f611e0f42f54eb0fc7c1f2fd8db042.svg b/_images/inheritance-11a9f06d57f611e0f42f54eb0fc7c1f2fd8db042.svg new file mode 100644 index 000000000..4fe058c2d --- /dev/null +++ b/_images/inheritance-11a9f06d57f611e0f42f54eb0fc7c1f2fd8db042.svg @@ -0,0 +1,104 @@ + + +inheritance96607a2eab + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +Subprogram + + +Subprogram + + + + + +DocumentedEntityMixin->Subprogram + + + + + +MethodMixin + + +MethodMixin + + + + + +ProcedureMethod + + +ProcedureMethod + + + + + +MethodMixin->ProcedureMethod + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Subprogram + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->Subprogram + + + + + +Procedure + + +Procedure + + + + + +Procedure->ProcedureMethod + + + + + +Subprogram->Procedure + + + + + \ No newline at end of file diff --git a/_images/inheritance-1228712660ac2583accc7c64453dae1953cdda7d.svg b/_images/inheritance-1228712660ac2583accc7c64453dae1953cdda7d.svg new file mode 100644 index 000000000..4355f3a3d --- /dev/null +++ b/_images/inheritance-1228712660ac2583accc7c64453dae1953cdda7d.svg @@ -0,0 +1,59 @@ + + +inheritancea4789ed5b9 + + +BaseExpression + + +BaseExpression + + + + + +UnaryExpression + + +UnaryExpression + + + + + +BaseExpression->UnaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +UnaryAndExpression + + +UnaryAndExpression + + + + + +UnaryExpression->UnaryAndExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-12d63b4c170d35457cd5752c3c39dad28db2b6ca.svg b/_images/inheritance-12d63b4c170d35457cd5752c3c39dad28db2b6ca.svg new file mode 100644 index 000000000..e672fb16e --- /dev/null +++ b/_images/inheritance-12d63b4c170d35457cd5752c3c39dad28db2b6ca.svg @@ -0,0 +1,44 @@ + + +inheritance5e1b84ab8b + + +AssertStatementMixin + + +AssertStatementMixin + + + + + +ReportStatementMixin + + +ReportStatementMixin + + + + + +ReportStatementMixin->AssertStatementMixin + + + + + +ConditionalMixin + + +ConditionalMixin + + + + + +ConditionalMixin->AssertStatementMixin + + + + + \ No newline at end of file diff --git a/_images/inheritance-12e25d62f0e0a14aef5f0e5fb5751c44baee6269.svg b/_images/inheritance-12e25d62f0e0a14aef5f0e5fb5751c44baee6269.svg new file mode 100644 index 000000000..d609e6d4e --- /dev/null +++ b/_images/inheritance-12e25d62f0e0a14aef5f0e5fb5751c44baee6269.svg @@ -0,0 +1,74 @@ + + +inheritance155a8126cf + + +Ieee + + +Ieee + + + + + +PredefinedLibrary + + +PredefinedLibrary + + + + + +PredefinedLibrary->Ieee + + + + + +Library + + +Library + + + + + +Library->PredefinedLibrary + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Library + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->Library + + + + + \ No newline at end of file diff --git a/_images/inheritance-132069306b633cdd31e87004ec028b708b8852ca.svg b/_images/inheritance-132069306b633cdd31e87004ec028b708b8852ca.svg new file mode 100644 index 000000000..ada04347b --- /dev/null +++ b/_images/inheritance-132069306b633cdd31e87004ec028b708b8852ca.svg @@ -0,0 +1,29 @@ + + +inheritance00bac13ca2 + + +AggregateElement + + +AggregateElement + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->AggregateElement + + + + + \ No newline at end of file diff --git a/_images/inheritance-1342d46b23ba8757165a0d5162d68e8908de91ce.svg b/_images/inheritance-1342d46b23ba8757165a0d5162d68e8908de91ce.svg new file mode 100644 index 000000000..18c3150dc --- /dev/null +++ b/_images/inheritance-1342d46b23ba8757165a0d5162d68e8908de91ce.svg @@ -0,0 +1,44 @@ + + +inheritancec3d93ba094 + + +LibraryClause + + +LibraryClause + + + + + +Reference + + +Reference + + + + + +Reference->LibraryClause + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Reference + + + + + \ No newline at end of file diff --git a/_images/inheritance-1389cebb5395fde485483b3f308ec58038cd3b3a.svg b/_images/inheritance-1389cebb5395fde485483b3f308ec58038cd3b3a.svg new file mode 100644 index 000000000..9b19d48de --- /dev/null +++ b/_images/inheritance-1389cebb5395fde485483b3f308ec58038cd3b3a.svg @@ -0,0 +1,74 @@ + + +inheritance5e131b75c5 + + +CompoundStatement + + +CompoundStatement + + + + + +SequentialStatement + + +SequentialStatement + + + + + +SequentialStatement->CompoundStatement + + + + + +LabeledEntityMixin + + +LabeledEntityMixin + + + + + +Statement + + +Statement + + + + + +LabeledEntityMixin->Statement + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Statement + + + + + +Statement->SequentialStatement + + + + + \ No newline at end of file diff --git a/_images/inheritance-13aff1d5aa1d4ea4511724fffaafd205e7f66248.svg b/_images/inheritance-13aff1d5aa1d4ea4511724fffaafd205e7f66248.svg new file mode 100644 index 000000000..057632352 --- /dev/null +++ b/_images/inheritance-13aff1d5aa1d4ea4511724fffaafd205e7f66248.svg @@ -0,0 +1,44 @@ + + +inheritance3188172b24 + + +Library + + +Library + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Library + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->Library + + + + + \ No newline at end of file diff --git a/_images/inheritance-151f6109542617a8b8b0682111524fe84d70396f.svg b/_images/inheritance-151f6109542617a8b8b0682111524fe84d70396f.svg new file mode 100644 index 000000000..2cc2358f0 --- /dev/null +++ b/_images/inheritance-151f6109542617a8b8b0682111524fe84d70396f.svg @@ -0,0 +1,89 @@ + + +inheritance6db9cdd8fd + + +BaseExpression + + +BaseExpression + + + + + +BinaryExpression + + +BinaryExpression + + + + + +BaseExpression->BinaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +RelationalExpression + + +RelationalExpression + + + + + +BinaryExpression->RelationalExpression + + + + + +MatchingLessThanExpression + + +MatchingLessThanExpression + + + + + +MatchingRelationalExpression + + +MatchingRelationalExpression + + + + + +MatchingRelationalExpression->MatchingLessThanExpression + + + + + +RelationalExpression->MatchingRelationalExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-15b58ac795168ee90e342f0770fd1cf435b72cd1.svg b/_images/inheritance-15b58ac795168ee90e342f0770fd1cf435b72cd1.svg new file mode 100644 index 000000000..2a15191d1 --- /dev/null +++ b/_images/inheritance-15b58ac795168ee90e342f0770fd1cf435b72cd1.svg @@ -0,0 +1,14 @@ + + +inheritance18f3c57d85 + + +NumericTypeMixin + + +NumericTypeMixin + + + + + \ No newline at end of file diff --git a/_images/inheritance-15c47244a7507d4b462b429f5ef6030aa334bc88.svg b/_images/inheritance-15c47244a7507d4b462b429f5ef6030aa334bc88.svg new file mode 100644 index 000000000..0c3499980 --- /dev/null +++ b/_images/inheritance-15c47244a7507d4b462b429f5ef6030aa334bc88.svg @@ -0,0 +1,164 @@ + + +inheritance1245085526 + + +ConcurrentDeclarationRegionMixin + + +ConcurrentDeclarationRegionMixin + + + + + +PackageBody + + +PackageBody + + + + + +ConcurrentDeclarationRegionMixin->PackageBody + + + + + +DesignUnit + + +DesignUnit + + + + + +SecondaryUnit + + +SecondaryUnit + + + + + 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000000000..8eef9d4dc --- /dev/null +++ b/_images/inheritance-15d0de86326c14e4b069b73da92f612fbb7b4454.svg @@ -0,0 +1,74 @@ + + +inheritance3cebad2fac + + +BaseExpression + + +BaseExpression + + + + + +Literal + + +Literal + + + + + +BaseExpression->Literal + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +NumericLiteral + + +NumericLiteral + + + + + +Literal->NumericLiteral + + + + + +PhysicalLiteral + + +PhysicalLiteral + + + + + +NumericLiteral->PhysicalLiteral + + + + + \ No newline at end of file diff --git a/_images/inheritance-15f933be1058bb9eeaade21c81f2d4980d35aeba.svg b/_images/inheritance-15f933be1058bb9eeaade21c81f2d4980d35aeba.svg new file mode 100644 index 000000000..4db4a45f8 --- /dev/null +++ b/_images/inheritance-15f933be1058bb9eeaade21c81f2d4980d35aeba.svg @@ -0,0 +1,14 @@ + + +inheritance37f67d789c + + +InterfaceItemWithModeMixin + + +InterfaceItemWithModeMixin + + + + + \ No newline at end of file diff --git a/_images/inheritance-175a775e48905bcda4e0bcb570a17a39198dd84e.svg b/_images/inheritance-175a775e48905bcda4e0bcb570a17a39198dd84e.svg new file mode 100644 index 000000000..0405b1ed3 --- /dev/null +++ b/_images/inheritance-175a775e48905bcda4e0bcb570a17a39198dd84e.svg @@ -0,0 +1,44 @@ + + +inheritancea3bc8179f1 + + +AttributeName + + +AttributeName + + + + + +Name + + +Name + + + + + +Name->AttributeName + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Name + + + + + \ No newline at end of file diff --git a/_images/inheritance-178c2a75f22f52bbd2678fd9f0f2bbd0259c3cc0.svg b/_images/inheritance-178c2a75f22f52bbd2678fd9f0f2bbd0259c3cc0.svg new file mode 100644 index 000000000..1e5d4fb73 --- /dev/null +++ b/_images/inheritance-178c2a75f22f52bbd2678fd9f0f2bbd0259c3cc0.svg @@ -0,0 +1,74 @@ + + +inheritance63237a36c1 + + +ConcurrentStatement + + +ConcurrentStatement + + + + + +Instantiation + + +Instantiation + + + + + +ConcurrentStatement->Instantiation + + + + + +Statement + + +Statement + + + + + +Statement->ConcurrentStatement + + + + + +LabeledEntityMixin + + +LabeledEntityMixin + + + + + +LabeledEntityMixin->Statement + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Statement + + + + + \ No newline at end of file diff --git a/_images/inheritance-17d4ce3121167d0b6bd001c3a82d37c6d924a365.svg b/_images/inheritance-17d4ce3121167d0b6bd001c3a82d37c6d924a365.svg new file mode 100644 index 000000000..a1624a6c3 --- /dev/null +++ b/_images/inheritance-17d4ce3121167d0b6bd001c3a82d37c6d924a365.svg @@ -0,0 +1,29 @@ + + +inheritance1de42c24c8 + + +AllPackageMembersReferenceSymbol + + +AllPackageMembersReferenceSymbol + + + + + +Symbol + + +Symbol + + + + + +Symbol->AllPackageMembersReferenceSymbol + + + + + \ No newline at end of file diff --git a/_images/inheritance-180bb7e0443f2da93f5560edc649db9ba772a7f6.svg b/_images/inheritance-180bb7e0443f2da93f5560edc649db9ba772a7f6.svg new file mode 100644 index 000000000..a03a68f3d --- /dev/null +++ b/_images/inheritance-180bb7e0443f2da93f5560edc649db9ba772a7f6.svg @@ -0,0 +1,104 @@ + + +inheritanced5e4cb1a53 + + +AssignmentMixin + + +AssignmentMixin + + + + + +VariableAssignmentMixin + + +VariableAssignmentMixin + + + + + +AssignmentMixin->VariableAssignmentMixin + + + + + +LabeledEntityMixin + + +LabeledEntityMixin + + + + + +Statement + + +Statement + + + + + +LabeledEntityMixin->Statement + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Statement + + + + + +SequentialStatement + + +SequentialStatement + + + + + +SequentialVariableAssignment + + +SequentialVariableAssignment + + + + + +SequentialStatement->SequentialVariableAssignment + + + + + +Statement->SequentialStatement + + + + + +VariableAssignmentMixin->SequentialVariableAssignment + + + + + \ No newline at end of file diff --git a/_images/inheritance-182a7afe0115a1eca5e7f1fdea1235c2aa23c131.svg b/_images/inheritance-182a7afe0115a1eca5e7f1fdea1235c2aa23c131.svg new file mode 100644 index 000000000..a18df7190 --- /dev/null +++ b/_images/inheritance-182a7afe0115a1eca5e7f1fdea1235c2aa23c131.svg @@ -0,0 +1,59 @@ + + +inheritancec36240a18f + + +BaseExpression + + +BaseExpression + + + + + +UnaryExpression + + +UnaryExpression + + + + + +BaseExpression->UnaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +NegationExpression + + +NegationExpression + + + + + +UnaryExpression->NegationExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-1864f8e3455cfc10ab24f66e6b81ae018ae14d99.svg b/_images/inheritance-1864f8e3455cfc10ab24f66e6b81ae018ae14d99.svg new file mode 100644 index 000000000..e92912a77 --- /dev/null +++ b/_images/inheritance-1864f8e3455cfc10ab24f66e6b81ae018ae14d99.svg @@ -0,0 +1,59 @@ + + +inheritance34ff4199ac + + +BaseExpression + + +BaseExpression + + + + + +Literal + + +Literal + + + + + +BaseExpression->Literal + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +StringLiteral + + +StringLiteral + + + + + +Literal->StringLiteral + + + + + \ No newline at end of file diff --git a/_images/inheritance-187f2fdc5c5b221c13ff12011313de8ffccfeb13.svg b/_images/inheritance-187f2fdc5c5b221c13ff12011313de8ffccfeb13.svg new file mode 100644 index 000000000..2b0977f9d --- /dev/null +++ b/_images/inheritance-187f2fdc5c5b221c13ff12011313de8ffccfeb13.svg @@ -0,0 +1,119 @@ + + +inheritance9583803eb5 + + +AssignmentMixin + + +AssignmentMixin + + + + + +SignalAssignmentMixin + + +SignalAssignmentMixin + + + + + +AssignmentMixin->SignalAssignmentMixin + + + + + +LabeledEntityMixin + + +LabeledEntityMixin + + + + + +Statement + + +Statement + + + + + +LabeledEntityMixin->Statement + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Statement + + + + + +SequentialSignalAssignment + + +SequentialSignalAssignment + + + + + +SequentialSimpleSignalAssignment + + +SequentialSimpleSignalAssignment + + + + + +SequentialSignalAssignment->SequentialSimpleSignalAssignment + + + + + +SequentialStatement + + +SequentialStatement + + + + + +SequentialStatement->SequentialSignalAssignment + + + + + +SignalAssignmentMixin->SequentialSignalAssignment + + + + + +Statement->SequentialStatement + + + + + \ No newline at end of file diff --git a/_images/inheritance-18a98c66c431455442d47341e81b36da692143a2.svg b/_images/inheritance-18a98c66c431455442d47341e81b36da692143a2.svg new file mode 100644 index 000000000..11fb674d4 --- /dev/null +++ b/_images/inheritance-18a98c66c431455442d47341e81b36da692143a2.svg @@ -0,0 +1,74 @@ + + +inheritanceb7c00ef165 + + +AddingExpression + + +AddingExpression + + + + + +AdditionExpression + + +AdditionExpression + + + + + +AddingExpression->AdditionExpression + + + + + +BinaryExpression + + +BinaryExpression + + + + + +BinaryExpression->AddingExpression + + + + + +BaseExpression + + +BaseExpression + + + + + +BaseExpression->BinaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-18b23f2490c2c047b6ff7ac98fd49b56adce6dcd.svg b/_images/inheritance-18b23f2490c2c047b6ff7ac98fd49b56adce6dcd.svg new file mode 100644 index 000000000..74c5ee333 --- /dev/null +++ b/_images/inheritance-18b23f2490c2c047b6ff7ac98fd49b56adce6dcd.svg @@ -0,0 +1,44 @@ + + +inheritance8926ecf18e + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +InterfaceItemMixin + + +InterfaceItemMixin + + + + + +DocumentedEntityMixin->InterfaceItemMixin + + + + + +GenericInterfaceItemMixin + + +GenericInterfaceItemMixin + + + + + +InterfaceItemMixin->GenericInterfaceItemMixin + + + + + \ No newline at end of file diff --git a/_images/inheritance-18cef8b3c5866c45906165d4495ee94e2f5708a3.svg b/_images/inheritance-18cef8b3c5866c45906165d4495ee94e2f5708a3.svg new file mode 100644 index 000000000..694f120a2 --- /dev/null +++ b/_images/inheritance-18cef8b3c5866c45906165d4495ee94e2f5708a3.svg @@ -0,0 +1,59 @@ + + +inheritance39547e52b0 + + +BaseExpression + + +BaseExpression + + + + + +BinaryExpression + + +BinaryExpression + + + + + +BaseExpression->BinaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +RangeExpression + + +RangeExpression + + + + + +BinaryExpression->RangeExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-1c4b4d91aa054c48abed5aa6735c28581318b628.svg b/_images/inheritance-1c4b4d91aa054c48abed5aa6735c28581318b628.svg new file mode 100644 index 000000000..56e08cb24 --- /dev/null +++ b/_images/inheritance-1c4b4d91aa054c48abed5aa6735c28581318b628.svg @@ -0,0 +1,74 @@ + + +inheritance050071eba9 + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +Obj + + +Obj + + + + + +DocumentedEntityMixin->Obj + + + + + +File + + +File + + + + + +Obj->File + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Obj + + + + + +MultipleNamedEntityMixin + + +MultipleNamedEntityMixin + + + + + +MultipleNamedEntityMixin->Obj + + + + + \ No newline at end of file diff --git a/_images/inheritance-1c570ed062fd4bc5d70781e96884f7d553046939.svg b/_images/inheritance-1c570ed062fd4bc5d70781e96884f7d553046939.svg new file mode 100644 index 000000000..2e0a99fb0 --- /dev/null +++ b/_images/inheritance-1c570ed062fd4bc5d70781e96884f7d553046939.svg @@ -0,0 +1,29 @@ + + +inheritancef7b44a1117 + + +PackageMemberReferenceSymbol + + +PackageMemberReferenceSymbol + + + + + +Symbol + + +Symbol + + + + + +Symbol->PackageMemberReferenceSymbol + + + + + \ No newline at end of file diff --git a/_images/inheritance-1c7f0dd9728e6b4c822f1d6a78aa9a07842d076c.svg b/_images/inheritance-1c7f0dd9728e6b4c822f1d6a78aa9a07842d076c.svg new file mode 100644 index 000000000..a76c07885 --- /dev/null +++ b/_images/inheritance-1c7f0dd9728e6b4c822f1d6a78aa9a07842d076c.svg @@ -0,0 +1,14 @@ + + +inheritance612701535b + + +PredefinedPackageMixin + + +PredefinedPackageMixin + + + + + \ No newline at end of file diff --git a/_images/inheritance-1ce6cc746313908b89c2b9622d7583a6aeefa0e0.svg b/_images/inheritance-1ce6cc746313908b89c2b9622d7583a6aeefa0e0.svg new file mode 100644 index 000000000..277007142 --- /dev/null +++ b/_images/inheritance-1ce6cc746313908b89c2b9622d7583a6aeefa0e0.svg @@ -0,0 +1,14 @@ + + +inheritancec3afef9e32 + + +MethodMixin + + +MethodMixin + + + + + \ No newline at end of file diff --git a/_images/inheritance-1cf081509fe3654e790dc4ad9da6ba976146f83d.svg b/_images/inheritance-1cf081509fe3654e790dc4ad9da6ba976146f83d.svg new file mode 100644 index 000000000..1240393a6 --- /dev/null +++ b/_images/inheritance-1cf081509fe3654e790dc4ad9da6ba976146f83d.svg @@ -0,0 +1,164 @@ + + +inheritancea56eb4de4f + + +ConcurrentDeclarationRegionMixin + + +ConcurrentDeclarationRegionMixin + + + + + +PackageBody + + +PackageBody + + + + + +ConcurrentDeclarationRegionMixin->PackageBody + + + + + +DesignUnit + + +DesignUnit + + + + + +SecondaryUnit + + +SecondaryUnit + + + + + +DesignUnit->SecondaryUnit + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->DesignUnit + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->DesignUnit + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->DesignUnit + + + + + +DesignUnitWithContextMixin + + +DesignUnitWithContextMixin + + + + + +DesignUnitWithContextMixin->PackageBody + + + + + +Math_Complex_Body + + +Math_Complex_Body + + + + + +PredefinedPackageBody + + +PredefinedPackageBody + + + + + +PredefinedPackageBody->Math_Complex_Body + + + + + +PackageBody->PredefinedPackageBody + + + + + +SecondaryUnit->PackageBody + + + + + +PredefinedPackageMixin + + +PredefinedPackageMixin + + + + + +PredefinedPackageMixin->PredefinedPackageBody + + + + + \ No newline at end of file diff --git a/_images/inheritance-1e80772bb7e0cc278be34bfc8347683f334a7f33.svg b/_images/inheritance-1e80772bb7e0cc278be34bfc8347683f334a7f33.svg new file mode 100644 index 000000000..f672bd217 --- /dev/null +++ b/_images/inheritance-1e80772bb7e0cc278be34bfc8347683f334a7f33.svg @@ -0,0 +1,44 @@ + + +inheritanced3a92d1c32 + + +DependencyGraphVertexKind + + +DependencyGraphVertexKind + + + + + +Flag + + +Flag + + + + + +Flag->DependencyGraphVertexKind + + + + + +Enum + + +Enum + + + + + +Enum->Flag + + + + + \ No newline at end of file diff --git a/_images/inheritance-1fb290bfc9aeca1bfd1a443fc9079c7e7e95c929.svg b/_images/inheritance-1fb290bfc9aeca1bfd1a443fc9079c7e7e95c929.svg new file mode 100644 index 000000000..a95fd37d3 --- /dev/null +++ b/_images/inheritance-1fb290bfc9aeca1bfd1a443fc9079c7e7e95c929.svg @@ -0,0 +1,14 @@ + + +inheritancef12c847272 + + +ConditionalMixin + + +ConditionalMixin + + + + + \ No newline at end of file diff --git a/_images/inheritance-202e92f5acb84bdb811abf8976588af7cc1e52c8.svg b/_images/inheritance-202e92f5acb84bdb811abf8976588af7cc1e52c8.svg new file mode 100644 index 000000000..95ef40189 --- /dev/null +++ b/_images/inheritance-202e92f5acb84bdb811abf8976588af7cc1e52c8.svg @@ -0,0 +1,164 @@ + + +inheritance8e987e798f + + +ConcurrentDeclarationRegionMixin + + +ConcurrentDeclarationRegionMixin + + + + + +Package + + +Package + + + + + +ConcurrentDeclarationRegionMixin->Package + + + + + +DesignUnit + + +DesignUnit + + + + + +PrimaryUnit + + +PrimaryUnit + + + + + +DesignUnit->PrimaryUnit + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->DesignUnit + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->DesignUnit + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->DesignUnit + + + + + +DesignUnitWithContextMixin + + +DesignUnitWithContextMixin + + + + + +DesignUnitWithContextMixin->Package + + + + + +Numeric_Bit + + +Numeric_Bit + + + + + +PredefinedPackage + + +PredefinedPackage + + + + + +PredefinedPackage->Numeric_Bit + + + + + +Package->PredefinedPackage + + + + + +PrimaryUnit->Package + + + + + +PredefinedPackageMixin + + +PredefinedPackageMixin + + + + + +PredefinedPackageMixin->PredefinedPackage + + + + + \ No newline at end of file diff --git a/_images/inheritance-21f781b72f160c379da6dfa912ff9c567c3d3378.svg b/_images/inheritance-21f781b72f160c379da6dfa912ff9c567c3d3378.svg new file mode 100644 index 000000000..163a48f90 --- /dev/null +++ b/_images/inheritance-21f781b72f160c379da6dfa912ff9c567c3d3378.svg @@ -0,0 +1,59 @@ + + +inheritance134110668c + + +ConstrainedArraySubtypeSymbol + + +ConstrainedArraySubtypeSymbol + + + + + +ConstrainedCompositeSubtypeSymbol + + +ConstrainedCompositeSubtypeSymbol + + + + + +ConstrainedCompositeSubtypeSymbol->ConstrainedArraySubtypeSymbol + + + + + +SubtypeSymbol + + +SubtypeSymbol + + + + + +SubtypeSymbol->ConstrainedCompositeSubtypeSymbol + + + + + +Symbol + + +Symbol + + + + + +Symbol->SubtypeSymbol + + + + + \ No newline at end of file diff --git a/_images/inheritance-253c9bff5358fc8edf26a5b3c30b985fb606c92a.svg b/_images/inheritance-253c9bff5358fc8edf26a5b3c30b985fb606c92a.svg new file mode 100644 index 000000000..4854c89d2 --- /dev/null +++ b/_images/inheritance-253c9bff5358fc8edf26a5b3c30b985fb606c92a.svg @@ -0,0 +1,119 @@ + + +inheritancea148513133 + + +AssertStatementMixin + + +AssertStatementMixin + + + + + +ConcurrentAssertStatement + + +ConcurrentAssertStatement + + + + + +AssertStatementMixin->ConcurrentAssertStatement + + + + + +ReportStatementMixin + + +ReportStatementMixin + + + + + +ReportStatementMixin->AssertStatementMixin + + + + + +ConditionalMixin + + +ConditionalMixin + + + + + +ConditionalMixin->AssertStatementMixin + + + + + +ConcurrentStatement + + +ConcurrentStatement + + + + + +ConcurrentStatement->ConcurrentAssertStatement + + + + + +Statement + + +Statement + + + + + +Statement->ConcurrentStatement + + + + + +LabeledEntityMixin + + +LabeledEntityMixin + + + + + +LabeledEntityMixin->Statement + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Statement + + + + + \ No newline at end of file diff --git a/_images/inheritance-263888a426e81f8c0f457568f767c191f532b002.svg b/_images/inheritance-263888a426e81f8c0f457568f767c191f532b002.svg new file mode 100644 index 000000000..6816436ec --- /dev/null +++ b/_images/inheritance-263888a426e81f8c0f457568f767c191f532b002.svg @@ -0,0 +1,29 @@ + + +inheritance912e238f28 + + +BaseChoice + + +BaseChoice + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseChoice + + + + + \ No newline at end of file diff --git a/_images/inheritance-2662969a7a47741c8643e01f04eeff524a99ec57.svg b/_images/inheritance-2662969a7a47741c8643e01f04eeff524a99ec57.svg new file mode 100644 index 000000000..c89ff57a7 --- /dev/null +++ b/_images/inheritance-2662969a7a47741c8643e01f04eeff524a99ec57.svg @@ -0,0 +1,29 @@ + + +inheritance013f8574a8 + + +ReferencedLibraryNotExistingError + + +ReferencedLibraryNotExistingError + + + + + +VHDLModelException + + +VHDLModelException + + + + + +VHDLModelException->ReferencedLibraryNotExistingError + + + + + \ No newline at end of file diff --git a/_images/inheritance-271a09a9f6796315acb432a4260c8199a18da5ce.svg b/_images/inheritance-271a09a9f6796315acb432a4260c8199a18da5ce.svg new file mode 100644 index 000000000..dbbe74278 --- /dev/null +++ b/_images/inheritance-271a09a9f6796315acb432a4260c8199a18da5ce.svg @@ -0,0 +1,134 @@ + + +inheritancedd69a9697d + + +BaseType + + +BaseType + + + + + +FullType + + +FullType + + + + + +BaseType->FullType + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseType + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->BaseType + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->BaseType + + + + + +ScalarType + + +ScalarType + + + + + +FullType->ScalarType + + + + + +NumericTypeMixin + + +NumericTypeMixin + + + + + +PhysicalType + + +PhysicalType + + + + + +NumericTypeMixin->PhysicalType + + + + + +RangedScalarType + + +RangedScalarType + + + + + +RangedScalarType->PhysicalType + + + + + +ScalarType->RangedScalarType + + + + + \ No newline at end of file diff --git a/_images/inheritance-272820532c1f2a29a0a8fa2672fb7231a3a612a9.svg b/_images/inheritance-272820532c1f2a29a0a8fa2672fb7231a3a612a9.svg new file mode 100644 index 000000000..fe413707c --- /dev/null +++ b/_images/inheritance-272820532c1f2a29a0a8fa2672fb7231a3a612a9.svg @@ -0,0 +1,104 @@ + + +inheritancee51f542c3c + + +CompoundStatement + + +CompoundStatement + + + + + +LoopStatement + + +LoopStatement + + + + + +CompoundStatement->LoopStatement + + + + + +SequentialStatement + + +SequentialStatement + + + + + +SequentialStatement->CompoundStatement + + + + + +LabeledEntityMixin + + +LabeledEntityMixin + + + + + +Statement + + +Statement + + + + + +LabeledEntityMixin->Statement + + + + + +SequentialStatementsMixin + + +SequentialStatementsMixin + + + + + +SequentialStatementsMixin->LoopStatement + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Statement + + + + + +Statement->SequentialStatement + + + + + \ No newline at end of file diff --git a/_images/inheritance-273c985a8fff3830a5e48d206d1f0dce9ceaada8.svg b/_images/inheritance-273c985a8fff3830a5e48d206d1f0dce9ceaada8.svg new file mode 100644 index 000000000..b6c894fc5 --- /dev/null +++ b/_images/inheritance-273c985a8fff3830a5e48d206d1f0dce9ceaada8.svg @@ -0,0 +1,44 @@ + + +inheritance8983f16ae9 + + +Enum + + +Enum + + + + + +Flag + + +Flag + + + + + +Enum->Flag + + + + + +ObjectGraphEdgeKind + + +ObjectGraphEdgeKind + + + + + +Flag->ObjectGraphEdgeKind + + + + + \ No newline at end of file diff --git a/_images/inheritance-27ddbb742bbe7a6409015dad1a5dc0b72162c378.svg b/_images/inheritance-27ddbb742bbe7a6409015dad1a5dc0b72162c378.svg new file mode 100644 index 000000000..fd2d33965 --- /dev/null +++ b/_images/inheritance-27ddbb742bbe7a6409015dad1a5dc0b72162c378.svg @@ -0,0 +1,89 @@ + + +inheritancebdb60137dc + + +BaseType + + +BaseType + + + + + +FullType + + +FullType + + + + + +BaseType->FullType + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseType + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->BaseType + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->BaseType + + + + + +ProtectedType + + +ProtectedType + + + + + +FullType->ProtectedType + + + + + \ No newline at end of file diff --git a/_images/inheritance-281117b7f4bdfce467350fabe6f639921d0cc3a8.svg b/_images/inheritance-281117b7f4bdfce467350fabe6f639921d0cc3a8.svg new file mode 100644 index 000000000..587d5f205 --- /dev/null +++ b/_images/inheritance-281117b7f4bdfce467350fabe6f639921d0cc3a8.svg @@ -0,0 +1,119 @@ + + +inheritancebc2dd1965d + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +Subprogram + + +Subprogram + + + + + +DocumentedEntityMixin->Subprogram + + + + + +GenericInstantiationMixin + + +GenericInstantiationMixin + + + + + +SubprogramInstantiationMixin + + +SubprogramInstantiationMixin + + + + + +GenericInstantiationMixin->SubprogramInstantiationMixin + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Subprogram + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->Subprogram + + + + + +Procedure + + +Procedure + + + + + +ProcedureInstantiation + + +ProcedureInstantiation + + + + + +Procedure->ProcedureInstantiation + + + + + +Subprogram->Procedure + + + + + +SubprogramInstantiationMixin->ProcedureInstantiation + + + + + \ No newline at end of file diff --git a/_images/inheritance-28541d00129dd53c5b34ae039c8bfe6ca655252a.svg b/_images/inheritance-28541d00129dd53c5b34ae039c8bfe6ca655252a.svg new file mode 100644 index 000000000..bff4a3e54 --- /dev/null +++ b/_images/inheritance-28541d00129dd53c5b34ae039c8bfe6ca655252a.svg @@ -0,0 +1,59 @@ + + +inheritanced40cf71c63 + + +AbsoluteExpression + + +AbsoluteExpression + + + + + +UnaryExpression + + +UnaryExpression + + + + + +UnaryExpression->AbsoluteExpression + + + + + +BaseExpression + + +BaseExpression + + + + + +BaseExpression->UnaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-2905b429671d5369593236667ae1701c683fa2bc.svg b/_images/inheritance-2905b429671d5369593236667ae1701c683fa2bc.svg new file mode 100644 index 000000000..f0bac8017 --- /dev/null +++ b/_images/inheritance-2905b429671d5369593236667ae1701c683fa2bc.svg @@ -0,0 +1,89 @@ + + +inheritance3831631eea + + +BaseExpression + + +BaseExpression + + + + + +Literal + + +Literal + + + + + +BaseExpression->Literal + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +NumericLiteral + + +NumericLiteral + + + + + +Literal->NumericLiteral + + + + + +PhysicalLiteral + + +PhysicalLiteral + + + + + +NumericLiteral->PhysicalLiteral + + + + + +PhysicalFloatingLiteral + + +PhysicalFloatingLiteral + + + + + +PhysicalLiteral->PhysicalFloatingLiteral + + + + + \ No newline at end of file diff --git a/_images/inheritance-290c5d031c21ada9b2cf4f63050e9786996743f7.svg b/_images/inheritance-290c5d031c21ada9b2cf4f63050e9786996743f7.svg new file mode 100644 index 000000000..5132354f4 --- /dev/null +++ b/_images/inheritance-290c5d031c21ada9b2cf4f63050e9786996743f7.svg @@ -0,0 +1,89 @@ + + +inheritance64b1b46af5 + + +BaseExpression + + +BaseExpression + + + + + +BinaryExpression + + +BinaryExpression + + + + + +BaseExpression->BinaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +ShiftExpression + + +ShiftExpression + + + + + +BinaryExpression->ShiftExpression + + + + + +ShiftArithmeticExpression + + +ShiftArithmeticExpression + + + + + +ShiftRightArithmeticExpression + + +ShiftRightArithmeticExpression + + + + + +ShiftArithmeticExpression->ShiftRightArithmeticExpression + + + + + +ShiftExpression->ShiftArithmeticExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-290ee0aca39e13ae279f92b0fc94c4b60fe99461.svg b/_images/inheritance-290ee0aca39e13ae279f92b0fc94c4b60fe99461.svg new file mode 100644 index 000000000..30aece4dc --- /dev/null +++ b/_images/inheritance-290ee0aca39e13ae279f92b0fc94c4b60fe99461.svg @@ -0,0 +1,89 @@ + + +inheritancee4a784ea0d + + +CaseGenerateStatement + + +CaseGenerateStatement + + + + + +GenerateStatement + + +GenerateStatement + + + + + +GenerateStatement->CaseGenerateStatement + + + + + +ConcurrentStatement + + +ConcurrentStatement + + + + + +ConcurrentStatement->GenerateStatement + + + + + +Statement + + +Statement + + + + + +Statement->ConcurrentStatement + + + + + +LabeledEntityMixin + + +LabeledEntityMixin + + + + + +LabeledEntityMixin->Statement + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Statement + + + + + \ No newline at end of file diff --git a/_images/inheritance-29e77464c2079a5b18f73d0d17599200228405c5.svg b/_images/inheritance-29e77464c2079a5b18f73d0d17599200228405c5.svg new file mode 100644 index 000000000..ecc0c34e2 --- /dev/null +++ b/_images/inheritance-29e77464c2079a5b18f73d0d17599200228405c5.svg @@ -0,0 +1,89 @@ + + +inheritance6b912cd543 + + +BaseType + + +BaseType + + + + + +FullType + + +FullType + + + + + +BaseType->FullType + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseType + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->BaseType + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->BaseType + + + + + +FileType + + +FileType + + + + + +FullType->FileType + + + + + \ No newline at end of file diff --git a/_images/inheritance-2a77f087a183e6f01739f013602c51e1e7374d6c.svg b/_images/inheritance-2a77f087a183e6f01739f013602c51e1e7374d6c.svg new file mode 100644 index 000000000..6edf3a17c --- /dev/null +++ b/_images/inheritance-2a77f087a183e6f01739f013602c51e1e7374d6c.svg @@ -0,0 +1,14 @@ + + +inheritanceed470e9ee7 + + +GenericInstantiationMixin + + +GenericInstantiationMixin + + + + + \ No newline at end of file diff --git a/_images/inheritance-2b4002b03054d283d3bbe7021bf9675d31c1555d.svg b/_images/inheritance-2b4002b03054d283d3bbe7021bf9675d31c1555d.svg new file mode 100644 index 000000000..a46cf3d52 --- /dev/null +++ b/_images/inheritance-2b4002b03054d283d3bbe7021bf9675d31c1555d.svg @@ -0,0 +1,59 @@ + + +inheritanceb294d5cf0b + + +ConcurrentStatement + + +ConcurrentStatement + + + + + +Statement + + +Statement + + + + + +Statement->ConcurrentStatement + + + + + +LabeledEntityMixin + + +LabeledEntityMixin + + + + + +LabeledEntityMixin->Statement + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Statement + + + + + \ No newline at end of file diff --git a/_images/inheritance-2b6689144c31d8c1a9ae416470846c2f97eaf08b.svg b/_images/inheritance-2b6689144c31d8c1a9ae416470846c2f97eaf08b.svg new file mode 100644 index 000000000..bc28eaba9 --- /dev/null +++ b/_images/inheritance-2b6689144c31d8c1a9ae416470846c2f97eaf08b.svg @@ -0,0 +1,29 @@ + + +inheritance032a0093b0 + + +Enum + + +Enum + + + + + +VHDLVersion + + +VHDLVersion + + + + + +Enum->VHDLVersion + + + + + \ No newline at end of file diff --git a/_images/inheritance-2b9d1358ca65eeeb96c03ebdea95313c58de7e7d.svg b/_images/inheritance-2b9d1358ca65eeeb96c03ebdea95313c58de7e7d.svg new file mode 100644 index 000000000..34b0b8173 --- /dev/null +++ b/_images/inheritance-2b9d1358ca65eeeb96c03ebdea95313c58de7e7d.svg @@ -0,0 +1,125 @@ + + +inheritance877a8edba2 + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +Obj + + +Obj + + + + + +DocumentedEntityMixin->Obj + + + + + +InterfaceItemMixin + + +InterfaceItemMixin + + + + + +DocumentedEntityMixin->InterfaceItemMixin + + + + + +File + + +File + + + + + +ParameterFileInterfaceItem + + +ParameterFileInterfaceItem + + + + + +File->ParameterFileInterfaceItem + + + + + +Obj->File + + + + + +ParameterInterfaceItemMixin + + +ParameterInterfaceItemMixin + + + + + +InterfaceItemMixin->ParameterInterfaceItemMixin + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Obj + + + + + +MultipleNamedEntityMixin + + +MultipleNamedEntityMixin + + + + + +MultipleNamedEntityMixin->Obj + + + + + +ParameterInterfaceItemMixin->ParameterFileInterfaceItem + + + + + \ No newline at end of file diff --git a/_images/inheritance-2c1be95df9c795155957caa7e909fbd47d57c4b7.svg b/_images/inheritance-2c1be95df9c795155957caa7e909fbd47d57c4b7.svg new file mode 100644 index 000000000..7c184cea2 --- /dev/null +++ b/_images/inheritance-2c1be95df9c795155957caa7e909fbd47d57c4b7.svg @@ -0,0 +1,149 @@ + + +inheritancef8cf8b22ea + + +ConcurrentDeclarationRegionMixin + + +ConcurrentDeclarationRegionMixin + + + + + +Package + + +Package + + + + + +ConcurrentDeclarationRegionMixin->Package + + + + + +DesignUnit + + +DesignUnit + + + + + +PrimaryUnit + + +PrimaryUnit + + + + + +DesignUnit->PrimaryUnit + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->DesignUnit + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->DesignUnit + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->DesignUnit + + + + + +DesignUnitWithContextMixin + + +DesignUnitWithContextMixin + + + + + +DesignUnitWithContextMixin->Package + + + + + +PredefinedPackage + + +PredefinedPackage + + + + + +Package->PredefinedPackage + + + + + +PrimaryUnit->Package + + + + + +PredefinedPackageMixin + + +PredefinedPackageMixin + + + + + +PredefinedPackageMixin->PredefinedPackage + + + + + \ No newline at end of file diff --git a/_images/inheritance-2dfc5c810579fd745f981c806b5447c0d406eca4.svg b/_images/inheritance-2dfc5c810579fd745f981c806b5447c0d406eca4.svg new file mode 100644 index 000000000..6a8bdbdbd --- /dev/null +++ b/_images/inheritance-2dfc5c810579fd745f981c806b5447c0d406eca4.svg @@ -0,0 +1,74 @@ + + +inheritance1106d0f985 + + +BaseExpression + + +BaseExpression + + + + + +BinaryExpression + + +BinaryExpression + + + + + +BaseExpression->BinaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +RelationalExpression + + +RelationalExpression + + + + + +BinaryExpression->RelationalExpression + + + + + +LessEqualExpression + + +LessEqualExpression + + + + + +RelationalExpression->LessEqualExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-2fec4cdabffcf103de26085c1ccfb799cb2ff7da.svg b/_images/inheritance-2fec4cdabffcf103de26085c1ccfb799cb2ff7da.svg new file mode 100644 index 000000000..460d5d5e6 --- /dev/null +++ b/_images/inheritance-2fec4cdabffcf103de26085c1ccfb799cb2ff7da.svg @@ -0,0 +1,74 @@ + + +inheritance30d8251100 + + +BaseExpression + + +BaseExpression + + + + + +BinaryExpression + + +BinaryExpression + + + + + +BaseExpression->BinaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +LogicalExpression + + +LogicalExpression + + + + + +BinaryExpression->LogicalExpression + + + + + +NandExpression + + +NandExpression + + + + + +LogicalExpression->NandExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-31917a07f9c74883b0b071d0950bba17fa4b483e.svg b/_images/inheritance-31917a07f9c74883b0b071d0950bba17fa4b483e.svg new file mode 100644 index 000000000..acf7d1a81 --- /dev/null +++ b/_images/inheritance-31917a07f9c74883b0b071d0950bba17fa4b483e.svg @@ -0,0 +1,29 @@ + + +inheritance58aa68d443 + + +ConfigurationExistsInLibraryError + + +ConfigurationExistsInLibraryError + + + + + +VHDLModelException + + +VHDLModelException + + + + + +VHDLModelException->ConfigurationExistsInLibraryError + + + + + \ No newline at end of file diff --git a/_images/inheritance-31e7f8f47047677be8646afba707211a5d433526.svg b/_images/inheritance-31e7f8f47047677be8646afba707211a5d433526.svg new file mode 100644 index 000000000..975a8845d --- /dev/null +++ b/_images/inheritance-31e7f8f47047677be8646afba707211a5d433526.svg @@ -0,0 +1,74 @@ + + +inheritancecb7d50c04f + + +BaseExpression + + +BaseExpression + + + + + +Literal + + +Literal + + + + + +BaseExpression->Literal + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +FloatingPointLiteral + + +FloatingPointLiteral + + + + + +NumericLiteral + + +NumericLiteral + + + + + +NumericLiteral->FloatingPointLiteral + + + + + +Literal->NumericLiteral + + + + + \ No newline at end of file diff --git a/_images/inheritance-32311b53970bde2eaeacd61d7ee0a98d2cc74b75.svg b/_images/inheritance-32311b53970bde2eaeacd61d7ee0a98d2cc74b75.svg new file mode 100644 index 000000000..f8662cc48 --- /dev/null +++ b/_images/inheritance-32311b53970bde2eaeacd61d7ee0a98d2cc74b75.svg @@ -0,0 +1,44 @@ + + +inheritance70e11edd31 + + +AssociationItem + + +AssociationItem + + + + + +GenericAssociationItem + + +GenericAssociationItem + + + + + +AssociationItem->GenericAssociationItem + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->AssociationItem + + + + + \ No newline at end of file diff --git a/_images/inheritance-34292389c4ec9be3fd551c9350fa31eaaaf86a5e.svg b/_images/inheritance-34292389c4ec9be3fd551c9350fa31eaaaf86a5e.svg new file mode 100644 index 000000000..9f149700c --- /dev/null +++ b/_images/inheritance-34292389c4ec9be3fd551c9350fa31eaaaf86a5e.svg @@ -0,0 +1,89 @@ + + +inheritance3919089eb6 + + +ConditionalMixin + + +ConditionalMixin + + + + + +LoopControlStatement + + +LoopControlStatement + + + + + +ConditionalMixin->LoopControlStatement + + + + + +LabeledEntityMixin + + +LabeledEntityMixin + + + + + +Statement + + +Statement + + + + + +LabeledEntityMixin->Statement + + + + + +SequentialStatement + + +SequentialStatement + + + + + +SequentialStatement->LoopControlStatement + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Statement + + + + + +Statement->SequentialStatement + + + + + \ No newline at end of file diff --git a/_images/inheritance-345d88e49ad3588d8ca0db5f5be79b13c2e0577d.svg b/_images/inheritance-345d88e49ad3588d8ca0db5f5be79b13c2e0577d.svg new file mode 100644 index 000000000..a10999b1f --- /dev/null +++ b/_images/inheritance-345d88e49ad3588d8ca0db5f5be79b13c2e0577d.svg @@ -0,0 +1,59 @@ + + +inheritancea93cf76d15 + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +InterfaceItemMixin + + +InterfaceItemMixin + + + + + +DocumentedEntityMixin->InterfaceItemMixin + + + + + +GenericInterfaceItemMixin + + +GenericInterfaceItemMixin + + + + + +GenericPackageInterfaceItem + + +GenericPackageInterfaceItem + + + + + +GenericInterfaceItemMixin->GenericPackageInterfaceItem + + + + + +InterfaceItemMixin->GenericInterfaceItemMixin + + + + + \ No newline at end of file diff --git a/_images/inheritance-352e25d35cac2441a62f1a612784c98a807790bc.svg b/_images/inheritance-352e25d35cac2441a62f1a612784c98a807790bc.svg new file mode 100644 index 000000000..36b0f8ac3 --- /dev/null +++ b/_images/inheritance-352e25d35cac2441a62f1a612784c98a807790bc.svg @@ -0,0 +1,104 @@ + + +inheritancef51d41baf9 + + +BaseConstant + + +BaseConstant + + + + + +Constant + + +Constant + + + + + +BaseConstant->Constant + + + + + +Obj + + +Obj + + + + + +Obj->BaseConstant + + + + + +WithDefaultExpressionMixin + + +WithDefaultExpressionMixin + + + + + +WithDefaultExpressionMixin->Constant + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->Obj + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Obj + + + + + +MultipleNamedEntityMixin + + +MultipleNamedEntityMixin + + + + + +MultipleNamedEntityMixin->Obj + + + + + \ No newline at end of file diff --git a/_images/inheritance-35314c39a752813cdc075e8e128cc4ec267f092d.svg b/_images/inheritance-35314c39a752813cdc075e8e128cc4ec267f092d.svg new file mode 100644 index 000000000..2a3c7c396 --- /dev/null +++ b/_images/inheritance-35314c39a752813cdc075e8e128cc4ec267f092d.svg @@ -0,0 +1,29 @@ + + +inheritancec2e8d97c35 + + +BranchMixin + + +BranchMixin + + + + + +ElseBranchMixin + + +ElseBranchMixin + + + + + +BranchMixin->ElseBranchMixin + + + + + \ No newline at end of file diff --git a/_images/inheritance-357e830e93a4e9e79849abf8c85813de7ec32271.svg b/_images/inheritance-357e830e93a4e9e79849abf8c85813de7ec32271.svg new file mode 100644 index 000000000..ad6601b77 --- /dev/null +++ b/_images/inheritance-357e830e93a4e9e79849abf8c85813de7ec32271.svg @@ -0,0 +1,164 @@ + + +inheritance7d5ce11772 + + +ConcurrentDeclarationRegionMixin + + +ConcurrentDeclarationRegionMixin + + + + + +Package + + +Package + + + + + +ConcurrentDeclarationRegionMixin->Package + + + + + +DesignUnit + + +DesignUnit + + + + + +PrimaryUnit + + +PrimaryUnit + + + + + +DesignUnit->PrimaryUnit + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->DesignUnit + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->DesignUnit + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->DesignUnit + + + + + +DesignUnitWithContextMixin + + +DesignUnitWithContextMixin + + + + + +DesignUnitWithContextMixin->Package + + + + + +Numeric_Std_Unsigned + + +Numeric_Std_Unsigned + + + + + +PredefinedPackage + + +PredefinedPackage + + + + + +PredefinedPackage->Numeric_Std_Unsigned + + + + + +Package->PredefinedPackage + + + + + +PrimaryUnit->Package + + + + + +PredefinedPackageMixin + + +PredefinedPackageMixin + + + + + +PredefinedPackageMixin->PredefinedPackage + + + + + \ No newline at end of file diff --git a/_images/inheritance-35b30e110230bc5804930b75bea1cf512bb5ea57.svg b/_images/inheritance-35b30e110230bc5804930b75bea1cf512bb5ea57.svg new file mode 100644 index 000000000..18c607afc --- /dev/null +++ b/_images/inheritance-35b30e110230bc5804930b75bea1cf512bb5ea57.svg @@ -0,0 +1,44 @@ + + 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+PhysicalIntegerLiteral + + +PhysicalIntegerLiteral + + + + + +PhysicalLiteral->PhysicalIntegerLiteral + + + + + \ No newline at end of file diff --git a/_images/inheritance-37a5e2cffd8e10f3573161bef527ed6164b3ae27.svg b/_images/inheritance-37a5e2cffd8e10f3573161bef527ed6164b3ae27.svg new file mode 100644 index 000000000..3df1d243f --- /dev/null +++ b/_images/inheritance-37a5e2cffd8e10f3573161bef527ed6164b3ae27.svg @@ -0,0 +1,29 @@ + + +inheritance54e9bed8f1 + + +SubtypeSymbol + + +SubtypeSymbol + + + + + +Symbol + + +Symbol + + + + + +Symbol->SubtypeSymbol + + + + + \ No newline at end of file diff --git a/_images/inheritance-37dc2924cd36faa4da5761c0c8486f7cb3d8eef6.svg b/_images/inheritance-37dc2924cd36faa4da5761c0c8486f7cb3d8eef6.svg new file mode 100644 index 000000000..0dc11dc67 --- /dev/null +++ b/_images/inheritance-37dc2924cd36faa4da5761c0c8486f7cb3d8eef6.svg @@ -0,0 +1,59 @@ + + +inheritance184430c792 + + +BaseType + + +BaseType + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseType + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->BaseType + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->BaseType + + + + + \ No newline at end of file diff --git a/_images/inheritance-380b7fc9881ae68db78cdb0de3cb73fc2ef34c09.svg b/_images/inheritance-380b7fc9881ae68db78cdb0de3cb73fc2ef34c09.svg new file mode 100644 index 000000000..8adfd4db5 --- /dev/null +++ b/_images/inheritance-380b7fc9881ae68db78cdb0de3cb73fc2ef34c09.svg @@ -0,0 +1,29 @@ + + +inheritanced056e10fcb + + +AssignmentMixin + + +AssignmentMixin + + + + + +VariableAssignmentMixin + + +VariableAssignmentMixin + + + + + +AssignmentMixin->VariableAssignmentMixin + + + + + \ No newline at end of file diff --git a/_images/inheritance-38e0f2f5528808d531bd32d3a0926100413c51a6.svg b/_images/inheritance-38e0f2f5528808d531bd32d3a0926100413c51a6.svg new file mode 100644 index 000000000..0738c8095 --- /dev/null +++ b/_images/inheritance-38e0f2f5528808d531bd32d3a0926100413c51a6.svg @@ -0,0 +1,44 @@ + + +inheritance62eb6f6735 + + +BaseExpression + + +BaseExpression + + + + + +UnaryExpression + + +UnaryExpression + + + + + +BaseExpression->UnaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-394ad453475137d54d9eb75020e3334c6bc2b87f.svg b/_images/inheritance-394ad453475137d54d9eb75020e3334c6bc2b87f.svg new file mode 100644 index 000000000..ac9231b20 --- /dev/null +++ b/_images/inheritance-394ad453475137d54d9eb75020e3334c6bc2b87f.svg @@ -0,0 +1,29 @@ + + +inheritance9b3ae9657c + + +Enum + + +Enum + + + + + +Mode + + +Mode + + + + + +Enum->Mode + + + + + \ No newline at end of file diff --git a/_images/inheritance-395032772e7419aa54e27024d17def99bba7839b.svg b/_images/inheritance-395032772e7419aa54e27024d17def99bba7839b.svg new file mode 100644 index 000000000..db23c6eaf --- /dev/null +++ b/_images/inheritance-395032772e7419aa54e27024d17def99bba7839b.svg @@ -0,0 +1,29 @@ + + +inheritance6211b518f9 + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +InterfaceItemMixin + + +InterfaceItemMixin + + + + + +DocumentedEntityMixin->InterfaceItemMixin + + + + + \ No newline at end of file diff --git a/_images/inheritance-3a610caa70ee9b06e7f08a2ca7687790a7458328.svg b/_images/inheritance-3a610caa70ee9b06e7f08a2ca7687790a7458328.svg new file mode 100644 index 000000000..bbca7f862 --- /dev/null +++ b/_images/inheritance-3a610caa70ee9b06e7f08a2ca7687790a7458328.svg @@ -0,0 +1,59 @@ + + +inheritance333edd468d + + +BaseExpression + + +BaseExpression + + + + + +UnaryExpression + + +UnaryExpression + + + + + +BaseExpression->UnaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +UnaryNandExpression + + +UnaryNandExpression + + + + + +UnaryExpression->UnaryNandExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-3a9e331b9c82ab5e2be22e28e7c1812678996ab3.svg b/_images/inheritance-3a9e331b9c82ab5e2be22e28e7c1812678996ab3.svg new file mode 100644 index 000000000..051bc08f2 --- /dev/null +++ b/_images/inheritance-3a9e331b9c82ab5e2be22e28e7c1812678996ab3.svg @@ -0,0 +1,14 @@ + + +inheritance4124164906 + + +ReportStatementMixin + + +ReportStatementMixin + + + + + \ No newline at end of file diff --git a/_images/inheritance-3b0f78bfbd8436235a13348656c8408f5ef5e91a.svg b/_images/inheritance-3b0f78bfbd8436235a13348656c8408f5ef5e91a.svg new file mode 100644 index 000000000..33f3a830e --- /dev/null +++ b/_images/inheritance-3b0f78bfbd8436235a13348656c8408f5ef5e91a.svg @@ -0,0 +1,44 @@ + + +inheritance7968cf5b49 + + +LabeledEntityMixin + + +LabeledEntityMixin + + + + + +Statement + + +Statement + + + + + +LabeledEntityMixin->Statement + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Statement + + + + + \ No newline at end of file diff --git a/_images/inheritance-3b17e6aa6cefcc176a84b2e91ef3e15b5dfc9650.svg b/_images/inheritance-3b17e6aa6cefcc176a84b2e91ef3e15b5dfc9650.svg new file mode 100644 index 000000000..6cceac732 --- /dev/null +++ b/_images/inheritance-3b17e6aa6cefcc176a84b2e91ef3e15b5dfc9650.svg @@ -0,0 +1,59 @@ + + +inheritancee6449dc3a9 + + +BaseExpression + + +BaseExpression + + + + + +UnaryExpression + + +UnaryExpression + + + + + +BaseExpression->UnaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +IdentityExpression + + +IdentityExpression + + + + + +UnaryExpression->IdentityExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-3b60557e9f4b763db0ed1d1042ee6e7a22f63022.svg b/_images/inheritance-3b60557e9f4b763db0ed1d1042ee6e7a22f63022.svg new file mode 100644 index 000000000..a26cebae3 --- /dev/null +++ b/_images/inheritance-3b60557e9f4b763db0ed1d1042ee6e7a22f63022.svg @@ -0,0 +1,119 @@ + + +inheritance5d99679732 + + +BaseType + + +BaseType + + + + + +FullType + + +FullType + + + + + +BaseType->FullType + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseType + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->BaseType + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->BaseType + + + + + +DiscreteTypeMixin + + +DiscreteTypeMixin + + + + + +EnumeratedType + + +EnumeratedType + + + + + +DiscreteTypeMixin->EnumeratedType + + + + + +ScalarType + + +ScalarType + + + + + +ScalarType->EnumeratedType + + + + + +FullType->ScalarType + + + + + \ No newline at end of file diff --git a/_images/inheritance-3bac3ea50ad75bd79158b22d07b42cff8e4e3867.svg b/_images/inheritance-3bac3ea50ad75bd79158b22d07b42cff8e4e3867.svg new file mode 100644 index 000000000..884f25199 --- /dev/null +++ b/_images/inheritance-3bac3ea50ad75bd79158b22d07b42cff8e4e3867.svg @@ -0,0 +1,59 @@ + + +inheritanceeeec406266 + + +BranchMixin + + +BranchMixin + + + + + +ConditionalBranchMixin + + +ConditionalBranchMixin + + + + + +BranchMixin->ConditionalBranchMixin + + + + + +IfBranchMixin + + +IfBranchMixin + + + + + +ConditionalBranchMixin->IfBranchMixin + + + + + +ConditionalMixin + + +ConditionalMixin + + + + + +ConditionalMixin->ConditionalBranchMixin + + + + + \ No newline at end of file diff --git a/_images/inheritance-3c096ed575f0b2fdd08ae49fba8759be05ed7b28.svg b/_images/inheritance-3c096ed575f0b2fdd08ae49fba8759be05ed7b28.svg new file mode 100644 index 000000000..4ce9ef21f --- /dev/null +++ b/_images/inheritance-3c096ed575f0b2fdd08ae49fba8759be05ed7b28.svg @@ -0,0 +1,74 @@ + + +inheritance9964fc2623 + + +BaseExpression + + +BaseExpression + + + + + +UnaryExpression + + +UnaryExpression + + + + + +BaseExpression->UnaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +ParenthesisExpression + + +ParenthesisExpression + + + + + +SubExpression + + +SubExpression + + + + + +ParenthesisExpression->SubExpression + + + + + +UnaryExpression->SubExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-3e9502ab10aa91c0d8ae92e0bd8e80f0a9b882ab.svg b/_images/inheritance-3e9502ab10aa91c0d8ae92e0bd8e80f0a9b882ab.svg new file mode 100644 index 000000000..61a0a1f57 --- /dev/null +++ b/_images/inheritance-3e9502ab10aa91c0d8ae92e0bd8e80f0a9b882ab.svg @@ -0,0 +1,74 @@ + + +inheritance3923ebf04f + + +BaseExpression + + +BaseExpression + + + + + +BinaryExpression + + +BinaryExpression + + + + + +BaseExpression->BinaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +MultiplyingExpression + + +MultiplyingExpression + + + + + +BinaryExpression->MultiplyingExpression + + + + + +MultiplyExpression + + +MultiplyExpression + + + + + +MultiplyingExpression->MultiplyExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-3f10e2bae567c8e3b49fbfc01c8a4231330b260f.svg b/_images/inheritance-3f10e2bae567c8e3b49fbfc01c8a4231330b260f.svg new file mode 100644 index 000000000..05c353091 --- /dev/null +++ b/_images/inheritance-3f10e2bae567c8e3b49fbfc01c8a4231330b260f.svg @@ -0,0 +1,44 @@ + + +inheritance3a1f6dbffb + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +InterfaceItemMixin + + +InterfaceItemMixin + + + + + +DocumentedEntityMixin->InterfaceItemMixin + + + + + +ParameterInterfaceItemMixin + + +ParameterInterfaceItemMixin + + + + + +InterfaceItemMixin->ParameterInterfaceItemMixin + + + + + \ No newline at end of file diff --git a/_images/inheritance-3f4a2bc449689528c3d786d88a7ece5145c2968c.svg b/_images/inheritance-3f4a2bc449689528c3d786d88a7ece5145c2968c.svg new file mode 100644 index 000000000..2ae90463d --- /dev/null +++ b/_images/inheritance-3f4a2bc449689528c3d786d88a7ece5145c2968c.svg @@ -0,0 +1,74 @@ + + +inheritance29e4db7ad8 + + +BaseType + + +BaseType + + + + + +Type + + +Type + + + + + +BaseType->Type + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseType + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->BaseType + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->BaseType + + + + + \ No newline at end of file diff --git a/_images/inheritance-41b344ba3d0301a16d5dd2cb4e85ba8967e1547f.svg b/_images/inheritance-41b344ba3d0301a16d5dd2cb4e85ba8967e1547f.svg new file mode 100644 index 000000000..80817e3fe --- /dev/null +++ b/_images/inheritance-41b344ba3d0301a16d5dd2cb4e85ba8967e1547f.svg @@ -0,0 +1,59 @@ + + +inheritancee719cdbb52 + + +Allocation + + +Allocation + + + + + +QualifiedExpressionAllocation + + +QualifiedExpressionAllocation + + + + + +Allocation->QualifiedExpressionAllocation + + + + + +BaseExpression + + +BaseExpression + + + + + +BaseExpression->Allocation + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-423dfdf4336e4ae0af40c6a5839c483bc76b7c39.svg b/_images/inheritance-423dfdf4336e4ae0af40c6a5839c483bc76b7c39.svg new file mode 100644 index 000000000..a0eb78435 --- /dev/null +++ b/_images/inheritance-423dfdf4336e4ae0af40c6a5839c483bc76b7c39.svg @@ -0,0 +1,119 @@ + + +inheritance9aa24fd915 + + +Branch + + +Branch + + + + + +IfBranch + + +IfBranch + + + + + +Branch->IfBranch + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Branch + + + + + +SequentialStatementsMixin + + +SequentialStatementsMixin + + + + + +SequentialStatementsMixin->Branch + + + + + +BranchMixin + + +BranchMixin + + + + + +ConditionalBranchMixin + + +ConditionalBranchMixin + + + + + +BranchMixin->ConditionalBranchMixin + + + + + +IfBranchMixin + + +IfBranchMixin + + + + + +ConditionalBranchMixin->IfBranchMixin + + + + + +ConditionalMixin + + +ConditionalMixin + + + + + +ConditionalMixin->ConditionalBranchMixin + + + + + +IfBranchMixin->IfBranch + + + + + \ No newline at end of file diff --git a/_images/inheritance-42408ca7511162044f8d47b7c86b515ba964db31.svg b/_images/inheritance-42408ca7511162044f8d47b7c86b515ba964db31.svg new file mode 100644 index 000000000..a05b5fe20 --- /dev/null +++ b/_images/inheritance-42408ca7511162044f8d47b7c86b515ba964db31.svg @@ -0,0 +1,14 @@ + + +inheritancea23c690b7f + + +LabeledEntityMixin + + +LabeledEntityMixin + + + + + \ No newline at end of file diff --git a/_images/inheritance-429195c6fb2b89e5a8ac3159153cd3417e2b9949.svg b/_images/inheritance-429195c6fb2b89e5a8ac3159153cd3417e2b9949.svg new file mode 100644 index 000000000..57cf9da1b --- /dev/null +++ b/_images/inheritance-429195c6fb2b89e5a8ac3159153cd3417e2b9949.svg @@ -0,0 +1,164 @@ + + +inheritanceca42a46f40 + + +ConcurrentDeclarationRegionMixin + + +ConcurrentDeclarationRegionMixin + + + + + +PackageBody + + +PackageBody + + + + + +ConcurrentDeclarationRegionMixin->PackageBody + + + + + +DesignUnit + + +DesignUnit + + + + + +SecondaryUnit + + +SecondaryUnit + + + + + +DesignUnit->SecondaryUnit + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->DesignUnit + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->DesignUnit + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->DesignUnit + + + + + +DesignUnitWithContextMixin + + +DesignUnitWithContextMixin + + + + + +DesignUnitWithContextMixin->PackageBody + + + + + +Float_Generic_Pkg_Body + + +Float_Generic_Pkg_Body + + + + + +PredefinedPackageBody + + +PredefinedPackageBody + + + + + +PredefinedPackageBody->Float_Generic_Pkg_Body + + + + + +PackageBody->PredefinedPackageBody + + + + + +SecondaryUnit->PackageBody + + + + + +PredefinedPackageMixin + + +PredefinedPackageMixin + + + + + +PredefinedPackageMixin->PredefinedPackageBody + + + + + \ No newline at end of file diff --git a/_images/inheritance-44315bec5bc076de8160c0149693437d4be2ad53.svg b/_images/inheritance-44315bec5bc076de8160c0149693437d4be2ad53.svg new file mode 100644 index 000000000..2f636f6b9 --- /dev/null +++ b/_images/inheritance-44315bec5bc076de8160c0149693437d4be2ad53.svg @@ -0,0 +1,89 @@ + + +inheritance5e2f317a3b + + +BaseConstant + + +BaseConstant + + + + + +DeferredConstant + + +DeferredConstant + + + + + +BaseConstant->DeferredConstant + + + + + +Obj + + +Obj + + + + + +Obj->BaseConstant + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->Obj + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Obj + + + + + +MultipleNamedEntityMixin + + +MultipleNamedEntityMixin + + + + + +MultipleNamedEntityMixin->Obj + + + + + \ No newline at end of file diff --git a/_images/inheritance-4592a17de4cbcb18b52a279643351a8eb6618321.svg b/_images/inheritance-4592a17de4cbcb18b52a279643351a8eb6618321.svg new file mode 100644 index 000000000..1fe22f370 --- /dev/null +++ b/_images/inheritance-4592a17de4cbcb18b52a279643351a8eb6618321.svg @@ -0,0 +1,164 @@ + + +inheritanced6e728915f + + +ConcurrentDeclarationRegionMixin + + +ConcurrentDeclarationRegionMixin + + + + + +PackageBody + + +PackageBody + + + + + +ConcurrentDeclarationRegionMixin->PackageBody + + + + + +DesignUnit + + +DesignUnit + + + + + +SecondaryUnit + + +SecondaryUnit + + + + + +DesignUnit->SecondaryUnit + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->DesignUnit + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->DesignUnit + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->DesignUnit + + + + + +DesignUnitWithContextMixin + + +DesignUnitWithContextMixin + + + + + +DesignUnitWithContextMixin->PackageBody + + + + + +PredefinedPackageBody + + +PredefinedPackageBody + + + + + +PackageBody->PredefinedPackageBody + + + + + +SecondaryUnit->PackageBody + + + + + +Standard_Body + + +Standard_Body + + + + + +PredefinedPackageBody->Standard_Body + + + + + +PredefinedPackageMixin + + +PredefinedPackageMixin + + + + + +PredefinedPackageMixin->PredefinedPackageBody + + + + + \ No newline at end of file diff --git a/_images/inheritance-45c2cff9003bc23a3bce6dc643cf72f3e3614886.svg b/_images/inheritance-45c2cff9003bc23a3bce6dc643cf72f3e3614886.svg new file mode 100644 index 000000000..e3ea0b3bb --- /dev/null +++ b/_images/inheritance-45c2cff9003bc23a3bce6dc643cf72f3e3614886.svg @@ -0,0 +1,164 @@ + + +inheritancef86839373d + + +ConcurrentDeclarationRegionMixin + + +ConcurrentDeclarationRegionMixin + + + + + +Package + + +Package + + + + + +ConcurrentDeclarationRegionMixin->Package + + + + + +DesignUnit + + +DesignUnit + + + + + +PrimaryUnit + + +PrimaryUnit + + + + + +DesignUnit->PrimaryUnit + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->DesignUnit + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->DesignUnit + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->DesignUnit + + + + + +DesignUnitWithContextMixin + + +DesignUnitWithContextMixin + + + + + +DesignUnitWithContextMixin->Package + + + + + +Numeric_Std + + +Numeric_Std + + + + + +PredefinedPackage + + +PredefinedPackage + + + + + +PredefinedPackage->Numeric_Std + + + + + +Package->PredefinedPackage + + + + + +PrimaryUnit->Package + + + + + +PredefinedPackageMixin + + +PredefinedPackageMixin + + + + + +PredefinedPackageMixin->PredefinedPackage + + + + + \ No newline at end of file diff --git a/_images/inheritance-46b9cfba2e99e83f5f999b8316baa0cdca6b2a5d.svg b/_images/inheritance-46b9cfba2e99e83f5f999b8316baa0cdca6b2a5d.svg new file mode 100644 index 000000000..1e4624871 --- /dev/null +++ b/_images/inheritance-46b9cfba2e99e83f5f999b8316baa0cdca6b2a5d.svg @@ -0,0 +1,89 @@ + + +inheritance5ed14ca82c + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +Obj + + +Obj + + + + + +DocumentedEntityMixin->Obj + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Obj + + + + + +MultipleNamedEntityMixin + + +MultipleNamedEntityMixin + + + + + +MultipleNamedEntityMixin->Obj + + + + + +Signal + + +Signal + + + + + +Obj->Signal + + + + + +WithDefaultExpressionMixin + + +WithDefaultExpressionMixin + + + + + +WithDefaultExpressionMixin->Signal + + + + + \ No newline at end of file diff --git a/_images/inheritance-46beeda1f78436a41b827c0e8febaf7e495cd8b6.svg b/_images/inheritance-46beeda1f78436a41b827c0e8febaf7e495cd8b6.svg new file mode 100644 index 000000000..b22504a72 --- /dev/null +++ b/_images/inheritance-46beeda1f78436a41b827c0e8febaf7e495cd8b6.svg @@ -0,0 +1,170 @@ + + +inheritance4f7ab58da6 + + +BaseConstant + + +BaseConstant + + + + + +Constant + + +Constant + + + + + +BaseConstant->Constant + + + + + +Obj + + +Obj + + + + + +Obj->BaseConstant + + + + + +ParameterConstantInterfaceItem + + +ParameterConstantInterfaceItem + + + + + +Constant->ParameterConstantInterfaceItem + + + + + +WithDefaultExpressionMixin + + +WithDefaultExpressionMixin + + + + + +WithDefaultExpressionMixin->Constant + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->Obj + + + + + +InterfaceItemMixin + + +InterfaceItemMixin + + + + + +DocumentedEntityMixin->InterfaceItemMixin + + + + + +ParameterInterfaceItemMixin + + +ParameterInterfaceItemMixin + + + + + +InterfaceItemMixin->ParameterInterfaceItemMixin + + + + + +InterfaceItemWithModeMixin + + +InterfaceItemWithModeMixin + + + + + +InterfaceItemWithModeMixin->ParameterConstantInterfaceItem + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Obj + + + + + +MultipleNamedEntityMixin + + +MultipleNamedEntityMixin + + + + + +MultipleNamedEntityMixin->Obj + + + + + +ParameterInterfaceItemMixin->ParameterConstantInterfaceItem + + + + + \ No newline at end of file diff --git a/_images/inheritance-46e0449c094995ed4ad03cfdf76bc82c3b70b7b5.svg b/_images/inheritance-46e0449c094995ed4ad03cfdf76bc82c3b70b7b5.svg new file mode 100644 index 000000000..1186b15cd --- /dev/null +++ b/_images/inheritance-46e0449c094995ed4ad03cfdf76bc82c3b70b7b5.svg @@ -0,0 +1,74 @@ + + +inheritancec236a433c6 + + +BaseExpression + + +BaseExpression + + + + + +BinaryExpression + + +BinaryExpression + + + + + +BaseExpression->BinaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +ShiftExpression + + +ShiftExpression + + + + + +BinaryExpression->ShiftExpression + + + + + +RotateExpression + + +RotateExpression + + + + + +ShiftExpression->RotateExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-4ab654ead496418b3988f34efa1d75d628da5e29.svg b/_images/inheritance-4ab654ead496418b3988f34efa1d75d628da5e29.svg new file mode 100644 index 000000000..9ab28f572 --- /dev/null +++ b/_images/inheritance-4ab654ead496418b3988f34efa1d75d628da5e29.svg @@ -0,0 +1,59 @@ + + +inheritanceeba6ed54d2 + + +ConstrainedCompositeSubtypeSymbol + + +ConstrainedCompositeSubtypeSymbol + + + + + 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b/_images/inheritance-4b33f457501211bfbb23363176a49fd13c1ff6fa.svg @@ -0,0 +1,29 @@ + + +inheritancefe3b3b54df + + +ComponentInstantiationSymbol + + +ComponentInstantiationSymbol + + + + + +Symbol + + +Symbol + + + + + +Symbol->ComponentInstantiationSymbol + + + + + \ No newline at end of file diff --git a/_images/inheritance-4b9941c529ef4f6f0078628c89cca3ad17db40f2.svg b/_images/inheritance-4b9941c529ef4f6f0078628c89cca3ad17db40f2.svg new file mode 100644 index 000000000..3ffefce2d --- /dev/null +++ b/_images/inheritance-4b9941c529ef4f6f0078628c89cca3ad17db40f2.svg @@ -0,0 +1,44 @@ + + +inheritance249cf4f211 + + +BaseChoice + + +BaseChoice + + + + + +SequentialChoice + + +SequentialChoice + + + + + +BaseChoice->SequentialChoice + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseChoice + + + + + \ No newline at end of file diff --git a/_images/inheritance-4cb49917fa302c8f3e1e26ade53ad758438c827f.svg b/_images/inheritance-4cb49917fa302c8f3e1e26ade53ad758438c827f.svg new file mode 100644 index 000000000..b0d163a97 --- /dev/null +++ b/_images/inheritance-4cb49917fa302c8f3e1e26ade53ad758438c827f.svg @@ -0,0 +1,89 @@ + + +inheritance59e80f9892 + + +ConditionalMixin + + +ConditionalMixin + + + + + +WaitStatement + + +WaitStatement + + + + + +ConditionalMixin->WaitStatement + + + + + +LabeledEntityMixin + + +LabeledEntityMixin + + + + + +Statement + + +Statement + + + + + +LabeledEntityMixin->Statement + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Statement + + + + + +SequentialStatement + + +SequentialStatement + + + + + +SequentialStatement->WaitStatement + + + + + +Statement->SequentialStatement + + + + + \ No newline at end of file diff --git a/_images/inheritance-4d48d6836da0d1c338c1fcc0f9d72b99a67f5180.svg b/_images/inheritance-4d48d6836da0d1c338c1fcc0f9d72b99a67f5180.svg new file mode 100644 index 000000000..04c0dcab2 --- /dev/null +++ b/_images/inheritance-4d48d6836da0d1c338c1fcc0f9d72b99a67f5180.svg @@ -0,0 +1,74 @@ + + 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+NamedEntityMixin + + + + + +NamedEntityMixin->BaseType + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->BaseType + + + + + +CompositeType + + +CompositeType + + + + + +RecordType + + +RecordType + + + + + +CompositeType->RecordType + + + + + +FullType->CompositeType + + + + + \ No newline at end of file diff --git a/_images/inheritance-4e6b3840e90d43a97aeea8ac0fd7315903ccc2ca.svg b/_images/inheritance-4e6b3840e90d43a97aeea8ac0fd7315903ccc2ca.svg new file mode 100644 index 000000000..437405c11 --- /dev/null +++ b/_images/inheritance-4e6b3840e90d43a97aeea8ac0fd7315903ccc2ca.svg @@ -0,0 +1,74 @@ + + +inheritanced125c42cf7 + + +AndExpression + + +AndExpression + + + + + +LogicalExpression + + +LogicalExpression + + + + + +LogicalExpression->AndExpression + + + + + +BaseExpression + + +BaseExpression + + + + + +BinaryExpression + + +BinaryExpression + + + + + +BaseExpression->BinaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +BinaryExpression->LogicalExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-50b4fbd23756991dc96e1c59c360d04b5b3c5023.svg b/_images/inheritance-50b4fbd23756991dc96e1c59c360d04b5b3c5023.svg new file mode 100644 index 000000000..cc7c27e22 --- /dev/null +++ b/_images/inheritance-50b4fbd23756991dc96e1c59c360d04b5b3c5023.svg @@ -0,0 +1,89 @@ + + +inheritancee0c6999752 + + +BaseExpression + + +BaseExpression + + + + + +BinaryExpression + + +BinaryExpression + + + + + +BaseExpression->BinaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +RelationalExpression + + +RelationalExpression + + + + + +BinaryExpression->RelationalExpression + + + + + +MatchingEqualExpression + + +MatchingEqualExpression + + + + + +MatchingRelationalExpression + + +MatchingRelationalExpression + + + + + +MatchingRelationalExpression->MatchingEqualExpression + + + + + +RelationalExpression->MatchingRelationalExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-5366cf423fd383534fe9726ce0ea94ceb83bebba.svg b/_images/inheritance-5366cf423fd383534fe9726ce0ea94ceb83bebba.svg new file mode 100644 index 000000000..2d4bda9de --- /dev/null +++ b/_images/inheritance-5366cf423fd383534fe9726ce0ea94ceb83bebba.svg @@ -0,0 +1,74 @@ + + +inheritance71fa07082e + + +DesignUnit + + +DesignUnit + + + + + +PrimaryUnit + + +PrimaryUnit + + + + + +DesignUnit->PrimaryUnit + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->DesignUnit + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->DesignUnit + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->DesignUnit + + + + + \ No newline at end of file diff --git a/_images/inheritance-543a9ac8018e7791e2e89e45026524acec11661b.svg b/_images/inheritance-543a9ac8018e7791e2e89e45026524acec11661b.svg new file mode 100644 index 000000000..8b5efd5af --- /dev/null +++ b/_images/inheritance-543a9ac8018e7791e2e89e45026524acec11661b.svg @@ -0,0 +1,29 @@ + + +inheritance0422672534 + + +SimpleObjectOrFunctionCallSymbol + + +SimpleObjectOrFunctionCallSymbol + + + + + +Symbol + + +Symbol + + + + + +Symbol->SimpleObjectOrFunctionCallSymbol + + + + + \ No newline at end of file diff --git a/_images/inheritance-553737de38994b22a726250892b3d17d1a30e32e.svg b/_images/inheritance-553737de38994b22a726250892b3d17d1a30e32e.svg new file mode 100644 index 000000000..4d224503d --- /dev/null +++ b/_images/inheritance-553737de38994b22a726250892b3d17d1a30e32e.svg @@ -0,0 +1,119 @@ + + +inheritance9497273ad0 + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +Subprogram + + +Subprogram + + + + + +DocumentedEntityMixin->Subprogram + + + + + +Function + + +Function + + + + + +FunctionInstantiation + + +FunctionInstantiation + + + + + +Function->FunctionInstantiation + + + + + +Subprogram->Function + + + + + +SubprogramInstantiationMixin + + +SubprogramInstantiationMixin + + + + + +SubprogramInstantiationMixin->FunctionInstantiation + + + + + +GenericInstantiationMixin + + +GenericInstantiationMixin + + + + + +GenericInstantiationMixin->SubprogramInstantiationMixin + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Subprogram + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->Subprogram + + + + + \ No newline at end of file diff --git a/_images/inheritance-562ddba870219d8141a5a6d1dddd3063a083ec1e.svg b/_images/inheritance-562ddba870219d8141a5a6d1dddd3063a083ec1e.svg new file mode 100644 index 000000000..2f704198f --- /dev/null +++ b/_images/inheritance-562ddba870219d8141a5a6d1dddd3063a083ec1e.svg @@ -0,0 +1,44 @@ + + +inheritance9e237bd57d + + +ModelEntity + + +ModelEntity + + + + + +Name + + +Name + + + + + +ModelEntity->Name + + + + + +SimpleName + + +SimpleName + + + + + +Name->SimpleName + + + + + \ No newline at end of file diff --git a/_images/inheritance-573832d933ea228650493c3b430168fedbdbdba8.svg b/_images/inheritance-573832d933ea228650493c3b430168fedbdbdba8.svg new file mode 100644 index 000000000..71ce34f04 --- /dev/null +++ b/_images/inheritance-573832d933ea228650493c3b430168fedbdbdba8.svg @@ -0,0 +1,119 @@ + + +inheritanceb7b299c29c + + +ConcurrentDeclarationRegionMixin + + +ConcurrentDeclarationRegionMixin + + + + + +ForGenerateStatement + + +ForGenerateStatement + + + + + +ConcurrentDeclarationRegionMixin->ForGenerateStatement + + + + + +ConcurrentStatement + + +ConcurrentStatement + + + + + +GenerateStatement + + +GenerateStatement + + + + + +ConcurrentStatement->GenerateStatement + + + + + +Statement + + +Statement + + + + + +Statement->ConcurrentStatement + + + + + +ConcurrentStatementsMixin + + +ConcurrentStatementsMixin + + + + + +ConcurrentStatementsMixin->ForGenerateStatement + + + + + +GenerateStatement->ForGenerateStatement + + + + + +LabeledEntityMixin + + +LabeledEntityMixin + + + + + +LabeledEntityMixin->Statement + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Statement + + + + + \ No newline at end of file diff --git a/_images/inheritance-57686a7e6a127cf4d05c7950a27e1f97f223a688.svg b/_images/inheritance-57686a7e6a127cf4d05c7950a27e1f97f223a688.svg new file mode 100644 index 000000000..a17445308 --- /dev/null +++ b/_images/inheritance-57686a7e6a127cf4d05c7950a27e1f97f223a688.svg @@ -0,0 +1,164 @@ + + +inheritance927e04c35b + + +ConcurrentDeclarationRegionMixin + + +ConcurrentDeclarationRegionMixin + + + + + +PackageBody + + +PackageBody + + + + + +ConcurrentDeclarationRegionMixin->PackageBody + + + + + +DesignUnit + + +DesignUnit + + + + + +SecondaryUnit + + +SecondaryUnit + + + + + +DesignUnit->SecondaryUnit + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->DesignUnit + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->DesignUnit + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->DesignUnit + + + + + +DesignUnitWithContextMixin + + +DesignUnitWithContextMixin + + + + + +DesignUnitWithContextMixin->PackageBody + + + + + +Fixed_Generic_Pkg_Body + + +Fixed_Generic_Pkg_Body + + + + + +PredefinedPackageBody + + +PredefinedPackageBody + + + + + +PredefinedPackageBody->Fixed_Generic_Pkg_Body + + + + + +PackageBody->PredefinedPackageBody + + + + + +SecondaryUnit->PackageBody + + + + + +PredefinedPackageMixin + + +PredefinedPackageMixin + + + + + +PredefinedPackageMixin->PredefinedPackageBody + + + + + \ No newline at end of file diff --git a/_images/inheritance-59b728d6ef5b44599d3149f633baf7a2235cb73e.svg b/_images/inheritance-59b728d6ef5b44599d3149f633baf7a2235cb73e.svg new file mode 100644 index 000000000..a3d3ec697 --- /dev/null +++ b/_images/inheritance-59b728d6ef5b44599d3149f633baf7a2235cb73e.svg @@ -0,0 +1,134 @@ + + +inheritanceb8bc770ac8 + + +BranchMixin + + +BranchMixin + + + + + +ConditionalBranchMixin + + +ConditionalBranchMixin + + + + + +BranchMixin->ConditionalBranchMixin + + + + + +ConcurrentDeclarationRegionMixin + + +ConcurrentDeclarationRegionMixin + + + + + +GenerateBranch + + +GenerateBranch + + + + + +ConcurrentDeclarationRegionMixin->GenerateBranch + + + + + +ConcurrentStatementsMixin + + +ConcurrentStatementsMixin + + + + + +ConcurrentStatementsMixin->GenerateBranch + + + + + +IfBranchMixin + + +IfBranchMixin + + + + + +ConditionalBranchMixin->IfBranchMixin + + + + + +ConditionalMixin + + +ConditionalMixin + + + + + +ConditionalMixin->ConditionalBranchMixin + + + + + +IfGenerateBranch + + +IfGenerateBranch + + + + + +GenerateBranch->IfGenerateBranch + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->GenerateBranch + + + + + +IfBranchMixin->IfGenerateBranch + + + + + \ No newline at end of file diff --git a/_images/inheritance-59faebdf0315c42a89350f3c9f3ae48264a0cf9a.svg b/_images/inheritance-59faebdf0315c42a89350f3c9f3ae48264a0cf9a.svg new file mode 100644 index 000000000..9fa84daa6 --- /dev/null +++ b/_images/inheritance-59faebdf0315c42a89350f3c9f3ae48264a0cf9a.svg @@ -0,0 +1,74 @@ + + +inheritancecc9cd2a534 + + +DesignUnit + + +DesignUnit + + + + + +SecondaryUnit + + +SecondaryUnit + + + + + +DesignUnit->SecondaryUnit + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->DesignUnit + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->DesignUnit + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->DesignUnit + + + + + \ No newline at end of file diff --git a/_images/inheritance-5a815b55a9bb3014875357ea985e5b5157aef262.svg b/_images/inheritance-5a815b55a9bb3014875357ea985e5b5157aef262.svg new file mode 100644 index 000000000..e3e06836e --- /dev/null +++ b/_images/inheritance-5a815b55a9bb3014875357ea985e5b5157aef262.svg @@ -0,0 +1,29 @@ + + +inheritance1816d03226 + + +PackageExistsInLibraryError + + +PackageExistsInLibraryError + + + + + +VHDLModelException + + +VHDLModelException + + + + + +VHDLModelException->PackageExistsInLibraryError + + + + + \ No newline at end of file diff --git a/_images/inheritance-5ad1db8f0defb30275fdcaa3a7cf6ccd31365cf5.svg b/_images/inheritance-5ad1db8f0defb30275fdcaa3a7cf6ccd31365cf5.svg new file mode 100644 index 000000000..720d976e8 --- /dev/null +++ b/_images/inheritance-5ad1db8f0defb30275fdcaa3a7cf6ccd31365cf5.svg @@ -0,0 +1,119 @@ + + +inheritance16fd4d227e + + +Branch + + +Branch + + + + + +ElsifBranch + + +ElsifBranch + + + + + +Branch->ElsifBranch + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Branch + + + + + +SequentialStatementsMixin + + +SequentialStatementsMixin + + + + + +SequentialStatementsMixin->Branch + + + + + +BranchMixin + + +BranchMixin + + + + + +ConditionalBranchMixin + + +ConditionalBranchMixin + + + + + +BranchMixin->ConditionalBranchMixin + + + + + +ElsifBranchMixin + + +ElsifBranchMixin + + + + + +ConditionalBranchMixin->ElsifBranchMixin + + + + + +ConditionalMixin + + +ConditionalMixin + + + + + +ConditionalMixin->ConditionalBranchMixin + + + + + +ElsifBranchMixin->ElsifBranch + + + + + \ No newline at end of file diff --git a/_images/inheritance-5b4fdf2522dc9f1f98a7379935aded446474cea0.svg b/_images/inheritance-5b4fdf2522dc9f1f98a7379935aded446474cea0.svg new file mode 100644 index 000000000..8ca8e0cdb --- /dev/null +++ b/_images/inheritance-5b4fdf2522dc9f1f98a7379935aded446474cea0.svg @@ -0,0 +1,89 @@ + + +inheritance440e26d3e9 + + +BaseExpression + + +BaseExpression + + + + + +BinaryExpression + + +BinaryExpression + + + + + +BaseExpression->BinaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +ShiftExpression + + +ShiftExpression + + + + + +BinaryExpression->ShiftExpression + + + + + +RotateExpression + + +RotateExpression + + + + + +RotateLeftExpression + + +RotateLeftExpression + + + + + +RotateExpression->RotateLeftExpression + + + + + +ShiftExpression->RotateExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-5b67b021f9204aa855b235a2231a9c7442c13887.svg b/_images/inheritance-5b67b021f9204aa855b235a2231a9c7442c13887.svg new file mode 100644 index 000000000..e928b9b78 --- /dev/null +++ b/_images/inheritance-5b67b021f9204aa855b235a2231a9c7442c13887.svg @@ -0,0 +1,29 @@ + + +inheritancefe9130ef2a + + +ContextExistsInLibraryError + + +ContextExistsInLibraryError + + + + + +VHDLModelException + + +VHDLModelException + + + + + +VHDLModelException->ContextExistsInLibraryError + + + + + \ No newline at end of file diff --git a/_images/inheritance-5b8b1f88d263f33685e59476a466ee8bb16a1e18.svg b/_images/inheritance-5b8b1f88d263f33685e59476a466ee8bb16a1e18.svg new file mode 100644 index 000000000..f7109924b --- /dev/null +++ b/_images/inheritance-5b8b1f88d263f33685e59476a466ee8bb16a1e18.svg @@ -0,0 +1,164 @@ + + +inheritancea5a65ccf06 + + +ConcurrentDeclarationRegionMixin + + +ConcurrentDeclarationRegionMixin + + + + + +PackageBody + + +PackageBody + + + + + +ConcurrentDeclarationRegionMixin->PackageBody + + + + + +DesignUnit + + +DesignUnit + + + + + +SecondaryUnit + + +SecondaryUnit + + + + + +DesignUnit->SecondaryUnit + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->DesignUnit + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->DesignUnit + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->DesignUnit + + + + + +DesignUnitWithContextMixin + + +DesignUnitWithContextMixin + + + + + +DesignUnitWithContextMixin->PackageBody + + + + + +PredefinedPackageBody + + +PredefinedPackageBody + + + + + +PackageBody->PredefinedPackageBody + + + + + +SecondaryUnit->PackageBody + + + + + +Std_logic_1164_Body + + +Std_logic_1164_Body + + + + + +PredefinedPackageBody->Std_logic_1164_Body + + + + + +PredefinedPackageMixin + + +PredefinedPackageMixin + + + + + +PredefinedPackageMixin->PredefinedPackageBody + + + + + \ No newline at end of file diff --git a/_images/inheritance-5c0a3c9476f1c40c754f1c6ef1885e022ad9bfbe.svg b/_images/inheritance-5c0a3c9476f1c40c754f1c6ef1885e022ad9bfbe.svg new file mode 100644 index 000000000..1c2d16308 --- /dev/null +++ b/_images/inheritance-5c0a3c9476f1c40c754f1c6ef1885e022ad9bfbe.svg @@ -0,0 +1,140 @@ + + +inheritance76ac8fae4b + + +BlockStatementMixin + + +BlockStatementMixin + + + + + +ConcurrentBlockStatement + + +ConcurrentBlockStatement + + + + + +BlockStatementMixin->ConcurrentBlockStatement + + + + + +ConcurrentStatement + + +ConcurrentStatement + + + + + +ConcurrentStatement->ConcurrentBlockStatement + + + + + +LabeledEntityMixin + + +LabeledEntityMixin + + + + + +LabeledEntityMixin->ConcurrentBlockStatement + + + + + +Statement + + +Statement + + + + + +LabeledEntityMixin->Statement + + + + + +ConcurrentDeclarationRegionMixin + + +ConcurrentDeclarationRegionMixin + + + + + +ConcurrentDeclarationRegionMixin->ConcurrentBlockStatement + + + + + +ConcurrentStatementsMixin + + +ConcurrentStatementsMixin + + + + + +ConcurrentStatementsMixin->ConcurrentBlockStatement + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->ConcurrentBlockStatement + + + + + +Statement->ConcurrentStatement + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Statement + + + + + \ No newline at end of file diff --git a/_images/inheritance-5cdc7b1c25f0f68703e25bfaebf3360ca9584f3d.svg b/_images/inheritance-5cdc7b1c25f0f68703e25bfaebf3360ca9584f3d.svg new file mode 100644 index 000000000..c25f43a9c --- /dev/null +++ b/_images/inheritance-5cdc7b1c25f0f68703e25bfaebf3360ca9584f3d.svg @@ -0,0 +1,59 @@ + + +inheritancea2761231bc + + +BaseExpression + + +BaseExpression + + + + + +Literal + + +Literal + + + + + +BaseExpression->Literal + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +CharacterLiteral + + +CharacterLiteral + + + + + +Literal->CharacterLiteral + + + + + \ No newline at end of file diff --git a/_images/inheritance-5d8e9192476cd1485f03467505a9ef57a2cddd2c.svg b/_images/inheritance-5d8e9192476cd1485f03467505a9ef57a2cddd2c.svg new file mode 100644 index 000000000..086727233 --- /dev/null +++ b/_images/inheritance-5d8e9192476cd1485f03467505a9ef57a2cddd2c.svg @@ -0,0 +1,74 @@ + + +inheritancee30643d748 + + +BaseExpression + + +BaseExpression + + + + + +BinaryExpression + + +BinaryExpression + + + + + +BaseExpression->BinaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +LogicalExpression + + +LogicalExpression + + + + + +BinaryExpression->LogicalExpression + + + + + +XnorExpression + + +XnorExpression + + + + + +LogicalExpression->XnorExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-5de1a8aac8cc7196659a2604098e4ed81a439bcb.svg b/_images/inheritance-5de1a8aac8cc7196659a2604098e4ed81a439bcb.svg new file mode 100644 index 000000000..4c9714ab4 --- /dev/null +++ b/_images/inheritance-5de1a8aac8cc7196659a2604098e4ed81a439bcb.svg @@ -0,0 +1,44 @@ + + +inheritance878d705068 + + +ModelEntity + + +ModelEntity + + + + + +Name + + +Name + + + + + +ModelEntity->Name + + + + + +SelectedName + + +SelectedName + + + + + +Name->SelectedName + + + + + \ No newline at end of file diff --git a/_images/inheritance-5efea9247b24bb51c57b69b6f7ffdf32a4d62c0c.svg b/_images/inheritance-5efea9247b24bb51c57b69b6f7ffdf32a4d62c0c.svg new file mode 100644 index 000000000..68f0e8ada --- /dev/null +++ b/_images/inheritance-5efea9247b24bb51c57b69b6f7ffdf32a4d62c0c.svg @@ -0,0 +1,155 @@ + + +inheritance245c447150 + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +InterfaceItemMixin + + +InterfaceItemMixin + + + + + +DocumentedEntityMixin->InterfaceItemMixin + + + + + +Obj + + +Obj + + + + + +DocumentedEntityMixin->Obj + + + + + +PortInterfaceItemMixin + + +PortInterfaceItemMixin + + + + + +InterfaceItemMixin->PortInterfaceItemMixin + + + + + +InterfaceItemWithModeMixin + + +InterfaceItemWithModeMixin + + + + + +InterfaceItemWithModeMixin->PortInterfaceItemMixin + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Obj + + + + + +MultipleNamedEntityMixin + + +MultipleNamedEntityMixin + + + + + +MultipleNamedEntityMixin->Obj + + + + + +Signal + + +Signal + + + + + +Obj->Signal + + + + + +PortSignalInterfaceItem + + +PortSignalInterfaceItem + + + + + +PortInterfaceItemMixin->PortSignalInterfaceItem + + + + + +Signal->PortSignalInterfaceItem + + + + + +WithDefaultExpressionMixin + + +WithDefaultExpressionMixin + + + + + +WithDefaultExpressionMixin->Signal + + + + + \ No newline at end of file diff --git a/_images/inheritance-5f9f63c037450a54adebc1d42e9d4eb8b2c6740a.svg b/_images/inheritance-5f9f63c037450a54adebc1d42e9d4eb8b2c6740a.svg new file mode 100644 index 000000000..e374dd25b --- /dev/null +++ b/_images/inheritance-5f9f63c037450a54adebc1d42e9d4eb8b2c6740a.svg @@ -0,0 +1,155 @@ + + +inheritanceab30f1ce04 + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +InterfaceItemMixin + + +InterfaceItemMixin + + + + + +DocumentedEntityMixin->InterfaceItemMixin + + + + + +Obj + + +Obj + + + + + +DocumentedEntityMixin->Obj + + + + + +ParameterInterfaceItemMixin + + +ParameterInterfaceItemMixin + + + + + +InterfaceItemMixin->ParameterInterfaceItemMixin + + + + + +InterfaceItemWithModeMixin + + +InterfaceItemWithModeMixin + + + + + +ParameterSignalInterfaceItem + + +ParameterSignalInterfaceItem + + + + + +InterfaceItemWithModeMixin->ParameterSignalInterfaceItem + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Obj + + + + + +MultipleNamedEntityMixin + + +MultipleNamedEntityMixin + + + + + +MultipleNamedEntityMixin->Obj + + + + + +Signal + + +Signal + + + + + +Obj->Signal + + + + + +ParameterInterfaceItemMixin->ParameterSignalInterfaceItem + + + + + +Signal->ParameterSignalInterfaceItem + + + + + +WithDefaultExpressionMixin + + +WithDefaultExpressionMixin + + + + + +WithDefaultExpressionMixin->Signal + + + + + \ No newline at end of file diff --git a/_images/inheritance-5fb6e0bc2bcc49652d6582b7bfd1df7afc32ca93.svg b/_images/inheritance-5fb6e0bc2bcc49652d6582b7bfd1df7afc32ca93.svg new file mode 100644 index 000000000..56c966938 --- /dev/null +++ b/_images/inheritance-5fb6e0bc2bcc49652d6582b7bfd1df7afc32ca93.svg @@ -0,0 +1,89 @@ + + +inheritancefbe9a0300f + + +Branch + + +Branch + + + + + +ElseBranch + + +ElseBranch + + + + + +Branch->ElseBranch + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Branch + + + + + +SequentialStatementsMixin + + +SequentialStatementsMixin + + + + + +SequentialStatementsMixin->Branch + + + + + +BranchMixin + + +BranchMixin + + + + + +ElseBranchMixin + + +ElseBranchMixin + + + + + +BranchMixin->ElseBranchMixin + + + + + +ElseBranchMixin->ElseBranch + + + + + \ No newline at end of file diff --git a/_images/inheritance-61916a9135d6a8588b8e53e92671f09d2bff7dd3.svg b/_images/inheritance-61916a9135d6a8588b8e53e92671f09d2bff7dd3.svg new file mode 100644 index 000000000..36ade1e4d --- /dev/null +++ b/_images/inheritance-61916a9135d6a8588b8e53e92671f09d2bff7dd3.svg @@ -0,0 +1,14 @@ + + +inheritance74f80df099 + + +ModelEntity + + +ModelEntity + + + + + \ No newline at end of file diff --git a/_images/inheritance-621bd6dba983f475a6bfa67cc0174a68edc62153.svg b/_images/inheritance-621bd6dba983f475a6bfa67cc0174a68edc62153.svg new file mode 100644 index 000000000..2518e6cea --- /dev/null +++ b/_images/inheritance-621bd6dba983f475a6bfa67cc0174a68edc62153.svg @@ -0,0 +1,89 @@ + + +inheritance9afca04233 + + +BaseType + + +BaseType + + + + + +FullType + + +FullType + + + + + +BaseType->FullType + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseType + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->BaseType + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->BaseType + + + + + +ScalarType + + +ScalarType + + + + + +FullType->ScalarType + + + + + \ No newline at end of file diff --git a/_images/inheritance-62aeccc1e421393bdf695f148363a8c81208b629.svg b/_images/inheritance-62aeccc1e421393bdf695f148363a8c81208b629.svg new file mode 100644 index 000000000..236c2bcc1 --- /dev/null +++ b/_images/inheritance-62aeccc1e421393bdf695f148363a8c81208b629.svg @@ -0,0 +1,59 @@ + + +inheritance52ef1d054c + + +BaseCase + + +BaseCase + + + + + +SequentialCase + + +SequentialCase + + + + + +BaseCase->SequentialCase + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseCase + + + + + +SequentialStatementsMixin + + +SequentialStatementsMixin + + + + + +SequentialStatementsMixin->SequentialCase + + + + + \ No newline at end of file diff --git a/_images/inheritance-64427c19b16641ea93729edb93b7625505b33302.svg b/_images/inheritance-64427c19b16641ea93729edb93b7625505b33302.svg new file mode 100644 index 000000000..5f315bccd --- /dev/null +++ b/_images/inheritance-64427c19b16641ea93729edb93b7625505b33302.svg @@ -0,0 +1,164 @@ + + +inheritancef96b4703dd + + +ConcurrentDeclarationRegionMixin + + +ConcurrentDeclarationRegionMixin + + + + + +Package + + +Package + + + + + +ConcurrentDeclarationRegionMixin->Package + + + + + +DesignUnit + + +DesignUnit + + + + + +PrimaryUnit + + +PrimaryUnit + + + + + +DesignUnit->PrimaryUnit + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->DesignUnit + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->DesignUnit + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->DesignUnit + + + + + +DesignUnitWithContextMixin + + +DesignUnitWithContextMixin + + + + + +DesignUnitWithContextMixin->Package + + + + + +Numeric_Bit_Unsigned + + +Numeric_Bit_Unsigned + + + + + +PredefinedPackage + + +PredefinedPackage + + + + + +PredefinedPackage->Numeric_Bit_Unsigned + + + + + +Package->PredefinedPackage + + + + + +PrimaryUnit->Package + + + + + +PredefinedPackageMixin + + +PredefinedPackageMixin + + + + + +PredefinedPackageMixin->PredefinedPackage + + + + + \ No newline at end of file diff --git a/_images/inheritance-64b25a6c213466d1654f2231fa87e3c0ef5644e4.svg b/_images/inheritance-64b25a6c213466d1654f2231fa87e3c0ef5644e4.svg new file mode 100644 index 000000000..67f3598e6 --- /dev/null +++ b/_images/inheritance-64b25a6c213466d1654f2231fa87e3c0ef5644e4.svg @@ -0,0 +1,59 @@ + + +inheritance9f4d5fbf4c + + +BaseChoice + + +BaseChoice + + + + + +ConcurrentChoice + + +ConcurrentChoice + + + + + +BaseChoice->ConcurrentChoice + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseChoice + + + + + +IndexedGenerateChoice + + +IndexedGenerateChoice + + + + + +ConcurrentChoice->IndexedGenerateChoice + + + + + \ No newline at end of file diff --git a/_images/inheritance-654f1720170a0cbe800449e67afcc82277f1f12b.svg b/_images/inheritance-654f1720170a0cbe800449e67afcc82277f1f12b.svg new file mode 100644 index 000000000..4b0f1f95f --- /dev/null +++ b/_images/inheritance-654f1720170a0cbe800449e67afcc82277f1f12b.svg @@ -0,0 +1,74 @@ + + +inheritancee7a084f4e2 + + +BaseExpression + + +BaseExpression + + + + + +BinaryExpression + + +BinaryExpression + + + + + +BaseExpression->BinaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +ShiftExpression + + +ShiftExpression + + + + + +BinaryExpression->ShiftExpression + + + + + +ShiftArithmeticExpression + + +ShiftArithmeticExpression + + + + + +ShiftExpression->ShiftArithmeticExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-65b3b3cc5ba76dc4a7b8b02892954cf7bd7091c3.svg b/_images/inheritance-65b3b3cc5ba76dc4a7b8b02892954cf7bd7091c3.svg new file mode 100644 index 000000000..099b7dc22 --- /dev/null +++ b/_images/inheritance-65b3b3cc5ba76dc4a7b8b02892954cf7bd7091c3.svg @@ -0,0 +1,89 @@ + + +inheritancecf5b896648 + + +ComponentInstantiation + + +ComponentInstantiation + + + + + +Instantiation + + +Instantiation + + + + + +Instantiation->ComponentInstantiation + + + + + +ConcurrentStatement + + +ConcurrentStatement + + + + + +ConcurrentStatement->Instantiation + + + + + +Statement + + +Statement + + + + + +Statement->ConcurrentStatement + + + + + +LabeledEntityMixin + + +LabeledEntityMixin + + + + + +LabeledEntityMixin->Statement + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Statement + + + + + \ No newline at end of file diff --git a/_images/inheritance-66318fd5e026a1ffe9f0cdc7a847fa0c243547d0.svg b/_images/inheritance-66318fd5e026a1ffe9f0cdc7a847fa0c243547d0.svg new file mode 100644 index 000000000..ef15c5d14 --- /dev/null +++ b/_images/inheritance-66318fd5e026a1ffe9f0cdc7a847fa0c243547d0.svg @@ -0,0 +1,29 @@ + + +inheritancebdcfc4fe7d + + +LibraryReferenceSymbol + + +LibraryReferenceSymbol + + + + + +Symbol + + +Symbol + + + + + +Symbol->LibraryReferenceSymbol + + + + + \ No newline at end of file diff --git a/_images/inheritance-665249744097c3bac80cb1e507e335c8309a6895.svg b/_images/inheritance-665249744097c3bac80cb1e507e335c8309a6895.svg new file mode 100644 index 000000000..1216967ec --- /dev/null +++ b/_images/inheritance-665249744097c3bac80cb1e507e335c8309a6895.svg @@ -0,0 +1,89 @@ + + +inheritance263175ec90 + + +ConcurrentStatement + + +ConcurrentStatement + + + + + +GenerateStatement + + +GenerateStatement + + + + + +ConcurrentStatement->GenerateStatement + + + + + +Statement + + +Statement + + + + + +Statement->ConcurrentStatement + + + + + +IfGenerateStatement + + +IfGenerateStatement + + + + + +GenerateStatement->IfGenerateStatement + + + + + +LabeledEntityMixin + + +LabeledEntityMixin + + + + + +LabeledEntityMixin->Statement + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Statement + + + + + \ No newline at end of file diff --git a/_images/inheritance-667ccbf70b1f9e5022c2283de231450e48574023.svg b/_images/inheritance-667ccbf70b1f9e5022c2283de231450e48574023.svg new file mode 100644 index 000000000..d126fe417 --- /dev/null +++ b/_images/inheritance-667ccbf70b1f9e5022c2283de231450e48574023.svg @@ -0,0 +1,89 @@ + + +inheritance019d303944 + + +ConcurrentStatement + + +ConcurrentStatement + + + + + +Instantiation + + +Instantiation + + + + + +ConcurrentStatement->Instantiation + + + + + +Statement + + +Statement + + + + + +Statement->ConcurrentStatement + + + + + +EntityInstantiation + + +EntityInstantiation + + + + + +Instantiation->EntityInstantiation + + + + + +LabeledEntityMixin + + +LabeledEntityMixin + + + + + +LabeledEntityMixin->Statement + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Statement + + + + + \ No newline at end of file diff --git a/_images/inheritance-671c4e5c63eb823368887818b031577f69ec6e96.svg b/_images/inheritance-671c4e5c63eb823368887818b031577f69ec6e96.svg new file mode 100644 index 000000000..5de231548 --- /dev/null +++ b/_images/inheritance-671c4e5c63eb823368887818b031577f69ec6e96.svg @@ -0,0 +1,44 @@ + + +inheritance0930291d57 + + +BranchMixin + + +BranchMixin + + + + + +ConditionalBranchMixin + + +ConditionalBranchMixin + + + + + +BranchMixin->ConditionalBranchMixin + + + + + +ConditionalMixin + + +ConditionalMixin + + + + + +ConditionalMixin->ConditionalBranchMixin + + + + + \ No newline at end of file diff --git a/_images/inheritance-675bb7df5ca0ccf1c05b66912cfe74f026794d8f.svg b/_images/inheritance-675bb7df5ca0ccf1c05b66912cfe74f026794d8f.svg new file mode 100644 index 000000000..acd9a6f70 --- /dev/null +++ b/_images/inheritance-675bb7df5ca0ccf1c05b66912cfe74f026794d8f.svg @@ -0,0 +1,59 @@ + + +inheritancec56f6c2124 + + +BaseExpression + + +BaseExpression + + + + + +Literal + + +Literal + + + + + +BaseExpression->Literal + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +NullLiteral + + +NullLiteral + + + + + +Literal->NullLiteral + + + + + \ No newline at end of file diff --git a/_images/inheritance-68817dd09724618f4c99ccc21242d20c0ad322c8.svg b/_images/inheritance-68817dd09724618f4c99ccc21242d20c0ad322c8.svg new file mode 100644 index 000000000..570f759d3 --- /dev/null +++ b/_images/inheritance-68817dd09724618f4c99ccc21242d20c0ad322c8.svg @@ -0,0 +1,125 @@ + + +inheritancee320da2d7f + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +Subprogram + + +Subprogram + + + + + +DocumentedEntityMixin->Subprogram + + + + + +InterfaceItemMixin + + +InterfaceItemMixin + + + + + +DocumentedEntityMixin->InterfaceItemMixin + + + + + +Function + + +Function + + + + + +GenericFunctionInterfaceItem + + +GenericFunctionInterfaceItem + + + + + +Function->GenericFunctionInterfaceItem + + + + + +Subprogram->Function + + + + + +GenericInterfaceItemMixin + + +GenericInterfaceItemMixin + + + + + +GenericInterfaceItemMixin->GenericFunctionInterfaceItem + + + + + +InterfaceItemMixin->GenericInterfaceItemMixin + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Subprogram + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->Subprogram + + + + + \ No newline at end of file diff --git a/_images/inheritance-6a99c4362290e2a373cf79763e6f54c74329fcb4.svg b/_images/inheritance-6a99c4362290e2a373cf79763e6f54c74329fcb4.svg new file mode 100644 index 000000000..d929f3052 --- /dev/null +++ b/_images/inheritance-6a99c4362290e2a373cf79763e6f54c74329fcb4.svg @@ -0,0 +1,29 @@ + + +inheritance20d40c01b5 + + +AssignmentMixin + + +AssignmentMixin + + + + + +SignalAssignmentMixin + + +SignalAssignmentMixin + + + + + +AssignmentMixin->SignalAssignmentMixin + + + + + \ No newline at end of file diff --git a/_images/inheritance-6cb8f5d3949e3d58af935f0256de862547f78b6c.svg b/_images/inheritance-6cb8f5d3949e3d58af935f0256de862547f78b6c.svg new file mode 100644 index 000000000..fc7a527dc --- /dev/null +++ b/_images/inheritance-6cb8f5d3949e3d58af935f0256de862547f78b6c.svg @@ -0,0 +1,14 @@ + + +inheritanced5e6cf9937 + + +Symbol + + +Symbol + + + + + \ No newline at end of file diff --git a/_images/inheritance-6cb9473402f68317e6b80146f8133b99cbcff551.svg b/_images/inheritance-6cb9473402f68317e6b80146f8133b99cbcff551.svg new file mode 100644 index 000000000..8c634b0d8 --- /dev/null +++ b/_images/inheritance-6cb9473402f68317e6b80146f8133b99cbcff551.svg @@ -0,0 +1,104 @@ + + +inheritanceae1df96650 + + +DesignUnit + + +DesignUnit + + + + + +PrimaryUnit + + +PrimaryUnit + + + + + +DesignUnit->PrimaryUnit + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->DesignUnit + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->DesignUnit + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->DesignUnit + + + + + +PSLPrimaryUnit + + +PSLPrimaryUnit + + + + + +VerificationProperty + + +VerificationProperty + + + + + +PSLPrimaryUnit->VerificationProperty + + + + + +PrimaryUnit->PSLPrimaryUnit + + + + + \ No newline at end of file diff --git a/_images/inheritance-6ded84dbca5b5e2c51e8472a46a7b38fd520a74c.svg b/_images/inheritance-6ded84dbca5b5e2c51e8472a46a7b38fd520a74c.svg new file mode 100644 index 000000000..a423d487c --- /dev/null +++ b/_images/inheritance-6ded84dbca5b5e2c51e8472a46a7b38fd520a74c.svg @@ -0,0 +1,89 @@ + + +inheritancec4ecd5a5d5 + + +ConditionalMixin + + +ConditionalMixin + + + + + +ReturnStatement + + +ReturnStatement + + + + + +ConditionalMixin->ReturnStatement + + + + + +LabeledEntityMixin + + +LabeledEntityMixin + + + + + +Statement + + +Statement + + + + + +LabeledEntityMixin->Statement + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Statement + + + + + +SequentialStatement + + +SequentialStatement + + + + + +SequentialStatement->ReturnStatement + + + + + +Statement->SequentialStatement + + + + + \ No newline at end of file diff --git a/_images/inheritance-6e2d0595e7444d6c54e9567f57bb182f94ee48c2.svg b/_images/inheritance-6e2d0595e7444d6c54e9567f57bb182f94ee48c2.svg new file mode 100644 index 000000000..c9e4e1fec --- /dev/null +++ b/_images/inheritance-6e2d0595e7444d6c54e9567f57bb182f94ee48c2.svg @@ -0,0 +1,44 @@ + + +inheritancecf23ae2215 + + +BaseExpression + + +BaseExpression + + + + + +TernaryExpression + + +TernaryExpression + + + + + +BaseExpression->TernaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-6f1463b9567b513edc9f560ed7b4e3d88ef32063.svg b/_images/inheritance-6f1463b9567b513edc9f560ed7b4e3d88ef32063.svg new file mode 100644 index 000000000..56824ca82 --- /dev/null +++ b/_images/inheritance-6f1463b9567b513edc9f560ed7b4e3d88ef32063.svg @@ -0,0 +1,149 @@ + + +inheritance449c5c6da2 + + +ConcurrentDeclarationRegionMixin + + +ConcurrentDeclarationRegionMixin + + + + + +PackageBody + + +PackageBody + + + + + +ConcurrentDeclarationRegionMixin->PackageBody + + + + + +DesignUnit + + +DesignUnit + + + + + +SecondaryUnit + + +SecondaryUnit + + + + + +DesignUnit->SecondaryUnit + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->DesignUnit + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->DesignUnit + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->DesignUnit + + + + + +DesignUnitWithContextMixin + + +DesignUnitWithContextMixin + + + + + +DesignUnitWithContextMixin->PackageBody + + + + + +PredefinedPackageBody + + +PredefinedPackageBody + + + + + +PackageBody->PredefinedPackageBody + + + + + +SecondaryUnit->PackageBody + + + + + +PredefinedPackageMixin + + +PredefinedPackageMixin + + + + + +PredefinedPackageMixin->PredefinedPackageBody + + + + + \ No newline at end of file diff --git a/_images/inheritance-6f1519448d119fe433abebdbf8f0e8260269ae20.svg b/_images/inheritance-6f1519448d119fe433abebdbf8f0e8260269ae20.svg new file mode 100644 index 000000000..806d631ac --- /dev/null +++ b/_images/inheritance-6f1519448d119fe433abebdbf8f0e8260269ae20.svg @@ -0,0 +1,29 @@ + + +inheritancedf8e8d736a + + +PackageBodyExistsError + + +PackageBodyExistsError + + + + + +VHDLModelException + + +VHDLModelException + + + + + +VHDLModelException->PackageBodyExistsError + + + + + \ No newline at end of file diff --git a/_images/inheritance-7004d6092720daa4d98c620ff0531d7c38592d09.svg b/_images/inheritance-7004d6092720daa4d98c620ff0531d7c38592d09.svg new file mode 100644 index 000000000..46070c1b8 --- /dev/null +++ b/_images/inheritance-7004d6092720daa4d98c620ff0531d7c38592d09.svg @@ -0,0 +1,59 @@ + + +inheritance2ae47fa7e4 + + +BaseExpression + + +BaseExpression + + + + + +BinaryExpression + + +BinaryExpression + + + + + +BaseExpression->BinaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +ShiftExpression + + +ShiftExpression + + + + + +BinaryExpression->ShiftExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-7155923a6006b2b7b362b48930137d89756f1071.svg b/_images/inheritance-7155923a6006b2b7b362b48930137d89756f1071.svg new file mode 100644 index 000000000..278157a8e --- /dev/null +++ b/_images/inheritance-7155923a6006b2b7b362b48930137d89756f1071.svg @@ -0,0 +1,164 @@ + + +inheritance6ac656da3e + + +ConcurrentDeclarationRegionMixin + + +ConcurrentDeclarationRegionMixin + + + + + +Package + + +Package + + + + + +ConcurrentDeclarationRegionMixin->Package + + + + + +DesignUnit + + +DesignUnit + + + + + +PrimaryUnit + + +PrimaryUnit + + + + + +DesignUnit->PrimaryUnit + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->DesignUnit + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->DesignUnit + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->DesignUnit + + + + + +DesignUnitWithContextMixin + + +DesignUnitWithContextMixin + + + + + +DesignUnitWithContextMixin->Package + + + + + +Float_Generic_Pkg + + +Float_Generic_Pkg + + + + + +PredefinedPackage + + +PredefinedPackage + + + + + +PredefinedPackage->Float_Generic_Pkg + + + + + +Package->PredefinedPackage + + + + + +PrimaryUnit->Package + + + + + +PredefinedPackageMixin + + +PredefinedPackageMixin + + + + + +PredefinedPackageMixin->PredefinedPackage + + + + + \ No newline at end of file diff --git a/_images/inheritance-71ee76e8d2b3febe24daf7ce1ae71cf5b62153bf.svg b/_images/inheritance-71ee76e8d2b3febe24daf7ce1ae71cf5b62153bf.svg new file mode 100644 index 000000000..dd726bbd7 --- /dev/null +++ b/_images/inheritance-71ee76e8d2b3febe24daf7ce1ae71cf5b62153bf.svg @@ -0,0 +1,14 @@ + + +inheritanceafbfadaac5 + + +ConcurrentStatementsMixin + + +ConcurrentStatementsMixin + + + + + \ No newline at end of file diff --git a/_images/inheritance-723c51012473b4b20c217444db731714e8b5ce1a.svg b/_images/inheritance-723c51012473b4b20c217444db731714e8b5ce1a.svg new file mode 100644 index 000000000..ec91c615a --- /dev/null +++ b/_images/inheritance-723c51012473b4b20c217444db731714e8b5ce1a.svg @@ -0,0 +1,44 @@ + + +inheritance87a2f76ab0 + + +AggregateElement + + +AggregateElement + + + + + +IndexedAggregateElement + + +IndexedAggregateElement + + + + + +AggregateElement->IndexedAggregateElement + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->AggregateElement + + + + + \ No newline at end of file diff --git a/_images/inheritance-723cf1a0a33f128bb689dbc05bb4432814877578.svg b/_images/inheritance-723cf1a0a33f128bb689dbc05bb4432814877578.svg new file mode 100644 index 000000000..65b8166b4 --- /dev/null +++ b/_images/inheritance-723cf1a0a33f128bb689dbc05bb4432814877578.svg @@ -0,0 +1,74 @@ + + +inheritance9b34bbe85b + + +ConcurrentStatement + + +ConcurrentStatement + + + + + +GenerateStatement + + +GenerateStatement + + + + + +ConcurrentStatement->GenerateStatement + + + + + +Statement + + +Statement + + + + + +Statement->ConcurrentStatement + + + + + +LabeledEntityMixin + + +LabeledEntityMixin + + + + + +LabeledEntityMixin->Statement + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Statement + + + + + \ No newline at end of file diff --git a/_images/inheritance-730423d756999b70b8da2afcdf39385d16acccd9.svg b/_images/inheritance-730423d756999b70b8da2afcdf39385d16acccd9.svg new file mode 100644 index 000000000..02d89fc8c --- /dev/null +++ b/_images/inheritance-730423d756999b70b8da2afcdf39385d16acccd9.svg @@ -0,0 +1,104 @@ + + +inheritancefe0cc6d17f + + +AssignmentMixin + + +AssignmentMixin + + + + + +SignalAssignmentMixin + + +SignalAssignmentMixin + + + + + +AssignmentMixin->SignalAssignmentMixin + + + + + +ConcurrentSignalAssignment + + +ConcurrentSignalAssignment + + + + + +ConcurrentStatement + + +ConcurrentStatement + + + + + +ConcurrentStatement->ConcurrentSignalAssignment + + + + + +SignalAssignmentMixin->ConcurrentSignalAssignment + + + + + +Statement + + +Statement + + + + + +Statement->ConcurrentStatement + + + + + +LabeledEntityMixin + + +LabeledEntityMixin + + + + + +LabeledEntityMixin->Statement + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Statement + + + + + \ No newline at end of file diff --git a/_images/inheritance-7366d3bee3aee4c2830228f5f45cf0c92d9bc23b.svg b/_images/inheritance-7366d3bee3aee4c2830228f5f45cf0c92d9bc23b.svg new file mode 100644 index 000000000..2149ff6a9 --- /dev/null +++ b/_images/inheritance-7366d3bee3aee4c2830228f5f45cf0c92d9bc23b.svg @@ -0,0 +1,59 @@ + + +inheritancecb26035bf3 + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +Obj + + +Obj + + + + + +DocumentedEntityMixin->Obj + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Obj + + + + + +MultipleNamedEntityMixin + + +MultipleNamedEntityMixin + + + + + +MultipleNamedEntityMixin->Obj + + + + + \ No newline at end of file diff --git a/_images/inheritance-73d397b8b0f572e8e4af254a22c338aa956485bf.svg b/_images/inheritance-73d397b8b0f572e8e4af254a22c338aa956485bf.svg new file mode 100644 index 000000000..373169ad1 --- /dev/null +++ b/_images/inheritance-73d397b8b0f572e8e4af254a22c338aa956485bf.svg @@ -0,0 +1,134 @@ + + +inheritance8fa4d3ddc2 + + +CompoundStatement + + +CompoundStatement + + + + + +LoopStatement + + +LoopStatement + + + + + +CompoundStatement->LoopStatement + + + + + +SequentialStatement + + +SequentialStatement + + + + + +SequentialStatement->CompoundStatement + + + + + +ConditionalMixin + + +ConditionalMixin + + + + + +WhileLoopStatement + + +WhileLoopStatement + + + + + +ConditionalMixin->WhileLoopStatement + + + + + +LabeledEntityMixin + + +LabeledEntityMixin + + + + + +Statement + + +Statement + + + + + +LabeledEntityMixin->Statement + + + + + +LoopStatement->WhileLoopStatement + + + + + +SequentialStatementsMixin + + +SequentialStatementsMixin + + + + + +SequentialStatementsMixin->LoopStatement + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Statement + + + + + +Statement->SequentialStatement + + + + + \ No newline at end of file diff --git a/_images/inheritance-75f057114f0cb84386e8a43f17548818e551de1c.svg b/_images/inheritance-75f057114f0cb84386e8a43f17548818e551de1c.svg new file mode 100644 index 000000000..89fefcf95 --- /dev/null +++ b/_images/inheritance-75f057114f0cb84386e8a43f17548818e551de1c.svg @@ -0,0 +1,164 @@ + + +inheritancec3d8af5da7 + + +ConcurrentDeclarationRegionMixin + + +ConcurrentDeclarationRegionMixin + + + + + +Package + + +Package + + + + + +ConcurrentDeclarationRegionMixin->Package + + + + + +DesignUnit + + +DesignUnit + + + + + +PrimaryUnit + + +PrimaryUnit + + + + + +DesignUnit->PrimaryUnit + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->DesignUnit + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->DesignUnit + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->DesignUnit + + + + + +DesignUnitWithContextMixin + + +DesignUnitWithContextMixin + + + + + +DesignUnitWithContextMixin->Package + + + + + +Fixed_Pkg + + +Fixed_Pkg + + + + + +PredefinedPackage + + +PredefinedPackage + + + + + +PredefinedPackage->Fixed_Pkg + + + + + +Package->PredefinedPackage + + + + + +PrimaryUnit->Package + + + + + +PredefinedPackageMixin + + +PredefinedPackageMixin + + + + + +PredefinedPackageMixin->PredefinedPackage + + + + + \ No newline at end of file diff --git a/_images/inheritance-76a76b007919c7860bd4deb15bece6fa837343e9.svg b/_images/inheritance-76a76b007919c7860bd4deb15bece6fa837343e9.svg new file mode 100644 index 000000000..301d21e0d --- /dev/null +++ b/_images/inheritance-76a76b007919c7860bd4deb15bece6fa837343e9.svg @@ -0,0 +1,164 @@ + + +inheritance81d7d7a8e9 + + +ConcurrentDeclarationRegionMixin + + +ConcurrentDeclarationRegionMixin + + + + + +PackageBody + + +PackageBody + + + + + +ConcurrentDeclarationRegionMixin->PackageBody + + + + + +DesignUnit + + +DesignUnit + + + + + +SecondaryUnit + + +SecondaryUnit + + + + + +DesignUnit->SecondaryUnit + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->DesignUnit + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->DesignUnit + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->DesignUnit + + + + + +DesignUnitWithContextMixin + + +DesignUnitWithContextMixin + + + + + +DesignUnitWithContextMixin->PackageBody + + + + + +Env_Body + + +Env_Body + + + + + +PredefinedPackageBody + + +PredefinedPackageBody + + + + + +PredefinedPackageBody->Env_Body + + + + + +PackageBody->PredefinedPackageBody + + + + + +SecondaryUnit->PackageBody + + + + + +PredefinedPackageMixin + + +PredefinedPackageMixin + + + + + +PredefinedPackageMixin->PredefinedPackageBody + + + + + \ No newline at end of file diff --git a/_images/inheritance-76c495e823198edbaa07c6c383d167b8f635c5f7.svg b/_images/inheritance-76c495e823198edbaa07c6c383d167b8f635c5f7.svg new file mode 100644 index 000000000..a4157b1d3 --- /dev/null +++ b/_images/inheritance-76c495e823198edbaa07c6c383d167b8f635c5f7.svg @@ -0,0 +1,14 @@ + + +inheritance8433ed06b5 + + +DesignUnitWithContextMixin + + +DesignUnitWithContextMixin + + + + + \ No newline at end of file diff --git a/_images/inheritance-76dc2a9bca77b7145dc299700872a1c5e1c37c74.svg b/_images/inheritance-76dc2a9bca77b7145dc299700872a1c5e1c37c74.svg new file mode 100644 index 000000000..ed0c285e6 --- /dev/null +++ b/_images/inheritance-76dc2a9bca77b7145dc299700872a1c5e1c37c74.svg @@ -0,0 +1,164 @@ + + +inheritance0217784c6c + + +ConcurrentDeclarationRegionMixin + + +ConcurrentDeclarationRegionMixin + + + + + +Package + + +Package + + + + + +ConcurrentDeclarationRegionMixin->Package + + + + + +DesignUnit + + +DesignUnit + + + + + +PrimaryUnit + + +PrimaryUnit + + + + + +DesignUnit->PrimaryUnit + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->DesignUnit + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->DesignUnit + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->DesignUnit + + + + + +DesignUnitWithContextMixin + + +DesignUnitWithContextMixin + + + + + +DesignUnitWithContextMixin->Package + + + + + +Float_Pkg + + +Float_Pkg + + + + + +PredefinedPackage + + +PredefinedPackage + + + + + +PredefinedPackage->Float_Pkg + + + + + +Package->PredefinedPackage + + + + + +PrimaryUnit->Package + + + + + +PredefinedPackageMixin + + +PredefinedPackageMixin + + + + + +PredefinedPackageMixin->PredefinedPackage + + + + + \ No newline at end of file diff --git a/_images/inheritance-78954745c6b5c23a203a20971a06493551367ee4.svg b/_images/inheritance-78954745c6b5c23a203a20971a06493551367ee4.svg new file mode 100644 index 000000000..6c0ca31f8 --- /dev/null +++ b/_images/inheritance-78954745c6b5c23a203a20971a06493551367ee4.svg @@ -0,0 +1,44 @@ + + +inheritancead26f30147 + + +Allocation + + +Allocation + + + + + +BaseExpression + + +BaseExpression + + + + + +BaseExpression->Allocation + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-79c0afcf0ea0eefdd85df8b7ac2e57d3ecf6ce43.svg b/_images/inheritance-79c0afcf0ea0eefdd85df8b7ac2e57d3ecf6ce43.svg new file mode 100644 index 000000000..20b0bd5cb --- /dev/null +++ b/_images/inheritance-79c0afcf0ea0eefdd85df8b7ac2e57d3ecf6ce43.svg @@ -0,0 +1,104 @@ + + +inheritanceaa5664dce5 + + +DesignUnit + + +DesignUnit + + + + + +PrimaryUnit + + +PrimaryUnit + + + + + +DesignUnit->PrimaryUnit + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->DesignUnit + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->DesignUnit + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->DesignUnit + + + + + +PSLPrimaryUnit + + +PSLPrimaryUnit + + + + + +VerificationMode + + +VerificationMode + + + + + +PSLPrimaryUnit->VerificationMode + + + + + +PrimaryUnit->PSLPrimaryUnit + + + + + \ No newline at end of file diff --git a/_images/inheritance-79f7dab3b42812df1cd93ec99ec4679b17e88cf1.svg b/_images/inheritance-79f7dab3b42812df1cd93ec99ec4679b17e88cf1.svg new file mode 100644 index 000000000..ee3ccf278 --- /dev/null +++ b/_images/inheritance-79f7dab3b42812df1cd93ec99ec4679b17e88cf1.svg @@ -0,0 +1,59 @@ + + +inheritance6e26919b20 + + +AddingExpression + + +AddingExpression + + + + + +BinaryExpression + + +BinaryExpression + + + + + +BinaryExpression->AddingExpression + + + + + +BaseExpression + + +BaseExpression + + + + + +BaseExpression->BinaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-7b13536ba6cbd74836fef9594daa053963c3293b.svg b/_images/inheritance-7b13536ba6cbd74836fef9594daa053963c3293b.svg new file mode 100644 index 000000000..95734673f --- /dev/null +++ b/_images/inheritance-7b13536ba6cbd74836fef9594daa053963c3293b.svg @@ -0,0 +1,89 @@ + + +inheritancece5df97909 + + +BaseExpression + + +BaseExpression + + + + + +BinaryExpression + + +BinaryExpression + + + + + +BaseExpression->BinaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +ShiftExpression + + +ShiftExpression + + + + + +BinaryExpression->ShiftExpression + + + + + +RotateExpression + + +RotateExpression + + + + + +RotateRightExpression + + +RotateRightExpression + + + + + +RotateExpression->RotateRightExpression + + + + + +ShiftExpression->RotateExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-7b77e944c036e0a0c91c9d9459695f0839a49991.svg b/_images/inheritance-7b77e944c036e0a0c91c9d9459695f0839a49991.svg new file mode 100644 index 000000000..9c16e933b --- /dev/null +++ b/_images/inheritance-7b77e944c036e0a0c91c9d9459695f0839a49991.svg @@ -0,0 +1,74 @@ + + +inheritanceec6af6aee6 + + +BaseExpression + + +BaseExpression + + + + + +BinaryExpression + + +BinaryExpression + + + + + +BaseExpression->BinaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +LogicalExpression + + +LogicalExpression + + + + + +BinaryExpression->LogicalExpression + + + + + +OrExpression + + +OrExpression + + + + + +LogicalExpression->OrExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-7cbe9b64071d48d457610b130e004ab239f6ccf4.svg b/_images/inheritance-7cbe9b64071d48d457610b130e004ab239f6ccf4.svg new file mode 100644 index 000000000..7ab3ad2eb --- /dev/null +++ b/_images/inheritance-7cbe9b64071d48d457610b130e004ab239f6ccf4.svg @@ -0,0 +1,74 @@ + + +inheritance83c732a95c + + +BaseExpression + + +BaseExpression + + + + + +BinaryExpression + + +BinaryExpression + + + + + +BaseExpression->BinaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +RelationalExpression + + +RelationalExpression + + + + + +BinaryExpression->RelationalExpression + + + + + +EqualExpression + + +EqualExpression + + + + + +RelationalExpression->EqualExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-7d94c85a1a8220df6200afffafaef8c5deef8865.svg b/_images/inheritance-7d94c85a1a8220df6200afffafaef8c5deef8865.svg new file mode 100644 index 000000000..b7f49f374 --- /dev/null +++ b/_images/inheritance-7d94c85a1a8220df6200afffafaef8c5deef8865.svg @@ -0,0 +1,59 @@ + + +inheritance1c02f2e68a + + +BaseChoice + + +BaseChoice + + + + + +SequentialChoice + + +SequentialChoice + + + + + +BaseChoice->SequentialChoice + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseChoice + + + + + +RangedChoice + + +RangedChoice + + + + + +SequentialChoice->RangedChoice + + + + + \ No newline at end of file diff --git a/_images/inheritance-7e31e37a23247af70c92b6460b41fa553d10e8e3.svg b/_images/inheritance-7e31e37a23247af70c92b6460b41fa553d10e8e3.svg new file mode 100644 index 000000000..7402a7727 --- /dev/null +++ b/_images/inheritance-7e31e37a23247af70c92b6460b41fa553d10e8e3.svg @@ -0,0 +1,164 @@ + + +inheritance7c00590ce2 + + +ConcurrentDeclarationRegionMixin + + +ConcurrentDeclarationRegionMixin + + + + + +Package + + +Package + + + + + +ConcurrentDeclarationRegionMixin->Package + + + + + +DesignUnit + + +DesignUnit + + + + + +PrimaryUnit + + +PrimaryUnit + + + + + +DesignUnit->PrimaryUnit + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->DesignUnit + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->DesignUnit + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->DesignUnit + + + + + +DesignUnitWithContextMixin + + +DesignUnitWithContextMixin + + + + + +DesignUnitWithContextMixin->Package + + + + + +Math_Real + + +Math_Real + + + + + +PredefinedPackage + + +PredefinedPackage + + + + + +PredefinedPackage->Math_Real + + + + + +Package->PredefinedPackage + + + + + +PrimaryUnit->Package + + + + + +PredefinedPackageMixin + + +PredefinedPackageMixin + + + + + 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b/_images/inheritance-7f2372efdedcfa0199a5a87303b19185bf7c6f84.svg @@ -0,0 +1,59 @@ + + +inheritance2919bf919a + + +AllName + + +AllName + + + + + +SelectedName + + +SelectedName + + + + + +SelectedName->AllName + + + + + +ModelEntity + + +ModelEntity + + + + + +Name + + +Name + + + + + +ModelEntity->Name + + + + + +Name->SelectedName + + + + + \ No newline at end of file diff --git a/_images/inheritance-7f8ff6711fde7f8dd34f7799b658b6258a429026.svg b/_images/inheritance-7f8ff6711fde7f8dd34f7799b658b6258a429026.svg new file mode 100644 index 000000000..5ea1ac311 --- /dev/null +++ b/_images/inheritance-7f8ff6711fde7f8dd34f7799b658b6258a429026.svg @@ -0,0 +1,59 @@ + + +inheritance1c17d3d2bf + + +BaseExpression + + +BaseExpression + + + + + +BinaryExpression + + +BinaryExpression + + + + + +BaseExpression->BinaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +LogicalExpression + + +LogicalExpression + + + + + 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b/_images/inheritance-83d45bef60679bc43f60c5f9d8ed4e431c64649a.svg @@ -0,0 +1,59 @@ + + +inheritancea7338e4bc4 + + +BaseExpression + + +BaseExpression + + + + + +Literal + + +Literal + + + + + +BaseExpression->Literal + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +BitStringLiteral + + +BitStringLiteral + + + + + +Literal->BitStringLiteral + + + + + \ No newline at end of file diff --git a/_images/inheritance-83eed60fd7809e7a4639c8dbdbabc72b62a9cf66.svg b/_images/inheritance-83eed60fd7809e7a4639c8dbdbabc72b62a9cf66.svg new file mode 100644 index 000000000..8d62e04a7 --- /dev/null +++ b/_images/inheritance-83eed60fd7809e7a4639c8dbdbabc72b62a9cf66.svg @@ -0,0 +1,29 @@ + + +inheritancef0d2d1ae36 + + +ModelEntity + + +ModelEntity + + + + + +Reference + + +Reference + + + + + +ModelEntity->Reference + + + + + \ No newline at end of file diff --git a/_images/inheritance-84e946d2f857a761a323e76c6d832d3103c5905f.svg b/_images/inheritance-84e946d2f857a761a323e76c6d832d3103c5905f.svg new file mode 100644 index 000000000..1525a3aa8 --- /dev/null +++ b/_images/inheritance-84e946d2f857a761a323e76c6d832d3103c5905f.svg @@ -0,0 +1,44 @@ + + +inheritanceaa8d2f1715 + + +AssociationItem + + +AssociationItem + + + + + +ParameterAssociationItem + + +ParameterAssociationItem + + + + + +AssociationItem->ParameterAssociationItem + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->AssociationItem + + + + + \ No newline at end of file diff --git a/_images/inheritance-85261f51301900915ecc69d6356e3de475c25bcb.svg b/_images/inheritance-85261f51301900915ecc69d6356e3de475c25bcb.svg new file mode 100644 index 000000000..8515b0e73 --- /dev/null +++ b/_images/inheritance-85261f51301900915ecc69d6356e3de475c25bcb.svg @@ -0,0 +1,104 @@ + + +inheritance83b5855a00 + + +BaseCase + + +BaseCase + + + + + +ConcurrentCase + + +ConcurrentCase + + + + + +BaseCase->ConcurrentCase + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseCase + + + + + +GenerateCase + + +GenerateCase + + + + + +ConcurrentCase->GenerateCase + + + + + +LabeledEntityMixin + + +LabeledEntityMixin + + + + + +LabeledEntityMixin->ConcurrentCase + + + + + +ConcurrentDeclarationRegionMixin + + +ConcurrentDeclarationRegionMixin + + + + + +ConcurrentDeclarationRegionMixin->ConcurrentCase + + + + + +ConcurrentStatementsMixin + + +ConcurrentStatementsMixin + + + + + +ConcurrentStatementsMixin->ConcurrentCase + + + + + \ No newline at end of file diff --git a/_images/inheritance-856226594ad549edf7a7556db526bd6cbc9282a6.svg b/_images/inheritance-856226594ad549edf7a7556db526bd6cbc9282a6.svg new file mode 100644 index 000000000..a811a3251 --- /dev/null +++ b/_images/inheritance-856226594ad549edf7a7556db526bd6cbc9282a6.svg @@ -0,0 +1,44 @@ + + +inheritanced74c242e22 + + +Enum + + +Enum + + + + + +Flag + + +Flag + + + + + +Enum->Flag + + + + + +ObjectGraphVertexKind + + +ObjectGraphVertexKind + + + + + +Flag->ObjectGraphVertexKind + + + + + \ No newline at end of file diff --git a/_images/inheritance-8583973ce9490e519aed7af918bff4b9263f2c5c.svg b/_images/inheritance-8583973ce9490e519aed7af918bff4b9263f2c5c.svg new file mode 100644 index 000000000..b645017e1 --- /dev/null +++ b/_images/inheritance-8583973ce9490e519aed7af918bff4b9263f2c5c.svg @@ -0,0 +1,89 @@ + + +inheritance1d19a82bec + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +Obj + + +Obj + + + + + +DocumentedEntityMixin->Obj + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Obj + + + + + +MultipleNamedEntityMixin + + +MultipleNamedEntityMixin + + + + + +MultipleNamedEntityMixin->Obj + + + + + +Variable + + +Variable + + + + + +Obj->Variable + + + + + +WithDefaultExpressionMixin + + +WithDefaultExpressionMixin + + + + + +WithDefaultExpressionMixin->Variable + + + + + \ No newline at end of file diff --git a/_images/inheritance-85a282d78326a34fd8b10ac3edc18cf31a708c78.svg b/_images/inheritance-85a282d78326a34fd8b10ac3edc18cf31a708c78.svg new file mode 100644 index 000000000..b82d92d66 --- /dev/null +++ b/_images/inheritance-85a282d78326a34fd8b10ac3edc18cf31a708c78.svg @@ -0,0 +1,29 @@ + + +inheritancec8446292b1 + + +LibraryExistsInDesignError + + +LibraryExistsInDesignError + + + + + +VHDLModelException + + +VHDLModelException + + + + + +VHDLModelException->LibraryExistsInDesignError + + + + + \ No newline at end of file diff --git a/_images/inheritance-8725910638cb3018e66e84a97022cf8887d09bc4.svg b/_images/inheritance-8725910638cb3018e66e84a97022cf8887d09bc4.svg new file mode 100644 index 000000000..c14c6f396 --- /dev/null +++ b/_images/inheritance-8725910638cb3018e66e84a97022cf8887d09bc4.svg @@ -0,0 +1,89 @@ + + +inheritancef8ac694c51 + + +CaseStatement + + +CaseStatement + + + + + +CompoundStatement + + +CompoundStatement + + + + + +CompoundStatement->CaseStatement + + + + + +SequentialStatement + + +SequentialStatement + + + + + +SequentialStatement->CompoundStatement + + + + + +LabeledEntityMixin + + +LabeledEntityMixin + + + + + +Statement + + +Statement + + + + + +LabeledEntityMixin->Statement + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Statement + + + + + +Statement->SequentialStatement + + + + + \ No newline at end of file diff --git a/_images/inheritance-889e5bba4a056f465a5a4b1885551ec9be268a76.svg b/_images/inheritance-889e5bba4a056f465a5a4b1885551ec9be268a76.svg new file mode 100644 index 000000000..68c06ba4b --- /dev/null +++ b/_images/inheritance-889e5bba4a056f465a5a4b1885551ec9be268a76.svg @@ -0,0 +1,14 @@ + + +inheritance9dc6cb97ea + + +BranchMixin + + +BranchMixin + + + + + \ No newline at end of file diff --git a/_images/inheritance-8a4c60e830cfa3b1cff6cd9fe0261ac6b490af5c.svg b/_images/inheritance-8a4c60e830cfa3b1cff6cd9fe0261ac6b490af5c.svg new file mode 100644 index 000000000..223bec401 --- /dev/null +++ b/_images/inheritance-8a4c60e830cfa3b1cff6cd9fe0261ac6b490af5c.svg @@ -0,0 +1,44 @@ + + +inheritancecb7222d1ad + + +AggregateElement + + +AggregateElement + + + + + +SimpleAggregateElement + + +SimpleAggregateElement + + + + + +AggregateElement->SimpleAggregateElement + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->AggregateElement + + + + + \ No newline at end of file diff --git a/_images/inheritance-8c9404518878da3344005013a174e7ed112110c4.svg b/_images/inheritance-8c9404518878da3344005013a174e7ed112110c4.svg new file mode 100644 index 000000000..a7c9dde96 --- /dev/null +++ b/_images/inheritance-8c9404518878da3344005013a174e7ed112110c4.svg @@ -0,0 +1,119 @@ + + +inheritanceca535f21be + + +ConcurrentDeclarationRegionMixin + + +ConcurrentDeclarationRegionMixin + + + + + +Package + + +Package + + + + + +ConcurrentDeclarationRegionMixin->Package + + + + + +DesignUnit + + +DesignUnit + + + + + +PrimaryUnit + + +PrimaryUnit + + + + + +DesignUnit->PrimaryUnit + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->DesignUnit + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->DesignUnit + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->DesignUnit + + + + + +DesignUnitWithContextMixin + + +DesignUnitWithContextMixin + + + + + +DesignUnitWithContextMixin->Package + + + + + +PrimaryUnit->Package + + + + + \ No newline at end of file diff --git a/_images/inheritance-8d1cf55b2336aba46c0fdd4b86a02fed21deaf60.svg b/_images/inheritance-8d1cf55b2336aba46c0fdd4b86a02fed21deaf60.svg new file mode 100644 index 000000000..7a2d3989a --- /dev/null +++ b/_images/inheritance-8d1cf55b2336aba46c0fdd4b86a02fed21deaf60.svg @@ -0,0 +1,74 @@ + + +inheritance9248d4a43c + + +BaseConstant + + +BaseConstant + + + + + +Obj + + +Obj + + + + + +Obj->BaseConstant + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->Obj + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Obj + + + + + +MultipleNamedEntityMixin + + +MultipleNamedEntityMixin + + + + + +MultipleNamedEntityMixin->Obj + + + + + \ No newline at end of file diff --git a/_images/inheritance-8e6e7d85afe8f0b5fa2cfc8cc19c5145b5dff2db.svg b/_images/inheritance-8e6e7d85afe8f0b5fa2cfc8cc19c5145b5dff2db.svg new file mode 100644 index 000000000..5bfc08938 --- /dev/null +++ b/_images/inheritance-8e6e7d85afe8f0b5fa2cfc8cc19c5145b5dff2db.svg @@ -0,0 +1,89 @@ + + +inheritancebff1087445 + + +BaseExpression + + +BaseExpression + + + + + +BinaryExpression + + +BinaryExpression + + + + + +BaseExpression->BinaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +RelationalExpression + + +RelationalExpression + + + + + +BinaryExpression->RelationalExpression + + + + + +MatchingLessEqualExpression + + +MatchingLessEqualExpression + + + + + +MatchingRelationalExpression + + +MatchingRelationalExpression + + + + + +MatchingRelationalExpression->MatchingLessEqualExpression + + + + + +RelationalExpression->MatchingRelationalExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-8ec750af75919cf9109c52e979b519300baf6758.svg b/_images/inheritance-8ec750af75919cf9109c52e979b519300baf6758.svg new file mode 100644 index 000000000..b43d82ef5 --- /dev/null +++ b/_images/inheritance-8ec750af75919cf9109c52e979b519300baf6758.svg @@ -0,0 +1,74 @@ + + +inheritance0814844dde + + +BaseExpression + + +BaseExpression + + + + + +BinaryExpression + + +BinaryExpression + + + + + +BaseExpression->BinaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +RelationalExpression + + +RelationalExpression + + + + + +BinaryExpression->RelationalExpression + + + + + +MatchingRelationalExpression + + +MatchingRelationalExpression + + + + + +RelationalExpression->MatchingRelationalExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-8fee363a20d21871af0b4bb80f396a363f3da73d.svg b/_images/inheritance-8fee363a20d21871af0b4bb80f396a363f3da73d.svg new file mode 100644 index 000000000..6efe16f88 --- /dev/null +++ b/_images/inheritance-8fee363a20d21871af0b4bb80f396a363f3da73d.svg @@ -0,0 +1,59 @@ + + +inheritance92d0d33c64 + + +DefaultClock + + +DefaultClock + + + + + +PSLEntity + + +PSLEntity + + + + + +PSLEntity->DefaultClock + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->DefaultClock + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->PSLEntity + + + + + \ No newline at end of file diff --git a/_images/inheritance-9002c000ee14eda8cd62ba9e2e21dd021bef68dd.svg b/_images/inheritance-9002c000ee14eda8cd62ba9e2e21dd021bef68dd.svg new file mode 100644 index 000000000..55631c171 --- /dev/null +++ b/_images/inheritance-9002c000ee14eda8cd62ba9e2e21dd021bef68dd.svg @@ -0,0 +1,59 @@ + + +inheritanceda5cbdf802 + + +BaseExpression + + +BaseExpression + + + + + +UnaryExpression + + +UnaryExpression + + + + + +BaseExpression->UnaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +UnaryOrExpression + + +UnaryOrExpression + + + + + +UnaryExpression->UnaryOrExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-91eb6cd38b10a1c5267aac0af182983e502d7f79.svg b/_images/inheritance-91eb6cd38b10a1c5267aac0af182983e502d7f79.svg new file mode 100644 index 000000000..101db5d66 --- /dev/null +++ b/_images/inheritance-91eb6cd38b10a1c5267aac0af182983e502d7f79.svg @@ -0,0 +1,74 @@ + + +inheritanced1f6b3e6bb + + +BaseExpression + + +BaseExpression + + + + + +BinaryExpression + + +BinaryExpression + + + + + +BaseExpression->BinaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +LogicalExpression + + +LogicalExpression + + + + + +BinaryExpression->LogicalExpression + + + + + +NorExpression + + +NorExpression + + + + + +LogicalExpression->NorExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-93c0fee9160fc45c389966671e184bc24fcf4a3f.svg b/_images/inheritance-93c0fee9160fc45c389966671e184bc24fcf4a3f.svg new file mode 100644 index 000000000..32b420fd0 --- /dev/null +++ b/_images/inheritance-93c0fee9160fc45c389966671e184bc24fcf4a3f.svg @@ -0,0 +1,164 @@ + + +inheritancea2594bcadb + + +ConcurrentDeclarationRegionMixin + + +ConcurrentDeclarationRegionMixin + + + + + +Package + + +Package + + + + + +ConcurrentDeclarationRegionMixin->Package + + + + + +DesignUnit + + +DesignUnit + + + + + +PrimaryUnit + + +PrimaryUnit + + + + + +DesignUnit->PrimaryUnit + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->DesignUnit + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->DesignUnit + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->DesignUnit + + + + + +DesignUnitWithContextMixin + + +DesignUnitWithContextMixin + + + + + +DesignUnitWithContextMixin->Package + + + + + +PredefinedPackage + + +PredefinedPackage + + + + + +Package->PredefinedPackage + + + + + +PrimaryUnit->Package + + + + + +Std_logic_misc + + +Std_logic_misc + + + + + +PredefinedPackage->Std_logic_misc + + + + + +PredefinedPackageMixin + + +PredefinedPackageMixin + + + + + +PredefinedPackageMixin->PredefinedPackage + + + + + \ No newline at end of file diff --git a/_images/inheritance-94bba9209ce66cde33aa25fa4d8f28e3852ab617.svg b/_images/inheritance-94bba9209ce66cde33aa25fa4d8f28e3852ab617.svg new file mode 100644 index 000000000..b89da2944 --- /dev/null +++ b/_images/inheritance-94bba9209ce66cde33aa25fa4d8f28e3852ab617.svg @@ -0,0 +1,164 @@ + + +inheritance06c8482587 + + +ConcurrentDeclarationRegionMixin + + +ConcurrentDeclarationRegionMixin + + + + + +Package + + +Package + + + + + +ConcurrentDeclarationRegionMixin->Package + + + + + +DesignUnit + + +DesignUnit + + + + + +PrimaryUnit + + +PrimaryUnit + + + + + +DesignUnit->PrimaryUnit + + + + + +ModelEntity + + +ModelEntity + + + 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@@ + + +inheritancebcc2b39d8a + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +InterfaceItemMixin + + +InterfaceItemMixin + + + + + +DocumentedEntityMixin->InterfaceItemMixin + + + + + +GenericInterfaceItemMixin + + +GenericInterfaceItemMixin + + + + + +GenericSubprogramInterfaceItem + + +GenericSubprogramInterfaceItem + + + + + +GenericInterfaceItemMixin->GenericSubprogramInterfaceItem + + + + + +InterfaceItemMixin->GenericInterfaceItemMixin + + + + + \ No newline at end of file diff --git a/_images/inheritance-96439a8358c499df02f1c0344d15b34c9408ace3.svg b/_images/inheritance-96439a8358c499df02f1c0344d15b34c9408ace3.svg new file mode 100644 index 000000000..8036fab28 --- /dev/null +++ b/_images/inheritance-96439a8358c499df02f1c0344d15b34c9408ace3.svg @@ -0,0 +1,59 @@ + + +inheritancef0175336ba + + +BaseExpression + + +BaseExpression + + + + + +UnaryExpression + + +UnaryExpression + + + + + +BaseExpression->UnaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +UnaryXnorExpression + + +UnaryXnorExpression + + + + + +UnaryExpression->UnaryXnorExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-970b3c1478f6a04aca143079f14737af854fe616.svg b/_images/inheritance-970b3c1478f6a04aca143079f14737af854fe616.svg new file mode 100644 index 000000000..4194b104c --- /dev/null +++ b/_images/inheritance-970b3c1478f6a04aca143079f14737af854fe616.svg @@ -0,0 +1,44 @@ + + +inheritanceae7fc14d84 + + +ModelEntity + + +ModelEntity + + + + + +RecordTypeElement + + +RecordTypeElement + + + + + +ModelEntity->RecordTypeElement + + + + + +MultipleNamedEntityMixin + + +MultipleNamedEntityMixin + + + + + +MultipleNamedEntityMixin->RecordTypeElement + + + + + \ No newline at end of file diff --git a/_images/inheritance-981844a166f112a18454a6ebca013576d0cb9754.svg b/_images/inheritance-981844a166f112a18454a6ebca013576d0cb9754.svg new file mode 100644 index 000000000..37d7a5ef8 --- /dev/null +++ b/_images/inheritance-981844a166f112a18454a6ebca013576d0cb9754.svg @@ -0,0 +1,44 @@ + + +inheritance57c17b13fa + + +Branch + + +Branch + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Branch + + + + + +SequentialStatementsMixin + + +SequentialStatementsMixin + + + + + +SequentialStatementsMixin->Branch + + + + + \ No newline at end of file diff --git a/_images/inheritance-990592e9c3e78a7c1a242ce18ccba02745184965.svg b/_images/inheritance-990592e9c3e78a7c1a242ce18ccba02745184965.svg new file mode 100644 index 000000000..0715837c3 --- /dev/null +++ b/_images/inheritance-990592e9c3e78a7c1a242ce18ccba02745184965.svg @@ -0,0 +1,89 @@ + + +inheritanceb1ec4c291f + + +BaseExpression + + +BaseExpression + + + + + +BinaryExpression + + +BinaryExpression + + + + + +BaseExpression->BinaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +ShiftExpression + + +ShiftExpression + + + + + +BinaryExpression->ShiftExpression + + + + + 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b/_images/inheritance-9ae3a152d47e27699eda82a4ec7dfc37602800fd.svg @@ -0,0 +1,149 @@ + + +inheritanceb9bd81935c + + +BaseType + + +BaseType + + + + + +FullType + + +FullType + + + + + +BaseType->FullType + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseType + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->BaseType + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->BaseType + + + + + +DiscreteTypeMixin + + +DiscreteTypeMixin + + + + + +IntegerType + + +IntegerType + + + + + +DiscreteTypeMixin->IntegerType + + + + + +ScalarType + + +ScalarType + + + + + +FullType->ScalarType + + + + + +RangedScalarType + + +RangedScalarType + + + + + +RangedScalarType->IntegerType + + + + + +NumericTypeMixin + + +NumericTypeMixin + + + + + +NumericTypeMixin->IntegerType + + + + + +ScalarType->RangedScalarType + + + + + \ No newline at end of file diff --git a/_images/inheritance-9b05bf36c201e3effd15c8e5eaa44ba15c293fc6.svg b/_images/inheritance-9b05bf36c201e3effd15c8e5eaa44ba15c293fc6.svg new file mode 100644 index 000000000..05b5e41b8 --- /dev/null +++ b/_images/inheritance-9b05bf36c201e3effd15c8e5eaa44ba15c293fc6.svg @@ -0,0 +1,29 @@ + + +inheritance0d7d04db9b + + +EntityInstantiationSymbol + + +EntityInstantiationSymbol + + + + + +Symbol + + +Symbol + + + + + +Symbol->EntityInstantiationSymbol + + + + + \ No newline at end of file diff --git a/_images/inheritance-9b9243598b652a76643b7e1e67ad1413df833a0c.svg b/_images/inheritance-9b9243598b652a76643b7e1e67ad1413df833a0c.svg new file mode 100644 index 000000000..dc12ff3b4 --- /dev/null +++ b/_images/inheritance-9b9243598b652a76643b7e1e67ad1413df833a0c.svg @@ -0,0 +1,59 @@ + + +inheritanceab0805c801 + + +DesignUnit + + +DesignUnit + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->DesignUnit + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->DesignUnit + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->DesignUnit + + + + + \ No newline at end of file diff --git a/_images/inheritance-9be1af63888b51c91828ea955fae477feca129f4.svg b/_images/inheritance-9be1af63888b51c91828ea955fae477feca129f4.svg new file mode 100644 index 000000000..ea2fda9b5 --- /dev/null +++ b/_images/inheritance-9be1af63888b51c91828ea955fae477feca129f4.svg @@ -0,0 +1,29 @@ + + +inheritance51789518b2 + + +Enum + + +Enum + + + + + +ObjectClass + + +ObjectClass + + + + + +Enum->ObjectClass + + + + + \ No newline at end of file diff --git a/_images/inheritance-9ce6739a61f06b221a2165788d7c79b0b9b70472.svg b/_images/inheritance-9ce6739a61f06b221a2165788d7c79b0b9b70472.svg new file mode 100644 index 000000000..4338930e0 --- /dev/null +++ b/_images/inheritance-9ce6739a61f06b221a2165788d7c79b0b9b70472.svg @@ -0,0 +1,14 @@ + + +inheritance3f7746e5d4 + + +ParenthesisExpression + + +ParenthesisExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-a0532f0845111951cb3e63159ce99dce1e5d718e.svg b/_images/inheritance-a0532f0845111951cb3e63159ce99dce1e5d718e.svg new file mode 100644 index 000000000..a9fb27ff3 --- /dev/null +++ b/_images/inheritance-a0532f0845111951cb3e63159ce99dce1e5d718e.svg @@ -0,0 +1,74 @@ + + +inheritance211bec14bb + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +Subprogram + + +Subprogram + + + + + +DocumentedEntityMixin->Subprogram + + + + + +Function + + +Function + + + + + +Subprogram->Function + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Subprogram + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->Subprogram + + + + + \ No newline at end of file diff --git a/_images/inheritance-a17fb35956fa77a17d7481b4e364bafcf5a8dc1a.svg b/_images/inheritance-a17fb35956fa77a17d7481b4e364bafcf5a8dc1a.svg new file mode 100644 index 000000000..6edae3820 --- /dev/null +++ b/_images/inheritance-a17fb35956fa77a17d7481b4e364bafcf5a8dc1a.svg @@ -0,0 +1,29 @@ + + +inheritancee2073c03f5 + + +ContextReferenceSymbol + + +ContextReferenceSymbol + + + + + +Symbol + + +Symbol + + + + + +Symbol->ContextReferenceSymbol + + + + + \ No newline at end of file diff --git a/_images/inheritance-a22e1fb12f25754fced72de831b1c52a5eb7dbb7.svg b/_images/inheritance-a22e1fb12f25754fced72de831b1c52a5eb7dbb7.svg new file mode 100644 index 000000000..f80441627 --- /dev/null +++ b/_images/inheritance-a22e1fb12f25754fced72de831b1c52a5eb7dbb7.svg @@ -0,0 +1,155 @@ + + +inheritancedebe7010fb + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +InterfaceItemMixin + + +InterfaceItemMixin + + + + + +DocumentedEntityMixin->InterfaceItemMixin + + + + + +Obj + + +Obj + + + + + +DocumentedEntityMixin->Obj + + + + + +ParameterInterfaceItemMixin + + +ParameterInterfaceItemMixin + + + + + +InterfaceItemMixin->ParameterInterfaceItemMixin + + + + + +InterfaceItemWithModeMixin + + +InterfaceItemWithModeMixin + + + + + +ParameterVariableInterfaceItem + + +ParameterVariableInterfaceItem + + + + + +InterfaceItemWithModeMixin->ParameterVariableInterfaceItem + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Obj + + + + + +MultipleNamedEntityMixin + + +MultipleNamedEntityMixin + + + + + +MultipleNamedEntityMixin->Obj + + + + + +Variable + + +Variable + + + + + +Obj->Variable + + + + + +ParameterInterfaceItemMixin->ParameterVariableInterfaceItem + + + + + +Variable->ParameterVariableInterfaceItem + + + + + +WithDefaultExpressionMixin + + +WithDefaultExpressionMixin + + + + + +WithDefaultExpressionMixin->Variable + + + + + \ No newline at end of file diff --git a/_images/inheritance-a2e243c825e7f11b721d1339e883f3014686654a.svg b/_images/inheritance-a2e243c825e7f11b721d1339e883f3014686654a.svg new file mode 100644 index 000000000..f56eddd79 --- /dev/null +++ b/_images/inheritance-a2e243c825e7f11b721d1339e883f3014686654a.svg @@ -0,0 +1,29 @@ + + +inheritancec09ff09711 + + +EntitySymbol + + +EntitySymbol + + + + + +Symbol + + +Symbol + + + + + +Symbol->EntitySymbol + + + + + \ No newline at end of file diff --git a/_images/inheritance-a2f9303f7f214e8888f3b967e141aac53f96e246.svg b/_images/inheritance-a2f9303f7f214e8888f3b967e141aac53f96e246.svg new file mode 100644 index 000000000..c312ab9cd --- /dev/null +++ b/_images/inheritance-a2f9303f7f214e8888f3b967e141aac53f96e246.svg @@ -0,0 +1,89 @@ + + +inheritance83c8ad6364 + + +BaseType + + +BaseType + + + + + +FullType + + +FullType + + + + + +BaseType->FullType + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseType + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->BaseType + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->BaseType + + + + + +ProtectedTypeBody + + +ProtectedTypeBody + + + + + +FullType->ProtectedTypeBody + + + + + \ No newline at end of file diff --git a/_images/inheritance-a3028027ec3d073349f03d9140a2265276229c5f.svg b/_images/inheritance-a3028027ec3d073349f03d9140a2265276229c5f.svg new file mode 100644 index 000000000..59a228b8f --- /dev/null +++ b/_images/inheritance-a3028027ec3d073349f03d9140a2265276229c5f.svg @@ -0,0 +1,104 @@ + + +inheritance41b486d74d + + +BranchMixin + + +BranchMixin + + + + + +ElseBranchMixin + + +ElseBranchMixin + + + + + +BranchMixin->ElseBranchMixin + + + + + +ConcurrentDeclarationRegionMixin + + +ConcurrentDeclarationRegionMixin + + + + + +GenerateBranch + + +GenerateBranch + + + + + +ConcurrentDeclarationRegionMixin->GenerateBranch + + + + + +ConcurrentStatementsMixin + + +ConcurrentStatementsMixin + + + + + +ConcurrentStatementsMixin->GenerateBranch + + + + + +ElseGenerateBranch + + +ElseGenerateBranch + + + + + +ElseBranchMixin->ElseGenerateBranch + + + + + +GenerateBranch->ElseGenerateBranch + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->GenerateBranch + + + + + \ No newline at end of file diff --git a/_images/inheritance-a3083734dfd87a58e60835eca5022595597754ab.svg b/_images/inheritance-a3083734dfd87a58e60835eca5022595597754ab.svg new file mode 100644 index 000000000..ff969f2da --- /dev/null +++ b/_images/inheritance-a3083734dfd87a58e60835eca5022595597754ab.svg @@ -0,0 +1,59 @@ + + +inheritance8733250380 + + +BaseChoice + + +BaseChoice + + + + + +ConcurrentChoice + + +ConcurrentChoice + + + + + +BaseChoice->ConcurrentChoice + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseChoice + + + + + +RangedGenerateChoice + + +RangedGenerateChoice + + + + + +ConcurrentChoice->RangedGenerateChoice + + + + + \ No newline at end of file diff --git a/_images/inheritance-a36fc00777307aa28a55fcf183e8d099ea88387e.svg b/_images/inheritance-a36fc00777307aa28a55fcf183e8d099ea88387e.svg new file mode 100644 index 000000000..a19bc0d38 --- /dev/null +++ b/_images/inheritance-a36fc00777307aa28a55fcf183e8d099ea88387e.svg @@ -0,0 +1,104 @@ + + +inheritance3e743755c8 + + +BaseType + + +BaseType + + + + + +FullType + + +FullType + + + + + +BaseType->FullType + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseType + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->BaseType + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->BaseType + + + + + +ScalarType + + +ScalarType + + + + + +FullType->ScalarType + + + + + +RangedScalarType + + +RangedScalarType + + + + + +ScalarType->RangedScalarType + + + + + \ No newline at end of file diff --git a/_images/inheritance-a4263dda459733ee709eaab8fc6db0d8d85863b0.svg b/_images/inheritance-a4263dda459733ee709eaab8fc6db0d8d85863b0.svg new file mode 100644 index 000000000..5c8263456 --- /dev/null +++ b/_images/inheritance-a4263dda459733ee709eaab8fc6db0d8d85863b0.svg @@ -0,0 +1,44 @@ + + +inheritance537c39ce8a + + +DependencyGraphEdgeKind + + +DependencyGraphEdgeKind + + + + + +Flag + + +Flag + + + + + +Flag->DependencyGraphEdgeKind + + + + + +Enum + + +Enum + + + + + +Enum->Flag + + + + + \ No newline at end of file diff --git a/_images/inheritance-a48f3cd442d3e0c7d0a9bcbdfd704c61434400c9.svg b/_images/inheritance-a48f3cd442d3e0c7d0a9bcbdfd704c61434400c9.svg new file mode 100644 index 000000000..7d5b99ec2 --- /dev/null +++ b/_images/inheritance-a48f3cd442d3e0c7d0a9bcbdfd704c61434400c9.svg @@ -0,0 +1,29 @@ + + +inheritanced8c2d95000 + + +ModelEntity + + +ModelEntity + + + + + +PSLEntity + + +PSLEntity + + + + + +ModelEntity->PSLEntity + + + + + \ No newline at end of file diff --git a/_images/inheritance-a4dce773865feb5f5d78d08b3bbc9c471cf6430c.svg b/_images/inheritance-a4dce773865feb5f5d78d08b3bbc9c471cf6430c.svg new file mode 100644 index 000000000..feed6f59c --- /dev/null +++ b/_images/inheritance-a4dce773865feb5f5d78d08b3bbc9c471cf6430c.svg @@ -0,0 +1,164 @@ + + +inheritance1bfaca2a79 + + +ConcurrentDeclarationRegionMixin + + +ConcurrentDeclarationRegionMixin + + + + + +PackageBody + + +PackageBody + + + + + +ConcurrentDeclarationRegionMixin->PackageBody + + + + + +DesignUnit + + +DesignUnit + + + + + +SecondaryUnit + + +SecondaryUnit + + + + + +DesignUnit->SecondaryUnit + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->DesignUnit + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->DesignUnit + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->DesignUnit + + + + + +DesignUnitWithContextMixin + + +DesignUnitWithContextMixin + + + + + +DesignUnitWithContextMixin->PackageBody + + + + + +PredefinedPackageBody + + +PredefinedPackageBody + + + + + +PackageBody->PredefinedPackageBody + + + + + +SecondaryUnit->PackageBody + + + + + +TextIO_Body + + +TextIO_Body + + + + + +PredefinedPackageBody->TextIO_Body + + + + + +PredefinedPackageMixin + + +PredefinedPackageMixin + + + + + +PredefinedPackageMixin->PredefinedPackageBody + + + + + \ No newline at end of file diff --git a/_images/inheritance-a4e78fca98af12c96a48239e04928cf20fe8fcbe.svg b/_images/inheritance-a4e78fca98af12c96a48239e04928cf20fe8fcbe.svg new file mode 100644 index 000000000..d4335c9ba --- /dev/null +++ b/_images/inheritance-a4e78fca98af12c96a48239e04928cf20fe8fcbe.svg @@ -0,0 +1,89 @@ + + +inheritancecce40f4126 + + +LabeledEntityMixin + + +LabeledEntityMixin + + + + + +Statement + + +Statement + + + + + +LabeledEntityMixin->Statement + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Statement + + + + + +ProcedureCallMixin + + +ProcedureCallMixin + + + + + +SequentialProcedureCall + + +SequentialProcedureCall + + + + + +ProcedureCallMixin->SequentialProcedureCall + + + + + +SequentialStatement + + +SequentialStatement + + + + + +SequentialStatement->SequentialProcedureCall + + + + + +Statement->SequentialStatement + + + + + \ No newline at end of file diff --git a/_images/inheritance-a5aa8c58a7349ca63d1d8c3c592954d85f18b3a0.svg b/_images/inheritance-a5aa8c58a7349ca63d1d8c3c592954d85f18b3a0.svg new file mode 100644 index 000000000..3eb5b1277 --- /dev/null +++ b/_images/inheritance-a5aa8c58a7349ca63d1d8c3c592954d85f18b3a0.svg @@ -0,0 +1,119 @@ + + +inheritance801b934d6d + + +CompoundStatement + + +CompoundStatement + + + + + +LoopStatement + + +LoopStatement + + + + + +CompoundStatement->LoopStatement + + + + + +SequentialStatement + + +SequentialStatement + + + + + +SequentialStatement->CompoundStatement + + + + + +ForLoopStatement + + +ForLoopStatement + + + + + +LoopStatement->ForLoopStatement + + + + + +LabeledEntityMixin + + +LabeledEntityMixin + + + + + +Statement + + +Statement + + + + + +LabeledEntityMixin->Statement + + + + + +SequentialStatementsMixin + + +SequentialStatementsMixin + + + + + +SequentialStatementsMixin->LoopStatement + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Statement + + + + + +Statement->SequentialStatement + + + + + \ No newline at end of file diff --git a/_images/inheritance-a62c19304ac9febe703eb7ce91f38174c7bf33d5.svg b/_images/inheritance-a62c19304ac9febe703eb7ce91f38174c7bf33d5.svg new file mode 100644 index 000000000..6180e1cf1 --- /dev/null +++ b/_images/inheritance-a62c19304ac9febe703eb7ce91f38174c7bf33d5.svg @@ -0,0 +1,44 @@ + + +inheritancee78472d626 + + +ConstrainedScalarSubtypeSymbol + + +ConstrainedScalarSubtypeSymbol + + + + + +SubtypeSymbol + + +SubtypeSymbol + + + + + +SubtypeSymbol->ConstrainedScalarSubtypeSymbol + + + + + +Symbol + + +Symbol + + + + + +Symbol->SubtypeSymbol + + + + + \ No newline at end of file diff --git a/_images/inheritance-a6c38d3df59c01a17b300fe603ef0d3817c68626.svg b/_images/inheritance-a6c38d3df59c01a17b300fe603ef0d3817c68626.svg new file mode 100644 index 000000000..256a4abc4 --- /dev/null +++ b/_images/inheritance-a6c38d3df59c01a17b300fe603ef0d3817c68626.svg @@ -0,0 +1,89 @@ + + +inheritance0c578db737 + + +CompoundStatement + + +CompoundStatement + + + + + +IfStatement + + +IfStatement + + + + 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+ +GenericInterfaceItemMixin + + +GenericInterfaceItemMixin + + + + + +GenericProcedureInterfaceItem + + +GenericProcedureInterfaceItem + + + + + +GenericInterfaceItemMixin->GenericProcedureInterfaceItem + + + + + +InterfaceItemMixin->GenericInterfaceItemMixin + + + + + +Procedure + + +Procedure + + + + + +Procedure->GenericProcedureInterfaceItem + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Subprogram + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->Subprogram + + + + + +Subprogram->Procedure + + + + + \ No newline at end of file diff --git a/_images/inheritance-a751c39e6a75a1d4ed88d935f2ff470c551ffc66.svg b/_images/inheritance-a751c39e6a75a1d4ed88d935f2ff470c551ffc66.svg new file mode 100644 index 000000000..43e2be5f9 --- /dev/null +++ b/_images/inheritance-a751c39e6a75a1d4ed88d935f2ff470c551ffc66.svg @@ -0,0 +1,74 @@ + + +inheritance80318b6b64 + + +BaseExpression + + +BaseExpression + + + + + +BinaryExpression + + +BinaryExpression + + + + + +BaseExpression->BinaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +RelationalExpression + + +RelationalExpression + + + + + +BinaryExpression->RelationalExpression + + + + + +GreaterEqualExpression + + +GreaterEqualExpression + + + + + +RelationalExpression->GreaterEqualExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-a7c8dbfef1dc0a18a77cd3d7f33940b8ac2fb65b.svg b/_images/inheritance-a7c8dbfef1dc0a18a77cd3d7f33940b8ac2fb65b.svg new file mode 100644 index 000000000..0af509910 --- /dev/null +++ b/_images/inheritance-a7c8dbfef1dc0a18a77cd3d7f33940b8ac2fb65b.svg @@ -0,0 +1,89 @@ + + +inheritance45eeece200 + + +BaseExpression + + +BaseExpression + + + + + +BinaryExpression + + +BinaryExpression + + + + + +BaseExpression->BinaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +RelationalExpression + + +RelationalExpression + + + + + +BinaryExpression->RelationalExpression + + + + + +MatchingGreaterEqualExpression + + +MatchingGreaterEqualExpression + + + + + +MatchingRelationalExpression + + +MatchingRelationalExpression + + + + + +MatchingRelationalExpression->MatchingGreaterEqualExpression + + + + + +RelationalExpression->MatchingRelationalExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-a8315b5c4739259fe7ec445cfe57acb4744c8267.svg b/_images/inheritance-a8315b5c4739259fe7ec445cfe57acb4744c8267.svg new file mode 100644 index 000000000..a923b4f74 --- /dev/null +++ b/_images/inheritance-a8315b5c4739259fe7ec445cfe57acb4744c8267.svg @@ -0,0 +1,14 @@ + + +inheritance39dba80b9b + + +DiscreteTypeMixin + + +DiscreteTypeMixin + + + + + \ No newline at end of file diff --git a/_images/inheritance-a9b10ad8df917ccd77e6c8b7ff8d28a6bbec1fdd.svg b/_images/inheritance-a9b10ad8df917ccd77e6c8b7ff8d28a6bbec1fdd.svg new file mode 100644 index 000000000..5ff4bd175 --- /dev/null +++ b/_images/inheritance-a9b10ad8df917ccd77e6c8b7ff8d28a6bbec1fdd.svg @@ -0,0 +1,74 @@ + + +inheritancee078c7d359 + + +Library + + +Library + + + + + +PredefinedLibrary + + +PredefinedLibrary + + + + + +Library->PredefinedLibrary + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Library + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->Library + + + + + +Std + + +Std + + + + + +PredefinedLibrary->Std + + + + + \ No newline at end of file diff --git a/_images/inheritance-aa17508119db153a42673755db84147355d1286c.svg b/_images/inheritance-aa17508119db153a42673755db84147355d1286c.svg new file mode 100644 index 000000000..3da0d42f1 --- /dev/null +++ b/_images/inheritance-aa17508119db153a42673755db84147355d1286c.svg @@ -0,0 +1,164 @@ + + +inheritanceac1db66c3b + + +ConcurrentDeclarationRegionMixin + + +ConcurrentDeclarationRegionMixin + + + + + +Package + + +Package + + + + + +ConcurrentDeclarationRegionMixin->Package + + + + + +DesignUnit + + +DesignUnit + + + + + +PrimaryUnit + + +PrimaryUnit + + + + + +DesignUnit->PrimaryUnit + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->DesignUnit + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->DesignUnit + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->DesignUnit + + + + + +DesignUnitWithContextMixin + + +DesignUnitWithContextMixin + + + + + +DesignUnitWithContextMixin->Package + + + + + +PredefinedPackage + + +PredefinedPackage + + + + + +Package->PredefinedPackage + + + + + +PrimaryUnit->Package + + + + + +Standard + + +Standard + + + + + +PredefinedPackage->Standard + + + + + +PredefinedPackageMixin + + +PredefinedPackageMixin + + + + + +PredefinedPackageMixin->PredefinedPackage + + + + + \ No newline at end of file diff --git a/_images/inheritance-aaac5f8e7eb940950dc9b0202d6e9474d6f25457.svg b/_images/inheritance-aaac5f8e7eb940950dc9b0202d6e9474d6f25457.svg new file mode 100644 index 000000000..8c5badd2e --- /dev/null +++ b/_images/inheritance-aaac5f8e7eb940950dc9b0202d6e9474d6f25457.svg @@ -0,0 +1,29 @@ + + +inheritanced1b609e6a8 + + +GenericEntityInstantiationMixin + + +GenericEntityInstantiationMixin + + + + + +GenericInstantiationMixin + + +GenericInstantiationMixin + + + + + +GenericInstantiationMixin->GenericEntityInstantiationMixin + + + + + \ No newline at end of file diff --git a/_images/inheritance-aadf75e54e9fd113e298596b00edb3aa8ffaf712.svg b/_images/inheritance-aadf75e54e9fd113e298596b00edb3aa8ffaf712.svg new file mode 100644 index 000000000..d8d6a8d0b --- /dev/null +++ b/_images/inheritance-aadf75e54e9fd113e298596b00edb3aa8ffaf712.svg @@ -0,0 +1,14 @@ + + +inheritancea663d504fd + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + \ No newline at end of file diff --git a/_images/inheritance-aae268b774f143228acd0ab4f588e051c9f67fea.svg b/_images/inheritance-aae268b774f143228acd0ab4f588e051c9f67fea.svg new file mode 100644 index 000000000..4443394f9 --- /dev/null +++ b/_images/inheritance-aae268b774f143228acd0ab4f588e051c9f67fea.svg @@ -0,0 +1,89 @@ + + +inheritance5080d1bbce + + +BaseExpression + + +BaseExpression + + + + + +BinaryExpression + + +BinaryExpression + + + + + +BaseExpression->BinaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +ShiftExpression + + +ShiftExpression + + + + + +BinaryExpression->ShiftExpression + + + + + +ShiftLogicExpression + + +ShiftLogicExpression + + + + + +ShiftExpression->ShiftLogicExpression + + + + + +ShiftRightLogicExpression + + +ShiftRightLogicExpression + + + + + +ShiftLogicExpression->ShiftRightLogicExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-ab3a413c3872acf922d37935edd9fb7d3bed9a7d.svg b/_images/inheritance-ab3a413c3872acf922d37935edd9fb7d3bed9a7d.svg new file mode 100644 index 000000000..8e2e0ddeb --- /dev/null +++ b/_images/inheritance-ab3a413c3872acf922d37935edd9fb7d3bed9a7d.svg @@ -0,0 +1,59 @@ + + +inheritance2a09777f72 + + +BaseExpression + + +BaseExpression + + + + + +UnaryExpression + + +UnaryExpression + + + + + +BaseExpression->UnaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +UnaryNorExpression + + +UnaryNorExpression + + + + + +UnaryExpression->UnaryNorExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-ab7564e67d307a028372cc7e823e33950de95bb9.svg b/_images/inheritance-ab7564e67d307a028372cc7e823e33950de95bb9.svg new file mode 100644 index 000000000..4cbdad041 --- /dev/null +++ b/_images/inheritance-ab7564e67d307a028372cc7e823e33950de95bb9.svg @@ -0,0 +1,89 @@ + + +inheritancef574a883d2 + + +BaseExpression + + +BaseExpression + + + + + +BinaryExpression + + +BinaryExpression + + + + + +BaseExpression->BinaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +RelationalExpression + + +RelationalExpression + + + + + +BinaryExpression->RelationalExpression + + + + + +MatchingRelationalExpression + + +MatchingRelationalExpression + + + + + +MatchingUnequalExpression + + +MatchingUnequalExpression + + + + + +MatchingRelationalExpression->MatchingUnequalExpression + + + + + +RelationalExpression->MatchingRelationalExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-aca664d72381a8177676518e27cb58919850af1c.svg b/_images/inheritance-aca664d72381a8177676518e27cb58919850af1c.svg new file mode 100644 index 000000000..e5c77670c --- /dev/null +++ b/_images/inheritance-aca664d72381a8177676518e27cb58919850af1c.svg @@ -0,0 +1,164 @@ + + +inheritance4adecebf5d + + +ConcurrentDeclarationRegionMixin + + +ConcurrentDeclarationRegionMixin + + + + + +Package + + +Package + + + + + +ConcurrentDeclarationRegionMixin->Package + + + + + +DesignUnit + + +DesignUnit + + + + + +PrimaryUnit + + +PrimaryUnit + + + + + +DesignUnit->PrimaryUnit + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->DesignUnit + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->DesignUnit + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->DesignUnit + + + + + +DesignUnitWithContextMixin + + +DesignUnitWithContextMixin + + + + + +DesignUnitWithContextMixin->Package + + + + + +Fixed_Float_Types + + +Fixed_Float_Types + + + + + +PredefinedPackage + + +PredefinedPackage + + + + + +PredefinedPackage->Fixed_Float_Types + + + + + +Package->PredefinedPackage + + + + + +PrimaryUnit->Package + + + + + +PredefinedPackageMixin + + +PredefinedPackageMixin + + + + + +PredefinedPackageMixin->PredefinedPackage + + + + + \ No newline at end of file diff --git a/_images/inheritance-ad9e09e9d1c97d7c6eca44cc5b54272903adfad9.svg b/_images/inheritance-ad9e09e9d1c97d7c6eca44cc5b54272903adfad9.svg new file mode 100644 index 000000000..b89cb9ca6 --- /dev/null +++ b/_images/inheritance-ad9e09e9d1c97d7c6eca44cc5b54272903adfad9.svg @@ -0,0 +1,104 @@ + + +inheritance9f8074caf4 + + +AssignmentMixin + + +AssignmentMixin + + + + + +SignalAssignmentMixin + + +SignalAssignmentMixin + + + + + +AssignmentMixin->SignalAssignmentMixin + + + + + +LabeledEntityMixin + + +LabeledEntityMixin + + + + + +Statement + + +Statement + + + + + +LabeledEntityMixin->Statement + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Statement + + + + + +SequentialSignalAssignment + + +SequentialSignalAssignment + + + + + +SequentialStatement + + +SequentialStatement + + + + + +SequentialStatement->SequentialSignalAssignment + + + + + +SignalAssignmentMixin->SequentialSignalAssignment + + + + + +Statement->SequentialStatement + + + + + \ No newline at end of file diff --git a/_images/inheritance-af2ae2c98a1f7245bc69287dd54301a27f7faa44.svg b/_images/inheritance-af2ae2c98a1f7245bc69287dd54301a27f7faa44.svg new file mode 100644 index 000000000..58e8c9ffb --- /dev/null +++ b/_images/inheritance-af2ae2c98a1f7245bc69287dd54301a27f7faa44.svg @@ -0,0 +1,29 @@ + + +inheritance8a20b739ef + + +ArchitectureSymbol + + +ArchitectureSymbol + + + + + +Symbol + + +Symbol + + + + + +Symbol->ArchitectureSymbol + + + + + \ No newline at end of file diff --git a/_images/inheritance-b17be5743d0caf58282db94de330c53435073015.svg b/_images/inheritance-b17be5743d0caf58282db94de330c53435073015.svg new file mode 100644 index 000000000..44b2d5c62 --- /dev/null +++ b/_images/inheritance-b17be5743d0caf58282db94de330c53435073015.svg @@ -0,0 +1,74 @@ + + +inheritance126e0bfaa0 + + +BaseType + + +BaseType + + + + + +Subtype + + +Subtype + + + + + +BaseType->Subtype + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseType + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->BaseType + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->BaseType + + + + + \ No newline at end of file diff --git a/_images/inheritance-b1c81ccf6e4235806135e0e3057f28ca5885b40b.svg b/_images/inheritance-b1c81ccf6e4235806135e0e3057f28ca5885b40b.svg new file mode 100644 index 000000000..60d060763 --- /dev/null +++ b/_images/inheritance-b1c81ccf6e4235806135e0e3057f28ca5885b40b.svg @@ -0,0 +1,164 @@ + + +inheritance18b3b8093d + + +ConcurrentDeclarationRegionMixin + + +ConcurrentDeclarationRegionMixin + + + + + +Package + + +Package + + + + + +ConcurrentDeclarationRegionMixin->Package + + + + + +DesignUnit + + +DesignUnit + + + + + +PrimaryUnit + + +PrimaryUnit + + + + + +DesignUnit->PrimaryUnit + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->DesignUnit + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->DesignUnit + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->DesignUnit + + + + + +DesignUnitWithContextMixin + + +DesignUnitWithContextMixin + + + + + +DesignUnitWithContextMixin->Package + + + + + +Env + + +Env + + + + + +PredefinedPackage + + +PredefinedPackage + + + + + +PredefinedPackage->Env + + + + + +Package->PredefinedPackage + + + + + +PrimaryUnit->Package + + + + + +PredefinedPackageMixin + + +PredefinedPackageMixin + + + + + +PredefinedPackageMixin->PredefinedPackage + + + + + \ No newline at end of file diff --git a/_images/inheritance-b37467e80df69c67b0c28f1d323e2dd19abe2f83.svg b/_images/inheritance-b37467e80df69c67b0c28f1d323e2dd19abe2f83.svg new file mode 100644 index 000000000..fce64cb10 --- /dev/null +++ b/_images/inheritance-b37467e80df69c67b0c28f1d323e2dd19abe2f83.svg @@ -0,0 +1,89 @@ + + +inheritance5e14d7bbd5 + + +DesignUnit + + +DesignUnit + + + + + +PrimaryUnit + + +PrimaryUnit + + + + + +DesignUnit->PrimaryUnit + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->DesignUnit + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->DesignUnit + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->DesignUnit + + + + + +PSLPrimaryUnit + + +PSLPrimaryUnit + + + + + +PrimaryUnit->PSLPrimaryUnit + + + + + \ No newline at end of file diff --git a/_images/inheritance-b43c51f30bec81b8714a5478274923fc604cb23c.svg b/_images/inheritance-b43c51f30bec81b8714a5478274923fc604cb23c.svg new file mode 100644 index 000000000..5deb035ce --- /dev/null +++ b/_images/inheritance-b43c51f30bec81b8714a5478274923fc604cb23c.svg @@ -0,0 +1,74 @@ + + +inheritance462993717f + + +BaseExpression + + +BaseExpression + + + + + +BinaryExpression + + +BinaryExpression + + + + + +BaseExpression->BinaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +RangeExpression + + +RangeExpression + + + + + +BinaryExpression->RangeExpression + + + + + +DescendingRangeExpression + + +DescendingRangeExpression + + + + + +RangeExpression->DescendingRangeExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-b6c44c2477a5029db09fbd873372431a5ef63687.svg b/_images/inheritance-b6c44c2477a5029db09fbd873372431a5ef63687.svg new file mode 100644 index 000000000..240122afd --- /dev/null +++ b/_images/inheritance-b6c44c2477a5029db09fbd873372431a5ef63687.svg @@ -0,0 +1,164 @@ + + +inheritancec91c21e962 + + +ConcurrentDeclarationRegionMixin + + +ConcurrentDeclarationRegionMixin + + + + + +PackageBody + + +PackageBody + + + + + +ConcurrentDeclarationRegionMixin->PackageBody + + + + + +DesignUnit + + +DesignUnit + + + + + +SecondaryUnit + + +SecondaryUnit + + + + + +DesignUnit->SecondaryUnit + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->DesignUnit + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->DesignUnit + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->DesignUnit + + + + + +DesignUnitWithContextMixin + + +DesignUnitWithContextMixin + + + + + +DesignUnitWithContextMixin->PackageBody + + + + + +Numeric_Bit_Unsigned_Body + + +Numeric_Bit_Unsigned_Body + + + + + +PredefinedPackageBody + + +PredefinedPackageBody + + + + + +PredefinedPackageBody->Numeric_Bit_Unsigned_Body + + + + + +PackageBody->PredefinedPackageBody + + + + + +SecondaryUnit->PackageBody + + + + + +PredefinedPackageMixin + + +PredefinedPackageMixin + + + + + +PredefinedPackageMixin->PredefinedPackageBody + + + + + \ No newline at end of file diff --git a/_images/inheritance-b6f58b5aebd770165a7903126fb01443707ab28b.svg b/_images/inheritance-b6f58b5aebd770165a7903126fb01443707ab28b.svg new file mode 100644 index 000000000..c37777cdd --- /dev/null +++ b/_images/inheritance-b6f58b5aebd770165a7903126fb01443707ab28b.svg @@ -0,0 +1,59 @@ + + +inheritance89e0ceedb6 + + +ConcurrentDeclarationRegionMixin + + +ConcurrentDeclarationRegionMixin + + + + + +GenerateBranch + + +GenerateBranch + + + + + +ConcurrentDeclarationRegionMixin->GenerateBranch + + + + + +ConcurrentStatementsMixin + + +ConcurrentStatementsMixin + + + + + +ConcurrentStatementsMixin->GenerateBranch + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->GenerateBranch + + + + + \ No newline at end of file diff --git a/_images/inheritance-b709d7643867c75c5710e180509ea1865e727f16.svg b/_images/inheritance-b709d7643867c75c5710e180509ea1865e727f16.svg new file mode 100644 index 000000000..5320dd3cb --- /dev/null +++ b/_images/inheritance-b709d7643867c75c5710e180509ea1865e727f16.svg @@ -0,0 +1,104 @@ + + +inheritance4a6bd0e3df + + +DesignUnit + + +DesignUnit + + + + + +PrimaryUnit + + +PrimaryUnit + + + + + +DesignUnit->PrimaryUnit + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->DesignUnit + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->DesignUnit + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->DesignUnit + + + + + +GenericInstantiationMixin + + +GenericInstantiationMixin + + + + + +PackageInstantiation + + +PackageInstantiation + + + + + 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b/_images/inheritance-b89af419c20e955d78f6606bb02578a3921321f8.svg @@ -0,0 +1,89 @@ + + +inheritance46c0dfd6ec + + +LabeledEntityMixin + + +LabeledEntityMixin + + + + + +Statement + + +Statement + + + + + +LabeledEntityMixin->Statement + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Statement + + + + + +ReportStatementMixin + + +ReportStatementMixin + + + + + +SequentialReportStatement + + +SequentialReportStatement + + + + + +ReportStatementMixin->SequentialReportStatement + + + + + +SequentialStatement + + +SequentialStatement + + + + + +SequentialStatement->SequentialReportStatement + + + + + +Statement->SequentialStatement + + + + + \ No newline at end of file diff --git a/_images/inheritance-b8d04c69149b743457e013f9cbf639e1bc18f62e.svg b/_images/inheritance-b8d04c69149b743457e013f9cbf639e1bc18f62e.svg new file mode 100644 index 000000000..810bd1c6c --- /dev/null +++ b/_images/inheritance-b8d04c69149b743457e013f9cbf639e1bc18f62e.svg @@ -0,0 +1,14 @@ + + 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b/_images/inheritance-b8fc221600cf874ef6719d957d8ffbd5767d9c88.svg @@ -0,0 +1,89 @@ + + +inheritancec13d6ee02e + + +AnonymousType + + +AnonymousType + + + + + +Type + + +Type + + + + + +Type->AnonymousType + + + + + +BaseType + + +BaseType + + + + + +BaseType->Type + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseType + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->BaseType + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->BaseType + + + + + \ No newline at end of file diff --git a/_images/inheritance-b9deae69969b1f3d124e5d83ba27953ccd7cbebb.svg b/_images/inheritance-b9deae69969b1f3d124e5d83ba27953ccd7cbebb.svg new file mode 100644 index 000000000..e79750d26 --- /dev/null +++ b/_images/inheritance-b9deae69969b1f3d124e5d83ba27953ccd7cbebb.svg @@ -0,0 +1,89 @@ + + +inheritancea09f72b942 + + +BaseExpression + + +BaseExpression + + + + + +BinaryExpression + + +BinaryExpression + + + + + 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a/_images/inheritance-ba7eb18410301c3b3389769a41125149212054af.svg b/_images/inheritance-ba7eb18410301c3b3389769a41125149212054af.svg new file mode 100644 index 000000000..a18f3691c --- /dev/null +++ b/_images/inheritance-ba7eb18410301c3b3389769a41125149212054af.svg @@ -0,0 +1,44 @@ + + +inheritance200a74259a + + +ModelEntity + + +ModelEntity + + + + + +Reference + + +Reference + + + + + +ModelEntity->Reference + + + + + +UseClause + + +UseClause + + + + + +Reference->UseClause + + + + + \ No newline at end of file diff --git a/_images/inheritance-bac10ba8f0a4a0aad64b5ec09e34bfdc4be06d19.svg b/_images/inheritance-bac10ba8f0a4a0aad64b5ec09e34bfdc4be06d19.svg new file mode 100644 index 000000000..e19b474fc --- /dev/null +++ b/_images/inheritance-bac10ba8f0a4a0aad64b5ec09e34bfdc4be06d19.svg @@ -0,0 +1,44 @@ + + +inheritance978b938a26 + + +BaseChoice + + +BaseChoice + + + + + +ConcurrentChoice + + +ConcurrentChoice + + + + + +BaseChoice->ConcurrentChoice + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseChoice + + + + + \ No newline at end of file diff --git a/_images/inheritance-bb192a87e09965ad8f1d7423e1b36f8e9507b762.svg b/_images/inheritance-bb192a87e09965ad8f1d7423e1b36f8e9507b762.svg new file mode 100644 index 000000000..81998a887 --- /dev/null +++ b/_images/inheritance-bb192a87e09965ad8f1d7423e1b36f8e9507b762.svg @@ -0,0 +1,104 @@ + + +inheritancec74d712283 + + +Configuration + + +Configuration + + + + + +PrimaryUnit + + +PrimaryUnit + + + + + +PrimaryUnit->Configuration + + + + + +DesignUnitWithContextMixin + + +DesignUnitWithContextMixin + + + + + +DesignUnitWithContextMixin->Configuration + + + + + +DesignUnit + + +DesignUnit + + + + + +DesignUnit->PrimaryUnit + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->DesignUnit + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->DesignUnit + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->DesignUnit + + + + + \ No newline at end of file diff --git a/_images/inheritance-bb431cec7a652a17f91bdf7b88624bc30a29162b.svg b/_images/inheritance-bb431cec7a652a17f91bdf7b88624bc30a29162b.svg new file mode 100644 index 000000000..9f71d6941 --- /dev/null +++ b/_images/inheritance-bb431cec7a652a17f91bdf7b88624bc30a29162b.svg @@ -0,0 +1,44 @@ + + +inheritance3976506a58 + + +SimpleSubtypeSymbol + + +SimpleSubtypeSymbol + + + + + +SubtypeSymbol + + +SubtypeSymbol + + + + + +SubtypeSymbol->SimpleSubtypeSymbol + + + + + +Symbol + + +Symbol + + + + + +Symbol->SubtypeSymbol + + + + + \ No newline at end of file diff --git a/_images/inheritance-bc2eb758d84f669cff3331c4c5a3c7edbd8118e3.svg b/_images/inheritance-bc2eb758d84f669cff3331c4c5a3c7edbd8118e3.svg new file mode 100644 index 000000000..df2b3b9e1 --- /dev/null +++ b/_images/inheritance-bc2eb758d84f669cff3331c4c5a3c7edbd8118e3.svg @@ -0,0 +1,134 @@ + + +inheritance88e9d1aaa6 + + +BranchMixin + + +BranchMixin + + + + + +ConditionalBranchMixin + + +ConditionalBranchMixin + + + + + +BranchMixin->ConditionalBranchMixin + + + + + +ConcurrentDeclarationRegionMixin + + +ConcurrentDeclarationRegionMixin + + + + + +GenerateBranch + + +GenerateBranch + + + + + +ConcurrentDeclarationRegionMixin->GenerateBranch + + + + + +ConcurrentStatementsMixin + + +ConcurrentStatementsMixin + + + + + +ConcurrentStatementsMixin->GenerateBranch + + + + + +ElsifBranchMixin + + +ElsifBranchMixin + + + + + +ConditionalBranchMixin->ElsifBranchMixin + + + + + +ConditionalMixin + + +ConditionalMixin + + + + + +ConditionalMixin->ConditionalBranchMixin + + + + + +ElsifGenerateBranch + + +ElsifGenerateBranch + + + + + +ElsifBranchMixin->ElsifGenerateBranch + + + + + +GenerateBranch->ElsifGenerateBranch + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->GenerateBranch + + + + + \ No newline at end of file diff --git a/_images/inheritance-bd30d501cad919fdca919b0c7293545466a61633.svg b/_images/inheritance-bd30d501cad919fdca919b0c7293545466a61633.svg new file mode 100644 index 000000000..82ec36305 --- /dev/null +++ b/_images/inheritance-bd30d501cad919fdca919b0c7293545466a61633.svg @@ -0,0 +1,59 @@ + + +inheritance34ed945e77 + + +BaseExpression + + +BaseExpression + + + + + +BinaryExpression + + +BinaryExpression + + + + + +BaseExpression->BinaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +RelationalExpression + + +RelationalExpression + + + + + +BinaryExpression->RelationalExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-bdfb222c3b3faae513ca078744ecd807b89555cb.svg b/_images/inheritance-bdfb222c3b3faae513ca078744ecd807b89555cb.svg new file mode 100644 index 000000000..181500c74 --- /dev/null +++ b/_images/inheritance-bdfb222c3b3faae513ca078744ecd807b89555cb.svg @@ -0,0 +1,29 @@ + + +inheritance544022e20e + + +EntityClass + + +EntityClass + + + + + +Enum + + +Enum + + + + + +Enum->EntityClass + + + + + \ No newline at end of file diff --git a/_images/inheritance-bec59857d57d823a6fe9d94205ed71db1fb074ea.svg b/_images/inheritance-bec59857d57d823a6fe9d94205ed71db1fb074ea.svg new file mode 100644 index 000000000..809d0a214 --- /dev/null +++ b/_images/inheritance-bec59857d57d823a6fe9d94205ed71db1fb074ea.svg @@ -0,0 +1,89 @@ + + +inheritancee1b2c861b3 + + +AccessType + + +AccessType + + + + + +FullType + + +FullType + + + + + +FullType->AccessType + + + + + +BaseType + + +BaseType + + + + + +BaseType->FullType + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseType + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->BaseType + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->BaseType + + + + + \ No newline at end of file diff --git a/_images/inheritance-bf72056d3ac67df3e61ba535f1b210108f885ef0.svg b/_images/inheritance-bf72056d3ac67df3e61ba535f1b210108f885ef0.svg new file mode 100644 index 000000000..3c533898b --- /dev/null +++ b/_images/inheritance-bf72056d3ac67df3e61ba535f1b210108f885ef0.svg @@ -0,0 +1,134 @@ + + +inheritance16e9523ad1 + + +BaseType + + +BaseType + + + + + +FullType + + +FullType + + + + + +BaseType->FullType + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseType + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->BaseType + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->BaseType + + + + + +ScalarType + + +ScalarType + + + + + +FullType->ScalarType + + + + + +NumericTypeMixin + + +NumericTypeMixin + + + + + +RealType + + +RealType + + + + + +NumericTypeMixin->RealType + + + + + +RangedScalarType + + +RangedScalarType + + + + + +RangedScalarType->RealType + + + + + +ScalarType->RangedScalarType + + + + + \ No newline at end of file diff --git a/_images/inheritance-c0b8fc127066e2da3d2cbe3af148a2cca40618b0.svg b/_images/inheritance-c0b8fc127066e2da3d2cbe3af148a2cca40618b0.svg new file mode 100644 index 000000000..245820b91 --- /dev/null +++ b/_images/inheritance-c0b8fc127066e2da3d2cbe3af148a2cca40618b0.svg @@ -0,0 +1,74 @@ + + +inheritance85726c16db + + +BaseExpression + + +BaseExpression + + + + + +BinaryExpression + + +BinaryExpression + + + + + +BaseExpression->BinaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +MultiplyingExpression + + +MultiplyingExpression + + + + + +BinaryExpression->MultiplyingExpression + + + + + +ExponentiationExpression + + +ExponentiationExpression + + + + + +MultiplyingExpression->ExponentiationExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-c0d3af9bc3b9d017fd2797c66040ad098a09ecce.svg b/_images/inheritance-c0d3af9bc3b9d017fd2797c66040ad098a09ecce.svg new file mode 100644 index 000000000..a6c8b1427 --- /dev/null +++ b/_images/inheritance-c0d3af9bc3b9d017fd2797c66040ad098a09ecce.svg @@ -0,0 +1,89 @@ + + +inheritance953873d1d9 + + +Context + + +Context + + + + + +PrimaryUnit + + +PrimaryUnit + + + + + +PrimaryUnit->Context + + + + + +DesignUnit + + +DesignUnit + + + + + +DesignUnit->PrimaryUnit + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->DesignUnit + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->DesignUnit + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->DesignUnit + + + + + \ No newline at end of file diff --git a/_images/inheritance-c0eb64ef3db16cdff892e1ad528919ef6dc38088.svg b/_images/inheritance-c0eb64ef3db16cdff892e1ad528919ef6dc38088.svg new file mode 100644 index 000000000..fdb8d4058 --- /dev/null +++ b/_images/inheritance-c0eb64ef3db16cdff892e1ad528919ef6dc38088.svg @@ -0,0 +1,14 @@ + + +inheritance02736034c8 + + +SequentialStatementsMixin + + +SequentialStatementsMixin + + + + + \ No newline at end of file diff --git a/_images/inheritance-c183d7eda3a0ddb9e46a4c422913b33f65f449da.svg b/_images/inheritance-c183d7eda3a0ddb9e46a4c422913b33f65f449da.svg new file mode 100644 index 000000000..5d11cd01d --- /dev/null +++ b/_images/inheritance-c183d7eda3a0ddb9e46a4c422913b33f65f449da.svg @@ -0,0 +1,119 @@ + + +inheritancef2f225670c + + +AssignmentMixin + + +AssignmentMixin + + + + + +SignalAssignmentMixin + + +SignalAssignmentMixin + + + + + +AssignmentMixin->SignalAssignmentMixin + + + + + +ConcurrentConditionalSignalAssignment + + +ConcurrentConditionalSignalAssignment + + + + + +ConcurrentSignalAssignment + + +ConcurrentSignalAssignment + + + + + +ConcurrentSignalAssignment->ConcurrentConditionalSignalAssignment + + + + + +ConcurrentStatement + + +ConcurrentStatement + + + + + +ConcurrentStatement->ConcurrentSignalAssignment + + + + + +SignalAssignmentMixin->ConcurrentSignalAssignment + + + + + +Statement + + +Statement + + + + + +Statement->ConcurrentStatement + + + + + +LabeledEntityMixin + + +LabeledEntityMixin + + + + + +LabeledEntityMixin->Statement + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Statement + + + + + \ No newline at end of file diff --git a/_images/inheritance-c195f5aae36146ea0682bccea8d5e45dd11b8211.svg b/_images/inheritance-c195f5aae36146ea0682bccea8d5e45dd11b8211.svg new file mode 100644 index 000000000..b0732e01a --- /dev/null +++ b/_images/inheritance-c195f5aae36146ea0682bccea8d5e45dd11b8211.svg @@ -0,0 +1,29 @@ + + +inheritance7581ab1270 + + +BaseExpression + + +BaseExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-c1b27db6ea33a3b3e5094402d8f060dd4ea3d3e5.svg b/_images/inheritance-c1b27db6ea33a3b3e5094402d8f060dd4ea3d3e5.svg new file mode 100644 index 000000000..7b94bf8fd --- /dev/null +++ b/_images/inheritance-c1b27db6ea33a3b3e5094402d8f060dd4ea3d3e5.svg @@ -0,0 +1,44 @@ + + +inheritanced72a330be9 + + +Aggregate + + +Aggregate + + + + + +BaseExpression + + +BaseExpression + + + + + +BaseExpression->Aggregate + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-c3a7ff47e9d4a053befdb53b89fafe749419ebbf.svg b/_images/inheritance-c3a7ff47e9d4a053befdb53b89fafe749419ebbf.svg new file mode 100644 index 000000000..d5ecb57af --- /dev/null +++ b/_images/inheritance-c3a7ff47e9d4a053befdb53b89fafe749419ebbf.svg @@ -0,0 +1,44 @@ + + +inheritance655ab2ff05 + + +AggregateElement + + +AggregateElement + + + + + +RangedAggregateElement + + +RangedAggregateElement + + + + + +AggregateElement->RangedAggregateElement + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->AggregateElement + + + + + \ No newline at end of file diff --git a/_images/inheritance-c51266d1032a64747807bf8111bf018632d0b4a3.svg b/_images/inheritance-c51266d1032a64747807bf8111bf018632d0b4a3.svg new file mode 100644 index 000000000..090374999 --- /dev/null +++ b/_images/inheritance-c51266d1032a64747807bf8111bf018632d0b4a3.svg @@ -0,0 +1,164 @@ + + +inheritanceb84e47764c + + +ConcurrentDeclarationRegionMixin + + +ConcurrentDeclarationRegionMixin + + + + + +Package + + +Package + + + + + +ConcurrentDeclarationRegionMixin->Package + + + + + +DesignUnit + + +DesignUnit + + + + + +PrimaryUnit + + +PrimaryUnit + + + + + +DesignUnit->PrimaryUnit + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->DesignUnit + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->DesignUnit + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->DesignUnit + + + + + +DesignUnitWithContextMixin + + +DesignUnitWithContextMixin + + + + + +DesignUnitWithContextMixin->Package + + + + + +PredefinedPackage + + +PredefinedPackage + + + + + +Package->PredefinedPackage + + + + + +PrimaryUnit->Package + + + + + +std_logic_textio + + +std_logic_textio + + + + + +PredefinedPackage->std_logic_textio + + + + + +PredefinedPackageMixin + + +PredefinedPackageMixin + + + + + +PredefinedPackageMixin->PredefinedPackage + + + + + \ No newline at end of file diff --git a/_images/inheritance-c738c447924640c882bbe0913e6559d8e73ef5e2.svg b/_images/inheritance-c738c447924640c882bbe0913e6559d8e73ef5e2.svg new file mode 100644 index 000000000..403f6f6c6 --- /dev/null +++ b/_images/inheritance-c738c447924640c882bbe0913e6559d8e73ef5e2.svg @@ -0,0 +1,29 @@ + + +inheritance9286b22121 + + +Direction + + +Direction + + + + + +Enum + + +Enum + + + + + +Enum->Direction + + + + + \ No newline at end of file diff --git a/_images/inheritance-c7fcc6557955bc9125037187d1ac3016a94cf92a.svg b/_images/inheritance-c7fcc6557955bc9125037187d1ac3016a94cf92a.svg new file mode 100644 index 000000000..bdf588aed --- /dev/null +++ b/_images/inheritance-c7fcc6557955bc9125037187d1ac3016a94cf92a.svg @@ -0,0 +1,89 @@ + + +inheritanced23f4eb606 + + +ConcurrentStatement + + +ConcurrentStatement + + + + + +Instantiation + + +Instantiation + + + + + +ConcurrentStatement->Instantiation + + + + + +Statement + + +Statement + + + + + +Statement->ConcurrentStatement + + + + + +ConfigurationInstantiation + + +ConfigurationInstantiation + + + + + +Instantiation->ConfigurationInstantiation + + + + + +LabeledEntityMixin + + +LabeledEntityMixin + + + + + +LabeledEntityMixin->Statement + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Statement + + + + + \ No newline at end of file diff --git a/_images/inheritance-c8b2076fe665965c77dee18bafb72d74f839d21a.svg b/_images/inheritance-c8b2076fe665965c77dee18bafb72d74f839d21a.svg new file mode 100644 index 000000000..8371d05e7 --- /dev/null +++ b/_images/inheritance-c8b2076fe665965c77dee18bafb72d74f839d21a.svg @@ -0,0 +1,125 @@ + + +inheritance59338c9b33 + + +BaseType + + +BaseType + + + + + +Type + + +Type + + + + + +BaseType->Type + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseType + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + 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--git a/_images/inheritance-ccabf45948c6e09c7398d6198c74b2a80b093dfe.svg b/_images/inheritance-ccabf45948c6e09c7398d6198c74b2a80b093dfe.svg new file mode 100644 index 000000000..480e10048 --- /dev/null +++ b/_images/inheritance-ccabf45948c6e09c7398d6198c74b2a80b093dfe.svg @@ -0,0 +1,29 @@ + + +inheritancefa65c068da + + +ModelEntity + + +ModelEntity + + + + + +WaveformElement + + +WaveformElement + + + + + +ModelEntity->WaveformElement + + + + + \ No newline at end of file diff --git a/_images/inheritance-ccbf95d3b936fc9db9ceb2cf456df4e2faa1ebb9.svg b/_images/inheritance-ccbf95d3b936fc9db9ceb2cf456df4e2faa1ebb9.svg new file mode 100644 index 000000000..3187f0edf --- /dev/null +++ b/_images/inheritance-ccbf95d3b936fc9db9ceb2cf456df4e2faa1ebb9.svg @@ -0,0 +1,29 @@ + + +inheritance22eb519fbf + + +PackageSymbol + + +PackageSymbol + + + + + +Symbol + + +Symbol + + + + + +Symbol->PackageSymbol + + + + + \ No newline at end of file diff --git a/_images/inheritance-cd563ea49b1e161bc4455336f7b77cc9089cddbc.svg b/_images/inheritance-cd563ea49b1e161bc4455336f7b77cc9089cddbc.svg new file mode 100644 index 000000000..3e2d0e44d --- /dev/null +++ b/_images/inheritance-cd563ea49b1e161bc4455336f7b77cc9089cddbc.svg @@ -0,0 +1,44 @@ + + +inheritance8bbfa73c9d + + +ModelEntity + + +ModelEntity + + + + + +Name + + +Name + + + + + +ModelEntity->Name + + + + + +ParenthesisName + + +ParenthesisName + + + + + +Name->ParenthesisName + + + + + \ No newline at end of file diff --git a/_images/inheritance-ce230f4c89a4e4228d3e85a220bbb9212d11c2b4.svg b/_images/inheritance-ce230f4c89a4e4228d3e85a220bbb9212d11c2b4.svg new file mode 100644 index 000000000..86a20f2fc --- /dev/null +++ b/_images/inheritance-ce230f4c89a4e4228d3e85a220bbb9212d11c2b4.svg @@ -0,0 +1,59 @@ + + +inheritancecba8d610dc + + +BaseExpression + + +BaseExpression + + + + + +TernaryExpression + + +TernaryExpression + + + + + +BaseExpression->TernaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +WhenElseExpression + + +WhenElseExpression + + + + + +TernaryExpression->WhenElseExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-ce6401442e55c8b78caa754557388c69c0af4457.svg b/_images/inheritance-ce6401442e55c8b78caa754557388c69c0af4457.svg new file mode 100644 index 000000000..44d1b5e69 --- /dev/null +++ b/_images/inheritance-ce6401442e55c8b78caa754557388c69c0af4457.svg @@ -0,0 +1,29 @@ + + +inheritance926c9b4989 + + +PackageReferenceSymbol + + +PackageReferenceSymbol + + + + + +Symbol + + +Symbol + + + + + +Symbol->PackageReferenceSymbol + + + + + \ No newline at end of file diff --git a/_images/inheritance-cec3bb4772b6e4ba9c87b122a5bec5918b1d653e.svg b/_images/inheritance-cec3bb4772b6e4ba9c87b122a5bec5918b1d653e.svg new file mode 100644 index 000000000..2435e53e7 --- /dev/null +++ b/_images/inheritance-cec3bb4772b6e4ba9c87b122a5bec5918b1d653e.svg @@ -0,0 +1,164 @@ + + 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+PredefinedPackageMixin + + + + + +PredefinedPackageMixin->PredefinedPackageBody + + + + + \ No newline at end of file diff --git a/_images/inheritance-ceea72606d7e039c4fadf14ab5ed7df7f992e36b.svg b/_images/inheritance-ceea72606d7e039c4fadf14ab5ed7df7f992e36b.svg new file mode 100644 index 000000000..87c6756fd --- /dev/null +++ b/_images/inheritance-ceea72606d7e039c4fadf14ab5ed7df7f992e36b.svg @@ -0,0 +1,29 @@ + + +inheritance3b6ce52305 + + +ModelEntity + + +ModelEntity + + + + + +Range + + +Range + + + + + +ModelEntity->Range + + + + + \ No newline at end of file diff --git a/_images/inheritance-cf5c42c6e986703472131fd8128fb4665ff41c5e.svg b/_images/inheritance-cf5c42c6e986703472131fd8128fb4665ff41c5e.svg new file mode 100644 index 000000000..41f2aa1da --- /dev/null +++ b/_images/inheritance-cf5c42c6e986703472131fd8128fb4665ff41c5e.svg @@ -0,0 +1,29 @@ + + +inheritance43197cf93f + + +ArchitectureExistsInLibraryError + + +ArchitectureExistsInLibraryError + + + + + +VHDLModelException + + +VHDLModelException + + + + + +VHDLModelException->ArchitectureExistsInLibraryError + + + + + \ No newline at end of file diff --git a/_images/inheritance-cf6e08b9162692df2682f1f67679767a878307af.svg b/_images/inheritance-cf6e08b9162692df2682f1f67679767a878307af.svg new file mode 100644 index 000000000..10ecbf9c3 --- /dev/null +++ b/_images/inheritance-cf6e08b9162692df2682f1f67679767a878307af.svg @@ -0,0 +1,164 @@ + + +inheritance66960ed388 + + +ConcurrentDeclarationRegionMixin + + +ConcurrentDeclarationRegionMixin + + + + + +Package + + +Package + + + + + +ConcurrentDeclarationRegionMixin->Package + + + + + +DesignUnit + + +DesignUnit + + + + + +PrimaryUnit + + +PrimaryUnit + + + + + +DesignUnit->PrimaryUnit + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->DesignUnit + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->DesignUnit + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->DesignUnit + + + + + +DesignUnitWithContextMixin + + +DesignUnitWithContextMixin + + + + + +DesignUnitWithContextMixin->Package + + + + + +PredefinedPackage + + +PredefinedPackage + + + + + +Package->PredefinedPackage + + + + + +PrimaryUnit->Package + + + + + +TextIO + + +TextIO + + + + + +PredefinedPackage->TextIO + + + + + +PredefinedPackageMixin + + +PredefinedPackageMixin + + + + + +PredefinedPackageMixin->PredefinedPackage + + + + + \ No newline at end of file diff --git a/_images/inheritance-d063cbd2eb10a5099cb747a8465dea63da6b171a.svg b/_images/inheritance-d063cbd2eb10a5099cb747a8465dea63da6b171a.svg new file mode 100644 index 000000000..f89bf5772 --- /dev/null +++ b/_images/inheritance-d063cbd2eb10a5099cb747a8465dea63da6b171a.svg @@ -0,0 +1,164 @@ + + +inheritance2d221c302d + + +ConcurrentDeclarationRegionMixin + + +ConcurrentDeclarationRegionMixin + + + + + +PackageBody + + +PackageBody + + + + + +ConcurrentDeclarationRegionMixin->PackageBody + + + + + +DesignUnit + + +DesignUnit + + + + + +SecondaryUnit + + +SecondaryUnit + + + + + +DesignUnit->SecondaryUnit + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->DesignUnit + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->DesignUnit + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->DesignUnit + + + + + +DesignUnitWithContextMixin + + +DesignUnitWithContextMixin + + + + + +DesignUnitWithContextMixin->PackageBody + + + + + +Math_Real_Body + + +Math_Real_Body + + + + + +PredefinedPackageBody + + +PredefinedPackageBody + + + + + +PredefinedPackageBody->Math_Real_Body + + + + + +PackageBody->PredefinedPackageBody + + + + + +SecondaryUnit->PackageBody + + + + + +PredefinedPackageMixin + + +PredefinedPackageMixin + + + + + +PredefinedPackageMixin->PredefinedPackageBody + + + + + \ No newline at end of file diff --git a/_images/inheritance-d1af42a7d7e76c4420ade784181a8277f8fc28ef.svg b/_images/inheritance-d1af42a7d7e76c4420ade784181a8277f8fc28ef.svg new file mode 100644 index 000000000..8c688c162 --- /dev/null +++ b/_images/inheritance-d1af42a7d7e76c4420ade784181a8277f8fc28ef.svg @@ -0,0 +1,14 @@ + + +inheritanceeb991d8a4d + + +ProcedureCallMixin + + +ProcedureCallMixin + + + + + \ No newline at end of file diff --git a/_images/inheritance-d21fe96d0e34a8161c079d76b9a2093ecbe8d689.svg b/_images/inheritance-d21fe96d0e34a8161c079d76b9a2093ecbe8d689.svg new file mode 100644 index 000000000..22bb1fb7a --- /dev/null +++ b/_images/inheritance-d21fe96d0e34a8161c079d76b9a2093ecbe8d689.svg @@ -0,0 +1,74 @@ + + +inheritanced82a32f0fb + + +BaseExpression + + +BaseExpression + + + + + +BinaryExpression + + +BinaryExpression + + + + + +BaseExpression->BinaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +RelationalExpression + + +RelationalExpression + + + + + +BinaryExpression->RelationalExpression + + + + + +LessThanExpression + + +LessThanExpression + + + + + +RelationalExpression->LessThanExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-d3612ce7fb393f59653e7e20da14c9e6dff9532b.svg b/_images/inheritance-d3612ce7fb393f59653e7e20da14c9e6dff9532b.svg new file mode 100644 index 000000000..5ea9f9217 --- /dev/null +++ b/_images/inheritance-d3612ce7fb393f59653e7e20da14c9e6dff9532b.svg @@ -0,0 +1,74 @@ + + +inheritancea570bd9fda + + +BaseExpression + + +BaseExpression + + + + + +BinaryExpression + + +BinaryExpression + + + + + +BaseExpression->BinaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +RelationalExpression + + +RelationalExpression + + + + + +BinaryExpression->RelationalExpression + + + + + +GreaterThanExpression + + +GreaterThanExpression + + + + + +RelationalExpression->GreaterThanExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-d368ff9dd2bfc3bef92c3151d0dcb29fe45fbf3f.svg b/_images/inheritance-d368ff9dd2bfc3bef92c3151d0dcb29fe45fbf3f.svg new file mode 100644 index 000000000..e03ab886e --- /dev/null +++ b/_images/inheritance-d368ff9dd2bfc3bef92c3151d0dcb29fe45fbf3f.svg @@ -0,0 +1,119 @@ + + +inheritance9005ca401a + + +AssignmentMixin + + +AssignmentMixin + + + + + +SignalAssignmentMixin + + +SignalAssignmentMixin + + + + + +AssignmentMixin->SignalAssignmentMixin + + + + + +ConcurrentSelectedSignalAssignment + + +ConcurrentSelectedSignalAssignment + + + + + +ConcurrentSignalAssignment + + +ConcurrentSignalAssignment + + + + + +ConcurrentSignalAssignment->ConcurrentSelectedSignalAssignment + + + + + +ConcurrentStatement + + +ConcurrentStatement + + + + + +ConcurrentStatement->ConcurrentSignalAssignment + + + + + +SignalAssignmentMixin->ConcurrentSignalAssignment + + + + + +Statement + + +Statement + + + + + +Statement->ConcurrentStatement + + + + + +LabeledEntityMixin + + +LabeledEntityMixin + + + + + +LabeledEntityMixin->Statement + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Statement + + + + + \ No newline at end of file diff --git a/_images/inheritance-d3e97cb9eb47447513d9622349da1a84f3b4c220.svg b/_images/inheritance-d3e97cb9eb47447513d9622349da1a84f3b4c220.svg new file mode 100644 index 000000000..31ca47d77 --- /dev/null +++ b/_images/inheritance-d3e97cb9eb47447513d9622349da1a84f3b4c220.svg @@ -0,0 +1,29 @@ + + +inheritancee7a3147e12 + + +AssociationItem + + +AssociationItem + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->AssociationItem + + + + + \ No newline at end of file diff --git a/_images/inheritance-d42643367840d1f46bf8c13b301f8353a84c621a.svg b/_images/inheritance-d42643367840d1f46bf8c13b301f8353a84c621a.svg new file mode 100644 index 000000000..7d37275ff --- /dev/null +++ b/_images/inheritance-d42643367840d1f46bf8c13b301f8353a84c621a.svg @@ -0,0 +1,44 @@ + + +inheritance0376ade860 + + +Document + + +Document + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Document + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->Document + + + + + \ No newline at end of file diff --git a/_images/inheritance-d5b3965bf88a513a3beb9e28d5592596229d6bc5.svg b/_images/inheritance-d5b3965bf88a513a3beb9e28d5592596229d6bc5.svg new file mode 100644 index 000000000..673fad877 --- /dev/null +++ b/_images/inheritance-d5b3965bf88a513a3beb9e28d5592596229d6bc5.svg @@ -0,0 +1,59 @@ + + +inheritance637d0c3895 + + +BaseChoice + + +BaseChoice + + + + + +SequentialChoice + + +SequentialChoice + + + + + +BaseChoice->SequentialChoice + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseChoice + + + + + +IndexedChoice + + +IndexedChoice + + + + + +SequentialChoice->IndexedChoice + + + + + \ No newline at end of file diff --git a/_images/inheritance-d63a0440aadf44d7a1d159484a7c7bf9795c68b1.svg b/_images/inheritance-d63a0440aadf44d7a1d159484a7c7bf9795c68b1.svg new file mode 100644 index 000000000..d696795fb --- /dev/null +++ b/_images/inheritance-d63a0440aadf44d7a1d159484a7c7bf9795c68b1.svg @@ -0,0 +1,59 @@ + + +inheritancef6e94dce00 + + +Alias + + +Alias + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Alias + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->Alias + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->Alias + + + + + \ No newline at end of file diff --git a/_images/inheritance-d72a76fd96f5a87915fabced42aebc777c1254cb.svg b/_images/inheritance-d72a76fd96f5a87915fabced42aebc777c1254cb.svg new file mode 100644 index 000000000..25bb9d951 --- /dev/null +++ b/_images/inheritance-d72a76fd96f5a87915fabced42aebc777c1254cb.svg @@ -0,0 +1,119 @@ + + +inheritance3c3ffed631 + + +AssertStatementMixin + + +AssertStatementMixin + + + + + +SequentialAssertStatement + + +SequentialAssertStatement + + + + + +AssertStatementMixin->SequentialAssertStatement + + + + + +ReportStatementMixin + + +ReportStatementMixin + + + + + +ReportStatementMixin->AssertStatementMixin + + + + + +ConditionalMixin + + +ConditionalMixin + + + + + +ConditionalMixin->AssertStatementMixin + + + + + +LabeledEntityMixin + + +LabeledEntityMixin + + + + + +Statement + + +Statement + + + + + +LabeledEntityMixin->Statement + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Statement + + + + + +SequentialStatement + + +SequentialStatement + + + + + +SequentialStatement->SequentialAssertStatement + + + + + +Statement->SequentialStatement + + + + + \ No newline at end of file diff --git a/_images/inheritance-d8ac8ca80ebda529446c124d91c007878673f72f.svg b/_images/inheritance-d8ac8ca80ebda529446c124d91c007878673f72f.svg new file mode 100644 index 000000000..6898e6a96 --- /dev/null +++ b/_images/inheritance-d8ac8ca80ebda529446c124d91c007878673f72f.svg @@ -0,0 +1,164 @@ + + +inheritance1151c7a813 + + +ConcurrentDeclarationRegionMixin + + +ConcurrentDeclarationRegionMixin + + + + + +PackageBody + + +PackageBody + + + + + +ConcurrentDeclarationRegionMixin->PackageBody + + + + + +DesignUnit + + +DesignUnit + + + + + +SecondaryUnit + + +SecondaryUnit + + + + + +DesignUnit->SecondaryUnit + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->DesignUnit + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->DesignUnit + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->DesignUnit + + + + + +DesignUnitWithContextMixin + + +DesignUnitWithContextMixin + + + + + +DesignUnitWithContextMixin->PackageBody + + + + + +Numeric_Bit_Body + + +Numeric_Bit_Body + + + + + +PredefinedPackageBody + + +PredefinedPackageBody + + + + + +PredefinedPackageBody->Numeric_Bit_Body + + + + + +PackageBody->PredefinedPackageBody + + + + + +SecondaryUnit->PackageBody + + + + + +PredefinedPackageMixin + + +PredefinedPackageMixin + + + + + +PredefinedPackageMixin->PredefinedPackageBody + + + + + \ No newline at end of file diff --git a/_images/inheritance-d903ef658d7758c61a36d25868b231ec570fc6a2.svg b/_images/inheritance-d903ef658d7758c61a36d25868b231ec570fc6a2.svg new file mode 100644 index 000000000..af979090a --- /dev/null +++ b/_images/inheritance-d903ef658d7758c61a36d25868b231ec570fc6a2.svg @@ -0,0 +1,164 @@ + + +inheritance53db814612 + + +ConcurrentDeclarationRegionMixin + + +ConcurrentDeclarationRegionMixin + + + + + +Package + + +Package + + + + + +ConcurrentDeclarationRegionMixin->Package + + + + + +DesignUnit + + +DesignUnit + + + + + +PrimaryUnit + + +PrimaryUnit + + + + + +DesignUnit->PrimaryUnit + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->DesignUnit + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->DesignUnit + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->DesignUnit + + + + + +DesignUnitWithContextMixin + + +DesignUnitWithContextMixin + + + + + +DesignUnitWithContextMixin->Package + + + + + +Fixed_Generic_Pkg + + +Fixed_Generic_Pkg + + + + + +PredefinedPackage + + +PredefinedPackage + + + + + +PredefinedPackage->Fixed_Generic_Pkg + + + + + +Package->PredefinedPackage + + + + + +PrimaryUnit->Package + + + + + +PredefinedPackageMixin + + +PredefinedPackageMixin + + + + + +PredefinedPackageMixin->PredefinedPackage + + + + + \ No newline at end of file diff --git a/_images/inheritance-d90dc30dd4ce21c1a049bc486de4ee098c832eb9.svg b/_images/inheritance-d90dc30dd4ce21c1a049bc486de4ee098c832eb9.svg new file mode 100644 index 000000000..72ee342bb --- /dev/null +++ b/_images/inheritance-d90dc30dd4ce21c1a049bc486de4ee098c832eb9.svg @@ -0,0 +1,89 @@ + + +inheritance4391dd6bc3 + + +ConcurrentProcedureCall + + +ConcurrentProcedureCall + + + + + +ConcurrentStatement + + +ConcurrentStatement + + + + + +ConcurrentStatement->ConcurrentProcedureCall + + + + + +ProcedureCallMixin + + +ProcedureCallMixin + + + + + +ProcedureCallMixin->ConcurrentProcedureCall + + + + + +Statement + + +Statement + + + + + +Statement->ConcurrentStatement + + + + + +LabeledEntityMixin + + +LabeledEntityMixin + + + + + +LabeledEntityMixin->Statement + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Statement + + + + + \ No newline at end of file diff --git a/_images/inheritance-da2abda11b0d0f1e9facab8bfe4a1ec4fce74010.svg b/_images/inheritance-da2abda11b0d0f1e9facab8bfe4a1ec4fce74010.svg new file mode 100644 index 000000000..f30352ca4 --- /dev/null +++ b/_images/inheritance-da2abda11b0d0f1e9facab8bfe4a1ec4fce74010.svg @@ -0,0 +1,14 @@ + + +inheritancea610ef3e4f + + +WithDefaultExpressionMixin + + +WithDefaultExpressionMixin + + + + + \ No newline at end of file diff --git a/_images/inheritance-dadff9c7392e0a2076776984597fac6890841746.svg b/_images/inheritance-dadff9c7392e0a2076776984597fac6890841746.svg new file mode 100644 index 000000000..cece66577 --- /dev/null +++ b/_images/inheritance-dadff9c7392e0a2076776984597fac6890841746.svg @@ -0,0 +1,29 @@ + + +inheritancee5a4c3d267 + + +IndexedObjectOrFunctionCallSymbol + + +IndexedObjectOrFunctionCallSymbol + + + + + +Symbol + + +Symbol + + + + + +Symbol->IndexedObjectOrFunctionCallSymbol + + + + + \ No newline at end of file diff --git a/_images/inheritance-dcc95b95b22e2f846d143a5f9e159b9642c015b2.svg b/_images/inheritance-dcc95b95b22e2f846d143a5f9e159b9642c015b2.svg new file mode 100644 index 000000000..61e5ba736 --- /dev/null +++ b/_images/inheritance-dcc95b95b22e2f846d143a5f9e159b9642c015b2.svg @@ -0,0 +1,89 @@ + + +inheritancecb50301fcb + + +BaseExpression + + +BaseExpression + + + + + +BinaryExpression + + +BinaryExpression + + + + + +BaseExpression->BinaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +RelationalExpression + + +RelationalExpression + + + + + +BinaryExpression->RelationalExpression + + + + + +MatchingGreaterThanExpression + + +MatchingGreaterThanExpression + + + + + +MatchingRelationalExpression + + +MatchingRelationalExpression + + + + + +MatchingRelationalExpression->MatchingGreaterThanExpression + + + + + +RelationalExpression->MatchingRelationalExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-df368d1ef7b7ff331f8f98fb98734cbbbc70f470.svg b/_images/inheritance-df368d1ef7b7ff331f8f98fb98734cbbbc70f470.svg new file mode 100644 index 000000000..f19b23558 --- /dev/null +++ b/_images/inheritance-df368d1ef7b7ff331f8f98fb98734cbbbc70f470.svg @@ -0,0 +1,44 @@ + + +inheritanceae258c7d90 + + +AttributeSpecification + + +AttributeSpecification + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->AttributeSpecification + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->AttributeSpecification + + + + + \ No newline at end of file diff --git a/_images/inheritance-dfbdaf913d1b75b71e7093f40dc0301f2d93b93e.svg b/_images/inheritance-dfbdaf913d1b75b71e7093f40dc0301f2d93b93e.svg new file mode 100644 index 000000000..0425d9251 --- /dev/null +++ b/_images/inheritance-dfbdaf913d1b75b71e7093f40dc0301f2d93b93e.svg @@ -0,0 +1,44 @@ + + +inheritance45b27b47af + + +AggregateElement + + +AggregateElement + + + + + +OthersAggregateElement + + +OthersAggregateElement + + + + + +AggregateElement->OthersAggregateElement + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->AggregateElement + + + + + \ No newline at end of file diff --git a/_images/inheritance-e100ccfb9deb41d7d112d1be0508347a7eb5f7f2.svg b/_images/inheritance-e100ccfb9deb41d7d112d1be0508347a7eb5f7f2.svg new file mode 100644 index 000000000..a54c500dd --- /dev/null +++ b/_images/inheritance-e100ccfb9deb41d7d112d1be0508347a7eb5f7f2.svg @@ -0,0 +1,89 @@ + + +inheritanced26fbde147 + + +BaseCase + + +BaseCase + + + + + +ConcurrentCase + + +ConcurrentCase + + + + + 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000000000..521a0ea18 --- /dev/null +++ b/_images/inheritance-e2e0484f1898a31e5535a275be3524de888958ad.svg @@ -0,0 +1,44 @@ + + +inheritance83e8eeb812 + + +DesignUnitKind + + +DesignUnitKind + + + + + +Flag + + +Flag + + + + + +Flag->DesignUnitKind + + + + + +Enum + + +Enum + + + + + +Enum->Flag + + + + + \ No newline at end of file diff --git a/_images/inheritance-e359c1b278bf257e439118e8e47c15ba69924884.svg b/_images/inheritance-e359c1b278bf257e439118e8e47c15ba69924884.svg new file mode 100644 index 000000000..937728ed9 --- /dev/null +++ b/_images/inheritance-e359c1b278bf257e439118e8e47c15ba69924884.svg @@ -0,0 +1,44 @@ + + +inheritance08a5c6a270 + + +AssociationItem + + +AssociationItem + + + + + +PortAssociationItem + + +PortAssociationItem + + + + + +AssociationItem->PortAssociationItem + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->AssociationItem + + + + + \ No newline at end of file diff --git a/_images/inheritance-e451416983bd770311cd571a27911c91f424226e.svg b/_images/inheritance-e451416983bd770311cd571a27911c91f424226e.svg new file mode 100644 index 000000000..099a6a872 --- /dev/null +++ b/_images/inheritance-e451416983bd770311cd571a27911c91f424226e.svg @@ -0,0 +1,59 @@ + + +inheritancec955d426d4 + + +BaseExpression + + +BaseExpression + + + + + +UnaryExpression + + +UnaryExpression + + + + + +BaseExpression->UnaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +UnaryXorExpression + + +UnaryXorExpression + + + + + +UnaryExpression->UnaryXorExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-e4ad9f6e1a0419558402f058a2196fbdfdc1ccae.svg b/_images/inheritance-e4ad9f6e1a0419558402f058a2196fbdfdc1ccae.svg new file mode 100644 index 000000000..f3ed596a7 --- /dev/null +++ b/_images/inheritance-e4ad9f6e1a0419558402f058a2196fbdfdc1ccae.svg @@ -0,0 +1,29 @@ + + +inheritance043e87d024 + + +GenericInstantiationMixin + + +GenericInstantiationMixin + + + + + +SubprogramInstantiationMixin + + +SubprogramInstantiationMixin + + + + + +GenericInstantiationMixin->SubprogramInstantiationMixin + + + + + \ No newline at end of file diff --git a/_images/inheritance-e9654bd474ea488c52928a7d5a072e02e9b0041b.svg b/_images/inheritance-e9654bd474ea488c52928a7d5a072e02e9b0041b.svg new file mode 100644 index 000000000..3e21514ba --- /dev/null +++ b/_images/inheritance-e9654bd474ea488c52928a7d5a072e02e9b0041b.svg @@ -0,0 +1,14 @@ + + +inheritance0e69332a06 + + +AssignmentMixin + + +AssignmentMixin + + + + + \ No newline at end of file diff --git a/_images/inheritance-ea5f5f801fa42e1fa5cccf1d57a740e7c87d9f42.svg b/_images/inheritance-ea5f5f801fa42e1fa5cccf1d57a740e7c87d9f42.svg new file mode 100644 index 000000000..16cd118ff --- /dev/null +++ b/_images/inheritance-ea5f5f801fa42e1fa5cccf1d57a740e7c87d9f42.svg @@ -0,0 +1,14 @@ + + +inheritance74fa809836 + + +MultipleNamedEntityMixin + + +MultipleNamedEntityMixin + + + + + \ No newline at end of file diff --git a/_images/inheritance-eb87df1984f3ff98cead0dd72789006e6bcc00d0.svg b/_images/inheritance-eb87df1984f3ff98cead0dd72789006e6bcc00d0.svg new file mode 100644 index 000000000..0488a056e --- /dev/null +++ b/_images/inheritance-eb87df1984f3ff98cead0dd72789006e6bcc00d0.svg @@ -0,0 +1,14 @@ + + +inheritanced4122256d9 + + +ConcurrentDeclarationRegionMixin + + +ConcurrentDeclarationRegionMixin + + + + + \ No newline at end of file diff --git a/_images/inheritance-ed3040f6b7d4ba15a6d5b3c95889a7c46806b7c0.svg b/_images/inheritance-ed3040f6b7d4ba15a6d5b3c95889a7c46806b7c0.svg new file mode 100644 index 000000000..edd947cb2 --- /dev/null +++ b/_images/inheritance-ed3040f6b7d4ba15a6d5b3c95889a7c46806b7c0.svg @@ -0,0 +1,74 @@ + + +inheritance28708a8651 + + +AscendingRangeExpression + + +AscendingRangeExpression + + + + + +RangeExpression + + +RangeExpression + + + + + +RangeExpression->AscendingRangeExpression + + + + + +BaseExpression + + +BaseExpression + + + + + +BinaryExpression + + +BinaryExpression + + + + + +BaseExpression->BinaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +BinaryExpression->RangeExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-ef4138a9ef72da499c9afea9df1f21d83a04718b.svg b/_images/inheritance-ef4138a9ef72da499c9afea9df1f21d83a04718b.svg new file mode 100644 index 000000000..08ea04070 --- /dev/null +++ b/_images/inheritance-ef4138a9ef72da499c9afea9df1f21d83a04718b.svg @@ -0,0 +1,119 @@ + + +inheritance39d81afff0 + + +AssignmentMixin + + +AssignmentMixin + + + + + +SignalAssignmentMixin + + +SignalAssignmentMixin + + + + + +AssignmentMixin->SignalAssignmentMixin + + + + + +ConcurrentSignalAssignment + + +ConcurrentSignalAssignment + + + + + +ConcurrentSimpleSignalAssignment + + +ConcurrentSimpleSignalAssignment + + + + + +ConcurrentSignalAssignment->ConcurrentSimpleSignalAssignment + + + + + +ConcurrentStatement + + +ConcurrentStatement + + + + + +ConcurrentStatement->ConcurrentSignalAssignment + + + + + +SignalAssignmentMixin->ConcurrentSignalAssignment + + + + + +Statement + + +Statement + + + + + +Statement->ConcurrentStatement + + + + + +LabeledEntityMixin + + +LabeledEntityMixin + + + + + +LabeledEntityMixin->Statement + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Statement + + + + + \ No newline at end of file diff --git a/_images/inheritance-ef6bf8b9d5a8c09f6af9714549a4462c452a23f1.svg b/_images/inheritance-ef6bf8b9d5a8c09f6af9714549a4462c452a23f1.svg new file mode 100644 index 000000000..a5100bc56 --- /dev/null +++ b/_images/inheritance-ef6bf8b9d5a8c09f6af9714549a4462c452a23f1.svg @@ -0,0 +1,59 @@ + + +inheritanced5e64a8b4e + + +BaseExpression + + +BaseExpression + + + + + +BinaryExpression + + +BinaryExpression + + + + + +BaseExpression->BinaryExpression + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +MultiplyingExpression + + +MultiplyingExpression + + + + + +BinaryExpression->MultiplyingExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-ef881bab0f95ca285bcb37fcb15773d81683e269.svg b/_images/inheritance-ef881bab0f95ca285bcb37fcb15773d81683e269.svg new file mode 100644 index 000000000..3d9957917 --- /dev/null +++ b/_images/inheritance-ef881bab0f95ca285bcb37fcb15773d81683e269.svg @@ -0,0 +1,44 @@ + + +inheritance8fa8460949 + + +ModelEntity + + +ModelEntity + + + + + +Name + + +Name + + + + + +ModelEntity->Name + + + + + +SlicedName + + +SlicedName + + + + + +Name->SlicedName + + + + + \ No newline at end of file diff --git a/_images/inheritance-f2b3e948d705393e7568d6c424b2dbc26569b164.svg b/_images/inheritance-f2b3e948d705393e7568d6c424b2dbc26569b164.svg new file mode 100644 index 000000000..7cdaa2f0b --- /dev/null +++ b/_images/inheritance-f2b3e948d705393e7568d6c424b2dbc26569b164.svg @@ -0,0 +1,59 @@ + + +inheritancee06be56031 + + +BaseExpression + + +BaseExpression + + + + + +Literal + + +Literal + + + + + +BaseExpression->Literal + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +EnumerationLiteral + + +EnumerationLiteral + + + + + +Literal->EnumerationLiteral + + + + + \ No newline at end of file diff --git a/_images/inheritance-f349ed7a737975f9f1605e8589a23dc62e790904.svg b/_images/inheritance-f349ed7a737975f9f1605e8589a23dc62e790904.svg new file mode 100644 index 000000000..0085891a0 --- /dev/null +++ b/_images/inheritance-f349ed7a737975f9f1605e8589a23dc62e790904.svg @@ -0,0 +1,29 @@ + + +inheritancefea031ab51 + + +LibraryRegisteredToForeignDesignError + + +LibraryRegisteredToForeignDesignError + + + + + +VHDLModelException + + +VHDLModelException + + + + + +VHDLModelException->LibraryRegisteredToForeignDesignError + + + + + \ No newline at end of file diff --git a/_images/inheritance-f36c1766a637f434ca8db1d4ad360579fab844cb.svg b/_images/inheritance-f36c1766a637f434ca8db1d4ad360579fab844cb.svg new file mode 100644 index 000000000..1ae895ea8 --- /dev/null +++ b/_images/inheritance-f36c1766a637f434ca8db1d4ad360579fab844cb.svg @@ -0,0 +1,44 @@ + + +inheritance31a1eff5d7 + + +ContextReference + + +ContextReference + + + + + +Reference + + +Reference + + + + + +Reference->ContextReference + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Reference + + + + + \ No newline at end of file diff --git a/_images/inheritance-f42acc26ac84a8f75d324d5a3f64960e8ddf12b8.svg b/_images/inheritance-f42acc26ac84a8f75d324d5a3f64960e8ddf12b8.svg new file mode 100644 index 000000000..a7fca8272 --- /dev/null +++ b/_images/inheritance-f42acc26ac84a8f75d324d5a3f64960e8ddf12b8.svg @@ -0,0 +1,59 @@ + + +inheritance70e456f3aa + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +Subprogram + + +Subprogram + + + + + +DocumentedEntityMixin->Subprogram + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Subprogram + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->Subprogram + + + + + \ No newline at end of file diff --git a/_images/inheritance-f5b99d6c600ef8b83762b1674ad8d60973c02a29.svg b/_images/inheritance-f5b99d6c600ef8b83762b1674ad8d60973c02a29.svg new file mode 100644 index 000000000..47ef0bf1f --- /dev/null +++ b/_images/inheritance-f5b99d6c600ef8b83762b1674ad8d60973c02a29.svg @@ -0,0 +1,104 @@ + + +inheritancef26d073291 + + +BaseCase + + +BaseCase + + + + + +ConcurrentCase + + +ConcurrentCase + + + + + +BaseCase->ConcurrentCase + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseCase + + + + + +OthersGenerateCase + + +OthersGenerateCase + + + + + +ConcurrentCase->OthersGenerateCase + + + + + +LabeledEntityMixin + + +LabeledEntityMixin + + + + + +LabeledEntityMixin->ConcurrentCase + + + + + +ConcurrentDeclarationRegionMixin + + +ConcurrentDeclarationRegionMixin + + + + + +ConcurrentDeclarationRegionMixin->ConcurrentCase + + + + + +ConcurrentStatementsMixin + + +ConcurrentStatementsMixin + + + + + +ConcurrentStatementsMixin->ConcurrentCase + + + + + \ No newline at end of file diff --git a/_images/inheritance-f7bbd53076411a8222f91cadac00fba13590da28.svg b/_images/inheritance-f7bbd53076411a8222f91cadac00fba13590da28.svg new file mode 100644 index 000000000..8c0451632 --- /dev/null +++ b/_images/inheritance-f7bbd53076411a8222f91cadac00fba13590da28.svg @@ -0,0 +1,74 @@ + + +inheritance1891a7dbc5 + + +BaseExpression + + +BaseExpression + + + + + +Literal + + +Literal + + + + + +BaseExpression->Literal + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +IntegerLiteral + + +IntegerLiteral + + + + + +NumericLiteral + + +NumericLiteral + + + + + +NumericLiteral->IntegerLiteral + + + + + +Literal->NumericLiteral + + + + + \ No newline at end of file diff --git a/_images/inheritance-f82f736199f217de049dc6c6e3f27d27fc2824d5.svg b/_images/inheritance-f82f736199f217de049dc6c6e3f27d27fc2824d5.svg new file mode 100644 index 000000000..76c778099 --- /dev/null +++ b/_images/inheritance-f82f736199f217de049dc6c6e3f27d27fc2824d5.svg @@ -0,0 +1,14 @@ + + +inheritance13022e8f35 + + +VHDLModelException + + +VHDLModelException + + + + + \ No newline at end of file diff --git a/_images/inheritance-f904cc25473db95bbc1b419139713bfa7acdaf00.svg b/_images/inheritance-f904cc25473db95bbc1b419139713bfa7acdaf00.svg new file mode 100644 index 000000000..37883d68c --- /dev/null +++ b/_images/inheritance-f904cc25473db95bbc1b419139713bfa7acdaf00.svg @@ -0,0 +1,59 @@ + + +inheritance04e4261ed7 + + +BaseExpression + + +BaseExpression + + + + + +Literal + + +Literal + + + + + +BaseExpression->Literal + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + +NumericLiteral + + +NumericLiteral + + + + + +Literal->NumericLiteral + + + + + \ No newline at end of file diff --git a/_images/inheritance-f918e6e7d604b9b9bc95e77de55bb495c279dd84.svg b/_images/inheritance-f918e6e7d604b9b9bc95e77de55bb495c279dd84.svg new file mode 100644 index 000000000..129e24b9d --- /dev/null +++ b/_images/inheritance-f918e6e7d604b9b9bc95e77de55bb495c279dd84.svg @@ -0,0 +1,29 @@ + + +inheritance3952958544 + + +Design + + +Design + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Design + + + + + \ No newline at end of file diff --git a/_images/inheritance-f9a5fb45ca313c2b903f906af8fe17d5575e31d7.svg b/_images/inheritance-f9a5fb45ca313c2b903f906af8fe17d5575e31d7.svg new file mode 100644 index 000000000..718aaa660 --- /dev/null +++ b/_images/inheritance-f9a5fb45ca313c2b903f906af8fe17d5575e31d7.svg @@ -0,0 +1,104 @@ + + +inheritance04dca26561 + + +ArrayType + + +ArrayType + + + + + +CompositeType + + +CompositeType + + + + + +CompositeType->ArrayType + + + + + +BaseType + + +BaseType + + + + + +FullType + + +FullType + + + + + +BaseType->FullType + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseType + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->BaseType + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->BaseType + + + + + +FullType->CompositeType + + + + + \ No newline at end of file diff --git a/_images/inheritance-fb173f59138b25f682a577b8b3d9bfc17dd3e1e4.svg b/_images/inheritance-fb173f59138b25f682a577b8b3d9bfc17dd3e1e4.svg new file mode 100644 index 000000000..cb0078a74 --- /dev/null +++ b/_images/inheritance-fb173f59138b25f682a577b8b3d9bfc17dd3e1e4.svg @@ -0,0 +1,104 @@ + + +inheritance07c122af6a + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +Subprogram + + +Subprogram + + + + + +DocumentedEntityMixin->Subprogram + + + + + +Function + + +Function + + + + + +FunctionMethod + + +FunctionMethod + + + + + +Function->FunctionMethod + + + + + +Subprogram->Function + + + + + +MethodMixin + + +MethodMixin + + + + + +MethodMixin->FunctionMethod + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->Subprogram + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->Subprogram + + + + + \ No newline at end of file diff --git a/_images/inheritance-fc603eaa2760afc5edc73af6b45b39a8ba35f77b.svg b/_images/inheritance-fc603eaa2760afc5edc73af6b45b39a8ba35f77b.svg new file mode 100644 index 000000000..b380f9793 --- /dev/null +++ b/_images/inheritance-fc603eaa2760afc5edc73af6b45b39a8ba35f77b.svg @@ -0,0 +1,74 @@ + + +inheritancef87cbe8893 + + +BaseType + + +BaseType + + + + + +FullType + + +FullType + + + + + +BaseType->FullType + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseType + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->BaseType + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->BaseType + + + + + \ No newline at end of file diff --git a/_images/inheritance-fca4a8d922a41c95123aa723cb052a391548e9db.svg b/_images/inheritance-fca4a8d922a41c95123aa723cb052a391548e9db.svg new file mode 100644 index 000000000..c213bf139 --- /dev/null +++ b/_images/inheritance-fca4a8d922a41c95123aa723cb052a391548e9db.svg @@ -0,0 +1,134 @@ + + +inheritance60a498c76a + + +Architecture + + +Architecture + + + + + +SecondaryUnit + + +SecondaryUnit + + + + + +SecondaryUnit->Architecture + + + + + +DesignUnitWithContextMixin + + +DesignUnitWithContextMixin + + + + + +DesignUnitWithContextMixin->Architecture + + + + + +ConcurrentDeclarationRegionMixin + + +ConcurrentDeclarationRegionMixin + + + + + +ConcurrentDeclarationRegionMixin->Architecture + + + + + +ConcurrentStatementsMixin + + +ConcurrentStatementsMixin + + + + + +ConcurrentStatementsMixin->Architecture + + + + + +DesignUnit + + +DesignUnit + + + + + +DesignUnit->SecondaryUnit + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->DesignUnit + + + + + +NamedEntityMixin + + +NamedEntityMixin + + + + + +NamedEntityMixin->DesignUnit + + + + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +DocumentedEntityMixin->DesignUnit + + + + + \ No newline at end of file diff --git a/_images/inheritance-fd9bbd49f9a291625ad0d0ee07a9d76f866aa014.svg b/_images/inheritance-fd9bbd49f9a291625ad0d0ee07a9d76f866aa014.svg new file mode 100644 index 000000000..9fc2bef47 --- /dev/null +++ b/_images/inheritance-fd9bbd49f9a291625ad0d0ee07a9d76f866aa014.svg @@ -0,0 +1,29 @@ + + +inheritance7732f6cfa7 + + +EntityExistsInLibraryError + + +EntityExistsInLibraryError + + + + + +VHDLModelException + + +VHDLModelException + + + + + +VHDLModelException->EntityExistsInLibraryError + + + + + \ No newline at end of file diff --git a/_images/inheritance-fe288618b1a1b50f05040118c3c7acb9c32d52fe.svg b/_images/inheritance-fe288618b1a1b50f05040118c3c7acb9c32d52fe.svg new file mode 100644 index 000000000..9d3f15047 --- /dev/null +++ b/_images/inheritance-fe288618b1a1b50f05040118c3c7acb9c32d52fe.svg @@ -0,0 +1,44 @@ + + +inheritance173233d03b + + +BaseExpression + + +BaseExpression + + + + + +Literal + + +Literal + + + + + +BaseExpression->Literal + + + + + +ModelEntity + + +ModelEntity + + + + + +ModelEntity->BaseExpression + + + + + \ No newline at end of file diff --git a/_images/inheritance-ff58ac86cffc5ffea8d0648417f945c887d0ee2c.svg b/_images/inheritance-ff58ac86cffc5ffea8d0648417f945c887d0ee2c.svg new file mode 100644 index 000000000..b134e0240 --- /dev/null +++ b/_images/inheritance-ff58ac86cffc5ffea8d0648417f945c887d0ee2c.svg @@ -0,0 +1,29 @@ + + +inheritance681660cbd4 + + +ConfigurationInstantiationSymbol + + +ConfigurationInstantiationSymbol + + + + + +Symbol + + +Symbol + + + + + +Symbol->ConfigurationInstantiationSymbol + + + + + \ No newline at end of file diff --git a/_images/inheritance-ff901af0f75bc136cc984f127d9ad99093a08b58.svg b/_images/inheritance-ff901af0f75bc136cc984f127d9ad99093a08b58.svg new file mode 100644 index 000000000..e2cc704b8 --- /dev/null +++ b/_images/inheritance-ff901af0f75bc136cc984f127d9ad99093a08b58.svg @@ -0,0 +1,59 @@ + + +inheritance85c96b3ccc + + +DocumentedEntityMixin + + +DocumentedEntityMixin + + + + + +InterfaceItemMixin + + +InterfaceItemMixin + + + + + +DocumentedEntityMixin->InterfaceItemMixin + + + + + +PortInterfaceItemMixin + + +PortInterfaceItemMixin + + + + + +InterfaceItemMixin->PortInterfaceItemMixin + + + + + +InterfaceItemWithModeMixin + + +InterfaceItemWithModeMixin + + + + + +InterfaceItemWithModeMixin->PortInterfaceItemMixin + + + + + \ No newline at end of file diff --git a/_images/logo.svg b/_images/logo.svg new file mode 100644 index 000000000..62d264f79 --- /dev/null +++ b/_images/logo.svg @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/_modules/index.html b/_modules/index.html new file mode 100644 index 000000000..d22de4d96 --- /dev/null +++ b/_modules/index.html @@ -0,0 +1,171 @@ + + + + + + Overview: module code — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
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  • Overview: module code
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+ + + + \ No newline at end of file diff --git a/_modules/pyVHDLModel.html b/_modules/pyVHDLModel.html new file mode 100644 index 000000000..9f92931a3 --- /dev/null +++ b/_modules/pyVHDLModel.html @@ -0,0 +1,2910 @@ + + + + + + pyVHDLModel — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
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+ +

Source code for pyVHDLModel

+# ==================================================================================================================== #
+#             __     ___   _ ____  _     __  __           _      _                                                     #
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |                                                    #
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |                                                    #
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |                                                    #
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|                                                    #
+#  |_|    |___/                                                                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""
+**An abstract VHDL language model.**
+
+This package provides a unified abstract language model for VHDL. Projects reading from source files can derive own
+classes and implement additional logic to create a concrete language model for their tools.
+
+Projects consuming pre-processed VHDL data (parsed, analyzed or elaborated) can build higher level features and services
+on such a model, while supporting multiple frontends.
+
+.. admonition:: Copyright Information
+
+   :copyright: Copyright 2017-2024 Patrick Lehmann - Bötzingen, Germany
+   :copyright: Copyright 2016-2017 Patrick Lehmann - Dresden, Germany
+   :license: Apache License, Version 2.0
+"""
+__author__ =    "Patrick Lehmann"
+__email__ =     "Paebbels@gmail.com"
+__copyright__ = "2016-2024, Patrick Lehmann"
+__license__ =   "Apache License, Version 2.0"
+__version__ =   "0.29.0"
+
+
+from enum                      import unique, Enum, Flag, auto
+from pathlib                   import Path
+from sys                       import version_info
+
+from typing                    import Union, Dict, cast, List, Generator, Optional as Nullable
+
+from pyTooling.Common          import getFullyQualifiedName
+from pyTooling.Decorators      import export, readonly
+from pyTooling.Graph           import Graph, Vertex, Edge
+
+from pyVHDLModel.Exception     import VHDLModelException
+from pyVHDLModel.Exception     import LibraryExistsInDesignError, LibraryRegisteredToForeignDesignError, LibraryNotRegisteredError, EntityExistsInLibraryError
+from pyVHDLModel.Exception     import ArchitectureExistsInLibraryError, PackageExistsInLibraryError, PackageBodyExistsError, ConfigurationExistsInLibraryError
+from pyVHDLModel.Exception     import ContextExistsInLibraryError, ReferencedLibraryNotExistingError
+from pyVHDLModel.Base          import ModelEntity, NamedEntityMixin, MultipleNamedEntityMixin, DocumentedEntityMixin
+from pyVHDLModel.Expression    import UnaryExpression, BinaryExpression, TernaryExpression
+from pyVHDLModel.Namespace     import Namespace
+from pyVHDLModel.Object        import Obj, Signal, Constant, DeferredConstant
+from pyVHDLModel.Symbol        import PackageReferenceSymbol, AllPackageMembersReferenceSymbol, PackageMemberReferenceSymbol, SimpleObjectOrFunctionCallSymbol
+from pyVHDLModel.Concurrent    import EntityInstantiation, ComponentInstantiation, ConfigurationInstantiation
+from pyVHDLModel.DesignUnit    import DesignUnit, PrimaryUnit, Architecture, PackageBody, Context, Entity, Configuration, Package
+from pyVHDLModel.PSLModel      import VerificationUnit, VerificationProperty, VerificationMode
+from pyVHDLModel.Instantiation import PackageInstantiation
+from pyVHDLModel.Type          import IntegerType, PhysicalType, ArrayType, RecordType
+
+
+

+[docs]
+@export
+@unique
+class VHDLVersion(Enum):
+	"""
+	An enumeration for all possible version numbers for VHDL and VHDL-AMS.
+
+	A version can be given as integer or string and is represented as a unified
+	enumeration value.
+
+	This enumeration supports compare operators.
+	"""
+
+	Any =                -1  #: Any
+	VHDL87 =             87  #: VHDL-1987
+	VHDL93 =             93  #: VHDL-1993
+	AMS93 =            1993  #: VHDL-AMS-1993
+	AMS99 =            1999  #: VHDL-AMS-1999
+	VHDL2000 =         2000  #: VHDL-2000
+	VHDL2002 =         2002  #: VHDL-2002
+	VHDL2008 =         2008  #: VHDL-2008
+	AMS2017 =          2017  #: VHDL-AMS-2017
+	VHDL2019 =         2019  #: VHDL-2019
+	Latest =          10000  #: Latest VHDL (2019)
+
+	__VERSION_MAPPINGS__: Dict[Union[int, str], Enum] = {
+		-1:       Any,
+		87:       VHDL87,
+		93:       VHDL93,
+		# 93:       AMS93,
+		99:       AMS99,
+		0:        VHDL2000,
+		2:        VHDL2002,
+		8:        VHDL2008,
+		17:       AMS2017,
+		19:       VHDL2019,
+		1987:     VHDL87,
+		# 1993:     VHDL93,
+		1993:     AMS93,
+		1999:     AMS99,
+		2000:     VHDL2000,
+		2002:     VHDL2002,
+		2008:     VHDL2008,
+		2017:     AMS2017,
+		2019:     VHDL2019,
+		10000:    Latest,
+		"Any":    Any,
+		"87":     VHDL87,
+		"93":     VHDL93,
+		# "93":     AMS93,
+		"99":     AMS99,
+		"00":     VHDL2000,
+		"02":     VHDL2002,
+		"08":     VHDL2008,
+		"17":     AMS2017,
+		"19":     VHDL2019,
+		"1987":   VHDL87,
+		# "1993":   VHDL93,
+		"1993":   AMS93,
+		"1999":   AMS99,
+		"2000":   VHDL2000,
+		"2002":   VHDL2002,
+		"2008":   VHDL2008,
+		"2017":   AMS2017,
+		"2019":   VHDL2019,
+		"Latest": Latest,
+	}  #: Dictionary of VHDL and VHDL-AMS year codes variants as integer and strings for mapping to unique enum values.
+
+

+[docs]
+	def __init__(self, *_) -> None:
+		"""Patch the embedded MAP dictionary"""
+		for k, v in self.__class__.__VERSION_MAPPINGS__.items():
+			if (not isinstance(v, self.__class__)) and (v == self.value):
+				self.__class__.__VERSION_MAPPINGS__[k] = self

+
+
+

+[docs]
+	@classmethod
+	def Parse(cls, value: Union[int, str]) -> "VHDLVersion":
+		"""
+		Parses a VHDL or VHDL-AMS year code as integer or string to an enum value.
+
+		:param value:       VHDL/VHDL-AMS year code.
+		:returns:           Enumeration value.
+		:raises ValueError: If the year code is not recognized.
+		"""
+		try:
+			return cls.__VERSION_MAPPINGS__[value]
+		except KeyError:
+			raise ValueError(f"Value '{value!s}' cannot be parsed to member of {cls.__name__}.")

+
+
+

+[docs]
+	def __lt__(self, other: Any) -> bool:
+		"""
+		Compare two VHDL/VHDL-AMS versions if the version is less than the second operand.
+
+		:param other:      Parameter to compare against.
+		:returns:          True if version is less than the second operand.
+		:raises TypeError: If parameter ``other`` is not of type :class:`VHDLVersion`.
+		"""
+		if isinstance(other, VHDLVersion):
+			return self.value < other.value
+		else:
+			raise TypeError("Second operand is not of type 'VHDLVersion'.")

+
+
+

+[docs]
+	def __le__(self, other: Any) -> bool:
+		"""
+		Compare two VHDL/VHDL-AMS versions if the version is less or equal than the second operand.
+
+		:param other:      Parameter to compare against.
+		:returns:          True if version is less or equal than the second operand.
+		:raises TypeError: If parameter ``other`` is not of type :class:`VHDLVersion`.
+		"""
+		if isinstance(other, VHDLVersion):
+			return self.value <= other.value
+		else:
+			raise TypeError("Second operand is not of type 'VHDLVersion'.")

+
+
+

+[docs]
+	def __gt__(self, other: Any) -> bool:
+		"""
+		Compare two VHDL/VHDL-AMS versions if the version is greater than the second operand.
+
+		:param other:      Parameter to compare against.
+		:returns:          True if version is greater than the second operand.
+		:raises TypeError: If parameter ``other`` is not of type :class:`VHDLVersion`.
+		"""
+		if isinstance(other, VHDLVersion):
+			return self.value > other.value
+		else:
+			raise TypeError("Second operand is not of type 'VHDLVersion'.")

+
+
+

+[docs]
+	def __ge__(self, other: Any) -> bool:
+		"""
+		Compare two VHDL/VHDL-AMS versions if the version is greater or equal than the second operand.
+
+		:param other:      Parameter to compare against.
+		:returns:          True if version is greater or equal than the second operand.
+		:raises TypeError: If parameter ``other`` is not of type :class:`VHDLVersion`.
+		"""
+		if isinstance(other, VHDLVersion):
+			return self.value >= other.value
+		else:
+			raise TypeError("Second operand is not of type 'VHDLVersion'.")

+
+
+

+[docs]
+	def __ne__(self, other: Any) -> bool:
+		"""
+		Compare two VHDL/VHDL-AMS versions if the version is unequal to the second operand.
+
+		:param other:      Parameter to compare against.
+		:returns:          True if version is unequal to the second operand.
+		:raises TypeError: If parameter ``other`` is not of type :class:`VHDLVersion`.
+		"""
+		if isinstance(other, VHDLVersion):
+			return self.value != other.value
+		else:
+			raise TypeError("Second operand is not of type 'VHDLVersion'.")

+
+
+

+[docs]
+	def __eq__(self, other: Any) -> bool:
+		"""
+		Compare two VHDL/VHDL-AMS versions if the version is equal to the second operand.
+
+		:param other:      Parameter to compare against.
+		:returns:          True if version is equal to the second operand.
+		:raises TypeError: If parameter ``other`` is not of type :class:`VHDLVersion`.
+		"""
+		if isinstance(other, VHDLVersion):
+			if (self is self.__class__.Any) or (other is self.__class__.Any):
+				return True
+			else:
+				return self.value == other.value
+		else:
+			raise TypeError("Second operand is not of type 'VHDLVersion'.")

+
+
+	@readonly
+	def IsVHDL(self) -> bool:
+		"""
+		Checks if the version is a VHDL (not VHDL-AMS) version.
+
+		:returns:          True if version is a VHDL version.
+		"""
+		return self in (self.VHDL87, self.VHDL93, self.VHDL2002, self.VHDL2008, self.VHDL2019)
+
+	@readonly
+	def IsAMS(self) -> bool:
+		"""
+		Checks if the version is a VHDL-AMS (not VHDL) version.
+
+		:returns:          True if version is a VHDL-AMS version.
+		"""
+		return self in (self.AMS93, self.AMS99, self.AMS2017)
+
+

+[docs]
+	def __str__(self) -> str:
+		"""
+		Formats the VHDL version to pattern ``VHDL'xx`` or in case of VHDL-AMS to ``VHDL-AMS'xx``.
+
+		:return: Formatted VHDL/VHDL-AMS version.
+		"""
+		if self.value == self.Any.value:
+			return "VHDL'Any"
+		elif self.value == self.Latest.value:
+			return "VHDL'Latest"
+
+		year = str(self.value)[-2:]
+		if self.IsVHDL:
+			return f"VHDL'{year}"
+		else:
+			return f"VHDL-AMS'{year}"

+
+
+

+[docs]
+	def __repr__(self) -> str:
+		"""
+		Formats the VHDL/VHDL-AMS version to pattern ``xxxx``.
+
+		:return: Formatted VHDL/VHDL-AMS version.
+		"""
+		if self.value == self.Any.value:
+			return "Any"
+		elif self.value == self.Latest.value:
+			return "Latest"
+		else:
+			return str(self.value)

+

+
+
+
+

+[docs]
+@export
+@unique
+class ObjectClass(Enum):
+	"""
+	An ``ObjectClass`` is an enumeration and represents an object's class (``constant``, ``signal``, ...).
+
+	In case no *object class* is defined, ``Default`` is used, so the *object class* is inferred from context.
+	"""
+
+	Default =    0  #: Object class not defined, thus it's context dependent.
+	Constant =   1  #: Constant
+	Variable =   2  #: Variable
+	Signal =     3  #: Signal
+	File =       4  #: File
+	Type =       5  #: Type
+	# FIXME: Package?
+	Procedure =  6  #: Procedure
+	Function =   7  #: Function
+
+

+[docs]
+	def __str__(self) -> str:
+		"""
+		Formats the object class.
+
+		:return: Formatted object class.
+		"""
+		return ("", "constant", "variable", "signal", "file", "type", "procedure", "function")[cast(int, self.value)]       # TODO: check performance

+

+
+
+
+

+[docs]
+@export
+@unique
+class DesignUnitKind(Flag):
+	"""
+	A ``DesignUnitKind`` is an enumeration and represents the kind of design unit (``Entity``, ``Architecture``, ...).
+
+	"""
+	Context = auto()                                                             #: Context
+	Package = auto()                                                             #: Package
+	PackageBody = auto()                                                         #: Package Body
+	Entity = auto()                                                              #: Entity
+	Architecture = auto()                                                        #: Architecture
+	Configuration = auto()                                                       #: Configuration
+
+	Primary = Context | Configuration | Entity | Package                         #: List of primary design units.
+	Secondary = PackageBody | Architecture                                       #: List of secondary design units.
+	WithContext = Configuration | Package | Entity | PackageBody | Architecture  #: List of design units with a context.
+	WithDeclaredItems = Package | Entity | PackageBody | Architecture            #: List of design units having a declaration region.
+
+	All = Primary | Secondary                                                    #: List of all design units.

+
+
+
+

+[docs]
+@export
+@unique
+class DependencyGraphVertexKind(Flag):
+	"""
+	A ``DependencyGraphVertexKind`` is an enumeration and represents the kind of vertex in the dependency graph.
+	"""
+	Document = auto()       #: A document (VHDL source file).
+	Library = auto()        #: A VHDL library.
+
+	Context = auto()        #: A context design unit.
+	Package = auto()        #: A package design unit.
+	PackageBody = auto()    #: A package body design unit.
+	Entity = auto()         #: A entity design unit.
+	Architecture = auto()   #: A architecture design unit.
+	Component = auto()      #: A VHDL component.
+	Configuration = auto()  #: A configuration design unit.

+
+
+
+

+[docs]
+@export
+@unique
+class DependencyGraphEdgeKind(Flag):
+	"""
+	A ``DependencyGraphEdgeKind`` is an enumeration and represents the kind of edge in the dependency graph.
+	"""
+	Document =       auto()
+	Library =        auto()
+	Context =        auto()
+	Package =        auto()
+	Entity =         auto()
+	# Architecture = auto()
+	Configuration =  auto()
+	Component =      auto()
+
+	DeclaredIn =     auto()
+	Order =          auto()
+	Reference =      auto()
+	Implementation = auto()
+	Instantiation =  auto()
+
+	SourceFile =                 Document | DeclaredIn
+	CompileOrder =               Document | Order
+
+	LibraryClause =              Library | Reference
+	UseClause =                  Package | Reference
+	ContextReference =           Context | Reference
+
+	EntityImplementation =       Entity | Implementation
+	PackageImplementation =      Package | Implementation
+
+	EntityInstantiation =        Entity | Instantiation
+	ComponentInstantiation =     Component | Instantiation
+	ConfigurationInstantiation = Configuration | Instantiation

+
+
+
+

+[docs]
+@export
+@unique
+class ObjectGraphVertexKind(Flag):
+	"""
+	A ``ObjectGraphVertexKind`` is an enumeration and represents the kind of vertex in the object graph.
+	"""
+	Type = auto()
+	Subtype = auto()
+
+	Constant = auto()
+	DeferredConstant = auto()
+	Variable = auto()
+	Signal = auto()
+	File = auto()
+
+	Alias = auto()

+
+
+
+

+[docs]
+@export
+@unique
+class ObjectGraphEdgeKind(Flag):
+	"""
+	A ``ObjectGraphEdgeKind`` is an enumeration and represents the kind of edge in the object graph.
+	"""
+	BaseType = auto()
+	Subtype = auto()
+
+	ReferenceInExpression = auto()

+
+
+
+

+[docs]
+@export
+class Design(ModelEntity):
+	"""
+	A ``Design`` represents set of VHDL libraries as well as all loaded and analysed source files (see :class:`~pyVHDLModel.Document`).
+
+	It's the root of this code document-object-model (CodeDOM). It contains at least one VHDL library (see :class:`~pyVHDLModel.Library`). When the design is
+	analysed (see :meth:`Analyze`), multiple graph data structures will be created and populated with vertices and edges. As a first result, the design's compile
+	order and hierarchy can be iterated. As a second result, the design's *top-level* is identified and referenced from the design (see :attr:`TopLevel`).
+
+	The *design* contains references to the following graphs:
+
+	* :attr:`DependencyGraph`
+	* :attr:`CompileOrderGraph`
+	* :attr:`HierarchyGraph`
+	* :attr:`ObjectGraph`
+	"""
+	_name:              Nullable[str]         #: Name of the design
+	_libraries:         Dict[str, 'Library']  #: List of all libraries defined for a design.
+	_documents:         List['Document']      #: List of all documents loaded for a design.
+	_dependencyGraph:   Graph[None, None, None, None, None, None, None, None, str, DesignUnit, None, None, None, None, None, None, None, None, None, None, None, None, None]   #: The graph of all dependencies in the designs.
+	_compileOrderGraph: Graph[None, None, None, None, None, None, None, None, None, 'Document', None, None, None, None, None, None, None, None, None, None, None, None, None]  #: A graph derived from dependency graph containing the order of documents for compilation.
+	_hierarchyGraph:    Graph[None, None, None, None, None, None, None, None, str, DesignUnit, None, None, None, None, None, None, None, None, None, None, None, None, None]   #: A graph derived from dependency graph containing the design hierarchy.
+	_objectGraph:       Graph[None, None, None, None, None, None, None, None, str, Obj, None, None, None, None, None, None, None, None, None, None, None, None, None]          #: The graph of all types and objects in the design.
+	_toplevel:          Union[Entity, Configuration]  #: When computed, the toplevel design unit is cached in this field.
+
+

+[docs]
+	def __init__(self, name: Nullable[str] = None) -> None:
+		"""
+		Initializes a VHDL design.
+
+		:param name: Name of the design.
+		"""
+		super().__init__()
+
+		self._name =      name
+		self._libraries = {}
+		self._documents = []
+
+		self._compileOrderGraph = Graph()
+		self._dependencyGraph = Graph()
+		self._hierarchyGraph = Graph()
+		self._objectGraph = Graph()
+		self._toplevel = None

+
+
+	@readonly
+	def Libraries(self) -> Dict[str, 'Library']:
+		"""
+		Read-only property to access the dictionary of library names and VHDL libraries (:attr:`_libraries`).
+
+		:returns: A dictionary of library names and VHDL libraries.
+		"""
+		return self._libraries
+
+	@readonly
+	def Documents(self) -> List['Document']:
+		"""
+		Read-only property to access the list of all documents (VHDL source files) loaded for this design (:attr:`_documents`).
+
+		:returns: A list of all documents.
+		"""
+		return self._documents
+
+	@readonly
+	def CompileOrderGraph(self) -> Graph:
+		"""
+		Read-only property to access the compile-order graph (:attr:`_compileOrderGraph`).
+
+		:returns: Reference to the compile-order graph.
+		"""
+		return self._compileOrderGraph
+
+	@readonly
+	def DependencyGraph(self) -> Graph:
+		"""
+		Read-only property to access the dependency graph (:attr:`_dependencyGraph`).
+
+		:returns: Reference to the dependency graph.
+		"""
+		return self._dependencyGraph
+
+	@readonly
+	def HierarchyGraph(self) -> Graph:
+		"""
+		Read-only property to access the hierarchy graph (:attr:`_hierarchyGraph`).
+
+		:returns: Reference to the hierarchy graph.
+		"""
+		return self._hierarchyGraph
+
+	@readonly
+	def ObjectGraph(self) -> Graph:
+		"""
+		Read-only property to access the object graph (:attr:`_objectGraph`).
+
+		:returns: Reference to the object graph.
+		"""
+		return self._objectGraph
+
+	@readonly
+	def TopLevel(self) -> Union[Entity, Configuration]:
+		"""
+		Read-only property to access the design's *top-level* (:attr:`_toplevel`).
+
+		When called the first time, the hierarchy graph is checked for its root elements. When there is only one root element in the graph, a new field ``toplevel``
+		is added to :attr:`_hierarchyGraph` referencing that single element. In addition, the result is cached in :attr:`_toplevel`.
+
+		:returns:                   Reference to the design's *top-level*.
+		:raises VHDLModelException: If the hierarchy graph is not yet computed from dependency graph.
+		:raises VHDLModelException: If there is more than one *top-level*.
+		"""
+		# Check for cached result
+		if self._toplevel is not None:
+			return self._toplevel
+
+		if self._hierarchyGraph.EdgeCount == 0:
+			raise VHDLModelException(f"Hierarchy is not yet computed from dependency graph.")
+
+		roots = tuple(self._hierarchyGraph.IterateRoots())
+		if len(roots) == 1:
+			toplevel = roots[0]
+			self._hierarchyGraph["toplevel"] = toplevel
+			self._toplevel = toplevel.Value
+
+			return toplevel.Value
+		else:
+			raise VHDLModelException(f"Found more than one toplevel: {', '.join(roots)}")
+
+

+[docs]
+	def LoadStdLibrary(self) -> 'Library':
+		"""
+		Load the predefined VHDL library ``std`` into the design.
+
+		This will create a virtual source code file ``std.vhdl`` and register VHDL design units of library ``std`` to that file.
+
+		:returns: The library object of library ``std``.
+		"""
+		from pyVHDLModel.STD import Std
+
+		doc = Document(Path("std.vhdl"), parent=self)
+
+		library = Std()
+		for designUnit in library.IterateDesignUnits():
+			doc._AddDesignUnit(designUnit)
+
+		self.AddLibrary(library)
+
+		return library

+
+
+

+[docs]
+	def LoadIEEELibrary(self) -> 'Library':
+		"""
+		Load the predefined VHDL library ``ieee`` into the design.
+
+		This will create a virtual source code file ``ieee.vhdl`` and register VHDL design units of library ``ieee`` to that file.
+
+		:returns: The library object of library ``ieee``.
+		"""
+		from pyVHDLModel.IEEE import Ieee
+
+		doc = Document(Path("ieee.vhdl"), parent=self)
+
+		library = Ieee()
+		for designUnit in library.IterateDesignUnits():
+			doc._AddDesignUnit(designUnit)
+
+		self.AddLibrary(library)
+
+		return library

+
+
+

+[docs]
+	def AddLibrary(self, library: 'Library') -> None:
+		"""
+		Add a VHDL library to the design.
+
+		Ensure the libraries name doesn't collide with existing libraries in the design. |br|
+		If ok, set the libraries parent reference to the design.
+
+		:param library:                                Library object to loaded.
+		:raises LibraryExistsInDesignError:            If the library already exists in the design.
+		:raises LibraryRegisteredToForeignDesignError: If library is already used by a different design.
+		"""
+		libraryIdentifier = library.NormalizedIdentifier
+		if libraryIdentifier in self._libraries:
+			raise LibraryExistsInDesignError(library)
+
+		if library._parent is not None:
+			raise LibraryRegisteredToForeignDesignError(library)
+
+		self._libraries[libraryIdentifier] = library
+		library._parent = self

+
+
+

+[docs]
+	def GetLibrary(self, libraryName: str) -> 'Library':
+		"""
+		Return an (existing) VHDL library object of name ``libraryName``.
+
+		If the requested VHDL library doesn't exist, a new VHDL library with that name will be created.
+
+		:param libraryName: Name of the requested VHDL library.
+		:returns:           The VHDL library object.
+		"""
+		libraryIdentifier = libraryName.lower()
+		try:
+			return self._libraries[libraryIdentifier]
+		except KeyError:
+			lib = Library(libraryName, parent=self)
+			self._libraries[libraryIdentifier] = lib
+			lib._parent = self
+			return lib

+
+
+	# TODO: allow overloaded parameter library to be str?
+

+[docs]
+	def AddDocument(self, document: 'Document', library: 'Library') -> None:
+		"""
+		Add a document (VHDL source file) to the design and register all embedded design units to the given VHDL library.
+
+		.. rubric:: Algorithm
+
+		1. Iterate all entities in the document
+
+		   1. Check if entity name might exist in target library.
+		   2. Add entity to library and update library membership.
+
+		2. Iterate all architectures in the document
+
+		   1. Check if architecture name might exist in target library.
+		   2. Add architecture to library and update library membership.
+
+		3. Iterate all packages in the document
+
+		   1. Check if package name might exist in target library.
+		   2. Add package to library and update library membership.
+
+		4. Iterate all package bodies in the document
+
+		   1. Check if package body name might exist in target library.
+		   2. Add package body to library and update library membership.
+
+		5. Iterate all configurations in the document
+
+		   1. Check if configuration name might exist in target library.
+		   2. Add configuration to library and update library membership.
+
+		6. Iterate all contexts in the document
+
+		   1. Check if context name might exist in target library.
+		   2. Add context to library and update library membership.
+
+		:param document:                           The VHDL source code file.
+		:param library:                            The VHDL library used to register the embedded design units to.
+		:raises LibraryNotRegisteredError:         If the given VHDL library is not a library in the design.
+		:raises EntityExistsInLibraryError:        If the processed entity's name is already existing in the VHDL library.
+		:raises ArchitectureExistsInLibraryError:  If the processed architecture's name is already existing in the VHDL library.
+		:raises PackageExistsInLibraryError:       If the processed package's name is already existing in the VHDL library.
+		:raises PackageBodyExistsError:            If the processed package body's name is already existing in the VHDL library.
+		:raises ConfigurationExistsInLibraryError: If the processed configuration's name is already existing in the VHDL library.
+		:raises ContextExistsInLibraryError:       If the processed context's name is already existing in the VHDL library.
+		"""
+		# FIXME: this checks for the library name, but not the object
+		# should the libraries parent be checked too?
+		if library._normalizedIdentifier not in self._libraries:
+			raise LibraryNotRegisteredError(library)
+
+		self._documents.append(document)
+		document._parent = self
+
+		for entityIdentifier, entity in document._entities.items():
+			if entityIdentifier in library._entities:
+				raise EntityExistsInLibraryError(entity, library)
+
+			library._entities[entityIdentifier] = entity
+			entity.Library = library
+
+		for entityIdentifier, architectures in document._architectures.items():
+			try:
+				architecturesPerEntity = library._architectures[entityIdentifier]
+				for architectureIdentifier, architecture in architectures.items():
+					if architectureIdentifier in architecturesPerEntity:
+						raise ArchitectureExistsInLibraryError(architecture, library._entities[entityIdentifier], library)
+
+					architecturesPerEntity[architectureIdentifier] = architecture
+					architecture.Library = library
+			except KeyError:
+				architecturesPerEntity = document._architectures[entityIdentifier].copy()
+				library._architectures[entityIdentifier] = architecturesPerEntity
+
+				for architecture in architecturesPerEntity.values():
+					architecture.Library = library
+
+		for packageIdentifier, package in document._packages.items():
+			if packageIdentifier in library._packages:
+				raise PackageExistsInLibraryError(package, library)
+
+			library._packages[packageIdentifier] = package
+			package.Library = library
+
+		for packageBodyIdentifier, packageBody in document._packageBodies.items():
+			if packageBodyIdentifier in library._packageBodies:
+				raise PackageBodyExistsError(packageBody, library)
+
+			library._packageBodies[packageBodyIdentifier] = packageBody
+			packageBody.Library = library
+
+		for configurationIdentifier, configuration in document._configurations.items():
+			if configurationIdentifier in library._configurations:
+				raise ConfigurationExistsInLibraryError(configuration, library)
+
+			library._configurations[configurationIdentifier] = configuration
+			configuration.Library = library
+
+		for contextIdentifier, context in document._contexts.items():
+			if contextIdentifier in library._contexts:
+				raise ContextExistsInLibraryError(context, library)
+
+			library._contexts[contextIdentifier] = context
+			context.Library = library

+
+
+

+[docs]
+	def IterateDesignUnits(self, filter: DesignUnitKind = DesignUnitKind.All) -> Generator[DesignUnit, None, None]:
+		"""
+		Iterate all design units in the design.
+
+		A union of :class:`DesignUnitKind` values can be given to filter the returned result for suitable design units.
+
+		.. rubric:: Algorithm
+
+		1. Iterate all VHDL libraries.
+
+		   1. Iterate all contexts in that library.
+		   2. Iterate all packages in that library.
+		   3. Iterate all package bodies in that library.
+		   4. Iterate all entites in that library.
+		   5. Iterate all architectures in that library.
+		   6. Iterate all configurations in that library.
+
+		:param filter: An enumeration with possibly multiple flags to filter the returned design units.
+		:returns:      A generator to iterate all matched design units in the design.
+
+		.. seealso::
+
+		   :meth:`pyVHDLModel.Library.IterateDesignUnits`
+		     Iterate all design units in the library.
+		   :meth:`pyVHDLModel.Document.IterateDesignUnits`
+		     Iterate all design units in the document.
+		"""
+		for library in self._libraries.values():
+			yield from library.IterateDesignUnits(filter)

+
+
+

+[docs]
+	def Analyze(self) -> None:
+		"""
+		Analyze the whole design.
+
+		.. rubric:: Algorithm
+
+		1. Analyze dependencies of design units. |br|
+		   This will also yield the design hierarchy and the compiler order.
+		2. Analyze dependencies of types and objects.
+
+		.. seealso::
+
+		   :meth:`AnalyzeDependencies`
+		     Analyze the dependencies of design units.
+
+		   :meth:`AnalyzeObjects`
+		     Analyze the dependencies of types and objects.
+		"""
+		self.AnalyzeDependencies()
+		self.AnalyzeObjects()

+
+
+

+[docs]
+	def AnalyzeDependencies(self) -> None:
+		"""
+		Analyze the dependencies of design units.
+
+		.. rubric:: Algorithm
+
+		1. Create all vertices of the dependency graph by iterating all design units in all libraries. |br|
+		   |rarr| :meth:`CreateDependencyGraph`
+		2. Create the compile order graph. |br|
+		   |rarr| :meth:`CreateCompileOrderGraph`
+		3. Index all packages. |br|
+		   |rarr| :meth:`IndexPackages`
+		4. Index all architectures. |br|
+		   |rarr| :meth:`IndexArchitectures`
+		5. Link all contexts |br|
+		   |rarr| :meth:`LinkContexts`
+		6. Link all architectures. |br|
+		   |rarr| :meth:`LinkArchitectures`
+		7. Link all package bodies. |br|
+		   |rarr| :meth:`LinkPackageBodies`
+		8. Link all library references. |br|
+		   |rarr| :meth:`LinkLibraryReferences`
+		9. Link all package references. |br|
+		   |rarr| :meth:`LinkPackageReferences`
+		10. Link all context references. |br|
+		    |rarr| :meth:`LinkContextReferences`
+		11. Link all components. |br|
+		    |rarr| :meth:`LinkComponents`
+		12. Link all instantiations. |br|
+		    |rarr| :meth:`LinkInstantiations`
+		13. Create the hierarchy graph. |br|
+		    |rarr| :meth:`CreateHierarchyGraph`
+		14. Compute the compile order. |br|
+		    |rarr| :meth:`ComputeCompileOrder`
+		"""
+		self.CreateDependencyGraph()
+		self.CreateCompileOrderGraph()
+
+		self.IndexPackages()
+		self.IndexArchitectures()
+
+		self.LinkContexts()
+		self.LinkArchitectures()
+		self.LinkPackageBodies()
+		self.LinkLibraryReferences()
+		self.LinkPackageReferences()
+		self.LinkContextReferences()
+
+		self.LinkComponents()
+		self.LinkInstantiations()
+		self.CreateHierarchyGraph()
+		self.ComputeCompileOrder()

+
+
+

+[docs]
+	def AnalyzeObjects(self) -> None:
+		"""
+		Analyze the dependencies of types and objects.
+
+		.. rubric:: Algorithm
+
+		1. Index all entities. |br|
+		   |rarr| :meth:`IndexEntities`
+		2. Index all package bodies. |br|
+		   |rarr| :meth:`IndexPackageBodies`
+		3. Import objects. |br|
+		   |rarr| :meth:`ImportObjects`
+		4. Create the type and object graph. |br|
+		   |rarr| :meth:`CreateTypeAndObjectGraph`
+		"""
+		self.IndexEntities()
+		self.IndexPackageBodies()
+
+		self.ImportObjects()
+		self.CreateTypeAndObjectGraph()

+
+
+

+[docs]
+	def CreateDependencyGraph(self) -> None:
+		"""
+		Create all vertices of the dependency graph by iterating all design units in all libraries.
+
+		This method will purely create a sea of vertices without any linking between vertices. The edges will be created later by other methods. |br|
+		See :meth:`AnalyzeDependencies` for these methods and their algorithmic order.
+
+		Each vertex has the following properties:
+
+		* The vertex' ID is the design unit's identifier.
+		* The vertex' value references the design unit.
+		* A key-value-pair called ``kind`` denotes the vertex's kind as an enumeration value of type :class:`DependencyGraphVertexKind`.
+		* A key-value-pair called ``predefined`` denotes if the referenced design unit is a predefined language entity.
+
+		.. rubric:: Algorithm
+
+		1. Iterate all libraries in the design.
+
+		   * Create a vertex for that library and reference the library by the vertex' value field. |br|
+		     In return, set the library's :attr:`~pyVHDLModel.Library._dependencyVertex` field to reference the created vertex.
+
+		   1. Iterate all contexts in that library.
+
+		      * Create a vertex for that context and reference the context by the vertex' value field. |br|
+		        In return, set the context's :attr:`~pyVHDLModel.DesignUnit.Context._dependencyVertex` field to reference the created vertex.
+
+		   2. Iterate all packages in that library.
+
+		      * Create a vertex for that package and reference the package by the vertex' value field. |br|
+		        In return, set the package's :attr:`~pyVHDLModel.DesignUnit.Package._dependencyVertex` field to reference the created vertex.
+
+		   3. Iterate all package bodies in that library.
+
+		      * Create a vertex for that package body and reference the package body by the vertex' value field. |br|
+		        In return, set the package body's :attr:`~pyVHDLModel.DesignUnit.PackageBody._dependencyVertex` field to reference the created vertex.
+
+		   4. Iterate all entities in that library.
+
+		      * Create a vertex for that entity and reference the entity by the vertex' value field. |br|
+		        In return, set the entity's :attr:`~pyVHDLModel.DesignUnit.Entity._dependencyVertex` field to reference the created vertex.
+
+		   5. Iterate all architectures in that library.
+
+		      * Create a vertex for that architecture and reference the architecture by the vertex' value field. |br|
+		        In return, set the architecture's :attr:`~pyVHDLModel.DesignUnit.Architecture._dependencyVertex` field to reference the created vertex.
+
+		   6. Iterate all configurations in that library.
+
+		      * Create a vertex for that configuration and reference the configuration by the vertex' value field. |br|
+		        In return, set the configuration's :attr:`~pyVHDLModel.DesignUnit.Configuration._dependencyVertex` field to reference the created vertex.
+		"""
+		predefinedLibraries = ("std", "ieee")
+
+		for libraryIdentifier, library in self._libraries.items():
+			dependencyVertex = Vertex(vertexID=f"{libraryIdentifier}", value=library, graph=self._dependencyGraph)
+			dependencyVertex["kind"] = DependencyGraphVertexKind.Library
+			dependencyVertex["predefined"] = libraryIdentifier in predefinedLibraries
+			library._dependencyVertex = dependencyVertex
+
+			for contextIdentifier, context in library._contexts.items():
+				dependencyVertex = Vertex(vertexID=f"{libraryIdentifier}.{contextIdentifier}", value=context, graph=self._dependencyGraph)
+				dependencyVertex["kind"] = DependencyGraphVertexKind.Context
+				dependencyVertex["predefined"] = context._parent._normalizedIdentifier in predefinedLibraries
+				context._dependencyVertex = dependencyVertex
+
+			for packageIdentifier, package in library._packages.items():
+				dependencyVertex = Vertex(vertexID=f"{libraryIdentifier}.{packageIdentifier}", value=package, graph=self._dependencyGraph)
+				dependencyVertex["kind"] = DependencyGraphVertexKind.Package
+				dependencyVertex["predefined"] = package._parent._normalizedIdentifier in predefinedLibraries
+				package._dependencyVertex = dependencyVertex
+
+			for packageBodyIdentifier, packageBody in library._packageBodies.items():
+				dependencyVertex = Vertex(vertexID=f"{libraryIdentifier}.{packageBodyIdentifier}(body)", value=packageBody, graph=self._dependencyGraph)
+				dependencyVertex["kind"] = DependencyGraphVertexKind.PackageBody
+				dependencyVertex["predefined"] = packageBody._parent._normalizedIdentifier in predefinedLibraries
+				packageBody._dependencyVertex = dependencyVertex
+
+			for entityIdentifier, entity in library._entities.items():
+				dependencyVertex = Vertex(vertexID=f"{libraryIdentifier}.{entityIdentifier}", value=entity, graph=self._dependencyGraph)
+				dependencyVertex["kind"] = DependencyGraphVertexKind.Entity
+				dependencyVertex["predefined"] = entity._parent._normalizedIdentifier in predefinedLibraries
+				entity._dependencyVertex = dependencyVertex
+
+			for entityIdentifier, architectures in library._architectures.items():
+				for architectureIdentifier, architecture in architectures.items():
+					dependencyVertex = Vertex(vertexID=f"{libraryIdentifier}.{entityIdentifier}({architectureIdentifier})", value=architecture, graph=self._dependencyGraph)
+					dependencyVertex["kind"] = DependencyGraphVertexKind.Architecture
+					dependencyVertex["predefined"] = architecture._parent._normalizedIdentifier in predefinedLibraries
+					architecture._dependencyVertex = dependencyVertex
+
+			for configurationIdentifier, configuration in library._configurations.items():
+				dependencyVertex = Vertex(vertexID=f"{libraryIdentifier}.{configurationIdentifier}", value=configuration, graph=self._dependencyGraph)
+				dependencyVertex["kind"] = DependencyGraphVertexKind.Configuration
+				dependencyVertex["predefined"] = configuration._parent._normalizedIdentifier in predefinedLibraries
+				configuration._dependencyVertex = dependencyVertex

+
+
+

+[docs]
+	def CreateCompileOrderGraph(self) -> None:
+		"""
+		Create a compile-order graph with bidirectional references to the dependency graph.
+
+		Add vertices representing a document (VHDL source file) to the dependency graph. Each "document" vertex in dependency graph is copied into the compile-order
+		graph and bidirectionally referenced.
+
+		In addition, each vertex of a corresponding design unit in a document is linked to the vertex representing that document to express the design unit in
+		document relationship.
+
+		Each added vertex has the following properties:
+
+		* The vertex' ID is the document's filename.
+		* The vertex' value references the document.
+		* A key-value-pair called ``kind`` denotes the vertex's kind as an enumeration value of type :class:`DependencyGraphVertexKind`.
+		* A key-value-pair called ``predefined`` does not exist.
+
+		.. rubric:: Algorithm
+
+		1. Iterate all documents in the design.
+
+		   * Create a vertex for that document and reference the document by the vertex' value field. |br|
+		     In return, set the documents's :attr:`~pyVHDLModel.Document._dependencyVertex` field to reference the created vertex.
+		   * Copy the vertex from dependency graph to compile-order graph and link both vertices bidirectionally. |br|
+		     In addition, set the documents's :attr:`~pyVHDLModel.Document._dependencyVertex` field to reference the copied vertex.
+
+		     * Add a key-value-pair called ``compileOrderVertex`` to the dependency graph's vertex.
+		     * Add a key-value-pair called ``dependencyVertex`` to the compiler-order graph's vertex.
+
+		   1. Iterate the documents design units and create an edge from the design unit's corresponding dependency vertex to the documents corresponding
+		      dependency vertex. This expresses a "design unit is located in document" relation.
+
+		      * Add a key-value-pair called `kind`` denoting the edge's kind as an enumeration value of type :class:`DependencyGraphEdgeKind`.
+		"""
+		for document in self._documents:
+			dependencyVertex = Vertex(vertexID=document.Path.name, value=document, graph=self._dependencyGraph)
+			dependencyVertex["kind"] = DependencyGraphVertexKind.Document
+			document._dependencyVertex = dependencyVertex
+
+			compilerOrderVertex = dependencyVertex.Copy(
+				self._compileOrderGraph,
+				copyDict=True,
+				linkingKeyToOriginalVertex="dependencyVertex",
+				linkingKeyFromOriginalVertex="compileOrderVertex"
+			)
+			document._compileOrderVertex = compilerOrderVertex
+
+			for designUnit in document._designUnits:
+				edge = dependencyVertex.EdgeFromVertex(designUnit._dependencyVertex)
+				edge["kind"] = DependencyGraphEdgeKind.SourceFile

+
+
+	def ImportObjects(self) -> None:
+		def _ImportObjects(package: Package) -> None:
+			for referencedLibrary in package._referencedPackages.values():
+				for referencedPackage in referencedLibrary.values():
+					for declaredItem in referencedPackage._declaredItems:
+						if isinstance(declaredItem, MultipleNamedEntityMixin):
+							for normalizedIdentifier in declaredItem._normalizedIdentifiers:
+								package._namespace._elements[normalizedIdentifier] = declaredItem
+						elif isinstance(declaredItem, NamedEntityMixin):
+							package._namespace._elements[declaredItem._normalizedIdentifier] = declaredItem
+						else:
+							raise VHDLModelException(f"Unexpected declared item.")
+
+		for libraryName in ("std", "ieee"):
+			for package in self.GetLibrary(libraryName).IterateDesignUnits(filter=DesignUnitKind.Package):  # type: Package
+				_ImportObjects(package)
+
+		for document in self.IterateDocumentsInCompileOrder():
+			for package in document.IterateDesignUnits(filter=DesignUnitKind.Package):  # type: Package
+				_ImportObjects(package)
+
+	def CreateTypeAndObjectGraph(self) -> None:
+		def _HandlePackage(package) -> None:
+			packagePrefix = f"{package.Library.NormalizedIdentifier}.{package.NormalizedIdentifier}"
+
+			for deferredConstant in package._deferredConstants.values():
+				print(f"Deferred Constant: {deferredConstant}")
+				deferredConstantVertex = Vertex(
+					vertexID=f"{packagePrefix}.{deferredConstant.NormalizedIdentifiers[0]}",
+					value=deferredConstant,
+					graph=self._objectGraph
+				)
+				deferredConstantVertex["kind"] = ObjectGraphVertexKind.DeferredConstant
+				deferredConstant._objectVertex = deferredConstantVertex
+
+			for constant in package._constants.values():
+				print(f"Constant: {constant}")
+				constantVertex = Vertex(
+					vertexID=f"{packagePrefix}.{constant.NormalizedIdentifiers[0]}",
+					value=constant,
+					graph=self._objectGraph
+				)
+				constantVertex["kind"] = ObjectGraphVertexKind.Constant
+				constant._objectVertex = constantVertex
+
+			for type in package._types.values():
+				print(f"Type: {type}")
+				typeVertex = Vertex(
+					vertexID=f"{packagePrefix}.{type.NormalizedIdentifier}",
+					value=type,
+					graph=self._objectGraph
+				)
+				typeVertex["kind"] = ObjectGraphVertexKind.Type
+				type._objectVertex = typeVertex
+
+			for subtype in package._subtypes.values():
+				print(f"Subtype: {subtype}")
+				subtypeVertex = Vertex(
+					vertexID=f"{packagePrefix}.{subtype.NormalizedIdentifier}",
+					value=subtype,
+					graph=self._objectGraph
+				)
+				subtypeVertex["kind"] = ObjectGraphVertexKind.Subtype
+				subtype._objectVertex = subtypeVertex
+
+			for function in package._functions.values():
+				print(f"Function: {function}")
+				functionVertex = Vertex(
+					vertexID=f"{packagePrefix}.{function.NormalizedIdentifier}",
+					value=function,
+					graph=self._objectGraph
+				)
+				functionVertex["kind"] = ObjectGraphVertexKind.Function
+				function._objectVertex = functionVertex
+
+			for procedure in package._procedures.values():
+				print(f"Procedure: {procedure}")
+				procedureVertex = Vertex(
+					vertexID=f"{packagePrefix}.{procedure.NormalizedIdentifier}",
+					value=procedure,
+					graph=self._objectGraph
+				)
+				procedureVertex["kind"] = ObjectGraphVertexKind.Function
+				procedure._objectVertex = procedureVertex
+
+			for signal in package._signals.values():
+				print(f"Signal: {signal}")
+				signalVertex = Vertex(
+					vertexID=f"{packagePrefix}.{signal.NormalizedIdentifiers[0]}",
+					value=signal,
+					graph=self._objectGraph
+				)
+				signalVertex["kind"] = ObjectGraphVertexKind.Signal
+				signal._objectVertex = signalVertex
+
+		def _LinkSymbolsInExpression(expression, namespace: Namespace, typeVertex: Vertex):
+			if isinstance(expression, UnaryExpression):
+				_LinkSymbolsInExpression(expression.Operand, namespace, typeVertex)
+			elif isinstance(expression, BinaryExpression):
+				_LinkSymbolsInExpression(expression.LeftOperand, namespace, typeVertex)
+				_LinkSymbolsInExpression(expression.RightOperand, namespace, typeVertex)
+			elif isinstance(expression, TernaryExpression):
+				pass
+			elif isinstance(expression, SimpleObjectOrFunctionCallSymbol):
+				obj = namespace.FindObject(expression)
+				expression._reference = obj
+
+				edge = obj._objectVertex.EdgeToVertex(typeVertex)
+				edge["kind"] = ObjectGraphEdgeKind.ReferenceInExpression
+			else:
+				pass
+
+		def _LinkItems(package: Package):
+			for item in package._declaredItems:
+				if isinstance(item, Constant):
+					print(f"constant: {item}")
+				elif isinstance(item, DeferredConstant):
+					print(f"deferred constant: {item}")
+				elif isinstance(item, Signal):
+					print(f"signal: {item}")
+				elif isinstance(item, IntegerType):
+					typeNode = item._objectVertex
+
+					_LinkSymbolsInExpression(item.Range.LeftBound, package._namespace, typeNode)
+					_LinkSymbolsInExpression(item.Range.RightBound, package._namespace, typeNode)
+				# elif isinstance(item, FloatingType):
+				# 	print(f"signal: {item}")
+				elif isinstance(item, PhysicalType):
+					typeNode = item._objectVertex
+
+					_LinkSymbolsInExpression(item.Range.LeftBound, package._namespace, typeNode)
+					_LinkSymbolsInExpression(item.Range.RightBound, package._namespace, typeNode)
+				elif isinstance(item, ArrayType):
+					# Resolve dimensions
+					for dimension in item._dimensions:
+						subtype = package._namespace.FindSubtype(dimension)
+						dimension._reference = subtype
+
+						edge = item._objectVertex.EdgeToVertex(subtype._objectVertex)
+						edge["kind"] = ObjectGraphEdgeKind.Subtype
+
+					# Resolve element subtype
+					subtype = package._namespace.FindSubtype(item._elementType)
+					item._elementType._reference = subtype
+
+					edge = item._objectVertex.EdgeToVertex(subtype._objectVertex)
+					edge["kind"] = ObjectGraphEdgeKind.Subtype
+				elif isinstance(item, RecordType):
+					# Resolve each elements subtype
+					for element in item._elements:
+						subtype = package._namespace.FindSubtype(element._subtype)
+						element._subtype._reference = subtype
+
+						edge = item._objectVertex.EdgeToVertex(subtype._objectVertex)
+						edge["kind"] = ObjectGraphEdgeKind.Subtype
+				else:
+					print(f"not handled: {item}")
+
+		for libraryName in ("std", "ieee"):
+			for package in self.GetLibrary(libraryName).IterateDesignUnits(filter=DesignUnitKind.Package):  # type: Package
+				_HandlePackage(package)
+				_LinkItems(package)
+
+		for document in self.IterateDocumentsInCompileOrder():
+			for package in document.IterateDesignUnits(filter=DesignUnitKind.Package):  # type: Package
+				_HandlePackage(package)
+				_LinkItems(package)
+
+

+[docs]
+	def LinkContexts(self) -> None:
+		"""
+		Resolves and links all items (library clauses, use clauses and nested context references) in contexts.
+
+		It iterates all contexts in the design. Therefore, the library of the context is used as the working library. By
+		default, the working library is implicitly referenced in :data:`_referencedLibraries`. In addition, a new empty
+		dictionary is created in :data:`_referencedPackages` and :data:`_referencedContexts` for that working library.
+
+		At first, all library clauses are resolved (a library clause my have multiple library reference symbols). For each
+		referenced library an entry in :data:`_referencedLibraries` is generated and new empty dictionaries in
+		:data:`_referencedPackages` and :data:`_referencedContexts` for that working library. In addition, a vertex in the
+		dependency graph is added for that relationship.
+
+		At second, all use clauses are resolved (a use clause my have multiple package member reference symbols). For each
+		referenced package,
+		"""
+		for context in self.IterateDesignUnits(DesignUnitKind.Context):  # type: Context
+			# Create entries in _referenced*** for the current working library under its real name.
+			workingLibrary: Library = context.Library
+			libraryNormalizedIdentifier = workingLibrary._normalizedIdentifier
+
+			context._referencedLibraries[libraryNormalizedIdentifier] = self._libraries[libraryNormalizedIdentifier]
+			context._referencedPackages[libraryNormalizedIdentifier] = {}
+			context._referencedContexts[libraryNormalizedIdentifier] = {}
+
+			# Process all library clauses
+			for libraryReference in context._libraryReferences:
+				# A library clause can have multiple comma-separated references
+				for libraryName in libraryReference.Symbols:
+					libraryNormalizedIdentifier = libraryName.Name._normalizedIdentifier
+					try:
+						library = self._libraries[libraryNormalizedIdentifier]
+					except KeyError:
+						raise ReferencedLibraryNotExistingError(context, libraryName)
+						# TODO: add position to these messages
+
+					libraryName.Library = library
+
+					context._referencedLibraries[libraryNormalizedIdentifier] = library
+					context._referencedPackages[libraryNormalizedIdentifier] = {}
+					context._referencedContexts[libraryNormalizedIdentifier] = {}
+					# TODO: warn duplicate library reference
+
+					dependency = context._dependencyVertex.EdgeToVertex(library._dependencyVertex, edgeValue=libraryReference)
+					dependency["kind"] = DependencyGraphEdgeKind.LibraryClause
+
+			# Process all use clauses
+			for packageReference in context.PackageReferences:
+				# A use clause can have multiple comma-separated references
+				for symbol in packageReference.Symbols:  # type: PackageReferenceSymbol
+					packageName = symbol.Name.Prefix
+					libraryName = packageName.Prefix
+
+					libraryNormalizedIdentifier = libraryName._normalizedIdentifier
+					packageNormalizedIdentifier = packageName._normalizedIdentifier
+
+					# In case work is used, resolve to the real library name.
+					if libraryNormalizedIdentifier == "work":
+						library: Library = context._parent
+						libraryNormalizedIdentifier = library._normalizedIdentifier
+					elif libraryNormalizedIdentifier not in context._referencedLibraries:
+						# TODO: This check doesn't trigger if it's the working library.
+						raise VHDLModelException(f"Use clause references library '{libraryName._identifier}', which was not referenced by a library clause.")
+					else:
+						library = self._libraries[libraryNormalizedIdentifier]
+
+					try:
+						package = library._packages[packageNormalizedIdentifier]
+					except KeyError:
+						raise VHDLModelException(f"Package '{packageName._identifier}' not found in {'working ' if libraryName._normalizedIdentifier == 'work' else ''}library '{library._identifier}'.")
+
+					symbol.Package = package
+
+					# TODO: warn duplicate package reference
+					context._referencedPackages[libraryNormalizedIdentifier][packageNormalizedIdentifier] = package
+
+					dependency = context._dependencyVertex.EdgeToVertex(package._dependencyVertex, edgeValue=packageReference)
+					dependency["kind"] = DependencyGraphEdgeKind.UseClause
+
+					# TODO: update the namespace with visible members
+					if isinstance(symbol, AllPackageMembersReferenceSymbol):
+						pass
+
+					elif isinstance(symbol, PackageMemberReferenceSymbol):
+						raise NotImplementedError()
+					else:
+						raise VHDLModelException()

+
+
+

+[docs]
+	def LinkArchitectures(self) -> None:
+		"""
+		Link all architectures to corresponding entities in all libraries.
+
+		.. rubric:: Algorithm
+
+		1. Iterate all libraries:
+
+		   1. Iterate all architecture groups (grouped per entity symbol's name).
+		      |rarr| :meth:`pyVHDLModel.Library.LinkArchitectures`
+
+		      * Check if entity symbol's name exists as an entity in this library.
+
+		      1. For each architecture in the same architecture group:
+
+		         * Add architecture to entities architecture dictionary :attr:`pyVHDLModel.DesignUnit.Entity._architectures`.
+		         * Assign found entity to architecture's entity symbol :attr:`pyVHDLModel.DesignUnit.Architecture._entity`
+		         * Set parent namespace of architecture's namespace to the entitie's namespace.
+		         * Add an edge in the dependency graph from the architecture's corresponding dependency vertex to the entity's corresponding dependency vertex.
+
+		.. seealso::
+
+		   :meth:`LinkPackageBodies`
+		     Link all package bodies to corresponding packages in all libraries.
+		"""
+		for library in self._libraries.values():
+			library.LinkArchitectures()

+
+
+

+[docs]
+	def LinkPackageBodies(self) -> None:
+		"""
+		Link all package bodies to corresponding packages in all libraries.
+
+		.. rubric:: Algorithm
+
+		1. Iterate all libraries:
+
+		   1. Iterate all package bodies.
+		      |rarr| :meth:`pyVHDLModel.Library.LinkPackageBodies`
+
+		      * Check if package body symbol's name exists as a package in this library.
+		      * Add package body to package :attr:`pyVHDLModel.DesignUnit.Package._packageBody`.
+		      * Assign found package to package body's package symbol :attr:`pyVHDLModel.DesignUnit.PackageBody._package`
+		      * Set parent namespace of package body's namespace to the package's namespace.
+		      * Add an edge in the dependency graph from the package body's corresponding dependency vertex to the package's corresponding dependency vertex.
+
+		.. seealso::
+
+		   :meth:`LinkArchitectures`
+		     Link all architectures to corresponding entities in all libraries.
+		"""
+		for library in self._libraries.values():
+			library.LinkPackageBodies()

+
+
+	def LinkLibraryReferences(self) -> None:
+		DEFAULT_LIBRARIES = ("std",)
+
+		for designUnit in self.IterateDesignUnits(DesignUnitKind.WithContext):
+			# All primary units supporting a context, have at least one library implicitly referenced
+			if isinstance(designUnit, PrimaryUnit):
+				for libraryIdentifier in DEFAULT_LIBRARIES:
+					referencedLibrary = self._libraries[libraryIdentifier]
+					designUnit._referencedLibraries[libraryIdentifier] = referencedLibrary
+					designUnit._referencedPackages[libraryIdentifier] = {}
+					designUnit._referencedContexts[libraryIdentifier] = {}
+					# TODO: catch KeyError on self._libraries[libName]
+					# TODO: warn duplicate library reference
+
+					dependency = designUnit._dependencyVertex.EdgeToVertex(referencedLibrary._dependencyVertex)
+					dependency["kind"] = DependencyGraphEdgeKind.LibraryClause
+
+				workingLibrary: Library = designUnit.Library
+				libraryIdentifier = workingLibrary.NormalizedIdentifier
+				referencedLibrary = self._libraries[libraryIdentifier]
+
+
+				designUnit._referencedLibraries[libraryIdentifier] = referencedLibrary
+				designUnit._referencedPackages[libraryIdentifier] = {}
+				designUnit._referencedContexts[libraryIdentifier] = {}
+
+				dependency = designUnit._dependencyVertex.EdgeToVertex(referencedLibrary._dependencyVertex)
+				dependency["kind"] = DependencyGraphEdgeKind.LibraryClause
+
+			# All secondary units inherit referenced libraries from their primary units.
+			else:
+				if isinstance(designUnit, Architecture):
+					referencedLibraries = designUnit.Entity.Entity._referencedLibraries
+				elif isinstance(designUnit, PackageBody):
+					referencedLibraries = designUnit.Package.Package._referencedLibraries
+				else:
+					raise VHDLModelException()
+
+				for libraryIdentifier, library in referencedLibraries.items():
+					designUnit._referencedLibraries[libraryIdentifier] = library
+
+			for libraryReference in designUnit._libraryReferences:
+				# A library clause can have multiple comma-separated references
+				for librarySymbol in libraryReference.Symbols:
+					libraryIdentifier = librarySymbol.Name.NormalizedIdentifier
+					try:
+						library = self._libraries[libraryIdentifier]
+					except KeyError:
+						ex = VHDLModelException(f"Library '{librarySymbol.Name.Identifier}' referenced by library clause of design unit '{designUnit.Identifier}' doesn't exist in design.")
+						ex.add_note(f"""Known libraries: '{"', '".join(library for library in self._libraries)}'""")
+						raise ex
+
+					librarySymbol.Library = library
+					designUnit._referencedLibraries[libraryIdentifier] = library
+					designUnit._referencedPackages[libraryIdentifier] = {}
+					designUnit._referencedContexts[libraryIdentifier] = {}
+					# TODO: warn duplicate library reference
+
+					dependency = designUnit._dependencyVertex.EdgeToVertex(library._dependencyVertex, edgeValue=libraryReference)
+					dependency["kind"] = DependencyGraphEdgeKind.LibraryClause
+
+	def LinkPackageReferences(self) -> None:
+		DEFAULT_PACKAGES = (
+			("std", ("standard",)),
+		)
+
+		for designUnit in self.IterateDesignUnits(DesignUnitKind.WithContext):
+			# All primary units supporting a context, have at least one package implicitly referenced
+			if isinstance(designUnit, PrimaryUnit):
+				if designUnit.Library.NormalizedIdentifier != "std" and \
+					designUnit.NormalizedIdentifier != "standard":
+					for lib in DEFAULT_PACKAGES:
+						if lib[0] not in designUnit._referencedLibraries:
+							raise VHDLModelException()
+						for pack in lib[1]:
+							referencedPackage = self._libraries[lib[0]]._packages[pack]
+							designUnit._referencedPackages[lib[0]][pack] = referencedPackage
+							# TODO: catch KeyError on self._libraries[lib[0]]._packages[pack]
+							# TODO: warn duplicate package reference
+
+							dependency = designUnit._dependencyVertex.EdgeToVertex(referencedPackage._dependencyVertex)
+							dependency["kind"] = DependencyGraphEdgeKind.UseClause
+
+			# All secondary units inherit referenced packages from their primary units.
+			else:
+				if isinstance(designUnit, Architecture):
+					referencedPackages = designUnit.Entity.Entity._referencedPackages
+				elif isinstance(designUnit, PackageBody):
+					referencedPackages = designUnit.Package.Package._referencedPackages
+				else:
+					raise VHDLModelException()
+
+				for packageIdentifier, package in referencedPackages.items():
+					designUnit._referencedPackages[packageIdentifier] = package
+
+			for packageReference in designUnit.PackageReferences:
+				# A use clause can have multiple comma-separated references
+				for packageMemberSymbol in packageReference.Symbols:
+					packageName = packageMemberSymbol.Name.Prefix
+					libraryName = packageName.Prefix
+
+					libraryIdentifier = libraryName.NormalizedIdentifier
+					packageIdentifier = packageName.NormalizedIdentifier
+
+					# In case work is used, resolve to the real library name.
+					if libraryIdentifier == "work":
+						library: Library = designUnit.Library
+						libraryIdentifier = library.NormalizedIdentifier
+					elif libraryIdentifier not in designUnit._referencedLibraries:
+						# TODO: This check doesn't trigger if it's the working library.
+						raise VHDLModelException(f"Use clause references library '{libraryName.Identifier}', which was not referenced by a library clause.")
+					else:
+						library = self._libraries[libraryIdentifier]
+
+					try:
+						package = library._packages[packageIdentifier]
+					except KeyError:
+						ex = VHDLModelException(f"Package '{packageName.Identifier}' not found in {'working ' if libraryName.NormalizedIdentifier == 'work' else ''}library '{library.Identifier}'.")
+						ex.add_note(f"Caused in design unit '{designUnit}' in file '{designUnit.Document}'.")
+						raise ex
+
+					packageMemberSymbol.Package = package
+
+					# TODO: warn duplicate package reference
+					designUnit._referencedPackages[libraryIdentifier][packageIdentifier] = package
+
+					dependency = designUnit._dependencyVertex.EdgeToVertex(package._dependencyVertex, edgeValue=packageReference)
+					dependency["kind"] = DependencyGraphEdgeKind.UseClause
+
+					# TODO: update the namespace with visible members
+					if isinstance(packageMemberSymbol, AllPackageMembersReferenceSymbol):
+						for componentIdentifier, component in package._components.items():
+							designUnit._namespace._elements[componentIdentifier] = component
+
+					elif isinstance(packageMemberSymbol, PackageMemberReferenceSymbol):
+						raise NotImplementedError()
+					else:
+						raise VHDLModelException()
+
+	def LinkContextReferences(self) -> None:
+		for designUnit in self.IterateDesignUnits():
+			for contextReference in designUnit._contextReferences:
+				# A context reference can have multiple comma-separated references
+				for contextSymbol in contextReference.Symbols:
+					libraryName = contextSymbol.Name.Prefix
+
+					libraryIdentifier = libraryName.NormalizedIdentifier
+					contextIdentifier = contextSymbol.Name.NormalizedIdentifier
+
+					# In case work is used, resolve to the real library name.
+					if libraryIdentifier == "work":
+						referencedLibrary = designUnit.Library
+						libraryIdentifier = referencedLibrary.NormalizedIdentifier
+					elif libraryIdentifier not in designUnit._referencedLibraries:
+						# TODO: This check doesn't trigger if it's the working library.
+						raise VHDLModelException(f"Context reference references library '{libraryName.Identifier}', which was not referenced by a library clause.")
+					else:
+						referencedLibrary = self._libraries[libraryIdentifier]
+
+					try:
+						referencedContext = referencedLibrary._contexts[contextIdentifier]
+					except KeyError:
+						raise VHDLModelException(f"Context '{contextSymbol.Name.Identifier}' not found in {'working ' if libraryName.NormalizedIdentifier == 'work' else ''}library '{referencedLibrary.Identifier}'.")
+
+					contextSymbol.Package = referencedContext
+
+					# TODO: warn duplicate referencedContext reference
+					designUnit._referencedContexts[libraryIdentifier][contextIdentifier] = referencedContext
+
+					dependency = designUnit._dependencyVertex.EdgeToVertex(referencedContext._dependencyVertex, edgeValue=contextReference)
+					dependency["kind"] = DependencyGraphEdgeKind.ContextReference
+
+		for vertex in self._dependencyGraph.IterateTopologically():
+			if vertex["kind"] is DependencyGraphVertexKind.Context:
+				context: Context = vertex.Value
+				for designUnitVertex in vertex.IteratePredecessorVertices():
+					designUnit: DesignUnit = designUnitVertex.Value
+					for libraryIdentifier, library in context._referencedLibraries.items():
+						# if libraryIdentifier in designUnit._referencedLibraries:
+						# 	raise VHDLModelException(f"Referenced library '{library.Identifier}' already exists in references for design unit '{designUnit.Identifier}'.")
+
+						designUnit._referencedLibraries[libraryIdentifier] = library
+						designUnit._referencedPackages[libraryIdentifier] = {}
+
+					for libraryIdentifier, packages in context._referencedPackages.items():
+						for packageIdentifier, package in packages.items():
+							if packageIdentifier in designUnit._referencedPackages:
+								raise VHDLModelException(f"Referenced package '{package.Identifier}' already exists in references for design unit '{designUnit.Identifier}'.")
+
+							designUnit._referencedPackages[libraryIdentifier][packageIdentifier] = package
+
+	def LinkComponents(self) -> None:
+		for package in self.IterateDesignUnits(DesignUnitKind.Package):  # type: Package
+			library = package._parent
+			for component in package._components.values():
+				try:
+					entity = library._entities[component.NormalizedIdentifier]
+				except KeyError:
+					print(f"Entity '{component.Identifier}' not found for component '{component.Identifier}' in library '{library.Identifier}'.")
+
+				component.Entity = entity
+
+				# QUESTION: Add link in dependency graph as dashed line from component to entity?
+				#           Currently, component has no _dependencyVertex field
+
+	def LinkInstantiations(self) -> None:
+		for architecture in self.IterateDesignUnits(DesignUnitKind.Architecture):  # type: Architecture
+			for instance in architecture.IterateInstantiations():
+				if isinstance(instance, EntityInstantiation):
+					libraryName = instance.Entity.Name.Prefix
+					libraryIdentifier = libraryName.Identifier
+					normalizedLibraryIdentifier = libraryName.NormalizedIdentifier
+					if normalizedLibraryIdentifier == "work":
+						libraryIdentifier = architecture.Library.Identifier
+						normalizedLibraryIdentifier = architecture.Library.NormalizedIdentifier
+					elif normalizedLibraryIdentifier not in architecture._referencedLibraries:
+						ex = VHDLModelException(f"Referenced library '{libraryIdentifier}' in direct entity instantiation '{instance.Label}: entity {instance.Entity.Prefix.Identifier}.{instance.Entity.Identifier}' not found in architecture '{architecture!r}'.")
+						ex.add_note(f"Add a library reference to the architecture or entity using a library clause like: 'library {libraryIdentifier};'.")
+						raise ex
+
+					try:
+						library = self._libraries[normalizedLibraryIdentifier]
+					except KeyError:
+						ex = VHDLModelException(f"Referenced library '{libraryIdentifier}' in direct entity instantiation '{instance.Label}: entity {instance.Entity.Prefix.Identifier}.{instance.Entity.Identifier}' not found in design.")
+						ex.add_note(f"No design units were parsed into library '{libraryIdentifier}'. Thus it doesn't exist in design.")
+						raise ex
+
+					try:
+						entity = library._entities[instance.Entity.Name.NormalizedIdentifier]
+					except KeyError:
+						ex = VHDLModelException(f"Referenced entity '{instance.Entity.Name.Identifier}' in direct entity instantiation '{instance.Label}: entity {instance.Entity.Name.Prefix.Identifier}.{instance.Entity.Name.Identifier}' not found in {'working ' if instance.Entity.Name.Prefix.NormalizedIdentifier == 'work' else ''}library '{libraryIdentifier}'.")
+						libs = [library.Identifier for library in self._libraries.values() for entityIdentifier in library._entities.keys() if entityIdentifier == instance.Entity.Name.NormalizedIdentifier]
+						if libs:
+							ex.add_note(f"Found entity '{instance.Entity!s}' in other libraries: {', '.join(libs)}")
+						raise ex
+
+					instance.Entity.Entity = entity
+
+					dependency = architecture._dependencyVertex.EdgeToVertex(entity._dependencyVertex, edgeValue=instance)
+					dependency["kind"] = DependencyGraphEdgeKind.EntityInstantiation
+
+				elif isinstance(instance, ComponentInstantiation):
+					component = architecture._namespace.FindComponent(instance.Component)
+
+					instance.Component.Component = component
+
+					dependency = architecture._dependencyVertex.EdgeToVertex(component.Entity._dependencyVertex, edgeValue=instance)
+					dependency["kind"] = DependencyGraphEdgeKind.ComponentInstantiation
+
+				elif isinstance(instance, ConfigurationInstantiation):
+					# pass
+					print(instance.Label, instance.Configuration)
+
+

+[docs]
+	def IndexPackages(self) -> None:
+		"""
+		Index all declared items in all packages in all libraries.
+
+		.. rubric:: Algorithm
+
+		1. Iterate all libraries:
+
+		   1. Iterate all packages |br|
+		      |rarr| :meth:`pyVHDLModel.Library.IndexPackages`
+
+		      * Index all declared items in that package. |br|
+		        |rarr| :meth:`pyVHDLModel.DesignUnit.Package.IndexDeclaredItems`
+
+		.. seealso::
+
+		   :meth:`IndexPackageBodies`
+		     Index all declared items in all package bodies in all libraries.
+		   :meth:`IndexEntities`
+		     Index all declared items in all entities in all libraries.
+		   :meth:`IndexArchitectures`
+		     Index all declared items in all architectures in all libraries.
+		"""
+		for library in self._libraries.values():
+			library.IndexPackages()

+
+
+

+[docs]
+	def IndexPackageBodies(self) -> None:
+		"""
+		Index all declared items in all packages in all libraries.
+
+		.. rubric:: Algorithm
+
+		1. Iterate all libraries:
+
+		   1. Iterate all packages |br|
+		      |rarr| :meth:`pyVHDLModel.Library.IndexPackageBodies`
+
+		      * Index all declared items in that package body. |br|
+		        |rarr| :meth:`pyVHDLModel.DesignUnit.PackageBody.IndexDeclaredItems`
+
+		.. seealso::
+
+		   :meth:`IndexPackages`
+		     Index all declared items in all packages in all libraries.
+		   :meth:`IndexEntities`
+		     Index all declared items in all entities in all libraries.
+		   :meth:`IndexArchitectures`
+		     Index all declared items in all architectures in all libraries.
+		"""
+		for library in self._libraries.values():
+			library.IndexPackageBodies()

+
+
+

+[docs]
+	def IndexEntities(self) -> None:
+		"""
+		Index all declared items in all packages in all libraries.
+
+		.. rubric:: Algorithm
+
+		1. Iterate all libraries:
+
+		   1. Iterate all packages |br|
+		      |rarr| :meth:`pyVHDLModel.Library.IndexEntities`
+
+		      * Index all declared items in that entity. |br|
+		        |rarr| :meth:`pyVHDLModel.DesignUnit.Entity.IndexDeclaredItems`
+
+		.. seealso::
+
+		   :meth:`IndexPackages`
+		     Index all declared items in all packages in all libraries.
+		   :meth:`IndexPackageBodies`
+		     Index all declared items in all package bodies in all libraries.
+		   :meth:`IndexArchitectures`
+		     Index all declared items in all architectures in all libraries.
+		"""
+		for library in self._libraries.values():
+			library.IndexEntities()

+
+
+

+[docs]
+	def IndexArchitectures(self) -> None:
+		"""
+		Index all declared items in all packages in all libraries.
+
+		.. rubric:: Algorithm
+
+		1. Iterate all libraries:
+
+		   1. Iterate all packages |br|
+		      |rarr| :meth:`pyVHDLModel.Library.IndexArchitectures`
+
+		      * Index all declared items in that architecture. |br|
+		        |rarr| :meth:`pyVHDLModel.DesignUnit.Architecture.IndexDeclaredItems`
+
+		.. seealso::
+
+		   :meth:`IndexPackages`
+		     Index all declared items in all packages in all libraries.
+		   :meth:`IndexPackageBodies`
+		     Index all declared items in all package bodies in all libraries.
+		   :meth:`IndexEntities`
+		     Index all declared items in all entities in all libraries.
+		"""
+		for library in self._libraries.values():
+			library.IndexArchitectures()

+
+
+

+[docs]
+	def CreateHierarchyGraph(self) -> None:
+		"""
+		Create the hierarchy graph from dependency graph.
+
+		.. rubric:: Algorithm
+
+		1. Iterate all vertices corresponding to entities and architectures in the dependency graph:
+
+		   * Copy these vertices to the hierarchy graph and create a bidirectional linking. |br|
+		     In addition, set the referenced design unit's :attr:`~pyVHDLModel.Document._hierarchyVertex` field to reference the copied vertex.
+
+		     * Add a key-value-pair called ``hierarchyVertex`` to the dependency graph's vertex.
+		     * Add a key-value-pair called ``dependencyVertex`` to the hierarchy graph's vertex.
+
+		2. Iterate all architectures ...
+
+		   .. todo:: Design::CreateHierarchyGraph describe algorithm
+
+		   1. Iterate all outbound edges
+
+		      .. todo:: Design::CreateHierarchyGraph describe algorithm
+		"""
+		# Copy all entity and architecture vertices from dependency graph to hierarchy graph and double-link them
+		entityArchitectureFilter = lambda v: v["kind"] in DependencyGraphVertexKind.Entity | DependencyGraphVertexKind.Architecture
+		for vertex in self._dependencyGraph.IterateVertices(predicate=entityArchitectureFilter):
+			hierarchyVertex = vertex.Copy(self._hierarchyGraph, copyDict=True, linkingKeyToOriginalVertex="dependencyVertex", linkingKeyFromOriginalVertex="hierarchyVertex")
+			vertex.Value._hierarchyVertex = hierarchyVertex
+
+		# Copy implementation edges from
+		for hierarchyArchitectureVertex in self._hierarchyGraph.IterateVertices(predicate=lambda v: v["kind"] is DependencyGraphVertexKind.Architecture):
+			for dependencyEdge in hierarchyArchitectureVertex["dependencyVertex"].IterateOutboundEdges():
+				kind: DependencyGraphEdgeKind = dependencyEdge["kind"]
+				if DependencyGraphEdgeKind.Implementation in kind:
+					hierarchyDestinationVertex = dependencyEdge.Destination["hierarchyVertex"]
+					newEdge = hierarchyArchitectureVertex.EdgeFromVertex(hierarchyDestinationVertex)
+				elif DependencyGraphEdgeKind.Instantiation in kind:
+					hierarchyDestinationVertex = dependencyEdge.Destination["hierarchyVertex"]
+
+					# FIXME: avoid parallel edges, to graph can be converted to a tree until "real" hierarchy is computed (unrole generics and blocks)
+					if hierarchyArchitectureVertex.HasEdgeToDestination(hierarchyDestinationVertex):
+						continue
+
+					newEdge = hierarchyArchitectureVertex.EdgeToVertex(hierarchyDestinationVertex)
+				else:
+					continue
+
+				newEdge["kind"] = kind

+
+
+	def ComputeCompileOrder(self) -> None:
+		def predicate(edge: Edge) -> bool:
+			return (
+				DependencyGraphEdgeKind.Implementation in edge["kind"] or
+				DependencyGraphEdgeKind.Instantiation in edge["kind"] or
+				DependencyGraphEdgeKind.UseClause in edge["kind"] or
+				DependencyGraphEdgeKind.ContextReference in edge["kind"]
+			) and edge.Destination["predefined"] is False
+
+		for edge in self._dependencyGraph.IterateEdges(predicate=predicate):
+			sourceDocument:      Document = edge.Source.Value.Document
+			destinationDocument: Document = edge.Destination.Value.Document
+
+			sourceVertex =      sourceDocument._compileOrderVertex
+			destinationVertex = destinationDocument._compileOrderVertex
+
+			# Don't add self-edges
+			if sourceVertex is destinationVertex:
+				continue
+			# Don't add parallel edges
+			elif sourceVertex.HasEdgeToDestination(destinationVertex):
+				continue
+
+			e = sourceVertex.EdgeToVertex(destinationVertex)
+			e["kind"] = DependencyGraphEdgeKind.CompileOrder
+
+			e = sourceVertex["dependencyVertex"].EdgeToVertex(destinationVertex["dependencyVertex"])
+			e["kind"] = DependencyGraphEdgeKind.CompileOrder
+
+

+[docs]
+	def IterateDocumentsInCompileOrder(self) -> Generator['Document', None, None]:
+		"""
+		Iterate all document in compile-order.
+
+		.. rubric:: Algorithm
+
+		* Check if compile-order graph was populated with vertices and its vertices are linked by edges.
+
+		1. Iterate compile-order graph in topological order. |br|
+		   :meth:`pyTooling.Graph.Graph.IterateTopologically`
+
+		   * yield the compiler-order vertex' referenced document.
+
+		:returns:                   A generator to iterate all documents in compile-order in the design.
+		:raises VHDLModelException: If compile-order was not computed.
+
+		.. seealso::
+
+		   .. todo:: missing text
+
+		      :meth:`pyVHDLModel.Design.ComputeCompileOrder`
+
+		"""
+		if self._compileOrderGraph.EdgeCount < self._compileOrderGraph.VertexCount - 1:
+			raise VHDLModelException(f"Compile order is not yet computed from dependency graph.")
+
+		for compileOrderNode in self._compileOrderGraph.IterateTopologically():
+			yield compileOrderNode.Value

+
+
+	def GetUnusedDesignUnits(self) -> List[DesignUnit]:
+		raise NotImplementedError()
+
+

+[docs]
+	def __repr__(self) -> str:
+		"""
+		Formats a representation of the design.
+
+		**Format:** ``Document: 'my_design'``
+
+		:returns: String representation of the design.
+		"""
+		return f"Design: {self._name}"

+
+
+	__str__ = __repr__

+
+
+
+

+[docs]
+@export
+class Library(ModelEntity, NamedEntityMixin):
+	"""A ``Library`` represents a VHDL library. It contains all *primary* and *secondary* design units."""
+
+	_contexts:       Dict[str, Context]                  #: Dictionary of all contexts defined in a library.
+	_configurations: Dict[str, Configuration]            #: Dictionary of all configurations defined in a library.
+	_entities:       Dict[str, Entity]                   #: Dictionary of all entities defined in a library.
+	_architectures:  Dict[str, Dict[str, Architecture]]  #: Dictionary of all architectures defined in a library.
+	_packages:       Dict[str, Package]                  #: Dictionary of all packages defined in a library.
+	_packageBodies:  Dict[str, PackageBody]              #: Dictionary of all package bodies defined in a library.
+
+	_dependencyVertex: Vertex[None, None, str, Union['Library', DesignUnit], None, None, None, None, None, None, None, None, None, None, None, None, None]  #: Reference to the vertex in the dependency graph representing the library. |br| This reference is set by :meth:`~pyVHDLModel.Design.CreateDependencyGraph`.
+
+

+[docs]
+	def __init__(self, identifier: str, parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+		NamedEntityMixin.__init__(self, identifier)
+
+		self._contexts =        {}
+		self._configurations =  {}
+		self._entities =        {}
+		self._architectures =   {}
+		self._packages =        {}
+		self._packageBodies =   {}
+
+		self._dependencyVertex = None

+
+
+	@readonly
+	def Contexts(self) -> Dict[str, Context]:
+		"""Returns a list of all context declarations declared in this library."""
+		return self._contexts
+
+	@readonly
+	def Configurations(self) -> Dict[str, Configuration]:
+		"""Returns a list of all configuration declarations declared in this library."""
+		return self._configurations
+
+	@readonly
+	def Entities(self) -> Dict[str, Entity]:
+		"""Returns a list of all entity declarations declared in this library."""
+		return self._entities
+
+	@readonly
+	def Architectures(self) -> Dict[str, Dict[str, Architecture]]:
+		"""Returns a list of all architectures declarations declared in this library."""
+		return self._architectures
+
+	@readonly
+	def Packages(self) -> Dict[str, Package]:
+		"""Returns a list of all package declarations declared in this library."""
+		return self._packages
+
+	@readonly
+	def PackageBodies(self) -> Dict[str, PackageBody]:
+		"""Returns a list of all package body declarations declared in this library."""
+		return self._packageBodies
+
+	@readonly
+	def DependencyVertex(self) -> Vertex:
+		"""
+		Read-only property to access the corresponding dependency vertex (:attr:`_dependencyVertex`).
+
+		The dependency vertex references this library by its value field.
+
+		:returns: The corresponding dependency vertex.
+		"""
+		return self._dependencyVertex
+
+

+[docs]
+	def IterateDesignUnits(self, filter: DesignUnitKind = DesignUnitKind.All) -> Generator[DesignUnit, None, None]:
+		"""
+		Iterate all design units in the library.
+
+		A union of :class:`DesignUnitKind` values can be given to filter the returned result for suitable design units.
+
+		.. rubric:: Algorithm
+
+		1. Iterate all contexts in that library.
+		2. Iterate all packages in that library.
+		3. Iterate all package bodies in that library.
+		4. Iterate all entites in that library.
+		5. Iterate all architectures in that library.
+		6. Iterate all configurations in that library.
+
+		:param filter: An enumeration with possibly multiple flags to filter the returned design units.
+		:returns:      A generator to iterate all matched design units in the library.
+
+		.. seealso::
+
+		   :meth:`pyVHDLModel.Design.IterateDesignUnits`
+		     Iterate all design units in the design.
+		   :meth:`pyVHDLModel.Document.IterateDesignUnits`
+		     Iterate all design units in the document.
+		"""
+		if DesignUnitKind.Context in filter:
+			for context in self._contexts.values():
+				yield context
+
+		if DesignUnitKind.Package in filter:
+			for package in self._packages.values():
+				yield package
+
+		if DesignUnitKind.PackageBody in filter:
+			for packageBody in self._packageBodies.values():
+				yield packageBody
+
+		if DesignUnitKind.Entity in filter:
+			for entity in self._entities.values():
+				yield entity
+
+		if DesignUnitKind.Architecture in filter:
+			for architectures in self._architectures.values():
+				for architecture in architectures.values():
+					yield architecture
+
+		if DesignUnitKind.Configuration in filter:
+			for configuration in self._configurations.values():
+				yield configuration

+
+
+		# for verificationProperty in self._verificationUnits.values():
+		# 	yield verificationProperty
+		# for verificationUnit in self._verificationProperties.values():
+		# 	yield entity
+		# for verificationMode in self._verificationModes.values():
+		# 	yield verificationMode
+
+

+[docs]
+	def LinkArchitectures(self) -> None:
+		"""
+		Link all architectures to corresponding entities.
+
+		.. rubric:: Algorithm
+
+		1. Iterate all architecture groups (grouped per entity symbol's name).
+
+		   * Check if entity symbol's name exists as an entity in this library.
+
+		   1. For each architecture in the same architecture group:
+
+		      * Add architecture to entities architecture dictionary :attr:`pyVHDLModel.DesignUnit.Entity._architectures`.
+		      * Assign found entity to architecture's entity symbol :attr:`pyVHDLModel.DesignUnit.Architecture._entity`
+		      * Set parent namespace of architecture's namespace to the entitie's namespace.
+		      * Add an edge in the dependency graph from the architecture's corresponding dependency vertex to the entity's corresponding dependency vertex.
+
+		:raises VHDLModelException: If entity name doesn't exist.
+		:raises VHDLModelException: If architecture name already exists for entity.
+
+		.. seealso::
+
+		   :meth:`LinkPackageBodies`
+		     Link all package bodies to corresponding packages.
+		"""
+		for entityName, architecturesPerEntity in self._architectures.items():
+			if entityName not in self._entities:
+				architectureNames = "', '".join(architecturesPerEntity.keys())
+				raise VHDLModelException(f"Entity '{entityName}' referenced by architecture(s) '{architectureNames}' doesn't exist in library '{self._identifier}'.")
+			# TODO: search in other libraries to find that entity.
+			# TODO: add code position
+
+			entity = self._entities[entityName]
+			for architecture in architecturesPerEntity.values():
+				if architecture._normalizedIdentifier in entity._architectures:
+					raise VHDLModelException(f"Architecture '{architecture._identifier}' already exists for entity '{entity._identifier}'.")
+				# TODO: add code position of existing and current
+
+				entity._architectures[architecture._normalizedIdentifier] = architecture
+				architecture._entity.Entity = entity
+				architecture._namespace._parentNamespace = entity._namespace
+
+				# add "architecture -> entity" relation in dependency graph
+				dependency = architecture._dependencyVertex.EdgeToVertex(entity._dependencyVertex)
+				dependency["kind"] = DependencyGraphEdgeKind.EntityImplementation

+
+
+

+[docs]
+	def LinkPackageBodies(self) -> None:
+		"""
+		Link all package bodies to corresponding packages.
+
+		.. rubric:: Algorithm
+
+		1. Iterate all package bodies.
+
+		   * Check if package body symbol's name exists as a package in this library.
+		   * Add package body to package :attr:`pyVHDLModel.DesignUnit.Package._packageBody`.
+		   * Assign found package to package body's package symbol :attr:`pyVHDLModel.DesignUnit.PackageBody._package`
+		   * Set parent namespace of package body's namespace to the package's namespace.
+		   * Add an edge in the dependency graph from the package body's corresponding dependency vertex to the package's corresponding dependency vertex.
+
+		:raises VHDLModelException: If package name doesn't exist.
+
+		.. seealso::
+
+		   :meth:`LinkArchitectures`
+		     Link all architectures to corresponding entities.
+		"""
+		for packageBodyName, packageBody in self._packageBodies.items():
+			if packageBodyName not in self._packages:
+				raise VHDLModelException(f"Package '{packageBodyName}' referenced by package body '{packageBodyName}' doesn't exist in library '{self._identifier}'.")
+
+			package = self._packages[packageBodyName]
+			package._packageBody = packageBody    # TODO: add warning if package had already a body, which is now replaced
+			packageBody._package.Package = package
+			packageBody._namespace._parentNamespace = package._namespace
+
+			# add "package body -> package" relation in dependency graph
+			dependency = packageBody._dependencyVertex.EdgeToVertex(package._dependencyVertex)
+			dependency["kind"] = DependencyGraphEdgeKind.PackageImplementation

+
+
+

+[docs]
+	def IndexPackages(self) -> None:
+		"""
+		Index declared items in all packages.
+
+		.. rubric:: Algorithm
+
+		1. Iterate all packages:
+
+		   * Index all declared items. |br|
+		     |rarr| :meth:`pyVHDLModel.DesignUnit.Package.IndexDeclaredItems`
+
+		.. seealso::
+
+		   :meth:`IndexPackageBodies`
+		     Index all declared items in a package body.
+		   :meth:`IndexEntities`
+		     Index all declared items in an entity.
+		   :meth:`IndexArchitectures`
+		     Index all declared items in an architecture.
+		"""
+		for package in self._packages.values():
+			if isinstance(package, Package):
+				package.IndexDeclaredItems()

+
+
+

+[docs]
+	def IndexPackageBodies(self) -> None:
+		"""
+		Index declared items in all package bodies.
+
+		.. rubric:: Algorithm
+
+		1. Iterate all package bodies:
+
+		   * Index all declared items. |br|
+		     |rarr| :meth:`pyVHDLModel.DesignUnit.PackageBody.IndexDeclaredItems`
+
+		.. seealso::
+
+		   :meth:`IndexPackages`
+		     Index all declared items in a package.
+		   :meth:`IndexEntities`
+		     Index all declared items in an entity.
+		   :meth:`IndexArchitectures`
+		     Index all declared items in an architecture.
+		"""
+		for packageBody in self._packageBodies.values():
+			packageBody.IndexDeclaredItems()

+
+
+

+[docs]
+	def IndexEntities(self) -> None:
+		"""
+		Index declared items in all entities.
+
+		.. rubric:: Algorithm
+
+		1. Iterate all entities:
+
+		   * Index all declared items. |br|
+		     |rarr| :meth:`pyVHDLModel.DesignUnit.Entity.IndexDeclaredItems`
+
+		.. seealso::
+
+		   :meth:`IndexPackages`
+		     Index all declared items in a package.
+		   :meth:`IndexPackageBodies`
+		     Index all declared items in a package body.
+		   :meth:`IndexArchitectures`
+		     Index all declared items in an architecture.
+		"""
+		for entity in self._entities.values():
+			entity.IndexDeclaredItems()

+
+
+

+[docs]
+	def IndexArchitectures(self) -> None:
+		"""
+		Index declared items in all architectures.
+
+		.. rubric:: Algorithm
+
+		1. Iterate all architectures:
+
+		   * Index all declared items. |br|
+		     |rarr| :meth:`pyVHDLModel.DesignUnit.Architecture.IndexDeclaredItems`
+
+		.. seealso::
+
+		   :meth:`IndexPackages`
+		     Index all declared items in a package.
+		   :meth:`IndexPackageBodies`
+		     Index all declared items in a package body.
+		   :meth:`IndexEntities`
+		     Index all declared items in an entity.
+		"""
+		for architectures in self._architectures.values():
+			for architecture in architectures.values():
+				architecture.IndexDeclaredItems()
+				architecture.IndexStatements()

+
+
+

+[docs]
+	def __repr__(self) -> str:
+		"""
+		Formats a representation of the library.
+
+		**Format:** ``Library: 'my_library'``
+
+		:returns: String representation of the library.
+		"""
+		return f"Library: '{self._identifier}'"

+
+
+	__str__ = __repr__

+
+
+
+

+[docs]
+@export
+class Document(ModelEntity, DocumentedEntityMixin):
+	"""A ``Document`` represents a sourcefile. It contains *primary* and *secondary* design units."""
+
+	_path:                   Path                                #: path to the document. ``None`` if virtual document.
+	_designUnits:            List[DesignUnit]                    #: List of all design units defined in a document.
+	_contexts:               Dict[str, Context]                  #: Dictionary of all contexts defined in a document.
+	_configurations:         Dict[str, Configuration]            #: Dictionary of all configurations defined in a document.
+	_entities:               Dict[str, Entity]                   #: Dictionary of all entities defined in a document.
+	_architectures:          Dict[str, Dict[str, Architecture]]  #: Dictionary of all architectures defined in a document.
+	_packages:               Dict[str, Package]                  #: Dictionary of all packages defined in a document.
+	_packageBodies:          Dict[str, PackageBody]              #: Dictionary of all package bodies defined in a document.
+	_verificationUnits:      Dict[str, VerificationUnit]         #: Dictionary of all PSL verification units defined in a document.
+	_verificationProperties: Dict[str, VerificationProperty]     #: Dictionary of all PSL verification properties defined in a document.
+	_verificationModes:      Dict[str, VerificationMode]         #: Dictionary of all PSL verification modes defined in a document.
+
+	_dependencyVertex:       Vertex[None, None, None, 'Document', None, None, None, None, None, None, None, None, None, None, None, None, None]  #: Reference to the vertex in the dependency graph representing the document. |br| This reference is set by :meth:`~pyVHDLModel.Design.CreateCompileOrderGraph`.
+	_compileOrderVertex:     Vertex[None, None, None, 'Document', None, None, None, None, None, None, None, None, None, None, None, None, None]  #: Reference to the vertex in the compile-order graph representing the document. |br| This reference is set by :meth:`~pyVHDLModel.Design.CreateCompileOrderGraph`.
+
+

+[docs]
+	def __init__(self, path: Path, documentation: Nullable[str] = None, parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+		DocumentedEntityMixin.__init__(self, documentation)
+
+		self._path =                   path
+		self._designUnits =            []
+		self._contexts =               {}
+		self._configurations =         {}
+		self._entities =               {}
+		self._architectures =          {}
+		self._packages =               {}
+		self._packageBodies =          {}
+		self._verificationUnits =      {}
+		self._verificationProperties = {}
+		self._verificationModes =      {}
+
+		self._dependencyVertex =   None
+		self._compileOrderVertex = None

+
+
+

+[docs]
+	def _AddEntity(self, item: Entity) -> None:
+		"""
+		Add an entity to the document's lists of design units.
+
+		:param item:                Entity object to be added to the document.
+		:raises TypeError:          If parameter 'item' is not of type :class:`~pyVHDLModel.DesignUnits.Entity`.
+		:raises VHDLModelException: If entity name already exists in document.
+		"""
+		if not isinstance(item, Entity):
+			ex = TypeError(f"Parameter 'item' is not of type 'Entity'.")
+			if version_info >= (3, 11):  # pragma: no cover
+				ex.add_note(f"Got type '{getFullyQualifiedName(item)}'.")
+			raise ex
+
+		identifier = item._normalizedIdentifier
+		if identifier in self._entities:
+			# TODO: use a more specific exception
+			raise VHDLModelException(f"An entity '{item._identifier}' already exists in this document.")
+
+		self._entities[identifier] = item
+		self._designUnits.append(item)
+		item._document = self

+
+
+

+[docs]
+	def _AddArchitecture(self, item: Architecture) -> None:
+		"""
+		Add an architecture to the document's lists of design units.
+
+		:param item:                Architecture object to be added to the document.
+		:raises TypeError:          If parameter 'item' is not of type :class:`~pyVHDLModel.DesignUnits.Architecture`.
+		:raises VHDLModelException: If architecture name already exists for the referenced entity name in document.
+		"""
+		if not isinstance(item, Architecture):
+			ex = TypeError(f"Parameter 'item' is not of type 'Architecture'.")
+			if version_info >= (3, 11):  # pragma: no cover
+				ex.add_note(f"Got type '{getFullyQualifiedName(item)}'.")
+			raise ex
+
+		entity = item._entity.Name
+		entityIdentifier = entity._normalizedIdentifier
+		try:
+			architectures = self._architectures[entityIdentifier]
+			if item._normalizedIdentifier in architectures:
+				# TODO: use a more specific exception
+				# FIXME: this is allowed and should be a warning or a strict mode.
+				raise VHDLModelException(f"An architecture '{item._identifier}' for entity '{entity._identifier}' already exists in this document.")
+
+			architectures[item.Identifier] = item
+		except KeyError:
+			self._architectures[entityIdentifier] = {item._identifier: item}
+
+		self._designUnits.append(item)
+		item._document = self

+
+
+

+[docs]
+	def _AddPackage(self, item: Package) -> None:
+		"""
+		Add a package to the document's lists of design units.
+
+		:param item:                Package object to be added to the document.
+		:raises TypeError:          If parameter 'item' is not of type :class:`~pyVHDLModel.DesignUnits.Package`.
+		:raises VHDLModelException: If package name already exists in document.
+		"""
+		if not isinstance(item, (Package, PackageInstantiation)):
+			ex = TypeError(f"Parameter 'item' is not of type 'Package' or 'PackageInstantiation'.")
+			if version_info >= (3, 11):  # pragma: no cover
+				ex.add_note(f"Got type '{getFullyQualifiedName(item)}'.")
+			raise ex
+
+		identifier = item._normalizedIdentifier
+		if identifier in self._packages:
+			# TODO: use a more specific exception
+			raise VHDLModelException(f"A package '{item._identifier}' already exists in this document.")
+
+		self._packages[identifier] = item
+		self._designUnits.append(item)
+		item._document = self

+
+
+

+[docs]
+	def _AddPackageBody(self, item: PackageBody) -> None:
+		"""
+		Add a package body to the document's lists of design units.
+
+		:param item:                Package body object to be added to the document.
+		:raises TypeError:          If parameter 'item' is not of type :class:`~pyVHDLModel.DesignUnits.PackageBody`.
+		:raises VHDLModelException: If package body name already exists in document.
+		"""
+		if not isinstance(item, PackageBody):
+			ex = TypeError(f"Parameter 'item' is not of type 'PackageBody'.")
+			if version_info >= (3, 11):  # pragma: no cover
+				ex.add_note(f"Got type '{getFullyQualifiedName(item)}'.")
+			raise ex
+
+		identifier = item._normalizedIdentifier
+		if identifier in self._packageBodies:
+			# TODO: use a more specific exception
+			raise VHDLModelException(f"A package body '{item._identifier}' already exists in this document.")
+
+		self._packageBodies[identifier] = item
+		self._designUnits.append(item)
+		item._document = self

+
+
+

+[docs]
+	def _AddContext(self, item: Context) -> None:
+		"""
+		Add a context to the document's lists of design units.
+
+		:param item:                Context object to be added to the document.
+		:raises TypeError:          If parameter 'item' is not of type :class:`~pyVHDLModel.DesignUnits.Context`.
+		:raises VHDLModelException: If context name already exists in document.
+		"""
+		if not isinstance(item, Context):
+			ex = TypeError(f"Parameter 'item' is not of type 'Context'.")
+			if version_info >= (3, 11):  # pragma: no cover
+				ex.add_note(f"Got type '{getFullyQualifiedName(item)}'.")
+			raise ex
+
+		identifier = item._normalizedIdentifier
+		if identifier in self._contexts:
+			# TODO: use a more specific exception
+			raise VHDLModelException(f"A context '{item._identifier}' already exists in this document.")
+
+		self._contexts[identifier] = item
+		self._designUnits.append(item)
+		item._document = self

+
+
+

+[docs]
+	def _AddConfiguration(self, item: Configuration) -> None:
+		"""
+		Add a configuration to the document's lists of design units.
+
+		:param item:                Configuration object to be added to the document.
+		:raises TypeError:          If parameter 'item' is not of type :class:`~pyVHDLModel.DesignUnits.Configuration`.
+		:raises VHDLModelException: If configuration name already exists in document.
+		"""
+		if not isinstance(item, Configuration):
+			ex = TypeError(f"Parameter 'item' is not of type 'Configuration'.")
+			if version_info >= (3, 11):  # pragma: no cover
+				ex.add_note(f"Got type '{getFullyQualifiedName(item)}'.")
+			raise ex
+
+		identifier = item._normalizedIdentifier
+		if identifier in self._configurations:
+			# TODO: use a more specific exception
+			raise VHDLModelException(f"A configuration '{item._identifier}' already exists in this document.")
+
+		self._configurations[identifier] = item
+		self._designUnits.append(item)
+		item._document = self

+
+
+	def _AddVerificationUnit(self, item: VerificationUnit) -> None:
+		if not isinstance(item, VerificationUnit):
+			ex = TypeError(f"Parameter 'item' is not of type 'VerificationUnit'.")
+			if version_info >= (3, 11):  # pragma: no cover
+				ex.add_note(f"Got type '{getFullyQualifiedName(item)}'.")
+			raise ex
+
+		identifier = item._normalizedIdentifier
+		if identifier in self._verificationUnits:
+			raise ValueError(f"A verification unit '{item._identifier}' already exists in this document.")
+
+		self._verificationUnits[identifier] = item
+		self._designUnits.append(item)
+		item._document = self
+
+	def _AddVerificationProperty(self, item: VerificationProperty) -> None:
+		if not isinstance(item, VerificationProperty):
+			ex = TypeError(f"Parameter 'item' is not of type 'VerificationProperty'.")
+			if version_info >= (3, 11):  # pragma: no cover
+				ex.add_note(f"Got type '{getFullyQualifiedName(item)}'.")
+			raise ex
+
+		identifier = item.NormalizedIdentifier
+		if identifier in self._verificationProperties:
+			raise ValueError(f"A verification property '{item.Identifier}' already exists in this document.")
+
+		self._verificationProperties[identifier] = item
+		self._designUnits.append(item)
+		item._document = self
+
+	def _AddVerificationMode(self, item: VerificationMode) -> None:
+		if not isinstance(item, VerificationMode):
+			ex = TypeError(f"Parameter 'item' is not of type 'VerificationMode'.")
+			if version_info >= (3, 11):  # pragma: no cover
+				ex.add_note(f"Got type '{getFullyQualifiedName(item)}'.")
+			raise ex
+
+		identifier = item.NormalizedIdentifier
+		if identifier in self._verificationModes:
+			raise ValueError(f"A verification mode '{item.Identifier}' already exists in this document.")
+
+		self._verificationModes[identifier] = item
+		self._designUnits.append(item)
+		item._document = self
+
+

+[docs]
+	def _AddDesignUnit(self, item: DesignUnit) -> None:
+		"""
+		Add a design unit to the document's lists of design units.
+
+		:param item:                Configuration object to be added to the document.
+		:raises TypeError:          If parameter 'item' is not of type :class:`~pyVHDLModel.DesignUnits.DesignUnit`.
+		:raises ValueError:         If parameter 'item' is an unknown :class:`~pyVHDLModel.DesignUnits.DesignUnit`.
+		:raises VHDLModelException: If configuration name already exists in document.
+		"""
+		if not isinstance(item, DesignUnit):
+			ex = TypeError(f"Parameter 'item' is not of type 'DesignUnit'.")
+			if version_info >= (3, 11):  # pragma: no cover
+				ex.add_note(f"Got type '{getFullyQualifiedName(item)}'.")
+			raise ex
+
+		if isinstance(item, Entity):
+			self._AddEntity(item)
+		elif isinstance(item, Architecture):
+			self._AddArchitecture(item)
+		elif isinstance(item, Package):
+			self._AddPackage(item)
+		elif isinstance(item, PackageBody):
+			self._AddPackageBody(item)
+		elif isinstance(item, Context):
+			self._AddContext(item)
+		elif isinstance(item, Configuration):
+			self._AddConfiguration(item)
+		elif isinstance(item, VerificationUnit):
+			self._AddVerificationUnit(item)
+		elif isinstance(item, VerificationProperty):
+			self._AddVerificationProperty(item)
+		elif isinstance(item, VerificationMode):
+			self._AddVerificationMode(item)
+		else:
+			ex = ValueError(f"Parameter 'item' is an unknown 'DesignUnit'.")
+			if version_info >= (3, 11):  # pragma: no cover
+				ex.add_note(f"Got type '{getFullyQualifiedName(item)}'.")
+			raise ex

+
+
+	@readonly
+	def Path(self) -> Path:
+		"""
+		Read-only property to access the document's path (:attr:`_path`).
+
+		:returns: The path of this document.
+		"""
+		return self._path
+
+	@readonly
+	def DesignUnits(self) -> List[DesignUnit]:
+		"""
+		Read-only property to access a list of all design units declarations found in this document (:attr:`_designUnits`).
+
+		:returns: List of all design units.
+		"""
+		return self._designUnits
+
+	@readonly
+	def Contexts(self) -> Dict[str, Context]:
+		"""
+		Read-only property to access a list of all context declarations found in this document (:attr:`_contexts`).
+
+		:returns: List of all contexts.
+		"""
+		return self._contexts
+
+	@readonly
+	def Configurations(self) -> Dict[str, Configuration]:
+		"""
+		Read-only property to access a list of all configuration declarations found in this document (:attr:`_configurations`).
+
+		:returns: List of all configurations.
+		"""
+		return self._configurations
+
+	@readonly
+	def Entities(self) -> Dict[str, Entity]:
+		"""
+		Read-only property to access a list of all entity declarations found in this document (:attr:`_entities`).
+
+		:returns: List of all entities.
+		"""
+		return self._entities
+
+	@readonly
+	def Architectures(self) -> Dict[str, Dict[str, Architecture]]:
+		"""
+		Read-only property to access a list of all architecture declarations found in this document (:attr:`_architectures`).
+
+		:returns: List of all architectures.
+		"""
+		return self._architectures
+
+	@readonly
+	def Packages(self) -> Dict[str, Package]:
+		"""
+		Read-only property to access a list of all package declarations found in this document (:attr:`_packages`).
+
+		:returns: List of all packages.
+		"""
+		return self._packages
+
+	@readonly
+	def PackageBodies(self) -> Dict[str, PackageBody]:
+		"""
+		Read-only property to access a list of all package body declarations found in this document (:attr:`_packageBodies`).
+
+		:returns: List of all package bodies.
+		"""
+		return self._packageBodies
+
+	@readonly
+	def VerificationUnits(self) -> Dict[str, VerificationUnit]:
+		"""
+		Read-only property to access a list of all verification unit declarations found in this document (:attr:`_verificationUnits`).
+
+		:returns: List of all verification units.
+		"""
+		return self._verificationUnits
+
+	@readonly
+	def VerificationProperties(self) -> Dict[str, VerificationProperty]:
+		"""
+		Read-only property to access a list of all verification properties declarations found in this document (:attr:`_verificationProperties`).
+
+		:returns: List of all verification properties.
+		"""
+		return self._verificationProperties
+
+	@readonly
+	def VerificationModes(self) -> Dict[str, VerificationMode]:
+		"""
+		Read-only property to access a list of all verification modes declarations found in this document (:attr:`_verificationModes`).
+
+		:returns: List of all verification modes.
+		"""
+		return self._verificationModes
+
+	@readonly
+	def CompileOrderVertex(self) -> Vertex[None, None, None, 'Document', None, None, None, None, None, None, None, None, None, None, None, None, None]:
+		"""
+		Read-only property to access the corresponding compile-order vertex (:attr:`_compileOrderVertex`).
+
+		The compile-order vertex references this document by its value field.
+
+		:returns: The corresponding compile-order vertex.
+		"""
+		return self._compileOrderVertex
+
+

+[docs]
+	def IterateDesignUnits(self, filter: DesignUnitKind = DesignUnitKind.All) -> Generator[DesignUnit, None, None]:
+		"""
+		Iterate all design units in the document.
+
+		A union of :class:`DesignUnitKind` values can be given to filter the returned result for suitable design units.
+
+		.. rubric:: Algorithm
+
+		* If contexts are selected in the filter:
+
+		  1. Iterate all contexts in that library.
+
+		* If packages are selected in the filter:
+
+		  1. Iterate all packages in that library.
+
+		* If package bodies are selected in the filter:
+
+		  1. Iterate all package bodies in that library.
+
+		* If entites are selected in the filter:
+
+		  1. Iterate all entites in that library.
+
+		* If architectures are selected in the filter:
+
+		  1. Iterate all architectures in that library.
+
+		* If configurations are selected in the filter:
+
+		  1. Iterate all configurations in that library.
+
+		:param filter: An enumeration with possibly multiple flags to filter the returned design units.
+		:returns:      A generator to iterate all matched design units in the document.
+
+		.. seealso::
+
+		   :meth:`pyVHDLModel.Design.IterateDesignUnits`
+		     Iterate all design units in the design.
+		   :meth:`pyVHDLModel.Library.IterateDesignUnits`
+		     Iterate all design units in the library.
+		"""
+		if DesignUnitKind.Context in filter:
+			for context in self._contexts.values():
+				yield context
+
+		if DesignUnitKind.Package in filter:
+			for package in self._packages.values():
+				yield package
+
+		if DesignUnitKind.PackageBody in filter:
+			for packageBody in self._packageBodies.values():
+				yield packageBody
+
+		if DesignUnitKind.Entity in filter:
+			for entity in self._entities.values():
+				yield entity
+
+		if DesignUnitKind.Architecture in filter:
+			for architectures in self._architectures.values():
+				for architecture in architectures.values():
+					yield architecture
+
+		if DesignUnitKind.Configuration in filter:
+			for configuration in self._configurations.values():
+				yield configuration

+
+
+		# for verificationProperty in self._verificationUnits.values():
+		# 	yield verificationProperty
+		# for verificationUnit in self._verificationProperties.values():
+		# 	yield entity
+		# for verificationMode in self._verificationModes.values():
+		# 	yield verificationMode
+
+

+[docs]
+	def __repr__(self) -> str:
+		"""
+		Formats a representation of the document.
+
+		**Format:** ``Document: 'path/to/file.vhdl'``
+
+		:returns: String representation of the document.
+		"""
+		return f"Document: '{self._path}'"

+
+
+	__str__ = __repr__

+
+
+ +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/_modules/pyVHDLModel/Association.html b/_modules/pyVHDLModel/Association.html new file mode 100644 index 000000000..5afac2c97 --- /dev/null +++ b/_modules/pyVHDLModel/Association.html @@ -0,0 +1,276 @@ + + + + + + pyVHDLModel.Association — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +

Source code for pyVHDLModel.Association

+# ==================================================================================================================== #
+#             __     ___   _ ____  _     __  __           _      _                                                     #
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |                                                    #
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |                                                    #
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |                                                    #
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|                                                    #
+#  |_|    |___/                                                                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""
+This module contains parts of an abstract document language model for VHDL.
+
+Associations are used in generic maps, port maps and parameter maps.
+"""
+from typing               import Optional as Nullable, Union
+
+from pyTooling.Decorators import export, readonly
+
+from pyVHDLModel.Base       import ModelEntity
+from pyVHDLModel.Symbol     import Symbol
+from pyVHDLModel.Expression import BaseExpression, QualifiedExpression, FunctionCall, TypeConversion, Literal
+
+
+ExpressionUnion = Union[
+	BaseExpression,
+	QualifiedExpression,
+	FunctionCall,
+	TypeConversion,
+	# ConstantOrSymbol,     TODO: ObjectSymbol
+	Literal,
+]
+
+
+

+[docs]
+@export
+class AssociationItem(ModelEntity):
+	"""
+	A base-class for all association items.
+	"""
+
+	_formal: Nullable[Symbol]
+	_actual: ExpressionUnion
+
+

+[docs]
+	def __init__(self, actual: ExpressionUnion, formal: Nullable[Symbol] = None) -> None:
+		super().__init__()
+
+		self._formal = formal
+		if formal is not None:
+			formal._parent = self
+
+		self._actual = actual

+
+		# actual._parent = self  # FIXME: actual is provided as None
+
+	@readonly
+	def Formal(self) -> Nullable[Symbol]:  # TODO: can also be a conversion function !!
+		return self._formal
+
+	@readonly
+	def Actual(self) -> ExpressionUnion:
+		return self._actual
+
+

+[docs]
+	def __str__(self) -> str:
+		if self._formal is None:
+			return str(self._actual)
+		else:
+			return f"{self._formal!s} => {self._actual!s}"

+

+
+
+
+

+[docs]
+@export
+class GenericAssociationItem(AssociationItem):
+	"""
+	A base-class for all generic association items used in generic map aspects.
+	"""

+
+
+
+

+[docs]
+@export
+class PortAssociationItem(AssociationItem):
+	"""
+	A base-class for all port association items used in port map aspects.
+	"""

+
+
+
+

+[docs]
+@export
+class ParameterAssociationItem(AssociationItem):
+	"""
+	A base-class for all parameter association items used in parameter map aspects.
+	"""

+
+
+ +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/_modules/pyVHDLModel/Base.html b/_modules/pyVHDLModel/Base.html new file mode 100644 index 000000000..f7e0b4102 --- /dev/null +++ b/_modules/pyVHDLModel/Base.html @@ -0,0 +1,704 @@ + + + + + + pyVHDLModel.Base — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +

Source code for pyVHDLModel.Base

+# ==================================================================================================================== #
+#             __     ___   _ ____  _     __  __           _      _                                                     #
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |                                                    #
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |                                                    #
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |                                                    #
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|                                                    #
+#  |_|    |___/                                                                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""
+This module contains parts of an abstract document language model for VHDL.
+
+Base-classes for the VHDL language model.
+"""
+from enum                  import unique, Enum
+from typing                import Type, Tuple, Iterable, Optional as Nullable, Union, cast
+
+from pyTooling.Decorators  import export, readonly
+from pyTooling.MetaClasses import ExtendedType
+
+
+__all__ = ["ExpressionUnion"]
+
+
+ExpressionUnion = Union[
+	'BaseExpression',
+	'QualifiedExpression',
+	'FunctionCall',
+	'TypeConversion',
+	# ConstantOrSymbol,     TODO: ObjectSymbol
+	'Literal',
+]
+
+
+

+[docs]
+@export
+@unique
+class Direction(Enum):
+	"""An enumeration representing a direction in a range	(``to`` or ``downto``)."""
+
+	To =      0  #: Ascending direction
+	DownTo =  1  #: Descending direction
+
+

+[docs]
+	def __str__(self) -> str:
+		"""
+		Formats the direction to ``to`` or ``downto``.
+
+		:returns: Formatted direction.
+		"""
+		return ("to", "downto")[cast(int, self.value)]       # TODO: check performance

+

+
+
+
+

+[docs]
+@export
+@unique
+class Mode(Enum):
+	"""
+	A ``Mode`` is an enumeration. It represents the direction of data exchange (``in``, ``out``, ...) for objects in
+	generic, port or parameter lists.
+
+	In case no *mode* is defined, ``Default`` is used, so the *mode* is inferred from context.
+	"""
+
+	Default = 0  #: Mode not defined, thus it's context dependent.
+	In =      1  #: Input
+	Out =     2  #: Output
+	InOut =   3  #: Bi-directional
+	Buffer =  4  #: Buffered output
+	Linkage = 5  #: undocumented
+
+

+[docs]
+	def __str__(self) -> str:
+		"""
+		Formats the direction.
+
+		:returns: Formatted direction.
+		"""
+		return ("", "in", "out", "inout", "buffer", "linkage")[cast(int, self.value)]       # TODO: check performance

+

+
+
+
+

+[docs]
+@export
+class ModelEntity(metaclass=ExtendedType, slots=True):
+	"""
+	``ModelEntity`` is the base-class for all classes in the VHDL language model, except for mixin classes (see multiple
+	inheritance) and enumerations.
+
+	Each entity in this model has a reference to its parent entity. Therefore, a protected variable :attr:`_parent` is
+	available and a readonly property :attr:`Parent`.
+	"""
+
+	_parent: 'ModelEntity'      #: Reference to a parent entity in the logical model hierarchy.
+
+

+[docs]
+	def __init__(self, parent: Nullable["ModelEntity"] = None) -> None:
+		"""
+		Initializes a VHDL model entity.
+
+		:param parent: The parent model entity of this entity.
+		"""
+		self._parent = parent

+
+
+	@readonly
+	def Parent(self) -> 'ModelEntity':
+		"""
+		Read-only property to access the model entity's parent element reference in a logical hierarchy (:attr:`_parent`).
+
+		:returns: Reference to the parent entity.
+		"""
+		return self._parent
+
+	def GetAncestor(self, type: Type) -> 'ModelEntity':
+		parent = self._parent
+		while not isinstance(parent, type):
+			parent = parent._parent
+
+		return parent

+
+
+
+

+[docs]
+@export
+class NamedEntityMixin(metaclass=ExtendedType, mixin=True):
+	"""
+	A ``NamedEntityMixin`` is a mixin class for all VHDL entities that have identifiers.
+
+	Protected variables :attr:`_identifier` and :attr:`_normalizedIdentifier` are available to derived classes as well as
+	two readonly properties :attr:`Identifier` and :attr:`NormalizedIdentifier` for public access.
+	"""
+
+	_identifier: str            #: The identifier of a model entity.
+	_normalizedIdentifier: str  #: The normalized (lower case) identifier of a model entity.
+
+

+[docs]
+	def __init__(self, identifier: str) -> None:
+		"""
+		Initializes a named entity.
+
+		:param identifier: Identifier (name) of the model entity.
+		"""
+		self._identifier = identifier
+		self._normalizedIdentifier = identifier.lower()

+
+
+	@readonly
+	def Identifier(self) -> str:
+		"""
+		Returns a model entity's identifier (name).
+
+		:returns: Name of a model entity.
+		"""
+		return self._identifier
+
+	@readonly
+	def NormalizedIdentifier(self) -> str:
+		"""
+		Returns a model entity's normalized identifier (lower case name).
+
+		:returns: Normalized name of a model entity.
+		"""
+		return self._normalizedIdentifier

+
+
+
+

+[docs]
+@export
+class MultipleNamedEntityMixin(metaclass=ExtendedType, mixin=True):
+	"""
+	A ``MultipleNamedEntityMixin`` is a mixin class for all VHDL entities that declare multiple instances at once by
+	defining multiple identifiers.
+
+	Protected variables :attr:`_identifiers` and :attr:`_normalizedIdentifiers` are available to derived classes as well
+	as two readonly properties :attr:`Identifiers` and :attr:`NormalizedIdentifiers` for public access.
+	"""
+
+	_identifiers:           Tuple[str]  #: A list of identifiers.
+	_normalizedIdentifiers: Tuple[str]  #: A list of normalized (lower case) identifiers.
+
+

+[docs]
+	def __init__(self, identifiers: Iterable[str]) -> None:
+		"""
+		Initializes a multiple-named entity.
+
+		:param identifiers: Sequence of identifiers (names) of the model entity.
+		"""
+		self._identifiers = tuple(identifiers)
+		self._normalizedIdentifiers = tuple([identifier.lower() for identifier in identifiers])

+
+
+	@readonly
+	def Identifiers(self) -> Tuple[str]:
+		"""
+		Returns a model entity's tuple of identifiers (names).
+
+		:returns: Tuple of identifiers.
+		"""
+		return self._identifiers
+
+	@readonly
+	def NormalizedIdentifiers(self) -> Tuple[str]:
+		"""
+		Returns a model entity's tuple of normalized identifiers (lower case names).
+
+		:returns: Tuple of normalized identifiers.
+		"""
+		return self._normalizedIdentifiers

+
+
+
+

+[docs]
+@export
+class LabeledEntityMixin(metaclass=ExtendedType, mixin=True):
+	"""
+	A ``LabeledEntityMixin`` is a mixin class for all VHDL entities that can have labels.
+
+	protected variables :attr:`_label` and :attr:`_normalizedLabel` are available to derived classes as well as two
+	readonly properties :attr:`Label` and :attr:`NormalizedLabel` for public access.
+	"""
+	_label:           Nullable[str]  #: The label of a model entity.
+	_normalizedLabel: Nullable[str]  #: The normalized (lower case) label of a model entity.
+
+

+[docs]
+	def __init__(self, label: Nullable[str]) -> None:
+		"""
+		Initializes a labeled entity.
+
+		:param label: Label of the model entity.
+		"""
+		self._label = label
+		self._normalizedLabel = label.lower() if label is not None else None

+
+
+	@readonly
+	def Label(self) -> Nullable[str]:
+		"""
+		Returns a model entity's label.
+
+		:returns: Label of a model entity.
+		"""
+		return self._label
+
+	@readonly
+	def NormalizedLabel(self) -> Nullable[str]:
+		"""
+		Returns a model entity's normalized (lower case) label.
+
+		:returns: Normalized label of a model entity.
+		"""
+		return self._normalizedLabel

+
+
+
+

+[docs]
+@export
+class DocumentedEntityMixin(metaclass=ExtendedType, mixin=True):
+	"""
+	A ``DocumentedEntityMixin`` is a mixin class for all VHDL entities that can have an associated documentation.
+
+	A protected variable :attr:`_documentation` is available to derived classes as well as a readonly property
+	:attr:`Documentation` for public access.
+	"""
+
+	_documentation: Nullable[str]  #: The associated documentation of a model entity.
+
+

+[docs]
+	def __init__(self, documentation: Nullable[str]) -> None:
+		"""
+		Initializes a documented entity.
+
+		:param documentation: Documentation of a model entity.
+		"""
+		self._documentation = documentation

+
+
+	@readonly
+	def Documentation(self) -> Nullable[str]:
+		"""
+		Returns a model entity's associated documentation.
+
+		:returns: Associated documentation of a model entity.
+		"""
+		return self._documentation

+
+
+
+

+[docs]
+@export
+class ConditionalMixin(metaclass=ExtendedType, mixin=True):
+	"""A ``ConditionalMixin`` is a mixin-class for all statements with a condition."""
+
+	_condition: ExpressionUnion
+
+

+[docs]
+	def __init__(self, condition: Nullable[ExpressionUnion] = None) -> None:
+		"""
+		Initializes a statement with a condition.
+
+		When the condition is not None, the condition's parent reference is set to this statement.
+
+		:param condition: The expression representing the condition.
+		"""
+		self._condition = condition
+		if condition is not None:
+			condition._parent = self

+
+
+	@readonly
+	def Condition(self) -> ExpressionUnion:
+		"""
+		Read-only property to access the condition of a statement (:attr:`_condition`).
+
+		:returns: The expression representing the condition of a statement.
+		"""
+		return self._condition

+
+
+
+

+[docs]
+@export
+class BranchMixin(metaclass=ExtendedType, mixin=True):
+	"""A ``BranchMixin`` is a mixin-class for all statements with branches."""
+
+

+[docs]
+	def __init__(self) -> None:
+		pass

+

+
+
+
+

+[docs]
+@export
+class ConditionalBranchMixin(BranchMixin, ConditionalMixin, mixin=True):
+	"""A ``BaseBranch`` is a mixin-class for all branch statements with a condition."""
+

+[docs]
+	def __init__(self, condition: ExpressionUnion) -> None:
+		super().__init__()
+		ConditionalMixin.__init__(self, condition)

+

+
+
+
+

+[docs]
+@export
+class IfBranchMixin(ConditionalBranchMixin, mixin=True):
+	"""A ``BaseIfBranch`` is a mixin-class for all if-branches."""

+
+
+
+

+[docs]
+@export
+class ElsifBranchMixin(ConditionalBranchMixin, mixin=True):
+	"""A ``BaseElsifBranch`` is a mixin-class for all elsif-branches."""

+
+
+
+

+[docs]
+@export
+class ElseBranchMixin(BranchMixin, mixin=True):
+	"""A ``BaseElseBranch`` is a mixin-class for all else-branches."""

+
+
+
+

+[docs]
+@export
+class ReportStatementMixin(metaclass=ExtendedType, mixin=True):
+	"""A ``MixinReportStatement`` is a mixin-class for all report and assert statements."""
+
+	_message:  Nullable[ExpressionUnion]
+	_severity: Nullable[ExpressionUnion]
+
+

+[docs]
+	def __init__(self, message: Nullable[ExpressionUnion] = None, severity: Nullable[ExpressionUnion] = None) -> None:
+		self._message = message
+		if message is not None:
+			message._parent = self
+
+		self._severity = severity
+		if severity is not None:
+			severity._parent = self

+
+
+	@property
+	def Message(self) -> Nullable[ExpressionUnion]:
+		return self._message
+
+	@property
+	def Severity(self) -> Nullable[ExpressionUnion]:
+		return self._severity

+
+
+
+

+[docs]
+@export
+class AssertStatementMixin(ReportStatementMixin, ConditionalMixin, mixin=True):
+	"""A ``MixinAssertStatement`` is a mixin-class for all assert statements."""
+
+

+[docs]
+	def __init__(self, condition: ExpressionUnion, message: Nullable[ExpressionUnion] = None, severity: Nullable[ExpressionUnion] = None) -> None:
+		super().__init__(message, severity)
+		ConditionalMixin.__init__(self, condition)

+

+
+
+
+class BlockStatementMixin(metaclass=ExtendedType, mixin=True):
+	"""A ``BlockStatement`` is a mixin-class for all block statements."""
+
+	def __init__(self) -> None:
+		pass
+
+
+

+[docs]
+@export
+class BaseChoice(ModelEntity):
+	"""A ``Choice`` is a base-class for all choices."""

+
+
+
+

+[docs]
+@export
+class BaseCase(ModelEntity):
+	"""
+	A ``Case`` is a base-class for all cases.
+	"""

+
+
+
+

+[docs]
+@export
+class Range(ModelEntity):
+	_leftBound:  ExpressionUnion
+	_rightBound: ExpressionUnion
+	_direction:  Direction
+
+

+[docs]
+	def __init__(self, leftBound: ExpressionUnion, rightBound: ExpressionUnion, direction: Direction, parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+
+		self._leftBound = leftBound
+		leftBound._parent = self
+
+		self._rightBound = rightBound
+		rightBound._parent = self
+
+		self._direction = direction

+
+
+	@property
+	def LeftBound(self) -> ExpressionUnion:
+		return self._leftBound
+
+	@property
+	def RightBound(self) -> ExpressionUnion:
+		return self._rightBound
+
+	@property
+	def Direction(self) -> Direction:
+		return self._direction
+
+

+[docs]
+	def __str__(self) -> str:
+		return f"{self._leftBound!s} {self._direction!s} {self._rightBound!s}"

+

+
+
+
+

+[docs]
+@export
+class WaveformElement(ModelEntity):
+	_expression: ExpressionUnion
+	_after: ExpressionUnion
+
+

+[docs]
+	def __init__(self, expression: ExpressionUnion, after: Nullable[ExpressionUnion] = None, parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+
+		self._expression = expression
+		expression._parent = self
+
+		self._after = after
+		if after is not None:
+			after._parent = self

+
+
+	@property
+	def Expression(self) -> ExpressionUnion:
+		return self._expression
+
+	@property
+	def After(self) -> Expression:
+		return self._after

+
+
+ +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/_modules/pyVHDLModel/Common.html b/_modules/pyVHDLModel/Common.html new file mode 100644 index 000000000..bf3ae7575 --- /dev/null +++ b/_modules/pyVHDLModel/Common.html @@ -0,0 +1,305 @@ + + + + + + pyVHDLModel.Common — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +

Source code for pyVHDLModel.Common

+# ==================================================================================================================== #
+#             __     ___   _ ____  _     __  __           _      _                                                     #
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |                                                    #
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |                                                    #
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |                                                    #
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|                                                    #
+#  |_|    |___/                                                                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""
+This module contains parts of an abstract document language model for VHDL.
+
+Common definitions and Mixins are used by many classes in the model as base-classes.
+"""
+from typing                  import List, Iterable, Union, Optional as Nullable
+
+from pyTooling.Decorators    import export, readonly
+from pyTooling.MetaClasses   import ExtendedType
+
+from pyVHDLModel.Base        import ModelEntity, LabeledEntityMixin
+from pyVHDLModel.Expression  import BaseExpression, QualifiedExpression, FunctionCall, TypeConversion, Literal
+from pyVHDLModel.Symbol      import Symbol
+from pyVHDLModel.Association import ParameterAssociationItem
+
+
+ExpressionUnion = Union[
+	BaseExpression,
+	QualifiedExpression,
+	FunctionCall,
+	TypeConversion,
+	# ConstantOrSymbol,     TODO: ObjectSymbol
+	Literal,
+]
+
+
+

+[docs]
+@export
+class Statement(ModelEntity, LabeledEntityMixin):
+	"""
+	A ``Statement`` is a base-class for all statements.
+	"""
+

+[docs]
+	def __init__(self, label: Nullable[str] = None, parent=None) -> None:
+		super().__init__(parent)
+		LabeledEntityMixin.__init__(self, label)

+

+
+
+
+

+[docs]
+@export
+class ProcedureCallMixin(metaclass=ExtendedType, mixin=True):
+	_procedure:         Symbol  # TODO: implement a ProcedureSymbol
+	_parameterMappings: List[ParameterAssociationItem]
+
+

+[docs]
+	def __init__(self, procedureName: Symbol, parameterMappings: Nullable[Iterable[ParameterAssociationItem]] = None) -> None:
+		self._procedure = procedureName
+		procedureName._parent = self
+
+		# TODO: extract to mixin
+		self._parameterMappings = []
+		if parameterMappings is not None:
+			for parameterMapping in parameterMappings:
+				self._parameterMappings.append(parameterMapping)
+				parameterMapping._parent = self

+
+
+	@readonly
+	def Procedure(self) -> Symbol:
+		return self._procedure
+
+	@property
+	def ParameterMappings(self) -> List[ParameterAssociationItem]:
+		return self._parameterMappings

+
+
+
+

+[docs]
+@export
+class AssignmentMixin(metaclass=ExtendedType, mixin=True):
+	"""A mixin-class for all assignment statements."""
+
+	_target: Symbol
+
+

+[docs]
+	def __init__(self, target: Symbol) -> None:
+		self._target = target
+		target._parent = self

+
+
+	@property
+	def Target(self) -> Symbol:
+		return self._target

+
+
+
+

+[docs]
+@export
+class SignalAssignmentMixin(AssignmentMixin, mixin=True):
+	"""A mixin-class for all signal assignment statements."""

+
+
+
+

+[docs]
+@export
+class VariableAssignmentMixin(AssignmentMixin, mixin=True):
+	"""A mixin-class for all variable assignment statements."""
+
+	# FIXME: move to sequential?
+	_expression: ExpressionUnion
+
+

+[docs]
+	def __init__(self, target: Symbol, expression: ExpressionUnion) -> None:
+		super().__init__(target)
+
+		self._expression = expression
+		expression._parent = self

+
+
+	@property
+	def Expression(self) -> ExpressionUnion:
+		return self._expression

+
+
+ +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/_modules/pyVHDLModel/Concurrent.html b/_modules/pyVHDLModel/Concurrent.html new file mode 100644 index 000000000..14473c546 --- /dev/null +++ b/_modules/pyVHDLModel/Concurrent.html @@ -0,0 +1,1198 @@ + + + + + + pyVHDLModel.Concurrent — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +

Source code for pyVHDLModel.Concurrent

+# ==================================================================================================================== #
+#             __     ___   _ ____  _     __  __           _      _                                                     #
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |                                                    #
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |                                                    #
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |                                                    #
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|                                                    #
+#  |_|    |___/                                                                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""
+This module contains parts of an abstract document language model for VHDL.
+
+Concurrent defines all concurrent statements used in entities, architectures, generates and block statements.
+"""
+from typing                  import List, Dict, Union, Iterable, Generator, Optional as Nullable
+
+from pyTooling.Decorators    import export, readonly
+from pyTooling.MetaClasses   import ExtendedType
+
+from pyVHDLModel.Base        import ModelEntity, LabeledEntityMixin, DocumentedEntityMixin, Range, BaseChoice, BaseCase, IfBranchMixin
+from pyVHDLModel.Base        import ElsifBranchMixin, ElseBranchMixin, AssertStatementMixin, BlockStatementMixin, WaveformElement
+from pyVHDLModel.Regions     import ConcurrentDeclarationRegionMixin
+from pyVHDLModel.Namespace   import Namespace
+from pyVHDLModel.Name        import Name
+from pyVHDLModel.Symbol      import ComponentInstantiationSymbol, EntityInstantiationSymbol, ArchitectureSymbol, ConfigurationInstantiationSymbol
+from pyVHDLModel.Expression  import BaseExpression, QualifiedExpression, FunctionCall, TypeConversion, Literal
+from pyVHDLModel.Association import AssociationItem, ParameterAssociationItem
+from pyVHDLModel.Interface   import PortInterfaceItemMixin
+from pyVHDLModel.Common      import Statement, ProcedureCallMixin, SignalAssignmentMixin
+from pyVHDLModel.Sequential  import SequentialStatement, SequentialStatementsMixin, SequentialDeclarationsMixin
+
+
+ExpressionUnion = Union[
+	BaseExpression,
+	QualifiedExpression,
+	FunctionCall,
+	TypeConversion,
+	# ConstantOrSymbol,     TODO: ObjectSymbol
+	Literal,
+]
+
+
+

+[docs]
+@export
+class ConcurrentStatement(Statement):
+	"""A base-class for all concurrent statements."""

+
+
+
+

+[docs]
+@export
+class ConcurrentStatementsMixin(metaclass=ExtendedType, mixin=True):
+	"""
+	A mixin-class for all language constructs supporting concurrent statements.
+
+	.. seealso::
+
+	   .. todo:: concurrent declaration region
+	"""
+
+	_statements:     List[ConcurrentStatement]
+
+	_instantiations: Dict[str, 'Instantiation']  # TODO: add another instantiation class level for entity/configuration/component inst.
+	_blocks:         Dict[str, 'ConcurrentBlockStatement']
+	_generates:      Dict[str, 'GenerateStatement']
+	_hierarchy:      Dict[str, Union['ConcurrentBlockStatement', 'GenerateStatement']]
+
+

+[docs]
+	def __init__(self, statements: Nullable[Iterable[ConcurrentStatement]] = None) -> None:
+		self._statements = []
+
+		self._instantiations = {}
+		self._blocks = {}
+		self._generates = {}
+		self._hierarchy = {}
+
+		if statements is not None:
+			for statement in statements:
+				self._statements.append(statement)
+				statement._parent = self

+
+
+	@readonly
+	def Statements(self) -> List[ConcurrentStatement]:
+		return self._statements
+
+	def IterateInstantiations(self) -> Generator['Instantiation', None, None]:
+		for instance in self._instantiations.values():
+			yield instance
+
+		for block in self._blocks.values():
+			yield from block.IterateInstantiations()
+
+		for generate in self._generates.values():
+			yield from generate.IterateInstantiations()
+
+	# TODO: move into _init__
+	def IndexStatements(self) -> None:
+		for statement in self._statements:
+			if isinstance(statement, (EntityInstantiation, ComponentInstantiation, ConfigurationInstantiation)):
+				self._instantiations[statement.NormalizedLabel] = statement
+			elif isinstance(statement, (ForGenerateStatement, IfGenerateStatement, CaseGenerateStatement)):
+				self._generates[statement.NormalizedLabel] = statement
+				statement.IndexStatement()
+			elif isinstance(statement, ConcurrentBlockStatement):
+				self._hierarchy[statement.NormalizedLabel] = statement
+				statement.IndexStatements()

+
+
+
+

+[docs]
+@export
+class Instantiation(ConcurrentStatement):
+	"""
+	A base-class for all (component) instantiations.
+	"""
+
+	_genericAssociations: List[AssociationItem]
+	_portAssociations: List[AssociationItem]
+
+

+[docs]
+	def __init__(
+		self,
+		label: str,
+		genericAssociations: Nullable[Iterable[AssociationItem]] = None,
+		portAssociations: Nullable[Iterable[AssociationItem]] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(label, parent)
+
+		# TODO: extract to mixin
+		self._genericAssociations = []
+		if genericAssociations is not None:
+			for association in genericAssociations:
+				self._genericAssociations.append(association)
+				association._parent = self
+
+		# TODO: extract to mixin
+		self._portAssociations = []
+		if portAssociations is not None:
+			for association in portAssociations:
+				self._portAssociations.append(association)
+				association._parent = self

+
+
+	@readonly
+	def GenericAssociations(self) -> List[AssociationItem]:
+		return self._genericAssociations
+
+	@property
+	def PortAssociations(self) -> List[AssociationItem]:
+		return self._portAssociations

+
+
+
+

+[docs]
+@export
+class ComponentInstantiation(Instantiation):
+	"""
+	Represents a component instantiation by referring to a component name.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      inst : component Counter;
+	"""
+
+	_component: ComponentInstantiationSymbol
+
+

+[docs]
+	def __init__(
+		self,
+		label: str,
+		componentSymbol: ComponentInstantiationSymbol,
+		genericAssociations: Nullable[Iterable[AssociationItem]] = None,
+		portAssociations: Nullable[Iterable[AssociationItem]] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(label, genericAssociations, portAssociations, parent)
+
+		self._component = componentSymbol
+		componentSymbol._parent = self

+
+
+	@property
+	def Component(self) -> ComponentInstantiationSymbol:
+		return self._component

+
+
+
+

+[docs]
+@export
+class EntityInstantiation(Instantiation):
+	"""
+	Represents an entity instantiation by referring to an entity name with optional architecture name.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      inst : entity work. Counter;
+	"""
+
+	_entity: EntityInstantiationSymbol
+	_architecture: ArchitectureSymbol
+
+

+[docs]
+	def __init__(
+		self,
+		label: str,
+		entitySymbol: EntityInstantiationSymbol,
+		architectureSymbol: Nullable[ArchitectureSymbol] = None,
+		genericAssociations: Nullable[Iterable[AssociationItem]] = None,
+		portAssociations: Nullable[Iterable[AssociationItem]] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(label, genericAssociations, portAssociations, parent)
+
+		self._entity = entitySymbol
+		entitySymbol._parent = self
+
+		self._architecture = architectureSymbol
+		if architectureSymbol is not None:
+			architectureSymbol._parent = self

+
+
+	@property
+	def Entity(self) -> EntityInstantiationSymbol:
+		return self._entity
+
+	@property
+	def Architecture(self) -> ArchitectureSymbol:
+		return self._architecture

+
+
+
+

+[docs]
+@export
+class ConfigurationInstantiation(Instantiation):
+	"""
+	Represents a configuration instantiation by referring to a configuration name.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      inst : configuration Counter;
+	"""
+
+	_configuration: ConfigurationInstantiationSymbol
+
+

+[docs]
+	def __init__(
+		self,
+		label: str,
+		configurationSymbol: ConfigurationInstantiationSymbol,
+		genericAssociations: Nullable[Iterable[AssociationItem]] = None,
+		portAssociations: Nullable[Iterable[AssociationItem]] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(label, genericAssociations, portAssociations, parent)
+
+		self._configuration = configurationSymbol
+		configurationSymbol._parent = self

+
+
+	@property
+	def Configuration(self) -> ConfigurationInstantiationSymbol:
+		return self._configuration

+
+
+
+

+[docs]
+@export
+class ProcessStatement(ConcurrentStatement, SequentialDeclarationsMixin, SequentialStatementsMixin, DocumentedEntityMixin):
+	"""
+	Represents a process statement with sensitivity list, sequential declaration region and sequential statements.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      proc: process(Clock)
+	        -- sequential declarations
+	      begin
+	        -- sequential statements
+	      end process;
+	"""
+
+	_sensitivityList: List[Name]  # TODO: implement a SignalSymbol
+
+

+[docs]
+	def __init__(
+		self,
+		label: Nullable[str] = None,
+		declaredItems: Nullable[Iterable] = None,
+		statements: Nullable[Iterable[SequentialStatement]] = None,
+		sensitivityList: Nullable[Iterable[Name]] = None,
+		documentation: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(label, parent)
+		SequentialDeclarationsMixin.__init__(self, declaredItems)
+		SequentialStatementsMixin.__init__(self, statements)
+		DocumentedEntityMixin.__init__(self, documentation)
+
+		if sensitivityList is None:
+			self._sensitivityList = None
+		else:
+			self._sensitivityList = []  # TODO: convert to dict
+			for signalSymbol in sensitivityList:
+				self._sensitivityList.append(signalSymbol)

+
+				# signalSymbol._parent = self  # FIXME: currently str are provided
+
+	@property
+	def SensitivityList(self) -> List[Name]:
+		return self._sensitivityList

+
+
+
+

+[docs]
+@export
+class ConcurrentProcedureCall(ConcurrentStatement, ProcedureCallMixin):
+

+[docs]
+	def __init__(
+		self,
+		label: str,
+		procedureName: Name,
+		parameterMappings: Nullable[Iterable[ParameterAssociationItem]] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(label, parent)
+		ProcedureCallMixin.__init__(self, procedureName, parameterMappings)

+

+
+
+
+

+[docs]
+@export
+class ConcurrentBlockStatement(ConcurrentStatement, BlockStatementMixin, LabeledEntityMixin, ConcurrentDeclarationRegionMixin, ConcurrentStatementsMixin, DocumentedEntityMixin):
+	_portItems:     List[PortInterfaceItemMixin]
+
+

+[docs]
+	def __init__(
+		self,
+		label: str,
+		portItems: Nullable[Iterable[PortInterfaceItemMixin]] = None,
+		declaredItems: Nullable[Iterable] = None,
+		statements: Iterable['ConcurrentStatement'] = None,
+		documentation: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(label, parent)
+		BlockStatementMixin.__init__(self)
+		LabeledEntityMixin.__init__(self, label)
+		ConcurrentDeclarationRegionMixin.__init__(self, declaredItems)
+		ConcurrentStatementsMixin.__init__(self, statements)
+		DocumentedEntityMixin.__init__(self, documentation)
+
+		# TODO: extract to mixin
+		self._portItems = []
+		if portItems is not None:
+			for item in portItems:
+				self._portItems.append(item)
+				item._parent = self

+
+
+	@property
+	def PortItems(self) -> List[PortInterfaceItemMixin]:
+		return self._portItems

+
+
+
+

+[docs]
+@export
+class GenerateBranch(ModelEntity, ConcurrentDeclarationRegionMixin, ConcurrentStatementsMixin):
+	"""
+	A base-class for all branches in a generate statements.
+
+	.. seealso::
+
+	   * :class:`If-generate branch <pyVHDLModel.Concurrent.IfGenerateBranch>`
+	   * :class:`Elsif-generate branch <pyVHDLModel.Concurrent.ElsifGenerateBranch>`
+	   * :class:`Else-generate branch <pyVHDLModel.Concurrent.ElseGenerateBranch>`
+	"""
+
+	_alternativeLabel:           Nullable[str]
+	_normalizedAlternativeLabel: Nullable[str]
+
+	_namespace:                  Namespace
+
+

+[docs]
+	def __init__(
+		self,
+		declaredItems: Nullable[Iterable] = None,
+		statements: Nullable[Iterable[ConcurrentStatement]] = None,
+		alternativeLabel: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(parent)
+		ConcurrentDeclarationRegionMixin.__init__(self, declaredItems)
+		ConcurrentStatementsMixin.__init__(self, statements)
+
+		self._alternativeLabel = alternativeLabel
+		self._normalizedAlternativeLabel = alternativeLabel.lower() if alternativeLabel is not None else None
+
+		self._namespace = Namespace(self._normalizedAlternativeLabel)

+
+
+	@property
+	def AlternativeLabel(self) -> Nullable[str]:
+		return self._alternativeLabel
+
+	@property
+	def NormalizedAlternativeLabel(self) -> Nullable[str]:
+		return self._normalizedAlternativeLabel

+
+
+
+

+[docs]
+@export
+class IfGenerateBranch(GenerateBranch, IfBranchMixin):
+	"""
+	Represents if-generate branch in a generate statement with a concurrent declaration region and concurrent statements.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      gen: if condition generate
+	        -- concurrent declarations
+	      begin
+	        -- concurrent statements
+	      elsif condition generate
+	        -- ...
+	      else generate
+	        -- ...
+	      end generate;
+	"""
+
+

+[docs]
+	def __init__(
+		self,
+		condition: ExpressionUnion,
+		declaredItems: Nullable[Iterable] = None,
+		statements: Nullable[Iterable[ConcurrentStatement]] = None,
+		alternativeLabel: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(declaredItems, statements, alternativeLabel, parent)
+		IfBranchMixin.__init__(self, condition)

+

+
+
+
+

+[docs]
+@export
+class ElsifGenerateBranch(GenerateBranch, ElsifBranchMixin):
+	"""
+	Represents elsif-generate branch in a generate statement with a concurrent declaration region and concurrent statements.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      gen: if condition generate
+	        -- ...
+	      elsif condition generate
+	        -- concurrent declarations
+	      begin
+	        -- concurrent statements
+	      else generate
+	        -- ...
+	      end generate;
+	"""
+
+

+[docs]
+	def __init__(
+		self,
+		condition: ExpressionUnion,
+		declaredItems: Nullable[Iterable] = None,
+		statements: Nullable[Iterable[ConcurrentStatement]] = None,
+		alternativeLabel: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(declaredItems, statements, alternativeLabel, parent)
+		ElsifBranchMixin.__init__(self, condition)

+

+
+
+
+

+[docs]
+@export
+class ElseGenerateBranch(GenerateBranch, ElseBranchMixin):
+	"""
+	Represents else-generate branch in a generate statement with a concurrent declaration region and concurrent statements.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      gen: if condition generate
+	        -- ...
+	      elsif condition generate
+	        -- ...
+	      else generate
+	        -- concurrent declarations
+	      begin
+	        -- concurrent statements
+	      end generate;
+	"""
+
+

+[docs]
+	def __init__(
+		self,
+		declaredItems: Nullable[Iterable] = None,
+		statements: Nullable[Iterable[ConcurrentStatement]] = None,
+		alternativeLabel: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(declaredItems, statements, alternativeLabel, parent)
+		ElseBranchMixin.__init__(self)

+

+
+
+
+

+[docs]
+@export
+class GenerateStatement(ConcurrentStatement):
+	"""
+	A base-class for all generate statements.
+
+	.. seealso::
+
+	   * :class:`If...generate statement <pyVHDLModel.Concurrent.IfGenerateStatement>`
+	   * :class:`Case...generate statement <pyVHDLModel.Concurrent.CaseGenerateStatement>`
+	   * :class:`For...generate statement <pyVHDLModel.Concurrent.ForGenerateStatement>`
+	"""
+
+	_namespace: Namespace
+
+

+[docs]
+	def __init__(
+		self,
+		label: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(label, parent)
+
+		self._namespace = Namespace(self._normalizedLabel)

+
+
+	# @mustoverride
+	def IterateInstantiations(self) -> Generator[Instantiation, None, None]:
+		raise NotImplementedError()
+
+	# @mustoverride
+	def IndexStatement(self) -> None:
+		raise NotImplementedError()

+
+
+
+

+[docs]
+@export
+class IfGenerateStatement(GenerateStatement):
+	"""
+	Represents an if...generate statement.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      gen: if condition generate
+	        -- ...
+	      elsif condition generate
+	        -- ...
+	      else generate
+	        -- ...
+	      end generate;
+
+	.. seealso::
+
+	   * :class:`Generate branch <pyVHDLModel.Concurrent.GenerateBranch>` base-class
+	   * :class:`If-generate branch <pyVHDLModel.Concurrent.IfGenerateBranch>`
+	   * :class:`Elsif-generate branch <pyVHDLModel.Concurrent.ElsifGenerateBranch>`
+	   * :class:`Else-generate branch <pyVHDLModel.Concurrent.ElseGenerateBranch>`
+	"""
+
+	_ifBranch:      IfGenerateBranch
+	_elsifBranches: List[ElsifGenerateBranch]
+	_elseBranch:    Nullable[ElseGenerateBranch]
+
+

+[docs]
+	def __init__(
+		self,
+		label: str,
+		ifBranch: IfGenerateBranch,
+		elsifBranches: Nullable[Iterable[ElsifGenerateBranch]] = None,
+		elseBranch: Nullable[ElseGenerateBranch] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(label, parent)
+
+		self._ifBranch = ifBranch
+		ifBranch._parent = self
+
+		self._elsifBranches = []
+		if elsifBranches is not None:
+			for branch in elsifBranches:
+				self._elsifBranches.append(branch)
+				branch._parent = self
+
+		if elseBranch is not None:
+			self._elseBranch = elseBranch
+			elseBranch._parent = self
+		else:
+			self._elseBranch = None

+
+
+	@property
+	def IfBranch(self) -> IfGenerateBranch:
+		return self._ifBranch
+
+	@property
+	def ElsifBranches(self) -> List[ElsifGenerateBranch]:
+		return self._elsifBranches
+
+	@property
+	def ElseBranch(self) -> Nullable[ElseGenerateBranch]:
+		return self._elseBranch
+
+	def IterateInstantiations(self) -> Generator[Instantiation, None, None]:
+		yield from self._ifBranch.IterateInstantiations()
+		for branch in self._elsifBranches:
+			yield from branch.IterateInstantiations()
+		if self._elseBranch is not None:
+			yield from self._ifBranch.IterateInstantiations()
+
+	def IndexStatement(self) -> None:
+		self._ifBranch.IndexStatements()
+		for branch in self._elsifBranches:
+			branch.IndexStatements()
+		if self._elseBranch is not None:
+			self._elseBranch.IndexStatements()

+
+
+
+

+[docs]
+@export
+class ConcurrentChoice(BaseChoice):
+	"""A base-class for all concurrent choices (in case...generate statements)."""

+
+
+
+

+[docs]
+@export
+class IndexedGenerateChoice(ConcurrentChoice):
+	_expression: ExpressionUnion
+
+

+[docs]
+	def __init__(self, expression: ExpressionUnion, parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+
+		self._expression = expression
+		expression._parent = self

+
+
+	@property
+	def Expression(self) -> ExpressionUnion:
+		return self._expression
+
+

+[docs]
+	def __str__(self) -> str:
+		return str(self._expression)

+

+
+
+
+

+[docs]
+@export
+class RangedGenerateChoice(ConcurrentChoice):
+	_range: 'Range'
+
+

+[docs]
+	def __init__(self, rng: 'Range', parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+
+		self._range = rng
+		rng._parent = self

+
+
+	@property
+	def Range(self) -> 'Range':
+		return self._range
+
+

+[docs]
+	def __str__(self) -> str:
+		return str(self._range)

+

+
+
+
+

+[docs]
+@export
+class ConcurrentCase(BaseCase, LabeledEntityMixin, ConcurrentDeclarationRegionMixin, ConcurrentStatementsMixin):
+

+[docs]
+	def __init__(
+		self,
+		declaredItems: Nullable[Iterable] = None,
+		statements: Nullable[Iterable[ConcurrentStatement]] = None,
+		alternativeLabel: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(parent)
+		LabeledEntityMixin.__init__(self, alternativeLabel)
+		ConcurrentDeclarationRegionMixin.__init__(self, declaredItems)
+		ConcurrentStatementsMixin.__init__(self, statements)

+

+
+
+
+

+[docs]
+@export
+class GenerateCase(ConcurrentCase):
+	_choices: List[ConcurrentChoice]
+
+

+[docs]
+	def __init__(
+		self,
+		choices: Iterable[ConcurrentChoice],
+		declaredItems: Nullable[Iterable] = None,
+		statements: Nullable[Iterable[ConcurrentStatement]] = None,
+		alternativeLabel: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(declaredItems, statements, alternativeLabel, parent)
+
+		# TODO: move to parent or grandparent
+		self._choices = []
+		if choices is not None:
+			for choice in choices:
+				self._choices.append(choice)
+				choice._parent = self

+
+
+	# TODO: move to parent or grandparent
+	@property
+	def Choices(self) -> List[ConcurrentChoice]:
+		return self._choices
+
+

+[docs]
+	def __str__(self) -> str:
+		return "when {choices} =>".format(choices=" | ".join(str(c) for c in self._choices))

+

+
+
+
+

+[docs]
+@export
+class OthersGenerateCase(ConcurrentCase):
+

+[docs]
+	def __str__(self) -> str:
+		return "when others =>"

+

+
+
+
+

+[docs]
+@export
+class CaseGenerateStatement(GenerateStatement):
+	"""
+	Represents a case...generate statement.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      gen: case selector generate
+	        case choice1 =>
+	          -- ...
+	        case choice2 =>
+	          -- ...
+	        case others =>
+	          -- ...
+	      end generate;
+	"""
+
+	_expression: ExpressionUnion
+	_cases:      List[GenerateCase]
+
+

+[docs]
+	def __init__(
+		self,
+		label: str,
+		expression: ExpressionUnion,
+		cases: Iterable[ConcurrentCase],
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(label, parent)
+
+		self._expression = expression
+		expression._parent = self
+
+		# TODO: create a mixin for things with cases
+		self._cases = []
+		if cases is not None:
+			for case in cases:
+				self._cases.append(case)
+				case._parent = self

+
+
+	@property
+	def SelectExpression(self) -> ExpressionUnion:
+		return self._expression
+
+	@property
+	def Cases(self) -> List[GenerateCase]:
+		return self._cases
+
+	def IterateInstantiations(self) -> Generator[Instantiation, None, None]:
+		for case in self._cases:
+			yield from case.IterateInstantiations()
+
+	def IndexStatement(self) -> None:
+		for case in self._cases:
+			case.IndexStatements()

+
+
+
+

+[docs]
+@export
+class ForGenerateStatement(GenerateStatement, ConcurrentDeclarationRegionMixin, ConcurrentStatementsMixin):
+	"""
+	Represents a for...generate statement.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      gen: for i in 0 to 3 generate
+	        -- ...
+	      end generate;
+	"""
+
+	_loopIndex: str
+	_range:     Range
+
+

+[docs]
+	def __init__(
+		self,
+		label: str,
+		loopIndex: str,
+		rng: Range,
+		declaredItems: Nullable[Iterable] = None,
+		statements: Nullable[Iterable[ConcurrentStatement]] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(label, parent)
+		ConcurrentDeclarationRegionMixin.__init__(self, declaredItems)
+		ConcurrentStatementsMixin.__init__(self, statements)
+
+		self._loopIndex = loopIndex
+
+		self._range = rng
+		rng._parent = self

+
+
+	@property
+	def LoopIndex(self) -> str:
+		return self._loopIndex
+
+	@property
+	def Range(self) -> Range:
+		return self._range
+
+	# IndexDeclaredItems = ConcurrentStatements.IndexDeclaredItems
+
+	def IndexStatement(self) -> None:
+		self.IndexStatements()
+
+	def IndexStatements(self) -> None:
+		super().IndexStatements()
+
+	def IterateInstantiations(self) -> Generator[Instantiation, None, None]:
+		return ConcurrentStatementsMixin.IterateInstantiations(self)

+
+
+
+

+[docs]
+@export
+class ConcurrentSignalAssignment(ConcurrentStatement, SignalAssignmentMixin):
+	"""
+	A base-class for concurrent signal assignments.
+
+	.. seealso::
+
+	   * :class:`~pyVHDLModel.Concurrent.ConcurrentSimpleSignalAssignment`
+	   * :class:`~pyVHDLModel.Concurrent.ConcurrentSelectedSignalAssignment`
+	   * :class:`~pyVHDLModel.Concurrent.ConcurrentConditionalSignalAssignment`
+	"""
+

+[docs]
+	def __init__(self, label: str, target: Name, parent: ModelEntity = None) -> None:
+		super().__init__(label, parent)
+		SignalAssignmentMixin.__init__(self, target)

+

+
+
+
+

+[docs]
+@export
+class ConcurrentSimpleSignalAssignment(ConcurrentSignalAssignment):
+	_waveform: List[WaveformElement]
+
+

+[docs]
+	def __init__(self, label: str, target: Name, waveform: Iterable[WaveformElement], parent: ModelEntity = None) -> None:
+		super().__init__(label, target, parent)
+
+		# TODO: extract to mixin
+		self._waveform = []
+		if waveform is not None:
+			for waveformElement in waveform:
+				self._waveform.append(waveformElement)
+				waveformElement._parent = self

+
+
+	@property
+	def Waveform(self) -> List[WaveformElement]:
+		return self._waveform

+
+
+
+

+[docs]
+@export
+class ConcurrentSelectedSignalAssignment(ConcurrentSignalAssignment):
+

+[docs]
+	def __init__(self, label: str, target: Name, expression: ExpressionUnion, parent: ModelEntity = None) -> None:
+		super().__init__(label, target, parent)

+

+
+
+
+

+[docs]
+@export
+class ConcurrentConditionalSignalAssignment(ConcurrentSignalAssignment):
+

+[docs]
+	def __init__(self, label: str, target: Name, expression: ExpressionUnion, parent: ModelEntity = None) -> None:
+		super().__init__(label, target, parent)

+

+
+
+
+

+[docs]
+@export
+class ConcurrentAssertStatement(ConcurrentStatement, AssertStatementMixin):
+

+[docs]
+	def __init__(
+		self,
+		condition: ExpressionUnion,
+		message: ExpressionUnion,
+		severity: Nullable[ExpressionUnion] = None,
+		label: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(label, parent)
+		AssertStatementMixin.__init__(self, condition, message, severity)

+

+
+
+ +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/_modules/pyVHDLModel/Declaration.html b/_modules/pyVHDLModel/Declaration.html new file mode 100644 index 000000000..94388a5f8 --- /dev/null +++ b/_modules/pyVHDLModel/Declaration.html @@ -0,0 +1,361 @@ + + + + + + pyVHDLModel.Declaration — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +

Source code for pyVHDLModel.Declaration

+# ==================================================================================================================== #
+#             __     ___   _ ____  _     __  __           _      _                                                     #
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |                                                    #
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |                                                    #
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |                                                    #
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|                                                    #
+#  |_|    |___/                                                                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""
+This module contains parts of an abstract document language model for VHDL.
+
+
+"""
+from enum                   import unique, Enum
+from typing                 import List, Iterable, Union, Optional as Nullable
+
+from pyTooling.Decorators   import export, readonly
+
+from pyVHDLModel.Base       import ModelEntity, NamedEntityMixin, DocumentedEntityMixin
+from pyVHDLModel.Expression import BaseExpression, QualifiedExpression, FunctionCall, TypeConversion, Literal
+from pyVHDLModel.Name       import Name
+from pyVHDLModel.Symbol     import Symbol
+
+
+
+ExpressionUnion = Union[
+	BaseExpression,
+	QualifiedExpression,
+	FunctionCall,
+	TypeConversion,
+	# ConstantOrSymbol,     TODO: ObjectSymbol
+	Literal,
+]
+
+
+

+[docs]
+@export
+@unique
+class EntityClass(Enum):
+	"""An ``EntityClass`` is an enumeration. It represents a VHDL language entity class (``entity``, ``label``, ...)."""
+
+	Entity =        0   #: Entity
+	Architecture =  1   #: Architecture
+	Configuration = 2   #: Configuration
+	Procedure =     3   #: Procedure
+	Function =      4   #: Function
+	Package =       5   #: Package
+	Type =          6   #: Type
+	Subtype =       7   #: Subtype
+	Constant =      8   #: Constant
+	Signal =        9   #: Signal
+	Variable =      10  #: Variable
+	Component =     11  #: Component
+	Label =         12  #: Label
+	Literal =       13  #: Literal
+	Units =         14  #: Units
+	Group =         15  #: Group
+	File =          16  #: File
+	Property =      17  #: Property
+	Sequence =      18  #: Sequence
+	View =          19  #: View
+	Others =        20  #: Others

+
+
+
+

+[docs]
+@export
+class Attribute(ModelEntity, NamedEntityMixin, DocumentedEntityMixin):
+	"""
+	Represents an attribute declaration.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      attribute TotalBits : natural;
+	"""
+
+	_subtype: Symbol
+
+

+[docs]
+	def __init__(
+		self,
+		identifier: str,
+		subtype: Symbol,
+		documentation: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(parent)
+		NamedEntityMixin.__init__(self, identifier)
+		DocumentedEntityMixin.__init__(self, documentation)
+
+		self._subtype = subtype
+		subtype._parent = self

+
+
+	@readonly
+	def Subtype(self) -> None:
+		return self._subtype

+
+
+
+

+[docs]
+@export
+class AttributeSpecification(ModelEntity, DocumentedEntityMixin):
+	"""
+	Represents an attribute specification.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      attribute TotalBits of BusType : subtype is 32;
+	"""
+
+	_identifiers: List[Name]
+	_attribute: Name
+	_entityClass: EntityClass
+	_expression: ExpressionUnion
+
+

+[docs]
+	def __init__(
+		self,
+		identifiers: Iterable[Name],
+		attribute: Name,
+		entityClass: EntityClass,
+		expression: ExpressionUnion,
+		documentation: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(parent)
+		DocumentedEntityMixin.__init__(self, documentation)
+
+		self._identifiers = []  # TODO: convert to dict
+		for identifier in identifiers:
+			self._identifiers.append(identifier)
+			identifier._parent = self
+
+		self._attribute = attribute
+		attribute._parent = self
+
+		self._entityClass = entityClass
+
+		self._expression = expression
+		expression._parent = self

+
+
+	@readonly
+	def Identifiers(self) -> List[Name]:
+		return self._identifiers
+
+	@readonly
+	def Attribute(self) -> Name:
+		return self._attribute
+
+	@readonly
+	def EntityClass(self) -> EntityClass:
+		return self._entityClass
+
+	@readonly
+	def Expression(self) -> ExpressionUnion:
+		return self._expression

+
+
+
+# TODO: move somewhere else
+

+[docs]
+@export
+class Alias(ModelEntity, NamedEntityMixin, DocumentedEntityMixin):
+

+[docs]
+	def __init__(self, identifier: str, documentation: Nullable[str] = None, parent: ModelEntity = None) -> None:
+		"""
+		Initializes underlying ``BaseType``.
+
+		:param identifier: Name of the type.
+		"""
+		super().__init__(parent)
+		NamedEntityMixin.__init__(self, identifier)
+		DocumentedEntityMixin.__init__(self, documentation)

+

+
+
+ +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/_modules/pyVHDLModel/DesignUnit.html b/_modules/pyVHDLModel/DesignUnit.html new file mode 100644 index 000000000..7e9791d5a --- /dev/null +++ b/_modules/pyVHDLModel/DesignUnit.html @@ -0,0 +1,1036 @@ + + + + + + pyVHDLModel.DesignUnit — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +

Source code for pyVHDLModel.DesignUnit

+# ==================================================================================================================== #
+#             __     ___   _ ____  _     __  __           _      _                                                     #
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |                                                    #
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |                                                    #
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |                                                    #
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|                                                    #
+#  |_|    |___/                                                                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""
+This module contains parts of an abstract document language model for VHDL.
+
+Design units are contexts, entities, architectures, packages and their bodies as well as configurations.
+"""
+from typing import List, Dict, Union, Iterable, Optional as Nullable
+
+from pyTooling.Decorators   import export, readonly
+from pyTooling.MetaClasses  import ExtendedType
+from pyTooling.Graph        import Vertex
+
+from pyVHDLModel.Exception  import VHDLModelException
+from pyVHDLModel.Base       import ModelEntity, NamedEntityMixin, DocumentedEntityMixin
+from pyVHDLModel.Namespace  import Namespace
+from pyVHDLModel.Regions    import ConcurrentDeclarationRegionMixin
+from pyVHDLModel.Symbol     import Symbol, PackageSymbol, EntitySymbol, LibraryReferenceSymbol
+from pyVHDLModel.Interface  import GenericInterfaceItemMixin, PortInterfaceItemMixin
+from pyVHDLModel.Object     import DeferredConstant
+from pyVHDLModel.Concurrent import ConcurrentStatement, ConcurrentStatementsMixin
+
+
+

+[docs]
+@export
+class Reference(ModelEntity):
+	"""
+	A base-class for all references.
+
+	.. seealso::
+
+	   * :class:`~pyVHDLModel.DesignUnit.LibraryClause`
+	   * :class:`~pyVHDLModel.DesignUnit.UseClause`
+	   * :class:`~pyVHDLModel.DesignUnit.ContextReference`
+	"""
+
+	_symbols:       List[Symbol]
+
+

+[docs]
+	def __init__(self, symbols: Iterable[Symbol], parent: ModelEntity = None) -> None:
+		"""
+		Initializes a reference by taking a list of symbols and a parent reference.
+
+		:param symbols: A list of symbols this reference references to.
+		:param parent:  Reference to the logical parent in the model hierarchy.
+		"""
+		super().__init__(parent)
+
+		self._symbols = [s for s in symbols]

+
+
+	@readonly
+	def Symbols(self) -> List[Symbol]:
+		"""
+		Read-only property to access the symbols this reference references to (:attr:`_symbols`).
+
+		:returns: A list of symbols.
+		"""
+		return self._symbols

+
+
+
+

+[docs]
+@export
+class LibraryClause(Reference):
+	"""
+	Represents a library clause.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      library std, ieee;
+	"""
+
+	@readonly
+	def Symbols(self) -> List[LibraryReferenceSymbol]:
+		"""
+		Read-only property to access the symbols this library clause references to (:attr:`_symbols`).
+
+		:returns: A list of library reference symbols.
+		"""
+		return self._symbols

+
+
+
+

+[docs]
+@export
+class UseClause(Reference):
+	"""
+	Represents a use clause.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      use std.text_io.all, ieee.numeric_std.all;
+	"""

+
+
+
+

+[docs]
+@export
+class ContextReference(Reference):
+	"""
+	Represents a context reference.
+
+	.. hint:: It's called *context reference* not *context clause* by the LRM.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      context ieee.ieee_std_context;
+	"""

+
+
+
+ContextUnion = Union[
+	LibraryClause,
+	UseClause,
+	ContextReference
+]
+
+
+

+[docs]
+@export
+class DesignUnitWithContextMixin(metaclass=ExtendedType, mixin=True):
+	"""
+	A mixin-class for all design units with a context.
+	"""

+
+
+
+

+[docs]
+@export
+class DesignUnit(ModelEntity, NamedEntityMixin, DocumentedEntityMixin):
+	"""
+	A base-class for all design units.
+
+	.. seealso::
+
+	   * :class:`Primary design units <pyVHDLModel.DesignUnit.PrimaryUnit>`
+
+	     * :class:`~pyVHDLModel.DesignUnit.Context`
+	     * :class:`~pyVHDLModel.DesignUnit.Entity`
+	     * :class:`~pyVHDLModel.DesignUnit.Package`
+	     * :class:`~pyVHDLModel.DesignUnit.Configuration`
+
+	   * :class:`Secondary design units <pyVHDLModel.DesignUnit.SecondaryUnit>`
+
+	     * :class:`~pyVHDLModel.DesignUnit.Architecture`
+	     * :class:`~pyVHDLModel.DesignUnit.PackageBody`
+	"""
+
+	_document: 'Document'                                  #: The VHDL library, the design unit was analyzed into.
+
+	# Either written as statements before (e.g. entity, architecture, package, ...), or as statements inside (context)
+	_contextItems:        List['ContextUnion']             #: List of all context items (library, use and context clauses).
+	_libraryReferences:   List['LibraryClause']            #: List of library clauses.
+	_packageReferences:   List['UseClause']                #: List of use clauses.
+	_contextReferences:   List['ContextReference']         #: List of context clauses.
+
+	_referencedLibraries: Dict[str, 'Library']             #: Referenced libraries based on explicit library clauses or implicit inheritance
+	_referencedPackages:  Dict[str, Dict[str, 'Package']]  #: Referenced packages based on explicit use clauses or implicit inheritance
+	_referencedContexts:  Dict[str, 'Context']             #: Referenced contexts based on explicit context references or implicit inheritance
+
+	_dependencyVertex:    Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]  #: Reference to the vertex in the dependency graph representing the design unit. |br| This reference is set by :meth:`~pyVHDLModel.Design.CreateDependencyGraph`.
+	_hierarchyVertex:     Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]  #: The vertex in the hierarchy graph
+
+	_namespace:           'Namespace'
+
+

+[docs]
+	def __init__(self, identifier: str, contextItems: Nullable[Iterable[ContextUnion]] = None, documentation: Nullable[str] = None, parent: ModelEntity = None) -> None:
+		"""
+		Initializes a design unit.
+
+		:param identifier:    Identifier (name) of the design unit.
+		:param contextItems:  A sequence of library, use or context clauses.
+		:param documentation: Associated documentation of the design unit.
+		:param parent:        Reference to the logical parent in the model hierarchy.
+		"""
+		super().__init__(parent)
+		NamedEntityMixin.__init__(self, identifier)
+		DocumentedEntityMixin.__init__(self, documentation)
+
+		self._document = None
+
+		self._contextItems = []
+		self._libraryReferences = []
+		self._packageReferences = []
+		self._contextReferences = []
+
+		if contextItems is not None:
+			for item in contextItems:
+				self._contextItems.append(item)
+				if isinstance(item, UseClause):
+					self._packageReferences.append(item)
+				elif isinstance(item, LibraryClause):
+					self._libraryReferences.append(item)
+				elif isinstance(item, ContextReference):
+					self._contextReferences.append(item)
+
+		self._referencedLibraries = {}
+		self._referencedPackages = {}
+		self._referencedContexts = {}
+
+		self._dependencyVertex = None
+		self._hierarchyVertex = None
+
+		self._namespace = Namespace(self._normalizedIdentifier)

+
+
+	@readonly
+	def Document(self) -> 'Document':
+		return self._document
+
+	@Document.setter
+	def Document(self, document: 'Document') -> None:
+		self._document = document
+
+	@property
+	def Library(self) -> 'Library':
+		return self._parent
+
+	@Library.setter
+	def Library(self, library: 'Library') -> None:
+		self._parent = library
+
+	@property
+	def ContextItems(self) -> List['ContextUnion']:
+		"""
+		Read-only property to access the sequence of all context items comprising library, use and context clauses
+		(:attr:`_contextItems`).
+
+		:returns: Sequence of context items.
+		"""
+		return self._contextItems
+
+	@property
+	def ContextReferences(self) -> List['ContextReference']:
+		"""
+		Read-only property to access the sequence of context clauses (:attr:`_contextReferences`).
+
+		:returns: Sequence of context clauses.
+		"""
+		return self._contextReferences
+
+	@property
+	def LibraryReferences(self) -> List['LibraryClause']:
+		"""
+		Read-only property to access the sequence of library clauses (:attr:`_libraryReferences`).
+
+		:returns: Sequence of library clauses.
+		"""
+		return self._libraryReferences
+
+	@property
+	def PackageReferences(self) -> List['UseClause']:
+		"""
+		Read-only property to access the sequence of use clauses (:attr:`_packageReferences`).
+
+		:returns: Sequence of use clauses.
+		"""
+		return self._packageReferences
+
+	@property
+	def ReferencedLibraries(self) -> Dict[str, 'Library']:
+		return self._referencedLibraries
+
+	@property
+	def ReferencedPackages(self) -> Dict[str, 'Package']:
+		return self._referencedPackages
+
+	@property
+	def ReferencedContexts(self) -> Dict[str, 'Context']:
+		return self._referencedContexts
+
+	@property
+	def DependencyVertex(self) -> Vertex:
+		"""
+		Read-only property to access the corresponding dependency vertex (:attr:`_dependencyVertex`).
+
+		The dependency vertex references this design unit by its value field.
+
+		:returns: The corresponding dependency vertex.
+		"""
+		return self._dependencyVertex
+
+	@property
+	def HierarchyVertex(self) -> Vertex:
+		"""
+		Read-only property to access the corresponding hierarchy vertex (:attr:`_hierarchyVertex`).
+
+		The hierarchy vertex references this design unit by its value field.
+
+		:returns: The corresponding hierarchy vertex.
+		"""
+		return self._hierarchyVertex

+
+
+
+

+[docs]
+@export
+class PrimaryUnit(DesignUnit):
+	"""
+	A base-class for all primary design units.
+
+	.. seealso::
+
+	   * :class:`~pyVHDLModel.DesignUnit.Context`
+	   * :class:`~pyVHDLModel.DesignUnit.Entity`
+	   * :class:`~pyVHDLModel.DesignUnit.Package`
+	   * :class:`~pyVHDLModel.DesignUnit.Configuration`
+	"""

+
+
+
+

+[docs]
+@export
+class SecondaryUnit(DesignUnit):
+	"""
+	A base-class for all secondary design units.
+
+	.. seealso::
+
+	   * :class:`~pyVHDLModel.DesignUnit.Architecture`
+	   * :class:`~pyVHDLModel.DesignUnit.PackageBody`
+	"""

+
+
+
+

+[docs]
+@export
+class Context(PrimaryUnit):
+	"""
+	Represents a context declaration.
+
+	A context contains a generic list of all its items (library clauses, use clauses and context references) in
+	:data:`_references`.
+
+	Furthermore, when a context gets initialized, the item kinds get separated into individual lists:
+
+	* :class:`~pyVHDLModel.DesignUnit.LibraryClause` |rarr| :data:`_libraryReferences`
+	* :class:`~pyVHDLModel.DesignUnit.UseClause` |rarr| :data:`_packageReferences`
+	* :class:`~pyVHDLModel.DesignUnit.ContextReference` |rarr| :data:`_contextReferences`
+
+	When :meth:`pyVHDLModel.Design.LinkContexts` got called, these lists were processed and the fields:
+
+	* :data:`_referencedLibraries` (:pycode:`Dict[libName, Library]`)
+	* :data:`_referencedPackages` (:pycode:`Dict[libName, [pkgName, Package]]`)
+	* :data:`_referencedContexts` (:pycode:`Dict[libName, [ctxName, Context]]`)
+
+	are populated.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      context ctx is
+	        -- ...
+	      end context;
+	"""
+
+	_references:        List[ContextUnion]
+
+

+[docs]
+	def __init__(self, identifier: str, references: Nullable[Iterable[ContextUnion]] = None, documentation: Nullable[str] = None, parent: ModelEntity = None) -> None:
+		super().__init__(identifier, None, documentation, parent)
+
+		self._references = []
+		self._libraryReferences = []
+		self._packageReferences = []
+		self._contextReferences = []
+
+		if references is not None:
+			for reference in references:
+				self._references.append(reference)
+				reference._parent = self
+
+				if isinstance(reference, LibraryClause):
+					self._libraryReferences.append(reference)
+				elif isinstance(reference, UseClause):
+					self._packageReferences.append(reference)
+				elif isinstance(reference, ContextReference):
+					self._contextReferences.append(reference)
+				else:
+					raise VHDLModelException()  # FIXME: needs exception message

+
+
+	@property
+	def LibraryReferences(self) -> List[LibraryClause]:
+		return self._libraryReferences
+
+	@property
+	def PackageReferences(self) -> List[UseClause]:
+		return self._packageReferences
+
+	@property
+	def ContextReferences(self) -> List[ContextReference]:
+		return self._contextReferences
+
+

+[docs]
+	def __str__(self) -> str:
+		lib = self._parent._identifier + "?" if self._parent is not None else ""
+
+		return f"Context: {lib}.{self._identifier}"

+

+
+
+
+

+[docs]
+@export
+class Package(PrimaryUnit, DesignUnitWithContextMixin, ConcurrentDeclarationRegionMixin):
+	"""
+	Represents a package declaration.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      package pkg is
+	        -- ...
+	      end package;
+	"""
+
+	_packageBody:       Nullable["PackageBody"]
+
+	_genericItems:      List[GenericInterfaceItemMixin]
+
+	_deferredConstants: Dict[str, DeferredConstant]
+	_components:        Dict[str, 'Component']
+
+

+[docs]
+	def __init__(
+		self,
+		identifier: str,
+		contextItems: Nullable[Iterable[ContextUnion]] = None,
+		genericItems: Nullable[Iterable[GenericInterfaceItemMixin]] = None,
+		declaredItems: Nullable[Iterable] = None,
+		documentation: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(identifier, contextItems, documentation, parent)
+		DesignUnitWithContextMixin.__init__(self)
+		ConcurrentDeclarationRegionMixin.__init__(self, declaredItems)
+
+		self._packageBody = None
+
+		# TODO: extract to mixin
+		self._genericItems = []  # TODO: convert to dict
+		if genericItems is not None:
+			for generic in genericItems:
+				self._genericItems.append(generic)
+				generic._parent = self
+
+		self._deferredConstants = {}
+		self._components = {}

+
+
+	@property
+	def PackageBody(self) -> Nullable["PackageBody"]:
+		return self._packageBody
+
+	@property
+	def GenericItems(self) -> List[GenericInterfaceItemMixin]:
+		return self._genericItems
+
+	@property
+	def DeclaredItems(self) -> List:
+		return self._declaredItems
+
+	@property
+	def DeferredConstants(self):
+		return self._deferredConstants
+
+	@property
+	def Components(self):
+		return self._components
+
+	def _IndexOtherDeclaredItem(self, item):
+		if isinstance(item, DeferredConstant):
+			for normalizedIdentifier in item.NormalizedIdentifiers:
+				self._deferredConstants[normalizedIdentifier] = item
+		elif isinstance(item, Component):
+			self._components[item.NormalizedIdentifier] = item
+		else:
+			super()._IndexOtherDeclaredItem(item)
+
+

+[docs]
+	def __str__(self) -> str:
+		lib = self._parent._identifier if self._parent is not None else "%"
+
+		return f"Package: '{lib}.{self._identifier}'"

+
+
+

+[docs]
+	def __repr__(self) -> str:
+		lib = self._parent._identifier if self._parent is not None else "%"
+
+		return f"{lib}.{self._identifier}"

+

+
+
+
+

+[docs]
+@export
+class PackageBody(SecondaryUnit, DesignUnitWithContextMixin, ConcurrentDeclarationRegionMixin):
+	"""
+	Represents a package body declaration.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      package body pkg is
+	        -- ...
+	      end package body;
+	"""
+
+	_package:       PackageSymbol
+
+

+[docs]
+	def __init__(
+		self,
+		packageSymbol: PackageSymbol,
+		contextItems: Nullable[Iterable[ContextUnion]] = None,
+		declaredItems: Nullable[Iterable] = None,
+		documentation: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(packageSymbol.Name.Identifier, contextItems, documentation, parent)
+		DesignUnitWithContextMixin.__init__(self)
+		ConcurrentDeclarationRegionMixin.__init__(self, declaredItems)
+
+		self._package = packageSymbol
+		packageSymbol._parent = self

+
+
+	@property
+	def Package(self) -> PackageSymbol:
+		return self._package
+
+	@property
+	def DeclaredItems(self) -> List:
+		return self._declaredItems
+
+	def LinkDeclaredItemsToPackage(self) -> None:
+		pass
+
+

+[docs]
+	def __str__(self) -> str:
+		lib = self._parent._identifier + "?" if self._parent is not None else ""
+
+		return f"Package Body: {lib}.{self._identifier}(body)"

+
+
+

+[docs]
+	def __repr__(self) -> str:
+		lib = self._parent._identifier + "?" if self._parent is not None else ""
+
+		return f"{lib}.{self._identifier}(body)"

+

+
+
+
+

+[docs]
+@export
+class Entity(PrimaryUnit, DesignUnitWithContextMixin, ConcurrentDeclarationRegionMixin, ConcurrentStatementsMixin):
+	"""
+	Represents an entity declaration.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      entity ent is
+	        -- ...
+	      end entity;
+	"""
+
+	_genericItems:  List[GenericInterfaceItemMixin]
+	_portItems:     List[PortInterfaceItemMixin]
+
+	_architectures: Dict[str, 'Architecture']
+
+

+[docs]
+	def __init__(
+		self,
+		identifier: str,
+		contextItems: Nullable[Iterable[ContextUnion]] = None,
+		genericItems: Nullable[Iterable[GenericInterfaceItemMixin]] = None,
+		portItems: Nullable[Iterable[PortInterfaceItemMixin]] = None,
+		declaredItems: Nullable[Iterable] = None,
+		statements: Nullable[Iterable[ConcurrentStatement]] = None,
+		documentation: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(identifier, contextItems, documentation, parent)
+		DesignUnitWithContextMixin.__init__(self)
+		ConcurrentDeclarationRegionMixin.__init__(self, declaredItems)
+		ConcurrentStatementsMixin.__init__(self, statements)
+
+		# TODO: extract to mixin
+		self._genericItems = []
+		if genericItems is not None:
+			for item in genericItems:
+				self._genericItems.append(item)
+				item._parent = self
+
+		# TODO: extract to mixin
+		self._portItems = []
+		if portItems is not None:
+			for item in portItems:
+				self._portItems.append(item)
+				item._parent = self
+
+		self._architectures = {}

+
+
+	# TODO: extract to mixin for generics
+	@property
+	def GenericItems(self) -> List[GenericInterfaceItemMixin]:
+		return self._genericItems
+
+	# TODO: extract to mixin for ports
+	@property
+	def PortItems(self) -> List[PortInterfaceItemMixin]:
+		return self._portItems
+
+	@property
+	def Architectures(self) -> Dict[str, 'Architecture']:
+		return self._architectures
+
+

+[docs]
+	def __str__(self) -> str:
+		lib = self._parent._identifier if self._parent is not None else "%"
+		archs = ', '.join(self._architectures.keys()) if self._architectures else "%"
+
+		return f"Entity: '{lib}.{self._identifier}({archs})'"

+
+
+

+[docs]
+	def __repr__(self) -> str:
+		lib = self._parent._identifier if self._parent is not None else "%"
+		archs = ', '.join(self._architectures.keys()) if self._architectures else "%"
+
+		return f"{lib}.{self._identifier}({archs})"

+

+
+
+
+

+[docs]
+@export
+class Architecture(SecondaryUnit, DesignUnitWithContextMixin, ConcurrentDeclarationRegionMixin, ConcurrentStatementsMixin):
+	"""
+	Represents an architecture declaration.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      architecture rtl of ent is
+	        -- ...
+	      begin
+	        -- ...
+	      end architecture;
+	"""
+
+	_entity: EntitySymbol
+
+

+[docs]
+	def __init__(
+		self,
+		identifier: str,
+		entity: EntitySymbol,
+		contextItems: Nullable[Iterable[Context]] = None,
+		declaredItems: Nullable[Iterable] = None,
+		statements: Iterable['ConcurrentStatement'] = None,
+		documentation: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(identifier, contextItems, documentation, parent)
+		DesignUnitWithContextMixin.__init__(self)
+		ConcurrentDeclarationRegionMixin.__init__(self, declaredItems)
+		ConcurrentStatementsMixin.__init__(self, statements)
+
+		self._entity = entity
+		entity._parent = self

+
+
+	@property
+	def Entity(self) -> EntitySymbol:
+		return self._entity
+
+

+[docs]
+	def __str__(self) -> str:
+		lib = self._parent._identifier if self._parent is not None else "%"
+		ent = self._entity._name._identifier if self._entity is not None else "%"
+
+		return f"Architecture: {lib}.{ent}({self._identifier})"

+
+
+

+[docs]
+	def __repr__(self) -> str:
+		lib = self._parent._identifier if self._parent is not None else "%"
+		ent = self._entity._name._identifier if self._entity is not None else "%"
+
+		return f"{lib}.{ent}({self._identifier})"

+

+
+
+
+

+[docs]
+@export
+class Component(ModelEntity, NamedEntityMixin, DocumentedEntityMixin):
+	"""
+	Represents a configuration declaration.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      component ent is
+	        -- ...
+	      end component;
+	"""
+
+	_genericItems:      List[GenericInterfaceItemMixin]
+	_portItems:         List[PortInterfaceItemMixin]
+
+	_entity:            Nullable[Entity]
+
+

+[docs]
+	def __init__(
+		self,
+		identifier: str,
+		genericItems: Nullable[Iterable[GenericInterfaceItemMixin]] = None,
+		portItems: Nullable[Iterable[PortInterfaceItemMixin]] = None,
+		documentation: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(parent)
+		NamedEntityMixin.__init__(self, identifier)
+		DocumentedEntityMixin.__init__(self, documentation)
+
+		# TODO: extract to mixin
+		self._genericItems = []
+		if genericItems is not None:
+			for item in genericItems:
+				self._genericItems.append(item)
+				item._parent = self
+
+		# TODO: extract to mixin
+		self._portItems = []
+		if portItems is not None:
+			for item in portItems:
+				self._portItems.append(item)
+				item._parent = self

+
+
+	@property
+	def GenericItems(self) -> List[GenericInterfaceItemMixin]:
+		return self._genericItems
+
+	@property
+	def PortItems(self) -> List[PortInterfaceItemMixin]:
+		return self._portItems
+
+	@property
+	def Entity(self) -> Nullable[Entity]:
+		return self._entity
+
+	@Entity.setter
+	def Entity(self, value: Entity) -> None:
+		self._entity = value

+
+
+
+

+[docs]
+@export
+class Configuration(PrimaryUnit, DesignUnitWithContextMixin):
+	"""
+	Represents a configuration declaration.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      configuration cfg of ent is
+	        for rtl
+	          -- ...
+	        end for;
+	      end configuration;
+	"""
+
+

+[docs]
+	def __init__(
+		self,
+		identifier: str,
+		contextItems: Nullable[Iterable[Context]] = None,
+		documentation: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(identifier, contextItems, documentation, parent)
+		DesignUnitWithContextMixin.__init__(self)

+
+
+

+[docs]
+	def __str__(self) -> str:
+		lib = self._parent._identifier if self._parent is not None else "%"
+
+		return f"Configuration: {lib}.{self._identifier}"

+
+
+

+[docs]
+	def __repr__(self) -> str:
+		lib = self._parent._identifier if self._parent is not None else "%"
+
+		return f"{lib}.{self._identifier}"

+

+
+
+ +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/_modules/pyVHDLModel/Exception.html b/_modules/pyVHDLModel/Exception.html new file mode 100644 index 000000000..405374351 --- /dev/null +++ b/_modules/pyVHDLModel/Exception.html @@ -0,0 +1,542 @@ + + + + + + pyVHDLModel.Exception — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +

Source code for pyVHDLModel.Exception

+# ==================================================================================================================== #
+#             __     ___   _ ____  _     __  __           _      _                                                     #
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |                                                    #
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |                                                    #
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |                                                    #
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|                                                    #
+#  |_|    |___/                                                                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""
+This module contains parts of an abstract document language model for VHDL.
+
+The module ``Exceptions`` contains all structured errors that are raised by pyVHDLModel. Besides a default error
+message in english, each exception object contains one or multiple references to the exception's context.
+"""
+from sys    import version_info
+from typing import List
+
+from pyTooling.Decorators import export, readonly
+
+from pyVHDLModel.Symbol import Symbol
+
+
+

+[docs]
+@export
+class VHDLModelException(Exception):
+	"""Base-class for all exceptions (errors) raised by pyVHDLModel."""
+
+	# WORKAROUND: for Python <3.11
+	# Implementing a dummy method for Python versions before
+	__notes__: List[str]
+	if version_info < (3, 11):  # pragma: no cover
+		def add_note(self, message: str) -> None:
+			try:
+				self.__notes__.append(message)
+			except AttributeError:
+				self.__notes__ = [message]

+
+
+
+

+[docs]
+@export
+class LibraryExistsInDesignError(VHDLModelException):
+	"""
+	This exception is raised, when the library is already existing in the design.
+
+	Message: :pycode:`f"Library '{library._identifier}' already exists in design."`
+	"""
+
+	_library: 'Library'
+
+	def __init__(self, library: 'Library') -> None:
+		"""
+		Initializes the exception message based on given library object.
+
+		:param library: The library that already exists in the design.
+		"""
+		super().__init__(f"Library '{library._identifier}' already exists in design.")
+		self._library = library
+
+	@readonly
+	def Library(self) -> 'Library':
+		"""
+		Read-only property to access the duplicate library (:attr:`_library`).
+
+		:returns: Duplicate library (by name).
+		"""
+		return self._library

+
+
+
+

+[docs]
+@export
+class LibraryRegisteredToForeignDesignError(VHDLModelException):
+	"""
+	This exception is raised, when the library is already registered to a foreign design.
+
+	Message: :pycode:`f"Library '{library._identifier}' already registered in design '{library.Parent}'."`
+	"""
+
+	_library: 'Library'
+
+	def __init__(self, library: 'Library') -> None:
+		"""
+		Initializes the exception message based on given library object.
+
+		:param library: The library that is already registered to another design.
+		"""
+		super().__init__(f"Library '{library._identifier}' already registered in design '{library.Parent}'.")
+		self._library = library
+
+	@readonly
+	def Library(self) -> 'Library':
+		return self._library

+
+
+
+

+[docs]
+@export
+class LibraryNotRegisteredError(VHDLModelException):
+	"""
+	This exception is raised, when the library is not registered in the design.
+
+	Message: :pycode:`f"Library '{library._identifier}' is not registered in the design."`
+	"""
+
+	_library: 'Library'
+
+	def __init__(self, library: 'Library') -> None:
+		"""
+		Initializes the exception message based on given library object.
+
+		:param library: The library that isn't registered in the design.
+		"""
+		super().__init__(f"Library '{library._identifier}' is not registered in the design.")
+		self._library = library
+
+	@readonly
+	def Library(self) -> 'Library':
+		return self._library

+
+
+
+

+[docs]
+@export
+class EntityExistsInLibraryError(VHDLModelException):
+	"""
+	This exception is raised, when the entity already existing in the library.
+
+	Message: :pycode:`f"Entity '{entity._identifier}' already exists in library '{library._identifier}'."`
+	"""
+
+	_library: 'Library'
+	_entity: 'Entity'
+
+	def __init__(self, entity: 'Entity', library: 'Library') -> None:
+		"""
+		Initializes the exception message based on given entity and library objects.
+
+		:param entity:  The entity that already exists in the library.
+		:param library: The library that already contains the entity.
+		"""
+		super().__init__(f"Entity '{entity._identifier}' already exists in library '{library._identifier}'.")
+		self._library = library
+		self._entity = entity
+
+	@readonly
+	def Library(self) -> 'Library':
+		return self._library
+
+	@readonly
+	def Entity(self) -> 'Entity':
+		return self._entity

+
+
+
+

+[docs]
+@export
+class ArchitectureExistsInLibraryError(VHDLModelException):
+	"""
+	This exception is raised, when the architecture already existing in the library.
+
+	Message: :pycode:`f"Architecture '{architecture._identifier}' for entity '{entity._identifier}' already exists in library '{library._identifier}'."`
+	"""
+
+	_library: 'Library'
+	_entity: 'Entity'
+	_architecture: 'Architecture'
+
+	def __init__(self, architecture: 'Architecture', entity: 'Entity', library: 'Library') -> None:
+		"""
+		Initializes the exception message based on given architecture, entity and library objects.
+
+		:param architecture: The architecture that already exists in the library.
+		:param entity:       The entity the architecture refers to, which already exists in the library.
+		:param library:      The library that already contains the architecture.
+		"""
+		super().__init__(f"Architecture '{architecture._identifier}' for entity '{entity._identifier}' already exists in library '{library._identifier}'.")
+		self._library = library
+		self._entity = entity
+		self._architecture = architecture
+
+	@readonly
+	def Library(self) -> 'Library':
+		return self._library
+
+	@readonly
+	def Entity(self) -> 'Entity':
+		return self._entity
+
+	@readonly
+	def Architecture(self) -> 'Architecture':
+		return self._architecture

+
+
+
+

+[docs]
+@export
+class PackageExistsInLibraryError(VHDLModelException):
+	"""
+	This exception is raised, when the package already existing in the library.
+
+	Message: :pycode:`f"Package '{package._identifier}' already exists in library '{library._identifier}'."`
+	"""
+
+	_library: 'Library'
+	_package: 'Package'
+
+	def __init__(self, package: 'Package', library: 'Library') -> None:
+		"""
+		Initializes the exception message based on given package and library objects.
+
+		:param package: The package that already exists in the library.
+		:param library: The library that already contains the package.
+		"""
+		super().__init__(f"Package '{package._identifier}' already exists in library '{library._identifier}'.")
+		self._library = library
+		self._package = package
+
+	@readonly
+	def Library(self) -> 'Library':
+		return self._library
+
+	@readonly
+	def Package(self) -> 'Package':
+		return self._package

+
+
+
+

+[docs]
+@export
+class PackageBodyExistsError(VHDLModelException):
+	"""
+	This exception is raised, when the package body already existing in the library.
+
+	Message: :pycode:`f"Package body '{packageBody._identifier}' already exists in library '{library._identifier}'."`
+	"""
+
+	_library: 'Library'
+	_packageBody: 'PackageBody'
+
+	def __init__(self, packageBody: 'PackageBody', library: 'Library') -> None:
+		"""
+		Initializes the exception message based on given package body and library objects.
+
+		:param packageBody: The package body that already exists in the library.
+		:param library:     The library that already contains the package body.
+		"""
+		super().__init__(f"Package body '{packageBody._identifier}' already exists in library '{library._identifier}'.")
+		self._library = library
+		self._packageBody = packageBody
+
+	@readonly
+	def Library(self) -> 'Library':
+		return self._library
+
+	@property
+	def PackageBody(self) -> 'PackageBody':
+		return self._packageBody

+
+
+
+

+[docs]
+@export
+class ConfigurationExistsInLibraryError(VHDLModelException):
+	"""
+	This exception is raised, when the configuration already existing in the library.
+
+	Message: :pycode:`f"Configuration '{configuration._identifier}' already exists in library '{library._identifier}'."`
+	"""
+
+	_library: 'Library'
+	_configuration: 'Configuration'
+
+	def __init__(self, configuration: 'Configuration', library: 'Library') -> None:
+		"""
+		Initializes the exception message based on given configuration and library objects.
+
+		:param configuration: The configuration that already exists in the library.
+		:param library:       The library that already contains the configuration.
+		"""
+		super().__init__(f"Configuration '{configuration._identifier}' already exists in library '{library._identifier}'.")
+		self._library = library
+		self._configuration = configuration
+
+	@property
+	def Library(self) -> 'Library':
+		return self._library
+
+	@property
+	def Configuration(self) -> 'Configuration':
+		return self._configuration

+
+
+
+

+[docs]
+@export
+class ContextExistsInLibraryError(VHDLModelException):
+	"""
+	This exception is raised, when the context already existing in the library.
+
+	Message: :pycode:`f"Context '{context._identifier}' already exists in library '{library._identifier}'."`
+	"""
+
+	_library: 'Library'
+	_context: 'Context'
+
+	def __init__(self, context: 'Context', library: 'Library') -> None:
+		"""
+		Initializes the exception message based on given context and library objects.
+
+		:param context: The context that already exists in the library.
+		:param library: The library that already contains the context.
+		"""
+		super().__init__(f"Context '{context._identifier}' already exists in library '{library._identifier}'.")
+		self._library = library
+		self._context = context
+
+	@property
+	def Library(self) -> 'Library':
+		return self._library
+
+	@property
+	def Context(self) -> 'Context':
+		return self._context

+
+
+
+

+[docs]
+@export
+class ReferencedLibraryNotExistingError(VHDLModelException):
+	"""
+	This exception is raised, when a library is referenced by a `library clause`, but doesn't exist in the design.
+
+	Message: :pycode:`f"Library '{librarySymbol.Name._identifier}' referenced by library clause of context '{context._identifier}' doesn't exist in design."`
+	"""
+
+	_librarySymbol: Symbol
+	_context: 'Context'
+
+	def __init__(self, context: 'Context', librarySymbol: Symbol) -> None:
+		"""
+		Initializes the exception message based on given context and library objects.
+
+		:param context:       The context that already exists in the library.
+		:param librarySymbol: The library that already contains the context.
+		"""
+		super().__init__(f"Library '{librarySymbol.Name._identifier}' referenced by library clause of context '{context._identifier}' doesn't exist in design.")
+		self._librarySymbol = librarySymbol
+		self._context = context
+
+	@property
+	def LibrarySymbol(self) -> Symbol:
+		return self._librarySymbol
+
+	@property
+	def Context(self) -> 'Context':
+		return self._context

+
+
+ +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/_modules/pyVHDLModel/Expression.html b/_modules/pyVHDLModel/Expression.html new file mode 100644 index 000000000..2a7f0de7b --- /dev/null +++ b/_modules/pyVHDLModel/Expression.html @@ -0,0 +1,1316 @@ + + + + + + pyVHDLModel.Expression — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +

Source code for pyVHDLModel.Expression

+# ==================================================================================================================== #
+#             __     ___   _ ____  _     __  __           _      _                                                     #
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |                                                    #
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |                                                    #
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |                                                    #
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|                                                    #
+#  |_|    |___/                                                                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""
+This module contains parts of an abstract document language model for VHDL.
+
+All declarations for literals, aggregates, operators forming an expressions.
+"""
+from typing               import Tuple, List, Iterable, Union
+
+from pyTooling.Decorators import export, readonly
+
+from pyVHDLModel.Base     import ModelEntity, Direction, Range
+from pyVHDLModel.Symbol   import Symbol
+
+
+ExpressionUnion = Union[
+	'BaseExpression',
+	'QualifiedExpression',
+	'FunctionCall',
+	'TypeConversion',
+	# ConstantOrSymbol,     TODO: ObjectSymbol
+	'Literal',
+]
+
+
+

+[docs]
+@export
+class BaseExpression(ModelEntity):
+	"""A ``BaseExpression`` is a base-class for all expressions."""

+
+
+
+

+[docs]
+@export
+class Literal(BaseExpression):
+	"""A ``Literal`` is a base-class for all literals."""

+
+
+
+

+[docs]
+@export
+class NullLiteral(Literal):
+

+[docs]
+	def __str__(self) -> str:
+		return "null"

+

+
+
+
+

+[docs]
+@export
+class EnumerationLiteral(Literal):
+	_value: str
+
+

+[docs]
+	def __init__(self, value: str, parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+
+		self._value = value

+
+
+	@readonly
+	def Value(self) -> str:
+		return self._value
+
+

+[docs]
+	def __str__(self) -> str:
+		return self._value

+

+
+
+
+

+[docs]
+@export
+class NumericLiteral(Literal):
+	"""A ``NumericLiteral`` is a base-class for all numeric literals."""

+
+
+
+

+[docs]
+@export
+class IntegerLiteral(NumericLiteral):
+	_value: int
+
+

+[docs]
+	def __init__(self, value: int) -> None:
+		super().__init__()
+		self._value = value

+
+
+	@readonly
+	def Value(self) -> int:
+		return self._value
+
+

+[docs]
+	def __str__(self) -> str:
+		return str(self._value)

+

+
+
+
+

+[docs]
+@export
+class FloatingPointLiteral(NumericLiteral):
+	_value: float
+
+

+[docs]
+	def __init__(self, value: float) -> None:
+		super().__init__()
+		self._value = value

+
+
+	@readonly
+	def Value(self) -> float:
+		return self._value
+
+

+[docs]
+	def __str__(self) -> str:
+		return str(self._value)

+

+
+
+
+

+[docs]
+@export
+class PhysicalLiteral(NumericLiteral):
+	_unitName: str
+
+

+[docs]
+	def __init__(self, unitName: str) -> None:
+		super().__init__()
+		self._unitName = unitName

+
+
+	@readonly
+	def UnitName(self) -> str:
+		return self._unitName
+
+

+[docs]
+	def __str__(self) -> str:
+		return f"{self._value} {self._unitName}"

+

+
+
+
+

+[docs]
+@export
+class PhysicalIntegerLiteral(PhysicalLiteral):
+	_value: int
+
+

+[docs]
+	def __init__(self, value: int, unitName: str) -> None:
+		super().__init__(unitName)
+		self._value = value

+
+
+	@readonly
+	def Value(self) -> int:
+		return self._value

+
+
+
+

+[docs]
+@export
+class PhysicalFloatingLiteral(PhysicalLiteral):
+	_value: float
+
+

+[docs]
+	def __init__(self, value: float, unitName: str) -> None:
+		super().__init__(unitName)
+		self._value = value

+
+
+	@readonly
+	def Value(self) -> float:
+		return self._value

+
+
+
+

+[docs]
+@export
+class CharacterLiteral(Literal):
+	_value: str
+
+

+[docs]
+	def __init__(self, value: str) -> None:
+		super().__init__()
+		self._value = value

+
+
+	@readonly
+	def Value(self) -> str:
+		return self._value
+
+

+[docs]
+	def __str__(self) -> str:
+		return str(self._value)

+

+
+
+
+

+[docs]
+@export
+class StringLiteral(Literal):
+	_value: str
+
+

+[docs]
+	def __init__(self, value: str) -> None:
+		super().__init__()
+		self._value = value

+
+
+	@readonly
+	def Value(self) -> str:
+		return self._value
+
+

+[docs]
+	def __str__(self) -> str:
+		return "\"" + self._value + "\""

+

+
+
+
+

+[docs]
+@export
+class BitStringLiteral(Literal):
+	_value: str
+
+

+[docs]
+	def __init__(self, value: str) -> None:
+		super().__init__()
+		self._value = value

+
+
+	@readonly
+	def Value(self) -> str:
+		return self._value
+
+

+[docs]
+	def __str__(self) -> str:
+		return "\"" + self._value + "\""

+

+
+
+
+

+[docs]
+@export
+class ParenthesisExpression: #(Protocol):
+	__slots__ = ()  # FIXME: use ExtendedType?
+
+	@readonly
+	def Operand(self) -> ExpressionUnion:
+		return None

+
+
+
+

+[docs]
+@export
+class UnaryExpression(BaseExpression):
+	"""A ``UnaryExpression`` is a base-class for all unary expressions."""
+
+	_FORMAT:  Tuple[str, str]
+	_operand: ExpressionUnion
+
+

+[docs]
+	def __init__(self, operand: ExpressionUnion, parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+
+		self._operand = operand

+
+		# operand._parent = self  # FIXME: operand is provided as None
+
+	@readonly
+	def Operand(self):
+		return self._operand
+
+

+[docs]
+	def __str__(self) -> str:
+		return f"{self._FORMAT[0]}{self._operand!s}{self._FORMAT[1]}"

+

+
+
+
+

+[docs]
+@export
+class NegationExpression(UnaryExpression):
+	_FORMAT = ("-", "")

+
+
+
+

+[docs]
+@export
+class IdentityExpression(UnaryExpression):
+	_FORMAT = ("+", "")

+
+
+
+

+[docs]
+@export
+class InverseExpression(UnaryExpression):
+	_FORMAT = ("not ", "")

+
+
+
+

+[docs]
+@export
+class UnaryAndExpression(UnaryExpression):
+	_FORMAT = ("and ", "")

+
+
+
+

+[docs]
+@export
+class UnaryNandExpression(UnaryExpression):
+	_FORMAT = ("nand ", "")

+
+
+
+

+[docs]
+@export
+class UnaryOrExpression(UnaryExpression):
+	_FORMAT = ("or ", "")

+
+
+
+

+[docs]
+@export
+class UnaryNorExpression(UnaryExpression):
+	_FORMAT = ("nor ", "")

+
+
+
+

+[docs]
+@export
+class UnaryXorExpression(UnaryExpression):
+	_FORMAT = ("xor ", "")

+
+
+
+

+[docs]
+@export
+class UnaryXnorExpression(UnaryExpression):
+	_FORMAT = ("xnor ", "")

+
+
+
+

+[docs]
+@export
+class AbsoluteExpression(UnaryExpression):
+	_FORMAT = ("abs ", "")

+
+
+
+

+[docs]
+@export
+class TypeConversion(UnaryExpression):
+	pass

+
+
+
+

+[docs]
+@export
+class SubExpression(UnaryExpression, ParenthesisExpression):
+	_FORMAT = ("(", ")")

+
+
+
+

+[docs]
+@export
+class BinaryExpression(BaseExpression):
+	"""A ``BinaryExpression`` is a base-class for all binary expressions."""
+
+	_FORMAT: Tuple[str, str, str]
+	_leftOperand:  ExpressionUnion
+	_rightOperand: ExpressionUnion
+
+

+[docs]
+	def __init__(self, leftOperand: ExpressionUnion, rightOperand: ExpressionUnion, parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+
+		self._leftOperand = leftOperand
+		leftOperand._parent = self
+
+		self._rightOperand = rightOperand
+		rightOperand._parent = self

+
+
+	@property
+	def LeftOperand(self):
+		return self._leftOperand
+
+	@property
+	def RightOperand(self):
+		return self._rightOperand
+
+

+[docs]
+	def __str__(self) -> str:
+		return "{leftOperator}{leftOperand!s}{middleOperator}{rightOperand!s}{rightOperator}".format(
+			leftOperator=self._FORMAT[0],
+			leftOperand=self._leftOperand,
+			middleOperator=self._FORMAT[1],
+			rightOperand=self._rightOperand,
+			rightOperator=self._FORMAT[2],
+		)

+

+
+
+
+

+[docs]
+@export
+class RangeExpression(BinaryExpression):
+	_direction: Direction
+
+	@property
+	def Direction(self) -> Direction:
+		return self._direction

+
+
+
+

+[docs]
+@export
+class AscendingRangeExpression(RangeExpression):
+	_direction = Direction.To
+	_FORMAT = ("", " to ", "")

+
+
+
+

+[docs]
+@export
+class DescendingRangeExpression(RangeExpression):
+	_direction = Direction.DownTo
+	_FORMAT = ("", " downto ", "")

+
+
+
+

+[docs]
+@export
+class AddingExpression(BinaryExpression):
+	"""A ``AddingExpression`` is a base-class for all adding expressions."""

+
+
+
+

+[docs]
+@export
+class AdditionExpression(AddingExpression):
+	_FORMAT = ("", " + ", "")

+
+
+
+

+[docs]
+@export
+class SubtractionExpression(AddingExpression):
+	_FORMAT = ("", " - ", "")

+
+
+
+

+[docs]
+@export
+class ConcatenationExpression(AddingExpression):
+	_FORMAT = ("", " & ", "")

+
+
+
+

+[docs]
+@export
+class MultiplyingExpression(BinaryExpression):
+	"""A ``MultiplyingExpression`` is a base-class for all multiplying expressions."""

+
+
+
+

+[docs]
+@export
+class MultiplyExpression(MultiplyingExpression):
+	_FORMAT = ("", " * ", "")

+
+
+
+

+[docs]
+@export
+class DivisionExpression(MultiplyingExpression):
+	_FORMAT = ("", " / ", "")

+
+
+
+

+[docs]
+@export
+class RemainderExpression(MultiplyingExpression):
+	_FORMAT = ("", " rem ", "")

+
+
+
+

+[docs]
+@export
+class ModuloExpression(MultiplyingExpression):
+	_FORMAT = ("", " mod ", "")

+
+
+
+

+[docs]
+@export
+class ExponentiationExpression(MultiplyingExpression):
+	_FORMAT = ("", "**", "")

+
+
+
+

+[docs]
+@export
+class LogicalExpression(BinaryExpression):
+	"""A ``LogicalExpression`` is a base-class for all logical expressions."""

+
+
+
+

+[docs]
+@export
+class AndExpression(LogicalExpression):
+	_FORMAT = ("", " and ", "")

+
+
+
+

+[docs]
+@export
+class NandExpression(LogicalExpression):
+	_FORMAT = ("", " nand ", "")

+
+
+
+

+[docs]
+@export
+class OrExpression(LogicalExpression):
+	_FORMAT = ("", " or ", "")

+
+
+
+

+[docs]
+@export
+class NorExpression(LogicalExpression):
+	_FORMAT = ("", " nor ", "")

+
+
+
+

+[docs]
+@export
+class XorExpression(LogicalExpression):
+	_FORMAT = ("", " xor ", "")

+
+
+
+

+[docs]
+@export
+class XnorExpression(LogicalExpression):
+	_FORMAT = ("", " xnor ", "")

+
+
+
+

+[docs]
+@export
+class RelationalExpression(BinaryExpression):
+	"""A ``RelationalExpression`` is a base-class for all shifting expressions."""

+
+
+
+

+[docs]
+@export
+class EqualExpression(RelationalExpression):
+	_FORMAT = ("", " = ", "")

+
+
+
+

+[docs]
+@export
+class UnequalExpression(RelationalExpression):
+	_FORMAT = ("", " /= ", "")

+
+
+
+

+[docs]
+@export
+class GreaterThanExpression(RelationalExpression):
+	_FORMAT = ("", " > ", "")

+
+
+
+

+[docs]
+@export
+class GreaterEqualExpression(RelationalExpression):
+	_FORMAT = ("", " >= ", "")

+
+
+
+

+[docs]
+@export
+class LessThanExpression(RelationalExpression):
+	_FORMAT = ("", " < ", "")

+
+
+
+

+[docs]
+@export
+class LessEqualExpression(RelationalExpression):
+	_FORMAT = ("", " <= ", "")

+
+
+
+

+[docs]
+@export
+class MatchingRelationalExpression(RelationalExpression):
+	pass

+
+
+
+

+[docs]
+@export
+class MatchingEqualExpression(MatchingRelationalExpression):
+	_FORMAT = ("", " ?= ", "")

+
+
+
+

+[docs]
+@export
+class MatchingUnequalExpression(MatchingRelationalExpression):
+	_FORMAT = ("", " ?/= ", "")

+
+
+
+

+[docs]
+@export
+class MatchingGreaterThanExpression(MatchingRelationalExpression):
+	_FORMAT = ("", " ?> ", "")

+
+
+
+

+[docs]
+@export
+class MatchingGreaterEqualExpression(MatchingRelationalExpression):
+	_FORMAT = ("", " ?>= ", "")

+
+
+
+

+[docs]
+@export
+class MatchingLessThanExpression(MatchingRelationalExpression):
+	_FORMAT = ("", " ?< ", "")

+
+
+
+

+[docs]
+@export
+class MatchingLessEqualExpression(MatchingRelationalExpression):
+	_FORMAT = ("", " ?<= ", "")

+
+
+
+

+[docs]
+@export
+class ShiftExpression(BinaryExpression):
+	"""A ``ShiftExpression`` is a base-class for all shifting expressions."""

+
+
+
+

+[docs]
+@export
+class ShiftLogicExpression(ShiftExpression):
+	pass

+
+
+
+

+[docs]
+@export
+class ShiftArithmeticExpression(ShiftExpression):
+	pass

+
+
+
+

+[docs]
+@export
+class RotateExpression(ShiftExpression):
+	pass

+
+
+
+

+[docs]
+@export
+class ShiftRightLogicExpression(ShiftLogicExpression):
+	_FORMAT = ("", " srl ", "")

+
+
+
+

+[docs]
+@export
+class ShiftLeftLogicExpression(ShiftLogicExpression):
+	_FORMAT = ("", " sll ", "")

+
+
+
+

+[docs]
+@export
+class ShiftRightArithmeticExpression(ShiftArithmeticExpression):
+	_FORMAT = ("", " sra ", "")

+
+
+
+

+[docs]
+@export
+class ShiftLeftArithmeticExpression(ShiftArithmeticExpression):
+	_FORMAT = ("", " sla ", "")

+
+
+
+

+[docs]
+@export
+class RotateRightExpression(RotateExpression):
+	_FORMAT = ("", " ror ", "")

+
+
+
+

+[docs]
+@export
+class RotateLeftExpression(RotateExpression):
+	_FORMAT = ("", " rol ", "")

+
+
+
+

+[docs]
+@export
+class QualifiedExpression(BaseExpression, ParenthesisExpression):
+	_operand:  ExpressionUnion
+	_subtype:  Symbol
+
+

+[docs]
+	def __init__(self, subtype: Symbol, operand: ExpressionUnion, parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+
+		self._operand = operand
+		operand._parent = self
+
+		self._subtype = subtype
+		subtype._parent = self

+
+
+	@property
+	def Operand(self):
+		return self._operand
+
+	@property
+	def Subtyped(self):
+		return self._subtype
+
+

+[docs]
+	def __str__(self) -> str:
+		return f"{self._subtype}'({self._operand!s})"

+

+
+
+
+

+[docs]
+@export
+class TernaryExpression(BaseExpression):
+	"""A ``TernaryExpression`` is a base-class for all ternary expressions."""
+
+	_FORMAT: Tuple[str, str, str, str]
+	_firstOperand:  ExpressionUnion
+	_secondOperand: ExpressionUnion
+	_thirdOperand:  ExpressionUnion
+
+

+[docs]
+	def __init__(self, parent: ModelEntity = None) -> None:
+		super().__init__(parent)

+
+
+		# FIXME: parameters and initializers are missing !!
+
+	@property
+	def FirstOperand(self):
+		return self._firstOperand
+
+	@property
+	def SecondOperand(self):
+		return self._secondOperand
+
+	@property
+	def ThirdOperand(self):
+		return self._thirdOperand
+
+

+[docs]
+	def __str__(self) -> str:
+		return "{beforeFirstOperator}{firstOperand!s}{beforeSecondOperator}{secondOperand!s}{beforeThirdOperator}{thirdOperand!s}{lastOperator}".format(
+			beforeFirstOperator=self._FORMAT[0],
+			firstOperand=self._firstOperand,
+			beforeSecondOperator=self._FORMAT[1],
+			secondOperand=self._secondOperand,
+			beforeThirdOperator=self._FORMAT[2],
+			thirdOperand=self._thirdOperand,
+			lastOperator=self._FORMAT[4],
+		)

+

+
+
+
+

+[docs]
+@export
+class WhenElseExpression(TernaryExpression):
+	_FORMAT = ("", " when ", " else ", "")

+
+
+
+

+[docs]
+@export
+class FunctionCall(BaseExpression):
+	pass

+
+
+
+

+[docs]
+@export
+class Allocation(BaseExpression):
+	pass

+
+
+
+

+[docs]
+@export
+class SubtypeAllocation(Allocation):
+	_subtype: Symbol
+
+

+[docs]
+	def __init__(self, subtype: Symbol, parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+
+		self._subtype = subtype
+		subtype._parent = self

+
+
+	@property
+	def Subtype(self) -> Symbol:
+		return self._subtype
+
+

+[docs]
+	def __str__(self) -> str:
+		return f"new {self._subtype!s}"

+

+
+
+
+

+[docs]
+@export
+class QualifiedExpressionAllocation(Allocation):
+	_qualifiedExpression: QualifiedExpression
+
+

+[docs]
+	def __init__(self, qualifiedExpression: QualifiedExpression, parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+
+		self._qualifiedExpression = qualifiedExpression
+		qualifiedExpression._parent = self

+
+
+	@property
+	def QualifiedExpression(self) -> QualifiedExpression:
+		return self._qualifiedExpression
+
+

+[docs]
+	def __str__(self) -> str:
+		return f"new {self._qualifiedExpression!s}"

+

+
+
+
+

+[docs]
+@export
+class AggregateElement(ModelEntity):
+	"""A ``AggregateElement`` is a base-class for all aggregate elements."""
+
+	_expression: ExpressionUnion
+
+

+[docs]
+	def __init__(self, expression: ExpressionUnion, parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+
+		self._expression = expression
+		expression._parent = self

+
+
+	@property
+	def Expression(self):
+		return self._expression

+
+
+
+

+[docs]
+@export
+class SimpleAggregateElement(AggregateElement):
+

+[docs]
+	def __str__(self) -> str:
+		return str(self._expression)

+

+
+
+
+

+[docs]
+@export
+class IndexedAggregateElement(AggregateElement):
+	_index: int
+
+

+[docs]
+	def __init__(self, index: ExpressionUnion, expression: ExpressionUnion, parent: ModelEntity = None) -> None:
+		super().__init__(expression, parent)
+
+		self._index = index

+
+
+	@property
+	def Index(self) -> int:
+		return self._index
+
+

+[docs]
+	def __str__(self) -> str:
+		return f"{self._index!s} => {self._expression!s}"

+

+
+
+
+

+[docs]
+@export
+class RangedAggregateElement(AggregateElement):
+	_range: Range
+
+

+[docs]
+	def __init__(self, rng: Range, expression: ExpressionUnion, parent: ModelEntity = None) -> None:
+		super().__init__(expression, parent)
+
+		self._range = rng
+		rng._parent = self

+
+
+	@property
+	def Range(self) -> Range:
+		return self._range
+
+

+[docs]
+	def __str__(self) -> str:
+		return f"{self._range!s} => {self._expression!s}"

+

+
+
+
+

+[docs]
+@export
+class NamedAggregateElement(AggregateElement):
+	_name: Symbol
+
+

+[docs]
+	def __init__(self, name: Symbol, expression: ExpressionUnion, parent: ModelEntity = None) -> None:
+		super().__init__(expression, parent)
+
+		self._name = name
+		name._parent = self

+
+
+	@property
+	def Name(self) -> Symbol:
+		return self._name
+
+

+[docs]
+	def __str__(self) -> str:
+		return "{name!s} => {value!s}".format(
+			name=self._name,
+			value=self._expression,
+		)

+

+
+
+
+

+[docs]
+@export
+class OthersAggregateElement(AggregateElement):
+

+[docs]
+	def __str__(self) -> str:
+		return "others => {value!s}".format(
+			value=self._expression,
+		)

+

+
+
+
+

+[docs]
+@export
+class Aggregate(BaseExpression):
+	_elements: List[AggregateElement]
+
+

+[docs]
+	def __init__(self, elements: Iterable[AggregateElement], parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+
+		self._elements = []
+		for element in elements:
+			self._elements.append(element)
+			element._parent = self

+
+
+	@property
+	def Elements(self) -> List[AggregateElement]:
+		return self._elements
+
+

+[docs]
+	def __str__(self) -> str:
+		choices = [str(element) for element in self._elements]
+		return "({choices})".format(
+			choices=", ".join(choices)
+		)

+

+
+
+ +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/_modules/pyVHDLModel/IEEE.html b/_modules/pyVHDLModel/IEEE.html new file mode 100644 index 000000000..52892013b --- /dev/null +++ b/_modules/pyVHDLModel/IEEE.html @@ -0,0 +1,695 @@ + + + + + + pyVHDLModel.IEEE — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +

Source code for pyVHDLModel.IEEE

+# ==================================================================================================================== #
+#             __     ___   _ ____  _     __  __           _      _                                                     #
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |                                                    #
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |                                                    #
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |                                                    #
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|                                                    #
+#  |_|    |___/                                                                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""This module contains library and package declarations for VHDL library ``IEEE``."""
+from pyTooling.Decorators   import export
+
+from pyVHDLModel.Expression import EnumerationLiteral
+from pyVHDLModel.Name       import SimpleName
+from pyVHDLModel.Predefined import PredefinedLibrary, PredefinedPackage, PredefinedPackageBody
+from pyVHDLModel.Symbol     import SimpleSubtypeSymbol
+from pyVHDLModel.Type       import EnumeratedType, ArrayType, Subtype
+
+
+

+[docs]
+@export
+class Ieee(PredefinedLibrary):
+	"""
+	Predefined VHDL library ``ieee``.
+
+	The following predefined packages are in this library:
+
+	* Math
+
+	  * :class:`~pyVHDLModel.IEEE.Math_Real`
+	  * :class:`~pyVHDLModel.IEEE.Math_Complex`
+
+	* Std_logic
+
+	  * :class:`~pyVHDLModel.IEEE.Std_Logic_1164`
+	  * :class:`~pyVHDLModel.IEEE.Std_Logic_TextIO`
+	  * :class:`~pyVHDLModel.IEEE.Std_Logic_Misc`
+
+	* Numeric
+
+	  * :class:`~pyVHDLModel.IEEE.Numeric_Bit`
+	  * :class:`~pyVHDLModel.IEEE.Numeric_Bit_Unsigned`
+	  * :class:`~pyVHDLModel.IEEE.Numeric_Std`
+	  * :class:`~pyVHDLModel.IEEE.Numeric_Std_Unsigned`
+
+	* Fixed/floating point
+
+	  * :class:`~pyVHDLModel.IEEE.Fixed_Float_Types`
+	  * :class:`~pyVHDLModel.IEEE.Fixed_Generic_Pkg`
+	  * :class:`~pyVHDLModel.IEEE.Fixed_Pkg`
+	  * :class:`~pyVHDLModel.IEEE.Float_Generic_Pkg`
+	  * :class:`~pyVHDLModel.IEEE.Float_Pkg`
+
+	.. seealso::
+
+	   Other predefined libraries:
+	     * Library :class:`~pyVHDLModel.STD.Std`
+	"""
+
+

+[docs]
+	def __init__(self) -> None:
+		super().__init__(PACKAGES)

+
+
+	def LoadSynopsysPackages(self) -> None:
+		self.AddPackages(PACKAGES_SYNOPSYS)

+
+
+
+
+

+[docs]
+@export
+class Math_Real(PredefinedPackage):
+	"""
+	Predefined package ``ieee.math_real``.
+	"""

+
+
+
+

+[docs]
+@export
+class Math_Real_Body(PredefinedPackageBody):
+	"""
+	Predefined package body of package ``ieee.math_real``.
+	"""

+
+
+
+

+[docs]
+@export
+class Math_Complex(PredefinedPackage):
+	"""
+	Predefined package ``ieee.math_complex``.
+	"""
+
+

+[docs]
+	def __init__(self) -> None:
+		super().__init__()
+
+		self._AddPackageClause(("work.math_real.all",))

+

+
+
+
+

+[docs]
+@export
+class Math_Complex_Body(PredefinedPackageBody):
+	"""
+	Predefined package body of package ``ieee.math_complex``.
+	"""
+
+

+[docs]
+	def __init__(self) -> None:
+		super().__init__()
+
+		self._AddPackageClause(("work.math_real.all",))

+

+
+
+
+

+[docs]
+@export
+class Std_logic_1164(PredefinedPackage):
+	"""
+	Predefined package ``ieee.std_logic_1164``.
+
+	Predefined types:
+
+	* ``std_ulogic``, ``std_ulogic_vector``
+	* ``std_logic``, ``std_logic_vector``
+	"""
+
+

+[docs]
+	def __init__(self) -> None:
+		super().__init__()
+
+		self._AddPackageClause(("STD.TEXTIO.all", ))
+
+		stdULogic = EnumeratedType("std_ulogic", (
+			EnumerationLiteral("U"),
+			EnumerationLiteral("X"),
+			EnumerationLiteral("0"),
+			EnumerationLiteral("1"),
+			EnumerationLiteral("Z"),
+			EnumerationLiteral("W"),
+			EnumerationLiteral("L"),
+			EnumerationLiteral("H"),
+			EnumerationLiteral("-"),
+		), None)
+		self._types[stdULogic._normalizedIdentifier] = stdULogic
+		self._declaredItems.append(stdULogic)
+
+		stdULogicVector = ArrayType("std_ulogic_vector", (SimpleSubtypeSymbol(SimpleName("natural")),), SimpleSubtypeSymbol(SimpleName("std_ulogic")), None)
+		self._types[stdULogicVector._normalizedIdentifier] = stdULogicVector
+		self._declaredItems.append(stdULogicVector)
+
+		stdLogic = Subtype("std_logic", SimpleSubtypeSymbol(SimpleName("std_ulogic")), None)
+		stdLogic._baseType = stdULogic
+		self._subtypes[stdLogic._normalizedIdentifier] = stdLogic
+		self._declaredItems.append(stdLogic)
+
+		stdLogicVector = Subtype("std_logic_vector", SimpleSubtypeSymbol(SimpleName("std_ulogic_vector")), None)
+		stdLogicVector._baseType = stdULogicVector
+		self._subtypes[stdLogicVector._normalizedIdentifier] = stdLogicVector
+		self._declaredItems.append(stdLogicVector)

+

+
+
+
+

+[docs]
+@export
+class Std_logic_1164_Body(PredefinedPackageBody):
+	"""
+	Predefined package body of package ``ieee.std_logic_1164``.
+	"""

+
+
+
+

+[docs]
+@export
+class std_logic_textio(PredefinedPackage):
+	"""
+	Predefined package ``ieee.std_logic_textio``.
+	"""
+
+

+[docs]
+	def __init__(self) -> None:
+		super().__init__()
+
+		self._AddPackageClause(("STD.TEXTIO.all", ))
+		self._AddLibraryClause(("IEEE", ))
+		self._AddPackageClause(("IEEE.std_logic_1164.all", ))

+

+
+
+
+

+[docs]
+@export
+class Std_logic_misc(PredefinedPackage):
+	"""
+	Predefined package ``ieee.std_logic_misc``.
+	"""
+
+

+[docs]
+	def __init__(self) -> None:
+		super().__init__()
+
+		self._AddLibraryClause(("IEEE", ))
+		self._AddPackageClause(("IEEE.std_logic_1164.all", ))

+

+
+
+
+

+[docs]
+@export
+class Std_logic_misc_Body(PredefinedPackageBody):
+	"""
+	Predefined package body of package ``ieee.std_logic_misc``.
+	"""

+
+
+
+

+[docs]
+@export
+class Numeric_Bit(PredefinedPackage):
+	"""
+	Predefined package ``ieee.numeric_bit``.
+	"""
+
+

+[docs]
+	def __init__(self) -> None:
+		super().__init__()
+
+		self._AddPackageClause(("STD.TEXTIO.all", ))

+

+
+
+
+

+[docs]
+@export
+class Numeric_Bit_Body(PredefinedPackageBody):
+	"""
+	Predefined package body of package ``ieee.numeric_bit``.
+	"""

+
+
+
+

+[docs]
+@export
+class Numeric_Bit_Unsigned(PredefinedPackage):
+	"""
+	Predefined package ``ieee.numeric_bit_unsigned``.
+	"""

+
+
+
+

+[docs]
+@export
+class Numeric_Bit_Unsigned_Body(PredefinedPackageBody):
+	"""
+	Predefined package body of package ``ieee.numeric_bit_unsigned``.
+	"""
+
+

+[docs]
+	def __init__(self) -> None:
+		super().__init__()
+
+		self._AddLibraryClause(("IEEE", ))
+		self._AddPackageClause(("IEEE.numeric_bit.all", ))

+

+
+
+
+

+[docs]
+@export
+class Numeric_Std(PredefinedPackage):
+	"""
+	Predefined package ``ieee.numeric_std``.
+
+	Predefined types:
+
+	* ``unresolved_unsigned``, ``unsigned``
+	* ``unresolved_signed``, ``signed``
+	"""
+
+

+[docs]
+	def __init__(self) -> None:
+		super().__init__()
+
+		self._AddPackageClause(("STD.TEXTIO.all", ))
+		self._AddLibraryClause(("IEEE", ))
+		self._AddPackageClause(("IEEE.std_logic_1164.all", ))
+
+		unresolvedUnsigned = ArrayType("unresolved_unsigned", (SimpleSubtypeSymbol(SimpleName("natural")),), SimpleSubtypeSymbol(SimpleName("std_ulogic")), None)
+		self._types[unresolvedUnsigned._normalizedIdentifier] = unresolvedUnsigned
+		self._declaredItems.append(unresolvedUnsigned)
+
+		unsigned = Subtype("unsigned", SimpleSubtypeSymbol(SimpleName("unresolved_unsigned")), None)
+		unsigned._baseType = unresolvedUnsigned
+		self._subtypes[unsigned._normalizedIdentifier] = unsigned
+		self._declaredItems.append(unsigned)
+
+		unresolvedSigned = ArrayType("unresolved_signed", (SimpleSubtypeSymbol(SimpleName("natural")),), SimpleSubtypeSymbol(SimpleName("std_ulogic")), None)
+		self._types[unresolvedSigned._normalizedIdentifier] = unresolvedSigned
+		self._declaredItems.append(unresolvedSigned)
+
+		signed = Subtype("signed", SimpleSubtypeSymbol(SimpleName("unresolved_signed")), None)
+		signed._baseType = unresolvedSigned
+		self._subtypes[signed._normalizedIdentifier] = signed
+		self._declaredItems.append(signed)

+

+
+
+
+

+[docs]
+@export
+class Numeric_Std_Body(PredefinedPackageBody):
+	"""
+	Predefined package body of package ``ieee.numeric_std``.
+	"""

+
+
+
+

+[docs]
+@export
+class Numeric_Std_Unsigned(PredefinedPackage):
+	"""
+	Predefined package ``ieee.numeric_std_unsigned``.
+	"""
+
+

+[docs]
+	def __init__(self) -> None:
+		super().__init__()
+
+		self._AddLibraryClause(("IEEE", ))
+		self._AddPackageClause(("IEEE.std_logic_1164.all", ))

+

+
+
+
+

+[docs]
+@export
+class Numeric_Std_Unsigned_Body(PredefinedPackageBody):
+	"""
+	Predefined package body of package ``ieee.numeric_std_unsigned``.
+	"""
+
+

+[docs]
+	def __init__(self) -> None:
+		super().__init__()
+
+		self._AddLibraryClause(("IEEE", ))
+		self._AddPackageClause(("IEEE.numeric_std.all", ))

+

+
+
+
+

+[docs]
+@export
+class Fixed_Float_Types(PredefinedPackage):
+	"""
+	Predefined package ``ieee.fixed_float_types``.
+	"""

+
+
+
+

+[docs]
+@export
+class Fixed_Generic_Pkg(PredefinedPackage):
+	"""
+	Predefined package ``ieee.fixed_generic_pkg``.
+	"""
+
+

+[docs]
+	def __init__(self) -> None:
+		super().__init__()
+
+		self._AddPackageClause(("STD.TEXTIO.all", ))
+		self._AddLibraryClause(("IEEE", ))
+		self._AddPackageClause(("IEEE.STD_LOGIC_1164.all", ))
+		self._AddPackageClause(("IEEE.NUMERIC_STD.all", ))
+		self._AddPackageClause(("IEEE.fixed_float_types.all", ))

+

+
+
+
+

+[docs]
+@export
+class Fixed_Generic_Pkg_Body(PredefinedPackageBody):
+	"""
+	Predefined package body of package ``ieee.fixed_generic_pkg``.
+	"""
+
+

+[docs]
+	def __init__(self) -> None:
+		super().__init__()
+
+		self._AddLibraryClause(("IEEE", ))
+		self._AddPackageClause(("IEEE.MATH_REAL.all", ))

+

+
+
+
+

+[docs]
+@export
+class Fixed_Pkg(PredefinedPackage):
+	"""
+	Predefined package ``ieee.fixed_pkg``.
+	"""
+

+[docs]
+	def __init__(self) -> None:
+		super().__init__()
+
+		self._AddLibraryClause(("IEEE", ))

+

+
+
+
+

+[docs]
+@export
+class Float_Generic_Pkg(PredefinedPackage):
+	"""
+	Predefined package ``ieee.float_generic_pkg``.
+	"""
+
+

+[docs]
+	def __init__(self) -> None:
+		super().__init__()
+
+		self._AddPackageClause(("STD.TEXTIO.all", ))
+		self._AddLibraryClause(("IEEE", ))
+		self._AddPackageClause(("IEEE.STD_LOGIC_1164.all", ))
+		self._AddPackageClause(("IEEE.NUMERIC_STD.all", ))
+		self._AddPackageClause(("IEEE.fixed_float_types.all", ))

+

+
+
+
+

+[docs]
+@export
+class Float_Generic_Pkg_Body(PredefinedPackageBody):
+	"""
+	Predefined package body of package ``ieee.float_generic_pkg``.
+	"""

+
+
+
+

+[docs]
+@export
+class Float_Pkg(PredefinedPackage):
+	"""
+	Predefined package ``ieee.float_pkg``.
+	"""
+
+

+[docs]
+	def __init__(self) -> None:
+		super().__init__()
+
+		self._AddLibraryClause(("IEEE", ))

+

+
+
+
+PACKAGES = (
+	(Math_Real,            Math_Real_Body),
+	(Math_Complex,         Math_Complex_Body),
+	(Std_logic_1164,       Std_logic_1164_Body),
+	(std_logic_textio,     None),
+	(Numeric_Bit,          Numeric_Bit_Body),
+	(Numeric_Bit_Unsigned, Numeric_Bit_Unsigned_Body),
+	(Numeric_Std,          Numeric_Std_Body),
+	(Numeric_Std_Unsigned, Numeric_Std_Unsigned_Body),
+	(Fixed_Float_Types,    None),
+	(Fixed_Generic_Pkg,    Fixed_Generic_Pkg_Body),
+	(Fixed_Pkg,            None),
+	(Float_Generic_Pkg,    Float_Generic_Pkg_Body),
+	(Float_Pkg,            None),
+)
+
+PACKAGES_SYNOPSYS = (
+	(Std_logic_misc,       Std_logic_misc_Body),
+)
+
+ +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/_modules/pyVHDLModel/Instantiation.html b/_modules/pyVHDLModel/Instantiation.html new file mode 100644 index 000000000..1915b6367 --- /dev/null +++ b/_modules/pyVHDLModel/Instantiation.html @@ -0,0 +1,281 @@ + + + + + + pyVHDLModel.Instantiation — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +

Source code for pyVHDLModel.Instantiation

+# ==================================================================================================================== #
+#             __     ___   _ ____  _     __  __           _      _                                                     #
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |                                                    #
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |                                                    #
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |                                                    #
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|                                                    #
+#  |_|    |___/                                                                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""
+This module contains parts of an abstract document language model for VHDL.
+
+Instantiations of packages, procedures, functions and protected types.
+"""
+from typing import List, Optional as Nullable
+
+from pyTooling.Decorators    import export, readonly
+from pyTooling.MetaClasses   import ExtendedType
+
+from pyVHDLModel.Base        import ModelEntity
+from pyVHDLModel.DesignUnit  import PrimaryUnit
+from pyVHDLModel.Association import GenericAssociationItem
+from pyVHDLModel.Subprogram  import Procedure, Function, Subprogram
+from pyVHDLModel.Symbol      import PackageReferenceSymbol
+
+
+

+[docs]
+@export
+class GenericInstantiationMixin(metaclass=ExtendedType, mixin=True):
+

+[docs]
+	def __init__(self) -> None:
+		pass

+

+
+
+
+

+[docs]
+@export
+class GenericEntityInstantiationMixin(GenericInstantiationMixin, mixin=True):
+

+[docs]
+	def __init__(self) -> None:
+		pass

+

+
+
+
+

+[docs]
+@export
+class SubprogramInstantiationMixin(GenericInstantiationMixin, mixin=True):
+	_subprogramReference: Subprogram  # FIXME: is this a subprogram symbol?
+
+

+[docs]
+	def __init__(self) -> None:
+		super().__init__()
+		self._subprogramReference = None

+

+
+
+
+

+[docs]
+@export
+class ProcedureInstantiation(Procedure, SubprogramInstantiationMixin):
+	pass

+
+
+
+

+[docs]
+@export
+class FunctionInstantiation(Function, SubprogramInstantiationMixin):
+	pass

+
+
+
+

+[docs]
+@export
+class PackageInstantiation(PrimaryUnit, GenericInstantiationMixin):
+	_packageReference: PackageReferenceSymbol
+	_genericAssociations: List[GenericAssociationItem]
+
+

+[docs]
+	def __init__(self, identifier: str, uninstantiatedPackage: PackageReferenceSymbol, documentation: Nullable[str] = None, parent: ModelEntity = None) -> None:
+		super().__init__(identifier, documentation, parent)
+		GenericEntityInstantiationMixin.__init__(self)
+
+		self._packageReference = uninstantiatedPackage
+		# uninstantiatedPackage._parent = self    # FIXME: uninstantiatedPackage is provided as int
+
+		# TODO: extract to mixin
+		self._genericAssociations = []

+
+
+	@readonly
+	def PackageReference(self) -> PackageReferenceSymbol:
+		return self._packageReference
+
+	@readonly
+	def GenericAssociations(self) -> List[GenericAssociationItem]:
+		return self._genericAssociations

+
+
+ +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/_modules/pyVHDLModel/Interface.html b/_modules/pyVHDLModel/Interface.html new file mode 100644 index 000000000..3f710000e --- /dev/null +++ b/_modules/pyVHDLModel/Interface.html @@ -0,0 +1,449 @@ + + + + + + pyVHDLModel.Interface — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +

Source code for pyVHDLModel.Interface

+# ==================================================================================================================== #
+#             __     ___   _ ____  _     __  __           _      _                                                     #
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |                                                    #
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |                                                    #
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |                                                    #
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|                                                    #
+#  |_|    |___/                                                                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""
+This module contains parts of an abstract document language model for VHDL.
+
+Interface items are used in generic, port and parameter declarations.
+"""
+from typing                 import Iterable, Optional as Nullable
+
+from pyTooling.Decorators   import export, readonly
+from pyTooling.MetaClasses  import ExtendedType
+
+from pyVHDLModel.Symbol     import Symbol
+from pyVHDLModel.Base       import ModelEntity, DocumentedEntityMixin, ExpressionUnion, Mode
+from pyVHDLModel.Object     import Constant, Signal, Variable, File
+from pyVHDLModel.Subprogram import Procedure, Function
+from pyVHDLModel.Type       import Type
+
+
+

+[docs]
+@export
+class InterfaceItemMixin(DocumentedEntityMixin, mixin=True):
+	"""An ``InterfaceItem`` is a base-class for all mixin-classes for all interface items."""
+
+

+[docs]
+	def __init__(self, documentation: Nullable[str] = None) -> None:
+		super().__init__(documentation)

+

+
+
+
+

+[docs]
+@export
+class InterfaceItemWithModeMixin(metaclass=ExtendedType, mixin=True):
+	"""An ``InterfaceItemWithMode`` is a mixin-class to provide a ``Mode`` to interface items."""
+
+	_mode: Mode
+
+

+[docs]
+	def __init__(self, mode: Mode) -> None:
+		self._mode = mode

+
+
+	@readonly
+	def Mode(self) -> Mode:
+		return self._mode

+
+
+
+

+[docs]
+@export
+class GenericInterfaceItemMixin(InterfaceItemMixin, mixin=True):
+	"""A ``GenericInterfaceItem`` is a mixin class for all generic interface items."""

+
+
+
+

+[docs]
+@export
+class PortInterfaceItemMixin(InterfaceItemMixin, InterfaceItemWithModeMixin, mixin=True):
+	"""A ``PortInterfaceItem`` is a mixin class for all port interface items."""
+
+

+[docs]
+	def __init__(self, mode: Mode) -> None:
+		super().__init__()
+		InterfaceItemWithModeMixin.__init__(self, mode)

+

+
+
+
+

+[docs]
+@export
+class ParameterInterfaceItemMixin(InterfaceItemMixin, mixin=True):
+	"""A ``ParameterInterfaceItem`` is a mixin class for all parameter interface items."""

+
+
+
+

+[docs]
+@export
+class GenericConstantInterfaceItem(Constant, GenericInterfaceItemMixin, InterfaceItemWithModeMixin):
+

+[docs]
+	def __init__(
+		self,
+		identifiers: Iterable[str],
+		mode: Mode,
+		subtype: Symbol,
+		defaultExpression: Nullable[ExpressionUnion] = None,
+		documentation: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(identifiers, subtype, defaultExpression, documentation, parent)
+		GenericInterfaceItemMixin.__init__(self)
+		InterfaceItemWithModeMixin.__init__(self, mode)

+

+
+
+
+

+[docs]
+@export
+class GenericTypeInterfaceItem(Type, GenericInterfaceItemMixin):
+

+[docs]
+	def __init__(self, identifier: str, documentation: Nullable[str] = None, parent: ModelEntity = None) -> None:
+		super().__init__(identifier, documentation, parent)
+		GenericInterfaceItemMixin.__init__(self)

+

+
+
+
+

+[docs]
+@export
+class GenericSubprogramInterfaceItem(GenericInterfaceItemMixin):
+	pass

+
+
+
+

+[docs]
+@export
+class GenericProcedureInterfaceItem(Procedure, GenericInterfaceItemMixin):
+

+[docs]
+	def __init__(self, identifier: str, documentation: Nullable[str] = None, parent: ModelEntity = None) -> None:
+		super().__init__(identifier, documentation, parent)
+		GenericInterfaceItemMixin.__init__(self)

+

+
+
+
+

+[docs]
+@export
+class GenericFunctionInterfaceItem(Function, GenericInterfaceItemMixin):
+

+[docs]
+	def __init__(self, identifier: str, documentation: Nullable[str] = None, parent: ModelEntity = None) -> None:
+		super().__init__(identifier, documentation, parent)
+		GenericInterfaceItemMixin.__init__(self)

+

+
+
+
+

+[docs]
+@export
+class GenericPackageInterfaceItem(GenericInterfaceItemMixin):
+

+[docs]
+	def __init__(self, identifier: str, documentation: Nullable[str] = None, parent: ModelEntity = None) -> None:
+		super().__init__(identifier, documentation, parent)
+		GenericInterfaceItemMixin.__init__(self)

+

+
+
+
+

+[docs]
+@export
+class PortSignalInterfaceItem(Signal, PortInterfaceItemMixin):
+

+[docs]
+	def __init__(
+		self,
+		identifiers: Iterable[str],
+		mode: Mode,
+		subtype: Symbol,
+		defaultExpression: Nullable[ExpressionUnion] = None,
+		documentation: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(identifiers, subtype, defaultExpression, documentation, parent)
+		PortInterfaceItemMixin.__init__(self, mode)

+

+
+
+
+

+[docs]
+@export
+class ParameterConstantInterfaceItem(Constant, ParameterInterfaceItemMixin, InterfaceItemWithModeMixin):
+

+[docs]
+	def __init__(
+		self,
+		identifiers: Iterable[str],
+		mode: Mode,
+		subtype: Symbol,
+		defaultExpression: Nullable[ExpressionUnion] = None,
+		documentation: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(identifiers, subtype, defaultExpression, documentation, parent)
+		ParameterInterfaceItemMixin.__init__(self)
+		InterfaceItemWithModeMixin.__init__(self, mode)

+

+
+
+
+

+[docs]
+@export
+class ParameterVariableInterfaceItem(Variable, ParameterInterfaceItemMixin, InterfaceItemWithModeMixin):
+

+[docs]
+	def __init__(
+		self,
+		identifiers: Iterable[str],
+		mode: Mode,
+		subtype: Symbol,
+		defaultExpression: Nullable[ExpressionUnion] = None,
+		documentation: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(identifiers, subtype, defaultExpression, documentation, parent)
+		ParameterInterfaceItemMixin.__init__(self)
+		InterfaceItemWithModeMixin.__init__(self, mode)

+

+
+
+
+

+[docs]
+@export
+class ParameterSignalInterfaceItem(Signal, ParameterInterfaceItemMixin, InterfaceItemWithModeMixin):
+

+[docs]
+	def __init__(
+		self,
+		identifiers: Iterable[str],
+		mode: Mode,
+		subtype: Symbol,
+		defaultExpression: Nullable[ExpressionUnion] = None,
+		documentation: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(identifiers, subtype, defaultExpression, documentation, parent)
+		ParameterInterfaceItemMixin.__init__(self)
+		InterfaceItemWithModeMixin.__init__(self, mode)

+

+
+
+
+

+[docs]
+@export
+class ParameterFileInterfaceItem(File, ParameterInterfaceItemMixin):
+

+[docs]
+	def __init__(
+		self,
+		identifiers: Iterable[str],
+		subtype: Symbol,
+		documentation: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(identifiers, subtype, documentation, parent)
+		ParameterInterfaceItemMixin.__init__(self)

+

+
+
+ +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/_modules/pyVHDLModel/Name.html b/_modules/pyVHDLModel/Name.html new file mode 100644 index 000000000..0d8c66138 --- /dev/null +++ b/_modules/pyVHDLModel/Name.html @@ -0,0 +1,447 @@ + + + + + + pyVHDLModel.Name — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +

Source code for pyVHDLModel.Name

+# ==================================================================================================================== #
+#             __     ___   _ ____  _     __  __           _      _                                                     #
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |                                                    #
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |                                                    #
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |                                                    #
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|                                                    #
+#  |_|    |___/                                                                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""
+This module contains parts of an abstract document language model for VHDL.
+
+VHDL uses *names* to express cross-references from *usage locations* to *declarations*. Here, *names* are single or
+combined identifiers. :mod:`Symbols <pyVHDLModel.Symbol>` are structures representing a *name* and a reference
+(pointer) to the referenced vhdl language entity.
+"""
+from typing import List, Iterable, Optional as Nullable
+
+from pyTooling.Decorators import export, readonly
+
+from pyVHDLModel.Base import ModelEntity, ExpressionUnion
+
+
+

+[docs]
+@export
+class Name(ModelEntity):
+	"""``Name`` is the base-class for all *names* in the VHDL language model."""
+
+	_identifier: str
+	_normalizedIdentifier: str
+	_root: Nullable['Name']     # TODO: seams to be unused. There is no reverse linking, or?
+	_prefix: Nullable['Name']
+
+

+[docs]
+	def __init__(self, identifier: str, prefix: Nullable["Name"] = None, parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+
+		self._identifier = identifier
+		self._normalizedIdentifier = identifier.lower()
+
+		if prefix is None:
+			self._prefix = None
+			self._root = self
+		else:
+			self._prefix = prefix
+			self._root = prefix._root

+
+
+	@readonly
+	def Identifier(self) -> str:
+		"""
+		The identifier the name is referencing.
+
+		:returns: The referenced identifier.
+		"""
+		return self._identifier
+
+	@readonly
+	def NormalizedIdentifier(self) -> str:
+		"""
+		The normalized identifier the name is referencing.
+
+		:returns: The referenced identifier (normalized).
+		"""
+		return self._normalizedIdentifier
+
+	@readonly
+	def Root(self) -> 'Name':
+		"""
+		The root (left-most) element in a chain of names.
+
+		In case the name is a :class:`simple name <SimpleName>`, the root points to the name itself.
+
+		:returns: The name's root element.
+		"""
+		return self._root
+
+	@readonly
+	def Prefix(self) -> Nullable['Name']:
+		"""
+		The name's prefix in a chain of names.
+
+		:returns: The name left from current name, if not a simple name, otherwise ``None``.
+		"""
+		return self._prefix
+
+	@readonly
+	def HasPrefix(self) -> bool:
+		"""
+		Returns true, if the name has a prefix.
+
+		This is true for all names except :class:`simple names <SimpleName>`.
+
+		:returns: ``True``, if the name as a prefix.
+		"""
+		return self._prefix is not None
+
+

+[docs]
+	def __repr__(self) -> str:
+		return f"Name: '{self.__str__()}'"

+
+
+

+[docs]
+	def __str__(self) -> str:
+		return self._identifier

+

+
+
+
+

+[docs]
+@export
+class SimpleName(Name):
+	"""
+	A *simple name* is a name made from a single word.
+
+	For example, the entity name in an architecture declaration is a simple name, while the name of the architecture
+	itself is an identifier. The simple name references is again an identifier in the entity declaration, thus names
+	reference other (already) declared language entities.
+	"""

+
+
+
+

+[docs]
+@export
+class ParenthesisName(Name):
+	_associations: List
+
+

+[docs]
+	def __init__(self, prefix: Name, associations: Iterable, parent: ModelEntity = None) -> None:
+		super().__init__("", prefix, parent)
+
+		self._associations = []
+		for association in associations:
+			self._associations.append(association)
+			association._parent = self

+
+
+	@readonly
+	def Associations(self) -> List:
+		return self._associations
+
+

+[docs]
+	def __str__(self) -> str:
+		return f"{self._prefix!s}({', '.join(str(a) for a in self._associations)})"

+

+
+
+
+

+[docs]
+@export
+class IndexedName(Name):
+	_indices: List[ExpressionUnion]
+
+

+[docs]
+	def __init__(self, prefix: Name, indices: Iterable[ExpressionUnion], parent: ModelEntity = None) -> None:
+		super().__init__("", prefix, parent)
+
+		self._indices = []
+		for index in indices:
+			self._indices.append(index)
+			index._parent = self

+
+
+	@readonly
+	def Indices(self) -> List[ExpressionUnion]:
+		return self._indices
+
+

+[docs]
+	def __str__(self) -> str:
+		return f"{self._prefix!s}({', '.join(str(i) for i in self._indices)})"

+

+
+
+
+

+[docs]
+@export
+class SlicedName(Name):
+	pass

+
+
+
+

+[docs]
+@export
+class SelectedName(Name):
+	"""
+	A *selected name* is a name made from multiple words separated by a dot (``.``).
+
+	For example, the library and entity name in a direct entity instantiation is a selected name. Here the entity
+	identifier is a selected name. The library identifier is a :class:`simple name <SimpleName>`, which is
+	referenced by the selected name via the :attr:`~pyVHDLModel.Name.Prefix` property.
+	"""
+
+

+[docs]
+	def __init__(self, identifier: str, prefix: Name, parent: ModelEntity = None) -> None:
+		super().__init__(identifier, prefix, parent)

+
+
+

+[docs]
+	def __str__(self) -> str:
+		return f"{self._prefix!s}.{self._identifier}"

+

+
+
+
+

+[docs]
+@export
+class AttributeName(Name):
+

+[docs]
+	def __init__(self, identifier: str, prefix: Name, parent: ModelEntity = None) -> None:
+		super().__init__(identifier, prefix, parent)

+
+
+

+[docs]
+	def __str__(self) -> str:
+		return f"{self._prefix!s}'{self._identifier}"

+

+
+
+
+

+[docs]
+@export
+class AllName(SelectedName):
+	"""
+	The *all name* represents the reserved word ``all`` used in names.
+
+	Most likely this name is used in use-statements.
+	"""
+

+[docs]
+	def __init__(self, prefix: Name, parent: ModelEntity = None) -> None:
+		super().__init__("all", prefix, parent)  # TODO: the case of 'ALL' is not preserved

+

+
+
+
+

+[docs]
+@export
+class OpenName(Name):
+	"""
+	The *open name* represents the reserved word ``open``.
+
+	Most likely this name is used in port associations.
+	"""
+

+[docs]
+	def __init__(self, parent: ModelEntity = None) -> None:
+		super().__init__("open", parent)  # TODO: the case of 'OPEN' is not preserved

+
+
+

+[docs]
+	def __str__(self) -> str:
+		return "open"

+

+
+
+ +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/_modules/pyVHDLModel/Object.html b/_modules/pyVHDLModel/Object.html new file mode 100644 index 000000000..2935f3eb2 --- /dev/null +++ b/_modules/pyVHDLModel/Object.html @@ -0,0 +1,444 @@ + + + + + + pyVHDLModel.Object — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +

Source code for pyVHDLModel.Object

+# ==================================================================================================================== #
+#             __     ___   _ ____  _     __  __           _      _                                                     #
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |                                                    #
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |                                                    #
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |                                                    #
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|                                                    #
+#  |_|    |___/                                                                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""
+This module contains parts of an abstract document language model for VHDL.
+
+Objects are constants, variables, signals and files.
+"""
+from typing                import Iterable, Optional as Nullable
+
+from pyTooling.Decorators  import export, readonly
+from pyTooling.MetaClasses import ExtendedType
+from pyTooling.Graph       import Vertex
+
+from pyVHDLModel.Base      import ModelEntity, MultipleNamedEntityMixin, DocumentedEntityMixin, ExpressionUnion
+from pyVHDLModel.Symbol    import Symbol
+
+
+

+[docs]
+@export
+class Obj(ModelEntity, MultipleNamedEntityMixin, DocumentedEntityMixin):
+	"""
+	Base-class for all objects (constants, signals, variables and files) in VHDL.
+
+	An object (syntax element) can define multiple objects (semantic elements) in a single declaration, thus
+	:class:`~pyVHDLModel.Base.MultipleNamedEntityMixin` is inherited. All objects can be documented, thus
+	:class:`~pyVHDLModel.Base.DocumentedEntityMixin` is inherited too.
+
+	Each object references a subtype via :data:`_subtype`.
+
+	Objects are elements in the type and object graph, thus a reference to a vertex in that graph is stored in
+	:data:`__objectVertex`.
+	"""
+
+	_subtype:      Symbol
+	_objectVertex: Nullable[Vertex]
+
+

+[docs]
+	def __init__(self, identifiers: Iterable[str], subtype: Symbol, documentation: Nullable[str] = None, parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+		MultipleNamedEntityMixin.__init__(self, identifiers)
+		DocumentedEntityMixin.__init__(self, documentation)
+
+		self._subtype = subtype
+		subtype._parent = self
+
+		self._objectVertex = None

+
+
+	@readonly
+	def Subtype(self) -> Symbol:
+		return self._subtype
+
+	@readonly
+	def ObjectVertex(self) -> Nullable[Vertex]:
+		"""
+		Read-only property to access the corresponding object vertex (:attr:`_objectVertex`).
+
+		The object vertex references this Object by its value field.
+
+		:returns: The corresponding object vertex.
+		"""
+		return self._objectVertex

+
+
+
+

+[docs]
+@export
+class WithDefaultExpressionMixin(metaclass=ExtendedType, mixin=True):
+	"""
+	A ``WithDefaultExpression`` is a mixin-class for all objects declarations accepting default expressions.
+
+	The default expression is referenced by :data:`__defaultExpression`. If no default expression is present, this field
+	is ``None``.
+	"""
+
+	_defaultExpression: Nullable[ExpressionUnion]
+
+

+[docs]
+	def __init__(self, defaultExpression: Nullable[ExpressionUnion] = None) -> None:
+		self._defaultExpression = defaultExpression
+		if defaultExpression is not None:
+			defaultExpression._parent = self

+
+
+	@readonly
+	def DefaultExpression(self) -> Nullable[ExpressionUnion]:
+		return self._defaultExpression

+
+
+
+

+[docs]
+@export
+class BaseConstant(Obj):
+	"""
+	Base-class for all constants (normal and deferred constants) in VHDL.
+	"""

+
+
+
+

+[docs]
+@export
+class Constant(BaseConstant, WithDefaultExpressionMixin):
+	"""
+	Represents a constant.
+
+	As constants (always) have a default expression, the class :class:`~pyVHDLModel.Object.WithDefaultExpressionMixin` is inherited.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      constant BITS : positive := 8;
+	"""
+
+

+[docs]
+	def __init__(
+		self,
+		identifiers: Iterable[str],
+		subtype: Symbol,
+		defaultExpression: Nullable[ExpressionUnion] = None,
+		documentation: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(identifiers, subtype, documentation, parent)
+		WithDefaultExpressionMixin.__init__(self, defaultExpression)

+

+
+
+
+

+[docs]
+@export
+class DeferredConstant(BaseConstant):
+	"""
+	Represents a deferred constant.
+
+	Deferred constants are forward declarations for a (complete) constant declaration, thus it contains a
+	field :data:`__constantReference` to the complete constant declaration.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      constant BITS : positive;
+	"""
+	_constantReference: Nullable[Constant]
+
+

+[docs]
+	def __init__(
+		self,
+		identifiers: Iterable[str],
+		subtype: Symbol,
+		documentation: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(identifiers, subtype, documentation, parent)

+
+
+	@readonly
+	def ConstantReference(self) -> Nullable[Constant]:
+		return self._constantReference
+
+

+[docs]
+	def __str__(self) -> str:
+		return f"constant {', '.join(self._identifiers)} : {self._subtype}"

+

+
+
+
+

+[docs]
+@export
+class Variable(Obj, WithDefaultExpressionMixin):
+	"""
+	Represents a variable.
+
+	As variables might have a default expression, the class :class:`~pyVHDLModel.Object.WithDefaultExpressionMixin` is inherited.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      variable result : natural := 0;
+	"""
+
+

+[docs]
+	def __init__(
+		self,
+		identifiers: Iterable[str],
+		subtype: Symbol,
+		defaultExpression: Nullable[ExpressionUnion] = None,
+		documentation: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(identifiers, subtype, documentation, parent)
+		WithDefaultExpressionMixin.__init__(self, defaultExpression)

+

+
+
+
+

+[docs]
+@export
+class SharedVariable(Obj):
+	"""
+	Represents a shared variable.
+
+	.. todo:: Shared variable object not implemented.
+	"""

+
+
+
+
+

+[docs]
+@export
+class Signal(Obj, WithDefaultExpressionMixin):
+	"""
+	Represents a signal.
+
+	As signals might have a default expression, the class :class:`~pyVHDLModel.Object.WithDefaultExpressionMixin` is inherited.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      signal counter : unsigned(7 downto 0) := '0';
+	"""
+
+

+[docs]
+	def __init__(
+		self,
+		identifiers: Iterable[str],
+		subtype: Symbol,
+		defaultExpression: Nullable[ExpressionUnion] = None,
+		documentation: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(identifiers, subtype, documentation, parent)
+		WithDefaultExpressionMixin.__init__(self, defaultExpression)

+

+
+
+
+

+[docs]
+@export
+class File(Obj):
+	"""
+	Represents a file.
+
+	.. todo:: File object not implemented.
+	"""

+
+
+ +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/_modules/pyVHDLModel/PSLModel.html b/_modules/pyVHDLModel/PSLModel.html new file mode 100644 index 000000000..ea501abb0 --- /dev/null +++ b/_modules/pyVHDLModel/PSLModel.html @@ -0,0 +1,253 @@ + + + + + + pyVHDLModel.PSLModel — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +

Source code for pyVHDLModel.PSLModel

+# ==================================================================================================================== #
+#             __     ___   _ ____  _     __  __           _      _                                                     #
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |                                                    #
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |                                                    #
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |                                                    #
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|                                                    #
+#  |_|    |___/                                                                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""
+This module contains an abstract document language model for PSL in VHDL.
+"""
+from pyTooling.Decorators import export
+
+from pyVHDLModel.Base       import ModelEntity, NamedEntityMixin
+from pyVHDLModel.DesignUnit import PrimaryUnit
+
+
+

+[docs]
+@export
+class PSLEntity(ModelEntity):
+	pass

+
+
+
+

+[docs]
+@export
+class PSLPrimaryUnit(PrimaryUnit):
+	pass

+
+
+
+

+[docs]
+@export
+class VerificationUnit(PSLPrimaryUnit):
+

+[docs]
+	def __init__(self, identifier: str) -> None:
+		super().__init__(identifier, parent=None)

+

+
+
+
+

+[docs]
+@export
+class VerificationProperty(PSLPrimaryUnit):
+

+[docs]
+	def __init__(self, identifier: str) -> None:
+		super().__init__(identifier, parent=None)

+

+
+
+
+

+[docs]
+@export
+class VerificationMode(PSLPrimaryUnit):
+

+[docs]
+	def __init__(self, identifier: str) -> None:
+		super().__init__(identifier, parent=None)

+

+
+
+
+

+[docs]
+@export
+class DefaultClock(PSLEntity, NamedEntityMixin):
+

+[docs]
+	def __init__(self, identifier: str) -> None:
+		super().__init__()
+		NamedEntityMixin.__init__(self, identifier)

+

+
+
+ +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/_modules/pyVHDLModel/Predefined.html b/_modules/pyVHDLModel/Predefined.html new file mode 100644 index 000000000..10aa92754 --- /dev/null +++ b/_modules/pyVHDLModel/Predefined.html @@ -0,0 +1,290 @@ + + + + + + pyVHDLModel.Predefined — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +

Source code for pyVHDLModel.Predefined

+# ==================================================================================================================== #
+#             __     ___   _ ____  _     __  __           _      _                                                     #
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |                                                    #
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |                                                    #
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |                                                    #
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|                                                    #
+#  |_|    |___/                                                                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""This module contains base-classes for predefined library and package declarations."""
+from typing                 import Iterable
+
+from pyTooling.Decorators   import export
+from pyTooling.MetaClasses  import ExtendedType
+
+from pyVHDLModel            import Library, Package, PackageBody, AllPackageMembersReferenceSymbol, PackageMemberReferenceSymbol
+from pyVHDLModel.Name       import SimpleName, SelectedName, AllName
+from pyVHDLModel.Symbol     import LibraryReferenceSymbol, PackageSymbol
+from pyVHDLModel.DesignUnit import LibraryClause, UseClause
+
+
+

+[docs]
+@export
+class PredefinedLibrary(Library):
+	"""
+	A base-class for predefined VHDL libraries.
+
+	VHDL defines 2 predefined libraries:
+
+	* :class:`~pyVHDLModel.STD.Std`
+	* :class:`~pyVHDLModel.IEEE.Ieee`
+	"""
+
+

+[docs]
+	def __init__(self, packages) -> None:
+		super().__init__(self.__class__.__name__, None)
+
+		self.AddPackages(packages)

+
+
+	def AddPackages(self, packages) -> None:
+		for packageType, packageBodyType in packages:
+			package: Package = packageType()
+			package.Library = self
+			self._packages[package.NormalizedIdentifier] = package
+
+			if packageBodyType is not None:
+				packageBody: PackageBody = packageBodyType()
+				packageBody.Library = self
+				self._packageBodies[packageBody.NormalizedIdentifier] = packageBody

+
+
+
+

+[docs]
+@export
+class PredefinedPackageMixin(metaclass=ExtendedType, mixin=True):
+	"""
+	A mixin-class for predefined VHDL packages and package bodies.
+	"""
+
+	def _AddLibraryClause(self, libraries: Iterable[str]):
+		symbols = [LibraryReferenceSymbol(SimpleName(libName)) for libName in libraries]
+		libraryClause = LibraryClause(symbols)
+
+		self._contextItems.append(libraryClause)
+		self._libraryReferences.append(libraryClause)
+
+	def _AddPackageClause(self, packages: Iterable[str]):
+		symbols = []
+		for qualifiedPackageName in packages:
+			libName, packName, members = qualifiedPackageName.split(".")
+
+			packageName = SelectedName(packName, SimpleName(libName))
+			if members.lower() == "all":
+				symbols.append(AllPackageMembersReferenceSymbol(AllName(packageName)))
+			else:
+				symbols.append(PackageMemberReferenceSymbol(SelectedName(members, packageName)))
+
+		useClause = UseClause(symbols)
+		self._contextItems.append(useClause)
+		self._packageReferences.append(useClause)

+
+
+
+

+[docs]
+@export
+class PredefinedPackage(Package, PredefinedPackageMixin):
+	"""
+	A base-class for predefined VHDL packages.
+	"""
+
+

+[docs]
+	def __init__(self) -> None:
+		super().__init__(self.__class__.__name__, parent=None)

+

+
+
+
+

+[docs]
+@export
+class PredefinedPackageBody(PackageBody, PredefinedPackageMixin):
+	"""
+	A base-class for predefined VHDL package bodies.
+	"""
+
+

+[docs]
+	def __init__(self) -> None:
+		packageSymbol = PackageSymbol(SimpleName(self.__class__.__name__[:-5]))
+		super().__init__(packageSymbol, parent=None)

+

+
+
+ +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/_modules/pyVHDLModel/Regions.html b/_modules/pyVHDLModel/Regions.html new file mode 100644 index 000000000..1c2aa804a --- /dev/null +++ b/_modules/pyVHDLModel/Regions.html @@ -0,0 +1,353 @@ + + + + + + pyVHDLModel.Regions — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +

Source code for pyVHDLModel.Regions

+# ==================================================================================================================== #
+#             __     ___   _ ____  _     __  __           _      _                                                     #
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |                                                    #
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |                                                    #
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |                                                    #
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|                                                    #
+#  |_|    |___/                                                                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""
+This module contains parts of an abstract document language model for VHDL.
+
+tbd.
+"""
+from typing                 import List, Dict, Iterable, Optional as Nullable
+
+from pyTooling.Decorators   import export, readonly
+from pyTooling.MetaClasses  import ExtendedType
+
+from pyVHDLModel.Object     import Constant, SharedVariable, File, Variable, Signal
+from pyVHDLModel.Subprogram import Subprogram, Function, Procedure
+from pyVHDLModel.Type       import Subtype, FullType
+
+
+

+[docs]
+@export
+class ConcurrentDeclarationRegionMixin(metaclass=ExtendedType, mixin=True):
+	# FIXME: define list prefix type e.g. via Union
+	_declaredItems:   List                              #: List of all declared items in this concurrent declaration region.
+
+	# _attributes:     Dict[str, Attribute]
+	# _aliases:        Dict[str, Alias]
+	_types:           Dict[str, FullType]               #: Dictionary of all types declared in this concurrent declaration region.
+	_subtypes:        Dict[str, Subtype]                #: Dictionary of all subtypes declared in this concurrent declaration region.
+	# _objects:        Dict[str, Union[Constant, Variable, Signal]]
+	_constants:       Dict[str, Constant]               #: Dictionary of all constants declared in this concurrent declaration region.
+	_signals:         Dict[str, Signal]                 #: Dictionary of all signals declared in this concurrent declaration region.
+	_sharedVariables: Dict[str, SharedVariable]         #: Dictionary of all shared variables declared in this concurrent declaration region.
+	_files:           Dict[str, File]                   #: Dictionary of all files declared in this concurrent declaration region.
+	# _subprograms:     Dict[str, Dict[str, Subprogram]]  #: Dictionary of all subprograms declared in this concurrent declaration region.
+	_functions:       Dict[str, Dict[str, Function]]    #: Dictionary of all functions declared in this concurrent declaration region.
+	_procedures:      Dict[str, Dict[str, Procedure]]   #: Dictionary of all procedures declared in this concurrent declaration region.
+
+

+[docs]
+	def __init__(self, declaredItems: Nullable[Iterable] = None) -> None:
+		# TODO: extract to mixin
+		self._declaredItems = []  # TODO: convert to dict
+		if declaredItems is not None:
+			for item in declaredItems:
+				self._declaredItems.append(item)
+				item._parent = self
+
+		self._types =       {}
+		self._subtypes =    {}
+		# self._objects =     {}
+		self._constants =   {}
+		self._signals =     {}
+		self._sharedVariables = {}
+		self._files =       {}
+		# self._subprograms = {}
+		self._functions =   {}
+		self._procedures =  {}

+
+
+	@readonly
+	def DeclaredItems(self) -> List:
+		return self._declaredItems
+
+	@readonly
+	def Types(self) -> Dict[str, FullType]:
+		return self._types
+
+	@readonly
+	def Subtypes(self) -> Dict[str, Subtype]:
+		return self._subtypes
+
+	# @readonly
+	# def Objects(self) -> Dict[str, Union[Constant, SharedVariable, Signal, File]]:
+	# 	return self._objects
+
+	@readonly
+	def Constants(self) -> Dict[str, Constant]:
+		return self._constants
+
+	@readonly
+	def Signals(self) -> Dict[str, Signal]:
+		return self._signals
+
+	@readonly
+	def SharedVariables(self) -> Dict[str, SharedVariable]:
+		return self._sharedVariables
+
+	@readonly
+	def Files(self) -> Dict[str, File]:
+		return self._files
+
+	# @readonly
+	# def Subprograms(self) -> Dict[str, Subprogram]:
+	# 	return self._subprograms
+
+	@readonly
+	def Functions(self) -> Dict[str, Dict[str, Function]]:
+		return self._functions
+
+	@readonly
+	def Procedures(self) -> Dict[str, Dict[str, Procedure]]:
+		return self._procedures
+
+

+[docs]
+	def IndexDeclaredItems(self) -> None:
+		"""
+		Index declared items listed in the concurrent declaration region.
+
+		.. rubric:: Algorithm
+
+		1. Iterate all declared items:
+
+		   * Every declared item is added to :attr:`_namespace`.
+		   * If the declared item is a :class:`~pyVHDLModel.Type.FullType`, then add an entry to :attr:`_types`.
+		   * If the declared item is a :class:`~pyVHDLModel.Type.SubType`, then add an entry to :attr:`_subtypes`.
+		   * If the declared item is a :class:`~pyVHDLModel.Subprogram.Function`, then add an entry to :attr:`_functions`.
+		   * If the declared item is a :class:`~pyVHDLModel.Subprogram.Procedure`, then add an entry to :attr:`_procedures`.
+		   * If the declared item is a :class:`~pyVHDLModel.Object.Constant`, then add an entry to :attr:`_constants`.
+		   * If the declared item is a :class:`~pyVHDLModel.Object.Signal`, then add an entry to :attr:`_signals`.
+		   * If the declared item is a :class:`~pyVHDLModel.Object.Variable`, TODO.
+		   * If the declared item is a :class:`~pyVHDLModel.Object.SharedVariable`, then add an entry to :attr:`_sharedVariables`.
+		   * If the declared item is a :class:`~pyVHDLModel.Object.File`, then add an entry to :attr:`_files`.
+		   * If the declared item is neither of these types, call :meth:`_IndexOtherDeclaredItem`. |br|
+		     Derived classes may override this virtual function.
+
+		.. seealso::
+
+		   :meth:`pyVHDLModel.Design.IndexPackages`
+		     Iterate all packages in the design and index declared items.
+		   :meth:`pyVHDLModel.Library.IndexPackages`
+		     Iterate all packages in the library and index declared items.
+		   :meth:`pyVHDLModel.Library._IndexOtherDeclaredItem`
+		     Iterate all packages in the library and index declared items.
+		"""
+		for item in self._declaredItems:
+			if isinstance(item, FullType):
+				self._types[item._normalizedIdentifier] = item
+				self._namespace._elements[item._normalizedIdentifier] = item
+			elif isinstance(item, Subtype):
+				self._subtypes[item._normalizedIdentifier] = item
+				self._namespace._elements[item._normalizedIdentifier] = item
+			elif isinstance(item, Function):
+				self._functions[item._normalizedIdentifier] = item
+				self._namespace._elements[item._normalizedIdentifier] = item
+			elif isinstance(item, Procedure):
+				self._procedures[item._normalizedIdentifier] = item
+				self._namespace._elements[item._normalizedIdentifier] = item
+			elif isinstance(item, Constant):
+				for normalizedIdentifier in item._normalizedIdentifiers:
+					self._constants[normalizedIdentifier] = item
+					self._namespace._elements[normalizedIdentifier] = item
+					# self._objects[normalizedIdentifier] = item
+			elif isinstance(item, Signal):
+				for normalizedIdentifier in item._normalizedIdentifiers:
+					self._signals[normalizedIdentifier] = item
+					self._namespace._elements[normalizedIdentifier] = item
+			elif isinstance(item, Variable):
+				print(f"IndexDeclaredItems - {item._identifiers}")
+			elif isinstance(item, SharedVariable):
+				for normalizedIdentifier in item._normalizedIdentifiers:
+					self._sharedVariables[normalizedIdentifier] = item
+					self._namespace._elements[normalizedIdentifier] = item
+			elif isinstance(item, File):
+				for normalizedIdentifier in item._normalizedIdentifiers:
+					self._files[normalizedIdentifier] = item
+					self._namespace._elements[normalizedIdentifier] = item
+			else:
+				self._IndexOtherDeclaredItem(item)

+
+
+	def _IndexOtherDeclaredItem(self, item) -> None:
+		print(f"_IndexOtherDeclaredItem - {item}\n  ({' -> '.join(t.__name__ for t in type(item).mro())})")

+
+
+ +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/_modules/pyVHDLModel/STD.html b/_modules/pyVHDLModel/STD.html new file mode 100644 index 000000000..899d29935 --- /dev/null +++ b/_modules/pyVHDLModel/STD.html @@ -0,0 +1,433 @@ + + + + + + pyVHDLModel.STD — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +

Source code for pyVHDLModel.STD

+# ==================================================================================================================== #
+#             __     ___   _ ____  _     __  __           _      _                                                     #
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |                                                    #
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |                                                    #
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |                                                    #
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|                                                    #
+#  |_|    |___/                                                                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""This module contains library and package declarations for VHDL library ``STD``."""
+
+from pyTooling.Decorators    import export
+
+from pyVHDLModel.Base        import Range, Direction
+from pyVHDLModel.Name        import SimpleName
+from pyVHDLModel.Symbol      import SimpleSubtypeSymbol
+from pyVHDLModel.Expression  import EnumerationLiteral, IntegerLiteral, PhysicalIntegerLiteral
+from pyVHDLModel.Type        import EnumeratedType, IntegerType, Subtype, PhysicalType, ArrayType
+from pyVHDLModel.Predefined  import PredefinedLibrary, PredefinedPackage, PredefinedPackageBody
+
+
+

+[docs]
+@export
+class Std(PredefinedLibrary):
+	"""
+	Predefined VHDL library ``std``.
+
+	The following predefined packages are in this library:
+
+	* :class:`~pyVHDLModel.STD.Standard`
+	* :class:`~pyVHDLModel.STD.Env`
+	* :class:`~pyVHDLModel.STD.TextIO`
+
+	.. seealso::
+
+	   Other predefined libraries:
+	     * Library :class:`~pyVHDLModel.IEEE.Ieee`
+	"""
+
+

+[docs]
+	def __init__(self) -> None:
+		super().__init__(PACKAGES)

+

+
+
+
+

+[docs]
+@export
+class Standard(PredefinedPackage):
+	"""
+	Predefined package ``std.standard``.
+
+	Predefined types:
+
+	* ``boolean``, ``boolean_vector``
+	* ``bit``, ``bit_vector``
+	* ``character``, ``string``
+	* ``integer``, ``integer_vector``
+	* ``natural``, ``positive``
+	* ``real``, ``real_vector``
+	* ``time``, ``time_vector``
+	* ``open_file_kind``, ``open_file_status``
+
+	.. seealso::
+
+	   Matching :class:`Package Body <pyVHDLModel.STD.Standard_Body>` declaration.
+	"""
+
+

+[docs]
+	def __init__(self) -> None:
+		super().__init__()
+
+		boolean = EnumeratedType("boolean", (EnumerationLiteral("false"), EnumerationLiteral("true")), None)
+		self._types[boolean._normalizedIdentifier] = boolean
+		self._declaredItems.append(boolean)
+
+		bit = EnumeratedType("bit", (EnumerationLiteral("'0'"), EnumerationLiteral("'1'")), None)
+		self._types[bit._normalizedIdentifier] = bit
+		self._declaredItems.append(bit)
+
+		chars = \
+			"nul", "soh", "stx", "etx", "eot", "enq", "ack", "bel", "bs", "ht", "lf", "vt", "ff", "cr", "so", "si", "dle", "dc1", "dc2", "dc3",\
+			"dc4", "nak", "syn", "etb", "can", "em", "sub", "esc", "fsp", "gsp", "rsp", "usp", "' '", "'!'", "'\"'", "'#'", "'$'", "'%'", "'&'", "'''",\
+			"'('", "')'", "'*'", "'+'", "','", "'-'", "'.'", "'/'", "'0'", "'1'", "'2'", "'3'", "'4'", "'5'", "'6'", "'7'", "'8'", "'9'", "':'", "';'",\
+			"'<'", "'='", "'>'", "'?'", "'@'", "'A'", "'B'", "'C'", "'D'", "'E'", "'F'", "'G'", "'H'", "'I'", "'J'", "'K'", "'L'", "'M'", "'N'", "'O'",\
+			"'P'", "'Q'", "'R'", "'S'", "'T'", "'U'", "'V'", "'W'", "'X'", "'Y'", "'Z'", "'['", "'\'", "']'", "'^'", "'_'", "'`'", "'a'", "'b'", "'c'",\
+			"'d'", "'e'", "'f'", "'g'", "'h'", "'i'", "'j'", "'k'", "'l'", "'m'", "'n'", "'o'", "'p'", "'q'", "'r'", "'s'", "'t'", "'u'", "'v'", "'w'",\
+			"'x'", "'y'", "'z'", "'{'", "'|'", "'}'", "'~'", "del", "c128", "c129", "c130", "c131", "c132", "c133", "c134", "c135", "c136", "c137", "c138", "c139",\
+			"c140", "c141", "c142", "c143", "c144", "c145", "c146", "c147", "c148", "c149", "c150", "c151", "c152", "c153", "c154", "c155", "c156", "c157", "c158", "c159",\
+			"' '", "'¡'", "'¢'", "'£'", "'¤'", "'¥'", "'¦'", "'§'", "'¨'", "'©'", "'ª'", "'«'", "'¬'", "'­'", "'®'", "'¯'", "'°'", "'±'", "'²'", "'³'",\
+			"'´'", "'µ'", "'¶'", "'·'", "'¸'", "'¹'", "'º'", "'»'", "'¼'", "'½'", "'¾'", "'¿'", "'À'", "'Á'", "'Â'", "'Ã'", "'Ä'", "'Å'", "'Æ'", "'Ç'",\
+			"'È'", "'É'", "'Ê'", "'Ë'", "'Ì'", "'Í'", "'Î'", "'Ï'", "'Ð'", "'Ñ'", "'Ò'", "'Ó'", "'Ô'", "'Õ'", "'Ö'", "'×'", "'Ø'", "'Ù'", "'Ú'", "'Û'",\
+			"'Ü'", "'Ý'", "'Þ'", "'ß'", "'à'", "'á'", "'â'", "'ã'", "'ä'", "'å'", "'æ'", "'ç'", "'è'", "'é'", "'ê'", "'ë'", "'ì'", "'í'", "'î'", "'ï'",\
+			"'ð'", "'ñ'", "'ò'", "'ó'", "'ô'", "'õ'", "'ö'", "'÷'", "'ø'", "'ù'", "'ú'", "'û'", "'ü'", "'ý'", "'þ'", "'ÿ'"
+		character = EnumeratedType("character", [EnumerationLiteral(char) for char in chars], None)
+		self._types[character._normalizedIdentifier] = character
+		self._declaredItems.append(character)
+
+		levels = "note", "warning", "error", "failure"
+		severityLevel = EnumeratedType("severityLevel", [EnumerationLiteral(level) for level in levels], None)
+		self._types[severityLevel._normalizedIdentifier] = severityLevel
+		self._declaredItems.append(severityLevel)
+
+		integer = IntegerType("integer", Range(IntegerLiteral(-2**31), IntegerLiteral(2**31 - 1), Direction.To), None)
+		self._types[integer._normalizedIdentifier] = integer
+		self._declaredItems.append(integer)
+
+		# real
+
+		time = PhysicalType("time", Range(IntegerLiteral(-2**63), IntegerLiteral(2**63 - 1), Direction.To), primaryUnit="fs", units=(
+			("ps", PhysicalIntegerLiteral(1000, "fs")),
+			("ns", PhysicalIntegerLiteral(1000, "ps")),
+			("us", PhysicalIntegerLiteral(1000, "ns")),
+			("ms", PhysicalIntegerLiteral(1000, "us")),
+			("sec", PhysicalIntegerLiteral(1000, "ms")),
+			("min", PhysicalIntegerLiteral(60, "sec")),
+			("hr", PhysicalIntegerLiteral(60, "min")),
+		), parent=None)
+		self._types[time._normalizedIdentifier] = time
+		self._declaredItems.append(time)
+
+		# delay_length
+
+		# now
+
+		natural = Subtype("natural", SimpleSubtypeSymbol(SimpleName("integer")), None)
+		natural._baseType = integer
+		natural._range = Range(IntegerLiteral(0), IntegerLiteral(2**31 - 1), Direction.To)
+		self._subtypes[natural._normalizedIdentifier] = natural
+		self._declaredItems.append(natural)
+
+		positive = Subtype("positive", SimpleSubtypeSymbol(SimpleName("integer")), None)
+		positive._baseType = integer
+		positive._range = Range(IntegerLiteral(1), IntegerLiteral(2**31 - 1), Direction.To)
+		self._subtypes[positive._normalizedIdentifier] = positive
+		self._declaredItems.append(positive)
+
+		string = ArrayType("string", (SimpleSubtypeSymbol(SimpleName("positive")),), SimpleSubtypeSymbol(SimpleName("character")), None)
+		self._types[string._normalizedIdentifier] = string
+		self._declaredItems.append(string)
+
+		booleanVector = ArrayType("boolean_vector", (SimpleSubtypeSymbol(SimpleName("natural")),), SimpleSubtypeSymbol(SimpleName("boolean")), None)
+		self._types[booleanVector._normalizedIdentifier] = booleanVector
+		self._declaredItems.append(booleanVector)
+
+		bitVector = ArrayType("bit_vector", (SimpleSubtypeSymbol(SimpleName("natural")),), SimpleSubtypeSymbol(SimpleName("bit")), None)
+		self._types[bitVector._normalizedIdentifier] = bitVector
+		self._declaredItems.append(bitVector)
+
+		integerVector = ArrayType("integer_vector", (SimpleSubtypeSymbol(SimpleName("natural")),), SimpleSubtypeSymbol(SimpleName("integer")), None)
+		self._types[integerVector._normalizedIdentifier] = integerVector
+		self._declaredItems.append(integerVector)
+
+		# real_vector
+
+		timeVector = ArrayType("time_vector", (SimpleSubtypeSymbol(SimpleName("natural")),), SimpleSubtypeSymbol(SimpleName("time")), None)
+		self._types[timeVector._normalizedIdentifier] = timeVector
+		self._declaredItems.append(timeVector)
+
+		fileOpenKinds = "read_mode", "write_mode", "append_mode"
+		openFileKind = EnumeratedType("open_file_kind", [EnumerationLiteral(kind) for kind in fileOpenKinds], None)
+		self._types[openFileKind._normalizedIdentifier] = openFileKind
+		self._declaredItems.append(openFileKind)
+
+		fileOpenStati = "open_ok", "status_error", "name_error", "mode_error"
+		fileOpenStatus = EnumeratedType("open_file_status", [EnumerationLiteral(status) for status in fileOpenStati], None)
+		self._types[fileOpenStatus._normalizedIdentifier] = fileOpenStatus
+		self._declaredItems.append(fileOpenStatus)

+

+
+
+		# attribute foreign
+
+
+

+[docs]
+@export
+class Standard_Body(PredefinedPackageBody):
+	"""
+	Predefined package body of package ``std.standard``.
+
+	.. seealso::
+
+	   Matching :class:`Package <pyVHDLModel.STD.Standard>` declaration.
+	"""

+
+
+
+

+[docs]
+@export
+class TextIO(PredefinedPackage):
+	"""
+	Predefined package ``std.textio``.
+
+	.. seealso::
+
+	   Matching :class:`Package Body <pyVHDLModel.STD.TextIO_Body>` declaration.
+	"""

+
+
+
+

+[docs]
+@export
+class TextIO_Body(PredefinedPackageBody):
+	"""
+	Predefined package body of package ``std.textio``.
+
+	.. seealso::
+
+	   Matching :class:`Package <pyVHDLModel.STD.TextIO>` declaration.
+	"""

+
+
+
+

+[docs]
+@export
+class Env(PredefinedPackage):
+	"""
+	Predefined package ``std.env``.
+
+	.. seealso::
+
+	   Matching :class:`Package Body <pyVHDLModel.STD.Env_Body>` declaration.
+	"""
+
+

+[docs]
+	def __init__(self) -> None:
+		super().__init__()
+
+		self._AddPackageClause(("work.textio.all",))

+

+
+
+
+

+[docs]
+@export
+class Env_Body(PredefinedPackageBody):
+	"""
+	Predefined package body of package ``std.env``.
+
+	.. seealso::
+
+	   Matching :class:`Package <pyVHDLModel.STD.Env>` declaration.
+	"""

+
+
+
+PACKAGES = (
+	(Standard, Standard_Body),
+	(TextIO, TextIO_Body),
+	(Env, Env_Body),
+)
+
+ +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/_modules/pyVHDLModel/Sequential.html b/_modules/pyVHDLModel/Sequential.html new file mode 100644 index 000000000..a9eea193d --- /dev/null +++ b/_modules/pyVHDLModel/Sequential.html @@ -0,0 +1,828 @@ + + + + + + pyVHDLModel.Sequential — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +

Source code for pyVHDLModel.Sequential

+# ==================================================================================================================== #
+#             __     ___   _ ____  _     __  __           _      _                                                     #
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |                                                    #
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |                                                    #
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |                                                    #
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|                                                    #
+#  |_|    |___/                                                                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""
+This module contains parts of an abstract document language model for VHDL.
+
+Declarations for sequential statements.
+"""
+from typing                  import List, Iterable, Optional as Nullable
+
+from pyTooling.Decorators    import export, readonly
+from pyTooling.MetaClasses   import ExtendedType
+
+from pyVHDLModel.Base        import ModelEntity, ExpressionUnion, Range, BaseChoice, BaseCase, ConditionalMixin, IfBranchMixin, ElsifBranchMixin
+from pyVHDLModel.Base        import ElseBranchMixin, ReportStatementMixin, AssertStatementMixin, WaveformElement
+from pyVHDLModel.Symbol      import Symbol
+from pyVHDLModel.Common      import Statement, ProcedureCallMixin
+from pyVHDLModel.Common      import SignalAssignmentMixin, VariableAssignmentMixin
+from pyVHDLModel.Association import ParameterAssociationItem
+
+
+

+[docs]
+@export
+class SequentialStatement(Statement):
+	"""A ``SequentialStatement`` is a base-class for all sequential statements."""

+
+
+
+

+[docs]
+@export
+class SequentialStatementsMixin(metaclass=ExtendedType, mixin=True):
+	_statements: List[SequentialStatement]
+
+

+[docs]
+	def __init__(self, statements: Nullable[Iterable[SequentialStatement]] = None) -> None:
+		# TODO: extract to mixin
+		self._statements = []
+		if statements is not None:
+			for item in statements:
+				self._statements.append(item)
+				item._parent = self

+
+
+	@readonly
+	def Statements(self) -> List[SequentialStatement]:
+		"""
+		Read-only property to access the list of sequential statements (:attr:`_statements`).
+
+		:returns: A list of sequential statements.
+		"""
+		return self._statements

+
+
+
+

+[docs]
+@export
+class SequentialProcedureCall(SequentialStatement, ProcedureCallMixin):
+

+[docs]
+	def __init__(
+		self,
+		procedureName: Symbol,
+		parameterMappings: Nullable[Iterable[ParameterAssociationItem]] = None,
+		label: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(label, parent)
+		ProcedureCallMixin.__init__(self, procedureName, parameterMappings)

+

+
+
+
+

+[docs]
+@export
+class SequentialSignalAssignment(SequentialStatement, SignalAssignmentMixin):
+

+[docs]
+	def __init__(self, target: Symbol, label: Nullable[str] = None, parent: ModelEntity = None) -> None:
+		super().__init__(label, parent)
+		SignalAssignmentMixin.__init__(self, target)

+

+
+
+
+

+[docs]
+@export
+class SequentialSimpleSignalAssignment(SequentialSignalAssignment):
+	_waveform: List[WaveformElement]
+
+

+[docs]
+	def __init__(self, target: Symbol, waveform: Iterable[WaveformElement], label: Nullable[str] = None, parent: ModelEntity = None) -> None:
+		super().__init__(target, label, parent)
+
+		# TODO: extract to mixin
+		self._waveform = []
+		if waveform is not None:
+			for waveformElement in waveform:
+				self._waveform.append(waveformElement)
+				waveformElement._parent = self

+
+
+	@readonly
+	def Waveform(self) -> List[WaveformElement]:
+		"""
+		Read-only property to access the list waveform elements (:attr:`_waveform`).
+
+		:returns: A list of waveform elements.
+		"""
+		return self._waveform

+
+
+
+

+[docs]
+@export
+class SequentialVariableAssignment(SequentialStatement, VariableAssignmentMixin):
+

+[docs]
+	def __init__(self, target: Symbol, expression: ExpressionUnion, label: Nullable[str] = None, parent: ModelEntity = None) -> None:
+		super().__init__(label, parent)
+		VariableAssignmentMixin.__init__(self, target, expression)

+

+
+
+
+

+[docs]
+@export
+class SequentialReportStatement(SequentialStatement, ReportStatementMixin):
+

+[docs]
+	def __init__(self, message: ExpressionUnion, severity: Nullable[ExpressionUnion] = None, label: Nullable[str] = None, parent: ModelEntity = None) -> None:
+		super().__init__(label, parent)
+		ReportStatementMixin.__init__(self, message, severity)

+

+
+
+
+

+[docs]
+@export
+class SequentialAssertStatement(SequentialStatement, AssertStatementMixin):
+

+[docs]
+	def __init__(
+		self,
+		condition: ExpressionUnion,
+		message: Nullable[ExpressionUnion] = None,
+		severity: Nullable[ExpressionUnion] = None,
+		label: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(label, parent)
+		AssertStatementMixin.__init__(self, condition, message, severity)

+

+
+
+
+

+[docs]
+@export
+class CompoundStatement(SequentialStatement):
+	"""A ``CompoundStatement`` is a base-class for all compound statements."""

+
+
+
+

+[docs]
+@export
+class Branch(ModelEntity, SequentialStatementsMixin):
+	"""A ``Branch`` is a base-class for all branches in a if statement."""
+
+

+[docs]
+	def __init__(self, statements: Nullable[Iterable[SequentialStatement]] = None, parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+		SequentialStatementsMixin.__init__(self, statements)

+

+
+
+
+

+[docs]
+@export
+class IfBranch(Branch, IfBranchMixin):
+

+[docs]
+	def __init__(self, condition: ExpressionUnion, statements: Nullable[Iterable[SequentialStatement]] = None, parent: ModelEntity = None) -> None:
+		super().__init__(statements, parent)
+		IfBranchMixin.__init__(self, condition)

+

+
+
+
+

+[docs]
+@export
+class ElsifBranch(Branch, ElsifBranchMixin):
+

+[docs]
+	def __init__(self, condition: ExpressionUnion, statements: Nullable[Iterable[SequentialStatement]] = None, parent: ModelEntity = None) -> None:
+		super().__init__(statements, parent)
+		ElsifBranchMixin.__init__(self, condition)

+

+
+
+
+

+[docs]
+@export
+class ElseBranch(Branch, ElseBranchMixin):
+

+[docs]
+	def __init__(self, statements: Nullable[Iterable[SequentialStatement]] = None, parent: ModelEntity = None) -> None:
+		super().__init__(statements, parent)
+		ElseBranchMixin.__init__(self)

+

+
+
+
+

+[docs]
+@export
+class IfStatement(CompoundStatement):
+	_ifBranch: IfBranch
+	_elsifBranches: List['ElsifBranch']
+	_elseBranch: Nullable[ElseBranch]
+
+

+[docs]
+	def __init__(
+		self,
+		ifBranch: IfBranch,
+		elsifBranches: Nullable[Iterable[ElsifBranch]] = None,
+		elseBranch: Nullable[ElseBranch] = None,
+		label: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(label, parent)
+
+		self._ifBranch = ifBranch
+		ifBranch._parent = self
+
+		self._elsifBranches = []
+		if elsifBranches is not None:
+			for branch in elsifBranches:
+				self._elsifBranches.append(branch)
+				branch._parent = self
+
+		if elseBranch is not None:
+			self._elseBranch = elseBranch
+			elseBranch._parent = self
+		else:
+			self._elseBranch = None

+
+
+	@readonly
+	def IfBranch(self) -> IfBranch:
+		"""
+		Read-only property to access the if-branch of the if-statement (:attr:`_ifBranch`).
+
+		:returns: The if-branch.
+		"""
+		return self._ifBranch
+
+	@property
+	def ElsIfBranches(self) -> List['ElsifBranch']:
+		"""
+		Read-only property to access the elsif-branch of the if-statement (:attr:`_elsifBranch`).
+
+		:returns: The elsif-branch.
+		"""
+		return self._elsifBranches
+
+	@property
+	def ElseBranch(self) -> Nullable[ElseBranch]:
+		"""
+		Read-only property to access the else-branch of the if-statement (:attr:`_elseBranch`).
+
+		:returns: The else-branch.
+		"""
+		return self._elseBranch

+
+
+
+

+[docs]
+@export
+class SequentialChoice(BaseChoice):
+	"""A ``SequentialChoice`` is a base-class for all sequential choices (in case statements)."""

+
+
+
+

+[docs]
+@export
+class IndexedChoice(SequentialChoice):
+	_expression: ExpressionUnion
+
+

+[docs]
+	def __init__(self, expression: ExpressionUnion, parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+
+		self._expression = expression

+
+		# expression._parent = self    # FIXME: received None
+
+	@property
+	def Expression(self) -> ExpressionUnion:
+		return self._expression
+
+

+[docs]
+	def __str__(self) -> str:
+		return str(self._expression)

+

+
+
+
+

+[docs]
+@export
+class RangedChoice(SequentialChoice):
+	_range: 'Range'
+
+

+[docs]
+	def __init__(self, rng: 'Range', parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+
+		self._range = rng
+		rng._parent = self

+
+
+	@property
+	def Range(self) -> 'Range':
+		return self._range
+
+

+[docs]
+	def __str__(self) -> str:
+		return str(self._range)

+

+
+
+
+

+[docs]
+@export
+class SequentialCase(BaseCase, SequentialStatementsMixin):
+	_choices: List
+
+

+[docs]
+	def __init__(self, statements: Nullable[Iterable[SequentialStatement]] = None, parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+		SequentialStatementsMixin.__init__(self, statements)

+
+
+		# TODO: what about choices?
+
+	@property
+	def Choices(self) -> List[BaseChoice]:
+		return self._choices

+
+
+
+

+[docs]
+@export
+class Case(SequentialCase):
+

+[docs]
+	def __init__(self, choices: Iterable[SequentialChoice], statements: Nullable[Iterable[SequentialStatement]] = None, parent: ModelEntity = None) -> None:
+		super().__init__(statements, parent)
+
+		self._choices = []
+		if choices is not None:
+			for choice in choices:
+				self._choices.append(choice)
+				choice._parent = self

+
+
+	@property
+	def Choices(self) -> List[SequentialChoice]:
+		return self._choices
+
+

+[docs]
+	def __str__(self) -> str:
+		return "when {choices} =>".format(choices=" | ".join(str(c) for c in self._choices))

+

+
+
+
+

+[docs]
+@export
+class OthersCase(SequentialCase):
+

+[docs]
+	def __str__(self) -> str:
+		return "when others =>"

+

+
+
+
+

+[docs]
+@export
+class CaseStatement(CompoundStatement):
+	_expression: ExpressionUnion
+	_cases:      List[SequentialCase]
+
+

+[docs]
+	def __init__(self, expression: ExpressionUnion, cases: Iterable[SequentialCase], label: Nullable[str] = None, parent: ModelEntity = None) -> None:
+		super().__init__(label, parent)
+
+		self._expression = expression
+		expression._parent = self
+
+		self._cases = []
+		if cases is not None:
+			for case in cases:
+				self._cases.append(case)
+				case._parent = self

+
+
+	@property
+	def SelectExpression(self) -> ExpressionUnion:
+		return self._expression
+
+	@property
+	def Cases(self) -> List[SequentialCase]:
+		return self._cases

+
+
+
+

+[docs]
+@export
+class LoopStatement(CompoundStatement, SequentialStatementsMixin):
+	"""A ``LoopStatement`` is a base-class for all loop statements."""
+
+

+[docs]
+	def __init__(self, statements: Nullable[Iterable[SequentialStatement]] = None, label: Nullable[str] = None, parent: ModelEntity = None) -> None:
+		super().__init__(label, parent)
+		SequentialStatementsMixin.__init__(self, statements)

+

+
+
+
+

+[docs]
+@export
+class EndlessLoopStatement(LoopStatement):
+	pass

+
+
+
+

+[docs]
+@export
+class ForLoopStatement(LoopStatement):
+	_loopIndex: str
+	_range:     Range
+
+

+[docs]
+	def __init__(self, loopIndex: str, rng: Range, statements: Nullable[Iterable[SequentialStatement]] = None, label: Nullable[str] = None, parent: ModelEntity = None) -> None:
+		super().__init__(statements, label, parent)
+
+		self._loopIndex = loopIndex
+
+		self._range = rng
+		rng._parent = self

+
+
+	@property
+	def LoopIndex(self) -> str:
+		return self._loopIndex
+
+	@property
+	def Range(self) -> Range:
+		return self._range

+
+
+
+

+[docs]
+@export
+class WhileLoopStatement(LoopStatement, ConditionalMixin):
+

+[docs]
+	def __init__(
+		self,
+		condition: ExpressionUnion,
+		statements: Nullable[Iterable[SequentialStatement]] = None,
+		label: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(statements, label, parent)
+		ConditionalMixin.__init__(self, condition)

+

+
+
+
+

+[docs]
+@export
+class LoopControlStatement(SequentialStatement, ConditionalMixin):
+	"""A ``LoopControlStatement`` is a base-class for all loop controlling statements."""
+
+	_loopReference: LoopStatement
+
+

+[docs]
+	def __init__(self, condition: Nullable[ExpressionUnion] = None, loopLabel: Nullable[str] = None, parent: ModelEntity = None) -> None:  # TODO: is this label (currently str) a Name or a Label class?
+		super().__init__(parent)
+		ConditionalMixin.__init__(self, condition)

+
+
+		# TODO: loopLabel
+		# TODO: loop reference -> is it a symbol?
+
+	@property
+	def LoopReference(self) -> LoopStatement:
+		return self._loopReference

+
+
+
+

+[docs]
+@export
+class NextStatement(LoopControlStatement):
+	pass

+
+
+
+

+[docs]
+@export
+class ExitStatement(LoopControlStatement):
+	pass

+
+
+
+

+[docs]
+@export
+class NullStatement(SequentialStatement):
+	pass

+
+
+
+

+[docs]
+@export
+class ReturnStatement(SequentialStatement, ConditionalMixin):
+	_returnValue: ExpressionUnion
+
+

+[docs]
+	def __init__(self, returnValue: Nullable[ExpressionUnion] = None, parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+		ConditionalMixin.__init__(self, returnValue)

+
+
+		# TODO: return value?
+
+	@property
+	def ReturnValue(self) -> ExpressionUnion:
+		return self._returnValue

+
+
+
+

+[docs]
+@export
+class WaitStatement(SequentialStatement, ConditionalMixin):
+	_sensitivityList: Nullable[List[Symbol]]
+	_timeout:         ExpressionUnion
+
+

+[docs]
+	def __init__(
+		self,
+		sensitivityList: Nullable[Iterable[Symbol]] = None,
+		condition: Nullable[ExpressionUnion] = None,
+		timeout: Nullable[ExpressionUnion] = None,
+		label: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(label, parent)
+		ConditionalMixin.__init__(self, condition)
+
+		if sensitivityList is None:
+			self._sensitivityList = None
+		else:
+			self._sensitivityList = []  # TODO: convert to dict
+			for signalSymbol in sensitivityList:
+				self._sensitivityList.append(signalSymbol)
+				signalSymbol._parent = self
+
+		self._timeout = timeout
+		if timeout is not None:
+			timeout._parent = self

+
+
+	@property
+	def SensitivityList(self) -> List[Symbol]:
+		return self._sensitivityList
+
+	@property
+	def Timeout(self) -> ExpressionUnion:
+		return self._timeout

+
+
+
+

+[docs]
+@export
+class SequentialDeclarationsMixin(metaclass=ExtendedType, mixin=True):
+	_declaredItems: List
+
+

+[docs]
+	def __init__(self, declaredItems: Iterable) -> None:
+		# TODO: extract to mixin
+		self._declaredItems = []  # TODO: convert to dict
+		if declaredItems is not None:
+			for item in declaredItems:
+				self._declaredItems.append(item)
+				item._parent = self

+
+
+	@property
+	def DeclaredItems(self) -> List:
+		return self._declaredItems

+
+
+ +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/_modules/pyVHDLModel/Subprogram.html b/_modules/pyVHDLModel/Subprogram.html new file mode 100644 index 000000000..fad4761a5 --- /dev/null +++ b/_modules/pyVHDLModel/Subprogram.html @@ -0,0 +1,319 @@ + + + + + + pyVHDLModel.Subprogram — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +

Source code for pyVHDLModel.Subprogram

+# ==================================================================================================================== #
+#             __     ___   _ ____  _     __  __           _      _                                                     #
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |                                                    #
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |                                                    #
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |                                                    #
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|                                                    #
+#  |_|    |___/                                                                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""
+This module contains parts of an abstract document language model for VHDL.
+
+Subprograms are procedures, functions and methods.
+"""
+from typing                 import List, Optional as Nullable
+
+from pyTooling.Decorators   import export, readonly
+from pyTooling.MetaClasses  import ExtendedType
+
+from pyVHDLModel.Base       import ModelEntity, NamedEntityMixin, DocumentedEntityMixin
+from pyVHDLModel.Type       import Subtype, ProtectedType
+from pyVHDLModel.Sequential import SequentialStatement
+
+
+

+[docs]
+@export
+class Subprogram(ModelEntity, NamedEntityMixin, DocumentedEntityMixin):
+	_genericItems:   List['GenericInterfaceItem']
+	_parameterItems: List['ParameterInterfaceItem']
+	_declaredItems:  List
+	_statements:     List['SequentialStatement']
+	_isPure:         bool
+
+

+[docs]
+	def __init__(self, identifier: str, isPure: bool, documentation: Nullable[str] = None, parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+		NamedEntityMixin.__init__(self, identifier)
+		DocumentedEntityMixin.__init__(self, documentation)
+
+		self._genericItems =    []  # TODO: convert to dict
+		self._parameterItems =  []  # TODO: convert to dict
+		self._declaredItems =   []  # TODO: use mixin class
+		self._statements =      []  # TODO: use mixin class
+		self._isPure =          isPure

+
+
+	@readonly
+	def GenericItems(self) -> List['GenericInterfaceItem']:
+		return self._genericItems
+
+	@readonly
+	def ParameterItems(self) -> List['ParameterInterfaceItem']:
+		return self._parameterItems
+
+	@readonly
+	def DeclaredItems(self) -> List:
+		return self._declaredItems
+
+	@readonly
+	def Statements(self) -> List['SequentialStatement']:
+		return self._statements
+
+	@readonly
+	def IsPure(self) -> bool:
+		return self._isPure

+
+
+
+

+[docs]
+@export
+class Procedure(Subprogram):
+

+[docs]
+	def __init__(self, identifier: str, documentation: Nullable[str] = None, parent: ModelEntity = None) -> None:
+		super().__init__(identifier, False, documentation, parent)

+

+
+
+
+

+[docs]
+@export
+class Function(Subprogram):
+	_returnType: Subtype
+
+

+[docs]
+	def __init__(self, identifier: str, isPure: bool = True, documentation: Nullable[str] = None, parent: ModelEntity = None) -> None:
+		super().__init__(identifier, isPure, documentation, parent)

+
+
+		# FIXME: return type is missing
+
+	@readonly
+	def ReturnType(self) -> Subtype:
+		return self._returnType

+
+
+
+

+[docs]
+@export
+class MethodMixin(metaclass=ExtendedType, mixin=True):
+	"""A ``Method`` is a mixin class for all subprograms in a protected type."""
+
+	_protectedType: ProtectedType
+
+

+[docs]
+	def __init__(self, protectedType: ProtectedType) -> None:
+		self._protectedType = protectedType
+		protectedType._parent = self

+
+
+	@readonly
+	def ProtectedType(self) -> ProtectedType:
+		return self._protectedType

+
+
+
+

+[docs]
+@export
+class ProcedureMethod(Procedure, MethodMixin):
+

+[docs]
+	def __init__(self, identifier: str, documentation: Nullable[str] = None, protectedType: Nullable[ProtectedType] = None, parent: ModelEntity = None) -> None:
+		super().__init__(identifier, documentation, parent)
+		MethodMixin.__init__(self, protectedType)

+

+
+
+
+

+[docs]
+@export
+class FunctionMethod(Function, MethodMixin):
+

+[docs]
+	def __init__(self, identifier: str, isPure: bool = True, documentation: Nullable[str] = None, protectedType: Nullable[ProtectedType] = None, parent: ModelEntity = None) -> None:
+		super().__init__(identifier, isPure, documentation, parent)
+		MethodMixin.__init__(self, protectedType)

+

+
+
+ +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/_modules/pyVHDLModel/Symbol.html b/_modules/pyVHDLModel/Symbol.html new file mode 100644 index 000000000..8725da9e2 --- /dev/null +++ b/_modules/pyVHDLModel/Symbol.html @@ -0,0 +1,751 @@ + + + + + + pyVHDLModel.Symbol — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +

Source code for pyVHDLModel.Symbol

+# ==================================================================================================================== #
+#             __     ___   _ ____  _     __  __           _      _                                                     #
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |                                                    #
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |                                                    #
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |                                                    #
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|                                                    #
+#  |_|    |___/                                                                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""
+This module contains parts of an abstract document language model for VHDL.
+
+Symbols are entity specific wrappers for names that reference VHDL language entities.
+"""
+from enum                  import Flag, auto
+from typing                import Any, Optional as Nullable, Iterable, List, Dict, Mapping
+
+from pyTooling.Decorators  import export, readonly
+from pyTooling.MetaClasses import ExtendedType
+
+from pyVHDLModel.Base      import Range
+from pyVHDLModel.Name      import Name, AllName
+
+
+

+[docs]
+@export
+class PossibleReference(Flag):
+	"""
+	Is an enumeration, representing possible targets for a reference in a :class:`~pyVHDLModel.Symbol`.
+	"""
+
+	Unknown =         0
+	Library =         auto()  #: Library
+	Entity =          auto()  #: Entity
+	Architecture =    auto()  #: Architecture
+	Component =       auto()  #: Component
+	Package =         auto()  #: Package
+	Configuration =   auto()  #: Configuration
+	Context =         auto()  #: Context
+	Type =            auto()  #: Type
+	Subtype =         auto()  #: Subtype
+	ScalarType =      auto()  #: ScalarType
+	ArrayType =       auto()  #: ArrayType
+	RecordType =      auto()  #: RecordType
+	RecordElement =   auto()  #: RecordElement
+	AccessType =      auto()  #: AccessType
+	ProtectedType =   auto()  #: ProtectedType
+	FileType =        auto()  #: FileType
+#	Alias =           auto()   # TODO: Is this needed?
+	Attribute =       auto()  #: Attribute
+	TypeAttribute =   auto()  #: TypeAttribute
+	ValueAttribute =  auto()  #: ValueAttribute
+	SignalAttribute = auto()  #: SignalAttribute
+	RangeAttribute =  auto()  #: RangeAttribute
+	ViewAttribute =   auto()  #: ViewAttribute
+	Constant =        auto()  #: Constant
+	Variable =        auto()  #: Variable
+	Signal =          auto()  #: Signal
+	File =            auto()  #: File
+#	Object =          auto()   # TODO: Is this needed?
+	EnumLiteral =     auto()  #: EnumLiteral
+	Procedure =       auto()  #: Procedure
+	Function =        auto()  #: Function
+	Label =           auto()  #: Label
+	View =            auto()  #: View
+
+	AnyType = ScalarType | ArrayType | RecordType | ProtectedType | AccessType | FileType | Subtype  #: Any possible type incl. subtypes.
+	Object = Constant | Variable | Signal  # | File                                                     #: Any object
+	SubProgram = Procedure | Function                                                                #: Any subprogram
+	PackageMember = AnyType | Object | SubProgram | Component                                        #: Any member of a package
+	SimpleNameInExpression = Constant | Variable | Signal | ScalarType | EnumLiteral | Function      #: Any possible item in an expression.

+
+
+
+

+[docs]
+@export
+class Symbol(metaclass=ExtendedType):
+	"""
+	Base-class for all symbol classes.
+	"""
+
+	_name:               Name               #: The name to reference the langauge entity.
+	_possibleReferences: PossibleReference  #: An enumeration to filter possible references.
+	_reference:          Nullable[Any]      #: The resolved language entity, otherwise ``None``.
+
+

+[docs]
+	def __init__(self, name: Name, possibleReferences: PossibleReference) -> None:
+		self._name = name
+		self._possibleReferences = possibleReferences
+		self._reference = None

+
+
+	@readonly
+	def Name(self) -> Name:
+		return self._name
+
+	@readonly
+	def Reference(self) -> Nullable[Any]:
+		return self._reference
+
+	@readonly
+	def IsResolved(self) -> bool:
+		return self._reference is not None
+
+	def __bool__(self) -> bool:
+		return self._reference is not None
+
+

+[docs]
+	def __repr__(self) -> str:
+		if self._reference is not None:
+			return f"{self.__class__.__name__}: '{self._name!s}' -> {self._reference!s}"
+
+		return f"{self.__class__.__name__}: '{self._name!s}' -> unresolved"

+
+
+

+[docs]
+	def __str__(self) -> str:
+		if self._reference is not None:
+			return str(self._reference)
+
+		return f"{self._name!s}?"

+

+
+
+
+

+[docs]
+@export
+class LibraryReferenceSymbol(Symbol):
+	"""
+	Represents a reference (name) to a library.
+
+	The internal name will be a :class:`~pyVHDLModel.Name.SimpleName`.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      library ieee;
+	      --      ^^^^
+	"""
+
+

+[docs]
+	def __init__(self, name: Name) -> None:
+		super().__init__(name, PossibleReference.Library)

+
+
+	@readonly
+	def Library(self) -> Nullable['Library']:
+		return self._reference
+
+	@Library.setter
+	def Library(self, value: 'Library') -> None:
+		self._reference = value

+
+
+
+

+[docs]
+@export
+class PackageReferenceSymbol(Symbol):
+	"""
+	Represents a reference (name) to a package.
+
+	The internal name will be a :class:`~pyVHDLModel.Name.SelectedName`.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      use ieee.numeric_std;
+	      --  ^^^^^^^^^^^^^^^^
+	"""
+
+

+[docs]
+	def __init__(self, name: Name) -> None:
+		super().__init__(name, PossibleReference.Package)

+
+
+	@property
+	def Package(self) -> Nullable['Package']:
+		return self._reference
+
+	@Package.setter
+	def Package(self, value: 'Package') -> None:
+		self._reference = value

+
+
+
+

+[docs]
+@export
+class ContextReferenceSymbol(Symbol):
+	"""
+	Represents a reference (name) to a context.
+
+	The internal name will be a :class:`~pyVHDLModel.Name.SelectedName`.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      context ieee.ieee_std_context;
+	      --      ^^^^^^^^^^^^^^^^^^^^^
+	"""
+
+

+[docs]
+	def __init__(self, name: Name) -> None:
+		super().__init__(name, PossibleReference.Context)

+
+
+	@property
+	def Context(self) -> 'Context':
+		return self._reference
+
+	@Context.setter
+	def Context(self, value: 'Context') -> None:
+		self._reference = value

+
+
+
+

+[docs]
+@export
+class PackageMemberReferenceSymbol(Symbol):
+	"""
+	Represents a reference (name) to a package member.
+
+	The internal name will be a :class:`~pyVHDLModel.Name.SelectedName`.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      use ieee.numeric_std.unsigned;
+	      --  ^^^^^^^^^^^^^^^^^^^^^^^^^
+	"""
+
+

+[docs]
+	def __init__(self, name: Name) -> None:
+		super().__init__(name, PossibleReference.PackageMember)

+
+
+	@property
+	def Member(self) -> Nullable['Package']:  # TODO: typehint
+		return self._reference
+
+	@Member.setter
+	def Member(self, value: 'Package') -> None:  # TODO: typehint
+		self._reference = value

+
+
+
+

+[docs]
+@export
+class AllPackageMembersReferenceSymbol(Symbol):
+	"""
+	Represents a reference (name) to all package members.
+
+	The internal name will be a :class:`~pyVHDLModel.Name.AllName`.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      use ieee.numeric_std.all;
+	      --  ^^^^^^^^^^^^^^^^^^^^
+	"""
+
+

+[docs]
+	def __init__(self, name: AllName) -> None:
+		super().__init__(name, PossibleReference.PackageMember)

+
+
+	@property
+	def Members(self) -> 'Package':  # TODO: typehint
+		return self._reference
+
+	@Members.setter
+	def Members(self, value: 'Package') -> None:  # TODO: typehint
+		self._reference = value

+
+
+
+

+[docs]
+@export
+class EntityInstantiationSymbol(Symbol):
+	"""
+	Represents a reference (name) to an entity in a direct entity instantiation.
+
+	The internal name will be a :class:`~pyVHDLModel.Name.SimpleName` or :class:`~pyVHDLModel.Name.SelectedName`.
+
+	.. admonition:: Example
+
+	    .. code-block:: VHDL
+
+	       inst : entity work.Counter;
+	       --            ^^^^^^^^^^^^
+	"""
+
+

+[docs]
+	def __init__(self, name: Name) -> None:
+		super().__init__(name, PossibleReference.Entity)

+
+
+	@property
+	def Entity(self) -> 'Entity':
+		return self._reference
+
+	@Entity.setter
+	def Entity(self, value: 'Entity') -> None:
+		self._reference = value

+
+
+
+

+[docs]
+@export
+class ComponentInstantiationSymbol(Symbol):
+	"""
+	Represents a reference (name) to an entity in a component instantiation.
+
+	The internal name will be a :class:`~pyVHDLModel.Name.SimpleName` or :class:`~pyVHDLModel.Name.SelectedName`.
+
+	.. admonition:: Example
+
+	    .. code-block:: VHDL
+
+	       inst : component Counter;
+	       --               ^^^^^^^
+	"""
+
+

+[docs]
+	def __init__(self, name: Name) -> None:
+		super().__init__(name, PossibleReference.Component)

+
+
+	@property
+	def Component(self) -> 'Component':
+		return self._reference
+
+	@Component.setter
+	def Component(self, value: 'Component') -> None:
+		self._reference = value

+
+
+
+

+[docs]
+@export
+class ConfigurationInstantiationSymbol(Symbol):
+	"""
+	Represents a reference (name) to an entity in a configuration instantiation.
+
+	The internal name will be a :class:`~pyVHDLModel.Name.SimpleName` or :class:`~pyVHDLModel.Name.SelectedName`.
+
+	.. admonition:: Example
+
+	    .. code-block:: VHDL
+
+	       inst : configuration Counter;
+	       --                   ^^^^^^^
+	"""
+
+

+[docs]
+	def __init__(self, name: Name) -> None:
+		super().__init__(name, PossibleReference.Configuration)

+
+
+	@property
+	def Configuration(self) -> 'Configuration':
+		return self._reference
+
+	@Configuration.setter
+	def Configuration(self, value: 'Configuration') -> None:
+		self._reference = value

+
+
+
+

+[docs]
+@export
+class EntitySymbol(Symbol):
+	"""
+	Represents a reference (name) to an entity in an architecture declaration.
+
+	The internal name will be a :class:`~pyVHDLModel.Name.SimpleName` or :class:`~pyVHDLModel.Name.SelectedName`.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      architecture rtl of Counter is
+	      --                  ^^^^^^^
+	      begin
+	      end architecture;
+	"""
+
+

+[docs]
+	def __init__(self, name: Name) -> None:
+		super().__init__(name, PossibleReference.Entity)

+
+
+	@property
+	def Entity(self) -> 'Entity':
+		return self._reference
+
+	@Entity.setter
+	def Entity(self, value: 'Entity') -> None:
+		self._reference = value

+
+
+
+

+[docs]
+@export
+class ArchitectureSymbol(Symbol):
+	"""An entity reference in an entity instantiation with architecture name."""
+
+

+[docs]
+	def __init__(self, name: Name) -> None:
+		super().__init__(name, PossibleReference.Architecture)

+
+
+	@property
+	def Architecture(self) -> 'Architecture':
+		return self._reference
+
+	@Architecture.setter
+	def Architecture(self, value: 'Architecture') -> None:
+		self._reference = value

+
+
+
+

+[docs]
+@export
+class PackageSymbol(Symbol):
+	"""
+	Represents a reference (name) to a package in a package body declaration.
+
+	The internal name will be a :class:`~pyVHDLModel.Name.SimpleName` or :class:`~pyVHDLModel.Name.SelectedName`.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      package body Utilities is
+	      --           ^^^^^^^^^
+	      end package body;
+	"""
+
+

+[docs]
+	def __init__(self, name: Name) -> None:
+		super().__init__(name, PossibleReference.Package)

+
+
+	@property
+	def Package(self) -> 'Package':
+		return self._reference
+
+	@Package.setter
+	def Package(self, value: 'Package') -> None:
+		self._reference = value

+
+
+
+

+[docs]
+@export
+class RecordElementSymbol(Symbol):
+

+[docs]
+	def __init__(self, name: Name) -> None:
+		super().__init__(name, PossibleReference.RecordElement)

+

+
+
+
+

+[docs]
+@export
+class SubtypeSymbol(Symbol):
+

+[docs]
+	def __init__(self, name: Name) -> None:
+		super().__init__(name, PossibleReference.Type | PossibleReference.Subtype)

+
+
+	@property
+	def Subtype(self) -> 'Subtype':
+		return self._reference
+
+	@Subtype.setter
+	def Subtype(self, value: 'Subtype') -> None:
+		self._reference = value

+
+
+
+

+[docs]
+@export
+class SimpleSubtypeSymbol(SubtypeSymbol):
+	pass

+
+
+
+

+[docs]
+@export
+class ConstrainedScalarSubtypeSymbol(SubtypeSymbol):
+	pass

+
+
+
+

+[docs]
+@export
+class ConstrainedCompositeSubtypeSymbol(SubtypeSymbol):
+	pass

+
+
+
+

+[docs]
+@export
+class ConstrainedArraySubtypeSymbol(ConstrainedCompositeSubtypeSymbol):
+	pass

+
+
+
+

+[docs]
+@export
+class ConstrainedRecordSubtypeSymbol(ConstrainedCompositeSubtypeSymbol):
+	pass

+
+
+
+

+[docs]
+@export
+class SimpleObjectOrFunctionCallSymbol(Symbol):
+

+[docs]
+	def __init__(self, name: Name) -> None:
+		super().__init__(name, PossibleReference.SimpleNameInExpression)

+

+
+
+
+

+[docs]
+@export
+class IndexedObjectOrFunctionCallSymbol(Symbol):
+

+[docs]
+	def __init__(self, name: Name) -> None:
+		super().__init__(name, PossibleReference.Object | PossibleReference.Function)

+

+
+
+ +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/_modules/pyVHDLModel/Type.html b/_modules/pyVHDLModel/Type.html new file mode 100644 index 000000000..b76f2122d --- /dev/null +++ b/_modules/pyVHDLModel/Type.html @@ -0,0 +1,670 @@ + + + + + + pyVHDLModel.Type — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +

Source code for pyVHDLModel.Type

+# ==================================================================================================================== #
+#             __     ___   _ ____  _     __  __           _      _                                                     #
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |                                                    #
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |                                                    #
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |                                                    #
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|                                                    #
+#  |_|    |___/                                                                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""
+This module contains parts of an abstract document language model for VHDL.
+
+Types.
+"""
+from typing                 import Union, List, Iterator, Iterable, Tuple, Optional as Nullable, Dict, Mapping
+
+from pyTooling.Decorators   import export, readonly
+from pyTooling.MetaClasses  import ExtendedType
+from pyTooling.Graph        import Vertex
+
+from pyVHDLModel.Base       import ModelEntity, NamedEntityMixin, MultipleNamedEntityMixin, DocumentedEntityMixin, ExpressionUnion, Range
+from pyVHDLModel.Symbol     import Symbol
+from pyVHDLModel.Name       import Name
+from pyVHDLModel.Expression import EnumerationLiteral, PhysicalIntegerLiteral
+
+
+

+[docs]
+@export
+class BaseType(ModelEntity, NamedEntityMixin, DocumentedEntityMixin):
+	"""``BaseType`` is the base-class of all type entities in this model."""
+
+	_objectVertex: Vertex
+
+

+[docs]
+	def __init__(self, identifier: str, documentation: Nullable[str] = None, parent: ModelEntity = None) -> None:
+		"""
+		Initializes underlying ``BaseType``.
+
+		:param identifier: Name of the type.
+		:param parent:     Reference to the logical parent in the model hierarchy.
+		"""
+		super().__init__(parent)
+		NamedEntityMixin.__init__(self, identifier)
+		DocumentedEntityMixin.__init__(self, documentation)
+
+		_objectVertex = None

+

+
+
+
+

+[docs]
+@export
+class Type(BaseType):
+	pass

+
+
+
+

+[docs]
+@export
+class AnonymousType(Type):
+	pass

+
+
+
+

+[docs]
+@export
+class FullType(BaseType):
+	pass

+
+
+
+

+[docs]
+@export
+class Subtype(BaseType):
+	_type:               Symbol
+	_baseType:           BaseType
+	_range:              Range
+	_resolutionFunction: 'Function'
+
+

+[docs]
+	def __init__(self, identifier: str, symbol: Symbol, parent: ModelEntity = None) -> None:
+		super().__init__(identifier, parent)
+
+		self._type = symbol
+		self._baseType = None
+		self._range = None
+		self._resolutionFunction = None

+
+
+	@readonly
+	def Type(self) -> Symbol:
+		return self._type
+
+	@readonly
+	def BaseType(self) -> BaseType:
+		return self._baseType
+
+	@readonly
+	def Range(self) -> Range:
+		return self._range
+
+	@readonly
+	def ResolutionFunction(self) -> 'Function':
+		return self._resolutionFunction
+
+

+[docs]
+	def __str__(self) -> str:
+		return f"subtype {self._identifier} is {self._baseType}"

+

+
+
+
+

+[docs]
+@export
+class ScalarType(FullType):
+	"""A ``ScalarType`` is a base-class for all scalar types."""

+
+
+
+

+[docs]
+@export
+class RangedScalarType(ScalarType):
+	"""A ``RangedScalarType`` is a base-class for all scalar types with a range."""
+
+	_range:      Union[Range, Name]
+	_leftBound:  ExpressionUnion
+	_rightBound: ExpressionUnion
+
+

+[docs]
+	def __init__(self, identifier: str, rng: Union[Range, Name], parent: ModelEntity = None) -> None:
+		super().__init__(identifier, parent)
+		self._range = rng

+
+
+	@readonly
+	def Range(self) -> Union[Range, Name]:
+		return self._range

+
+
+
+

+[docs]
+@export
+class NumericTypeMixin(metaclass=ExtendedType, mixin=True):
+	"""A ``NumericType`` is a mixin class for all numeric types."""
+
+

+[docs]
+	def __init__(self) -> None:
+		pass

+

+
+
+
+

+[docs]
+@export
+class DiscreteTypeMixin(metaclass=ExtendedType, mixin=True):
+	"""A ``DiscreteType`` is a mixin class for all discrete types."""
+
+

+[docs]
+	def __init__(self) -> None:
+		pass

+

+
+
+
+

+[docs]
+@export
+class EnumeratedType(ScalarType, DiscreteTypeMixin):
+	_literals: List[EnumerationLiteral]
+
+

+[docs]
+	def __init__(self, identifier: str, literals: Iterable[EnumerationLiteral], parent: ModelEntity = None) -> None:
+		super().__init__(identifier, parent)
+
+		self._literals = []
+		if literals is not None:
+			for literal in literals:
+				self._literals.append(literal)
+				literal._parent = self

+
+
+	@readonly
+	def Literals(self) -> List[EnumerationLiteral]:
+		return self._literals
+
+

+[docs]
+	def __str__(self) -> str:
+		return f"{self._identifier} is ({', '.join(str(l) for l in self._literals)})"

+

+
+
+
+

+[docs]
+@export
+class IntegerType(RangedScalarType, NumericTypeMixin, DiscreteTypeMixin):
+

+[docs]
+	def __init__(self, identifier: str, rng: Union[Range, Name], parent: ModelEntity = None) -> None:
+		super().__init__(identifier, rng, parent)

+
+
+

+[docs]
+	def __str__(self) -> str:
+		return f"{self._identifier} is range {self._range}"

+

+
+
+
+

+[docs]
+@export
+class RealType(RangedScalarType, NumericTypeMixin):
+

+[docs]
+	def __init__(self, identifier: str, rng: Union[Range, Name], parent: ModelEntity = None) -> None:
+		super().__init__(identifier, rng, parent)

+
+
+

+[docs]
+	def __str__(self) -> str:
+		return f"{self._identifier} is range {self._range}"

+

+
+
+
+

+[docs]
+@export
+class PhysicalType(RangedScalarType, NumericTypeMixin):
+	_primaryUnit:    str
+	_secondaryUnits: List[Tuple[str, PhysicalIntegerLiteral]]
+
+

+[docs]
+	def __init__(
+		self,
+		identifier: str,
+		rng: Union[Range, Name],
+		primaryUnit: str,
+		units: Iterable[Tuple[str, PhysicalIntegerLiteral]],
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(identifier, rng, parent)
+
+		self._primaryUnit = primaryUnit
+
+		self._secondaryUnits = []  # TODO: convert to dict
+		for unit in units:
+			self._secondaryUnits.append(unit)
+			unit[1]._parent = self

+
+
+	@readonly
+	def PrimaryUnit(self) -> str:
+		return self._primaryUnit
+
+	@property
+	def SecondaryUnits(self) -> List[Tuple[str, PhysicalIntegerLiteral]]:
+		return self._secondaryUnits
+
+

+[docs]
+	def __str__(self) -> str:
+		return f"{self._identifier} is range {self._range} units {self._primaryUnit}; {'; '.join(su + ' = ' + str(pu) for su, pu in self._secondaryUnits)};"

+

+
+
+
+

+[docs]
+@export
+class CompositeType(FullType):
+	"""A ``CompositeType`` is a base-class for all composite types."""

+
+
+
+

+[docs]
+@export
+class ArrayType(CompositeType):
+	_dimensions:  List[Range]
+	_elementType: Symbol
+
+

+[docs]
+	def __init__(
+		self,
+		identifier: str,
+		indices: Iterable,
+		elementSubtype: Symbol,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(identifier, parent)
+
+		self._dimensions = []
+		for index in indices:
+			self._dimensions.append(index)
+			# index._parent = self  # FIXME: indices are provided as empty list
+
+		self._elementType = elementSubtype

+
+		# elementSubtype._parent = self   # FIXME: subtype is provided as None
+
+	@property
+	def Dimensions(self) -> List[Range]:
+		return self._dimensions
+
+	@property
+	def ElementType(self) -> Symbol:
+		return self._elementType
+
+

+[docs]
+	def __str__(self) -> str:
+		return f"{self._identifier} is array({'; '.join(str(r) for r in self._dimensions)}) of {self._elementType}"

+

+
+
+
+

+[docs]
+@export
+class RecordTypeElement(ModelEntity, MultipleNamedEntityMixin):
+	_subtype: Symbol
+
+

+[docs]
+	def __init__(self, identifiers: Iterable[str], subtype: Symbol, parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+		MultipleNamedEntityMixin.__init__(self, identifiers)
+
+		self._subtype = subtype
+		subtype._parent = self

+
+
+	@property
+	def Subtype(self) -> Symbol:
+		return self._subtype
+
+

+[docs]
+	def __str__(self) -> str:
+		return f"{', '.join(self._identifiers)} : {self._subtype}"

+

+
+
+
+

+[docs]
+@export
+class RecordType(CompositeType):
+	_elements: List[RecordTypeElement]
+
+

+[docs]
+	def __init__(self, identifier: str, elements: Nullable[Iterable[RecordTypeElement]] = None, parent: ModelEntity = None) -> None:
+		super().__init__(identifier, parent)
+
+		self._elements = []  # TODO: convert to dict
+		if elements is not None:
+			for element in elements:
+				self._elements.append(element)
+				element._parent = self

+
+
+	@property
+	def Elements(self) -> List[RecordTypeElement]:
+		return self._elements
+
+

+[docs]
+	def __str__(self) -> str:
+		return f"{self._identifier} is record {'; '.join(str(re) for re in self._elements)};"

+

+
+
+
+

+[docs]
+@export
+class ProtectedType(FullType):
+	_methods: List[Union['Procedure', 'Function']]
+
+

+[docs]
+	def __init__(self, identifier: str, methods: Union[List, Iterator] = None, parent: ModelEntity = None) -> None:
+		super().__init__(identifier, parent)
+
+		self._methods = []
+		if methods is not None:
+			for method in methods:
+				self._methods.append(method)
+				method._parent = self

+
+
+	@property
+	def Methods(self) -> List[Union['Procedure', 'Function']]:
+		return self._methods

+
+
+
+

+[docs]
+@export
+class ProtectedTypeBody(FullType):
+	_methods: List[Union['Procedure', 'Function']]
+
+

+[docs]
+	def __init__(self, identifier: str, declaredItems: Union[List, Iterator] = None, parent: ModelEntity = None) -> None:
+		super().__init__(identifier, parent)
+
+		self._methods = []
+		if declaredItems is not None:
+			for method in declaredItems:
+				self._methods.append(method)
+				method._parent = self

+
+
+	# FIXME: needs to be declared items or so
+	@property
+	def Methods(self) -> List[Union['Procedure', 'Function']]:
+		return self._methods

+
+
+
+

+[docs]
+@export
+class AccessType(FullType):
+	_designatedSubtype: Symbol
+
+

+[docs]
+	def __init__(self, identifier: str, designatedSubtype: Symbol, parent: ModelEntity = None) -> None:
+		super().__init__(identifier, parent)
+
+		self._designatedSubtype = designatedSubtype
+		designatedSubtype._parent = self

+
+
+	@property
+	def DesignatedSubtype(self):
+		return self._designatedSubtype
+
+

+[docs]
+	def __str__(self) -> str:
+		return f"{self._identifier} is access {self._designatedSubtype}"

+

+
+
+
+

+[docs]
+@export
+class FileType(FullType):
+	_designatedSubtype: Symbol
+
+

+[docs]
+	def __init__(self, identifier: str, designatedSubtype: Symbol, parent: ModelEntity = None) -> None:
+		super().__init__(identifier, parent)
+
+		self._designatedSubtype = designatedSubtype
+		designatedSubtype._parent = self

+
+
+	@property
+	def DesignatedSubtype(self):
+		return self._designatedSubtype
+
+

+[docs]
+	def __str__(self) -> str:
+		return f"{self._identifier} is access {self._designatedSubtype}"

+

+
+
+ +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/_report_static/sphinx-reports.e44b1595f1e09d5e109d001839ba3f42.css b/_report_static/sphinx-reports.e44b1595f1e09d5e109d001839ba3f42.css new file mode 100644 index 000000000..02468d35c --- /dev/null +++ b/_report_static/sphinx-reports.e44b1595f1e09d5e109d001839ba3f42.css @@ -0,0 +1,48 @@ +/* + * Disable odd/even coloring for docutils tables if it's a coverage table. + * Otherwise, the 'nth-child' rule will always override row colors indicating the coverage level. + */ +.rst-content table.docutils:not(.field-list) tr:nth-child(2n-1) td { + background-color: unset; +} + +/* + * Coloring for 0..30, 30..50, 50..80, 80..90, 90.100% coverage + */ +/* very good */ +.report-cov-below100 { + background: rgba(0, 200, 82, .4); +} +/* good */ +.report-cov-below90 { + background: rgba(0, 200, 82, .2); +} +/* modest */ +.report-cov-below80 { + background: rgba(255, 145, 0, .2); +} +/* bad */ +.report-cov-below50 { + background: rgba(255, 82, 82, .2); +} +/* very bad */ +.report-cov-below30 { + background: rgba(101, 31, 255, .2); +} +/* internal error */ +.report-cov-error{ + background: rgba(255, 0, 0, .4); +} + +.report-dep-summary-row { + font-weight: bold; +} +.report-codecov-summary-row { + font-weight: bold; +} +.report-doccov-summary-row { + font-weight: bold; +} +.report-unittest-summary-row { + font-weight: bold; +} diff --git a/_sources/Analyze/index.rst.txt b/_sources/Analyze/index.rst.txt new file mode 100644 index 000000000..1ee2a845f --- /dev/null +++ b/_sources/Analyze/index.rst.txt @@ -0,0 +1,103 @@ +.. _analyze: + +Analyze +####### + +1. Dependency analysis + +Dependency Analysis +******************* + +1. Create Dependency Graph +========================== + +Create unconnected vertices in the design's dependency graph for every VHDL library object and every design unit. + +The vertex's ``ID`` field is set to a unique identifying string. |br| +The following patterns are used: + +Libraries + The normalized library name: ``library``. +Contexts + The normalized library and context name: ``library.context``. +Entities + The normalized library and entity name: ``library.entity``. +Architectures + The normalized library, entity and architecture name in parenthesis: ``library.entity(architecture)``. +Packages + The normalized library and package name: ``library.package``. +Package Bodies + The normalized library and package name: ``library.package(body)``. + +The vertex's ``Value`` field references to the library or design unit object respectively. + +Each vertex has two attributes: + +``"kind"`` + A kind attribute is set to an enumeration value of :py:class:`~pyVHDLModel.DependencyGraphVertexKind` representing + vertex kind (type). +``"predefined"`` + A predefined attribute is set to ``True``, if the library or design unit is a VHDL predefined language entity from + e.g. from ``std`` or ``ieee``. + +Lastly, every vertex is assigned to a :py:attr:``~pyVHDLModel.DesignUnit.DesignUnit._dependencyVertex`` field. Thus, +there is a double reference from graph's vertex via ``Value`` to the DOM object as well as in reverse via +``_dependencyVertex`` to the representing vertex. + +.. code-block:: vhdl + + predefinedLibraries = ("std", "ieee") + + for libraryIdentifier, library in self._libraries.items(): + dependencyVertex = Vertex(vertexID=f"{libraryIdentifier}", value=library, graph=self._dependencyGraph) + dependencyVertex["kind"] = DependencyGraphVertexKind.Library + dependencyVertex["predefined"] = libraryIdentifier in predefinedLibraries + library._dependencyVertex = dependencyVertex + + for contextIdentifier, context in library._contexts.items(): + dependencyVertex = Vertex(vertexID=f"{libraryIdentifier}.{contextIdentifier}", value=context, graph=self._dependencyGraph) + dependencyVertex["kind"] = DependencyGraphVertexKind.Context + dependencyVertex["predefined"] = context._library._normalizedIdentifier in predefinedLibraries + context._dependencyVertex = dependencyVertex + + +2. Create Compile Order Graph +============================= + +3. Index Packages +================= + +4. Index Architectures +====================== + +5. Link Contexts +================ + +6. Link Architectures +===================== + +7. Link Package Bodies +====================== + +8. Link Library References +========================== + +9. Link Package References +========================== + +10. Link Context References +=========================== + +11. Link Components +=================== + +12. Link Instantiations +======================= + +13. Create Hierarchy Graph +========================== + +14. Compute Compile Order +========================= + + diff --git a/_sources/ChangeLog/index.rst.txt b/_sources/ChangeLog/index.rst.txt new file mode 100644 index 000000000..f4a65d0af --- /dev/null +++ b/_sources/ChangeLog/index.rst.txt @@ -0,0 +1,12 @@ +ChangeLog +######### + +Upcoming Release +================ + +* tbd + +26.12.2020 +========== + +`pyVHDLModel` was split from `pyVHDLParser` (v0.6.0) as an independent Python package. diff --git a/_sources/DataStructure/CompileOrderGraph.rst.txt b/_sources/DataStructure/CompileOrderGraph.rst.txt new file mode 100644 index 000000000..42adda4e0 --- /dev/null +++ b/_sources/DataStructure/CompileOrderGraph.rst.txt @@ -0,0 +1,4 @@ +.. _datastruct:compileordergraph: + +Compile Order Graph +################### diff --git a/_sources/DataStructure/DependencyGraph.rst.txt b/_sources/DataStructure/DependencyGraph.rst.txt new file mode 100644 index 000000000..46b58426d --- /dev/null +++ b/_sources/DataStructure/DependencyGraph.rst.txt @@ -0,0 +1,4 @@ +.. _datastruct:dependencygraph: + +Dependency Graph +################ diff --git a/_sources/DataStructure/HierarchyGraph.rst.txt b/_sources/DataStructure/HierarchyGraph.rst.txt new file mode 100644 index 000000000..002c0d726 --- /dev/null +++ b/_sources/DataStructure/HierarchyGraph.rst.txt @@ -0,0 +1,4 @@ +.. _datastruct:hierarchygraph: + +Hierarchy Graph +############### diff --git a/_sources/DataStructure/index.rst.txt b/_sources/DataStructure/index.rst.txt new file mode 100644 index 000000000..fc5d67b3f --- /dev/null +++ b/_sources/DataStructure/index.rst.txt @@ -0,0 +1,70 @@ +.. _datastruct: + +Data Structures +############### + +Besides the document object model as a tree-like structure, pyVHDLModel has either lists, lookup dictionaries, direct +cross-references or dedicated data structure (tree, graph, …) for connecting multiple objects together. + +Graphs +****** + +pyVHDLModel uses the graph implementation from :pyTool:mod:`pyTooling.Graph` as it provides an object oriented programming +interface to vertices and edges. + +Dependency Graph +================ + +The dependency graph describes dependencies between: + +* Sourcecode files +* VHDL libraries +* Contexts +* Packages +* Entities +* Architectures +* Packages +* Package Bodies +* Configurations + +The relation can be: + +* Defined in source file +* references +* implements +* instantiates +* needs to be analyzed before + + +Hierarchy Graph +=============== + +The hierarchy graph can be derived from dependency graph by: + +1. copying all entity and architecture vertices +2. copying all implements dependency edges +3. copying all instantiates edges in reverse direction + +The graph can then be scanned for a root vertices (no inbound edges). If only a single root vertex exists, this vertex +references the toplevel of the design. + + +Compile Order Graph +=================== + +The compile order can be derived from dependency graph by: + +1. copying all document vertices +2. iterating all edges in the dependency graph. + 1. resolve the source and the destination to the referenced design units + 2. resolved further to the documents these design units are declared in + 3. resolve further which vertices correspond in the compile order graph + 4. if edges does not yet exist, add an edge between two documents in the compile order graph + + +.. toctree:: + :hidden: + + DependencyGraph + HierarchyGraph + CompileOrderGraph diff --git a/_sources/Dependency.rst.txt b/_sources/Dependency.rst.txt new file mode 100644 index 000000000..9e1b4c0b1 --- /dev/null +++ b/_sources/Dependency.rst.txt @@ -0,0 +1,166 @@ +.. _dependency: + +Dependency +########## + +.. |img-pyVHDLModel-lib-status| image:: https://img.shields.io/librariesio/release/pypi/pyVHDLModel + :alt: Libraries.io status for latest release + :height: 22 + :target: https://libraries.io/github/VHDL/pyVHDLModel + ++------------------------------------------+------------------------------------------+ +| `Libraries.io `_ | Requires.io | ++==========================================+==========================================+ +| |img-pyVHDLModel-lib-status| | Service was shutdown | ++------------------------------------------+------------------------------------------+ + + +.. _dependency-package: + +pyVHDLModel Package +******************* + ++--------------------------------------------------------+-------------+------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+ +| **Package** | **Version** | **License** | **Dependencies** | ++========================================================+=============+==========================================================================================+=================================================================================================================================+ +| `pyTooling `__ | ≥6.6 | `Apache License, 2.0 `__ | *None* | ++--------------------------------------------------------+-------------+------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+ + + +.. _dependency-testing: + +Unit Testing / Coverage / Type Checking (Optional) +************************************************** + +Additional Python packages needed for testing, code coverage collection and static type checking. These packages are +only needed for developers or on a CI server, thus sub-dependencies are not evaluated further. + + +.. rubric:: Manually Installing Test Requirements + +Use the :file:`tests/requirements.txt` file to install all dependencies via ``pip3``. The file will recursively install +the mandatory dependencies too. + +.. code-block:: shell + + pip3 install -U -r tests/requirements.txt + + +.. rubric:: Dependency List + ++---------------------------------------------------------------------+-------------+----------------------------------------------------------------------------------------+----------------------+ +| **Package** | **Version** | **License** | **Dependencies** | ++=====================================================================+=============+========================================================================================+======================+ +| `pytest `__ | ≥8.3 | `MIT `__ | *Not yet evaluated.* | ++---------------------------------------------------------------------+-------------+----------------------------------------------------------------------------------------+----------------------+ +| `pytest-cov `__ | ≥5.0 | `MIT `__ | *Not yet evaluated.* | ++---------------------------------------------------------------------+-------------+----------------------------------------------------------------------------------------+----------------------+ +| `Coverage `__ | ≥7.6 | `Apache License, 2.0 `__ | *Not yet evaluated.* | ++---------------------------------------------------------------------+-------------+----------------------------------------------------------------------------------------+----------------------+ +| `mypy `__ | ≥1.11 | `MIT `__ | *Not yet evaluated.* | ++---------------------------------------------------------------------+-------------+----------------------------------------------------------------------------------------+----------------------+ +| `typing-extensions `__ | ≥4.12 | `PSF-2.0 `__ | *Not yet evaluated.* | ++---------------------------------------------------------------------+-------------+----------------------------------------------------------------------------------------+----------------------+ +| `lxml `__ | ≥5.3 | `BSD 3-Clause `__ | *Not yet evaluated.* | ++---------------------------------------------------------------------+-------------+----------------------------------------------------------------------------------------+----------------------+ + + +.. _dependency-documentation: + +Sphinx Documentation (Optional) +******************************* + +Additional Python packages needed for documentation generation. These packages are only needed for developers or on a +CI server, thus sub-dependencies are not evaluated further. + + +.. rubric:: Manually Installing Documentation Requirements + +Use the :file:`doc/requirements.txt` file to install all dependencies via ``pip3``. The file will recursively install +the mandatory dependencies too. + +.. code-block:: shell + + pip3 install -U -r doc/requirements.txt + + +.. rubric:: Dependency List + ++-------------------------------------------------------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------+----------------------+ +| **Package** | **Version** | **License** | **Dependencies** | ++=================================================================================================+==============+==========================================================================================================+======================+ +| `pyTooling `__ | ≥6.6 | `Apache License, 2.0 `__ | *None* | ++-------------------------------------------------------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------+----------------------+ +| `Sphinx `__ | ≥7.4 | `BSD 3-Clause `__ | *Not yet evaluated.* | ++-------------------------------------------------------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------+----------------------+ +| `sphinxcontrib-mermaid `__ | ≥0.9.2 | `BSD `__ | *Not yet evaluated.* | ++-------------------------------------------------------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------+----------------------+ +| `autoapi `__ | ≥2.0.1 | `Apache License, 2.0 `__ | *Not yet evaluated.* | ++-------------------------------------------------------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------+----------------------+ +| `sphinx_btd_theme `__ | | `MIT `__ | *Not yet evaluated.* | ++-------------------------------------------------------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------+----------------------+ +| !! `sphinx_fontawesome `__ | ≥0.0.6 | `GPL 2.0 `__ | *Not yet evaluated.* | ++-------------------------------------------------------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------+----------------------+ +| `sphinx_autodoc_typehints `__ | ≥2.3 | `MIT `__ | *Not yet evaluated.* | ++-------------------------------------------------------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------+----------------------+ + + +.. _dependency-packaging: + +Packaging (Optional) +******************** + +Additional Python packages needed for installation package generation. These packages are only needed for developers or +on a CI server, thus sub-dependencies are not evaluated further. + + +.. rubric:: Manually Installing Packaging Requirements + +Use the :file:`build/requirements.txt` file to install all dependencies via ``pip3``. The file will recursively +install the mandatory dependencies too. + +.. code-block:: shell + + pip3 install -U -r build/requirements.txt + + +.. rubric:: Dependency List + ++----------------------------------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+ +| **Package** | **Version** | **License** | **Dependencies** | ++============================================================================+==============+==========================================================================================================+======================================================================================================================================================+ +| `pyTooling `__ | ≥6.6 | `Apache License, 2.0 `__ | *None* | ++----------------------------------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+ +| `wheel `__ | ≥0.44 | `MIT `__ | *Not yet evaluated.* | ++----------------------------------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+ + + +.. _dependency-publishing: + +Publishing (CI-Server only) +*************************** + +Additional Python packages needed for publishing the generated installation package to e.g, PyPI or any equivalent +services. These packages are only needed for maintainers or on a CI server, thus sub-dependencies are not evaluated +further. + + +.. rubric:: Manually Installing Publishing Requirements + +Use the :file:`dist/requirements.txt` file to install all dependencies via ``pip3``. The file will recursively +install the mandatory dependencies too. + +.. code-block:: shell + + pip3 install -U -r dist/requirements.txt + + +.. rubric:: Dependency List + ++----------------------------------------------------------+--------------+-------------------------------------------------------------------------------------------+----------------------+ +| **Package** | **Version** | **License** | **Dependencies** | ++==========================================================+==============+===========================================================================================+======================+ +| `wheel `__ | ≥0.44 | `MIT `__ | *Not yet evaluated.* | ++----------------------------------------------------------+--------------+-------------------------------------------------------------------------------------------+----------------------+ +| `Twine `__ | ≥5.1 | `Apache License, 2.0 `__ | *Not yet evaluated.* | ++----------------------------------------------------------+--------------+-------------------------------------------------------------------------------------------+----------------------+ diff --git a/_sources/Doc-License.rst.txt b/_sources/Doc-License.rst.txt new file mode 100644 index 000000000..1258fbc2c --- /dev/null +++ b/_sources/Doc-License.rst.txt @@ -0,0 +1,353 @@ +.. _DOCLICENSE: + +.. Note:: This is a local copy of the `Creative Commons - Attribution 4.0 International (CC BY 4.0) `__. + +.. Attention:: This **CC BY 4.0** license applies only to the **documentation** of this project. + + +Creative Commons Attribution 4.0 International +############################################## + +Creative Commons Corporation (“Creative Commons”) is not a law firm and does not +provide legal services or legal advice. Distribution of Creative Commons public +licenses does not create a lawyer-client or other relationship. Creative Commons +makes its licenses and related information available on an “as-is” basis. +Creative Commons gives no warranties regarding its licenses, any material +licensed under their terms and conditions, or any related information. Creative +Commons disclaims all liability for damages resulting from their use to the +fullest extent possible. + +.. topic:: Using Creative Commons Public Licenses + + Creative Commons public licenses provide a standard set of terms and conditions + that creators and other rights holders may use to share original works of + authorship and other material subject to copyright and certain other rights + specified in the public license below. The following considerations are for + informational purposes only, are not exhaustive, and do not form part of our + licenses. + + * **Considerations for licensors:** Our public licenses are intended for use + by those authorized to give the public permission to use material in ways + otherwise restricted by copyright and certain other rights. Our licenses are + irrevocable. Licensors should read and understand the terms and conditions + of the license they choose before applying it. Licensors should also secure + all rights necessary before applying our licenses so that the public can reuse + the material as expected. Licensors should clearly mark any material not + subject to the license. This includes other CC-licensed material, or material + used under an exception or limitation to copyright. + `More considerations for licensors `__. + + * **Considerations for the public:** By using one of our public licenses, a + licensor grants the public permission to use the licensed material under + specified terms and conditions. If the licensor’s permission is not necessary + for any reason–for example, because of any applicable exception or limitation + to copyright–then that use is not regulated by the license. Our licenses grant + only permissions under copyright and certain other rights that a licensor has + authority to grant. Use of the licensed material may still be restricted for + other reasons, including because others have copyright or other rights in the + material. A licensor may make special requests, such as asking that all + changes be marked or described. Although not required by our licenses, you are + encouraged to respect those requests where reasonable. + `More considerations for the public `__. + +:xlarge:`Creative Commons Attribution 4.0 International Public License` + +By exercising the Licensed Rights (defined below), You accept and agree to be +bound by the terms and conditions of this Creative Commons Attribution 4.0 +International Public License ("Public License"). To the extent this Public +License may be interpreted as a contract, You are granted the Licensed Rights +in consideration of Your acceptance of these terms and conditions, and the +Licensor grants You such rights in consideration of benefits the Licensor +receives from making the Licensed Material available under these terms and +conditions. + +Section 1 – Definitions. +======================== + +a. **Adapted Material** means material subject to Copyright and Similar + Rights that is derived from or based upon the Licensed Material and in + which the Licensed Material is translated, altered, arranged, transformed, or + otherwise modified in a manner requiring permission under the Copyright and + Similar Rights held by the Licensor. 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Notwithstanding, +Creative Commons may elect to apply one of its public licenses to material it +publishes and in those instances will be considered the “Licensor.” Except for +the limited purpose of indicating that material is shared under a Creative +Commons public license or as otherwise permitted by the Creative Commons +policies published at `creativecommons.org/policies `__, +Creative Commons does not authorize the use of the trademark “Creative Commons” +or any other trademark or logo of Creative Commons without its prior written +consent including, without limitation, in connection with any unauthorized +modifications to any of its public licenses or any other arrangements, +understandings, or agreements concerning use of licensed material. For the +avoidance of doubt, this paragraph does not form part of the public licenses. + +Creative Commons may be contacted at `creativecommons.org `__ diff --git a/_sources/DocCoverage.rst.txt b/_sources/DocCoverage.rst.txt new file mode 100644 index 000000000..c1e75266a --- /dev/null +++ b/_sources/DocCoverage.rst.txt @@ -0,0 +1,7 @@ +Documentation Coverage +###################### + +Documentation coverage generated by `docstr-coverage `__. + +.. report:doc-coverage:: + :packageid: src diff --git a/_sources/GettingStarted.rst.txt b/_sources/GettingStarted.rst.txt new file mode 100644 index 000000000..ab14c1ade --- /dev/null +++ b/_sources/GettingStarted.rst.txt @@ -0,0 +1,261 @@ +.. _GettingStarted: + +Getting Started +############### + +*pyVHDLModel* is a VHDL language model without any parser. There are currently two parsers available that can serve as a +frontend to pyVHDLModel. These parsers can generate a VHDL language model instance from VHDL source files: + +* pyVHDLParser (currently broken) +* GHDL + + +pyVHDLParser +************ + +The pyVHDLParser is a token-stream based parser creating a code document object model (CodeDOM) derived from +pyVHDLModel. Actually, pyVHDlModel was originally part of that parser, until it got refactored into this standalone +package so multiple frontends (parsers) and backends (analysis tools) can use this VHDL language model as a common API. + +.. warning:: Currently, pyVHDLParser is not aligned with latest updates in pyVHDLModel. + + +GHDL as Parser +************** + +The free and open-source VHDL-2008 simulator **GHDL** offers a Python binding, so Python code can access ``libghdl``. +This binding layer is exposed in the ``pyGHDL.libghdl`` package. In addition, GHDL offers a ``pyGHDL.dom`` package +implementing derived classes of pyVHDLModel. Each derived class adds translation methods (``.parse(iirNode)``) from +GHDL's internal data structure IIR to the code document object model (CodeDOM) of pyVHDLModel. + + +Installation and Setup +====================== + +To use pyVHDLModel a tool offering a parser like GHDL is required. GHDL itself offers multiple options for installation. +In addition it has multiple backends. For the usage with pyVHDLModel, an ``mcode`` backend is preferred, as it's faster +and doesn't write ``*.o`` files to the disk. As most Python installation are nowadays 64-bit, an ``mcode 64-bit`` +variant of GHDL would be best. + +On Windows - Native +""""""""""""""""""" + +Assuming a 64-bit Windows installation and a 64-bit CPython (`python.org `__) +installation, it's suggested to install: + +* `GHDL 3.0.0-dev - MinGW64 - mcode - standalone `__ +* `GHDL 3.0.0-dev - UCRT64 - mcode - standalone `__ + +As development of Python packages ``pyGHDL.dom`` and ``pyVHDLModel`` are under quick development cycles, a GHDL +``nightly`` build is suggested compared to the stable releases (once a year). These nightly builds are provided as ZIP +files on GitHub: https://github.com/ghdl/ghdl/releases/tag/nightly (or use links from above). + +At next, unpack the ZIP files content to e.g. :file:`C:\\Tools\\GHDL\\3.0.0-dev` (GHDL installation directory). This ZIP +file brings the GHDL synthesis and simulation tool as well as :file:`libghdl-3_0_0_dev.dll` needed as a parser frontend. + + +On Windows - MSYS2 +"""""""""""""""""" + +Assuming a 64-bit Windows installation and an `MSYS2 `__ installation in :file:`C:\msys64`. + + +.. rubric:: MSYS2 Prepartions and GHDL/libghdl Installation + +Start either the MinGW64 or UCRT64 environment and then use :command:`pacman` to install GHDL. The following steps are +explained for UCRT64, but can be applied to MinGW64 similarly. + +.. admonition:: Bash + + .. code-block:: bash + + # Update MSYS2 to latest package releases + pacman -Suyy + + # If the core system was updated, a second run might be required. + pacman -Suyy + + # Search for available GHDL packages + pacman -Ss ghdl + # mingw32/mingw-w64-i686-ghdl-mcode 2.0.0.r870.g1cc85c578-1 (mingw-w64-i686-eda) [Installiert] + # GHDL: the open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL (mcode backend) (mingw-w64) + # mingw64/mingw-w64-x86_64-ghdl-llvm 2.0.0.r870.g1cc85c578-1 (mingw-w64-x86_64-eda) [Installiert] + # GHDL: the open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL (LLVM backend) (mingw-w64) + # ucrt64/mingw-w64-ucrt-x86_64-ghdl-llvm 2.0.0.r870.g1cc85c578-1 (mingw-w64-ucrt-x86_64-eda) [Installiert] + # GHDL: the open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL (LLVM backend) (mingw-w64) + + # Note: The GHDL version is 870 commits after 2.0.0 release and has Git hash "1cc85c578" (without prefix 'g') + + # Install GHDL for UCRT64 + pacman -S ucrt64/mingw-w64-ucrt-x86_64-ghdl-llvm + +.. rubric:: Installing pyGHDL + +At next, pyGHDL matching the currently installed GHDL version must be installed. At best, pyGHDL matches the exact Git +hash of GHDL, so there is no discrepancy between the libghdl binary and the DLL binding layer in ``pyGHDL.libghdl``. + +Assuming *Git for Windows* is installed and available in PowerShell, the following command will install pyGHDL via PIP: + +.. admonition:: PowerShell + + .. code-block:: powershell + + # Install pyGHDL + pip install git+https://github.com/ghdl/ghdl.git@$(ghdl version hash). + + +On Windows from Sources +""""""""""""""""""""""" + +Assuming a 64-bit Windows installation, a 64-bit CPython (`python.org `__) +installation as well as an `MSYS2 `__ installation in :file:`C:\msys64`. + +.. rubric:: MSYS2 Prepartions + +Start either the MinGW64 or UCRT64 environment and then use :command:`pacman` to install build dependencies. The +following steps are explained for UCRT64, but can be applied to MinGW64 similarly. + +.. admonition:: Bash + + .. code-block:: bash + + # Update MSYS2 to latest package releases + pacman -Suyy + + # If the core system was updated, a second run might be required. + pacman -Suyy + + # Install system dependencies + pacman -S git + pacman -S make + pacman -S diffutils + + # Install GHDL build dependencies (GCC with Ada support) + pacman -S ucrt64/mingw-w64-ucrt-x86_64-gcc-ada + +.. rubric:: Building GHDL and libghdl + +The next steps will clone GHDL from GitHub, configure the software, build the binaries, run the testsuite and install +all needed result files into the installation directory. + +.. admonition:: Bash + + .. code-block:: bash + + # Clone GHDL repository + mkdir -p /c/Tools/GHDL + cd /c/Tools/GHDL + git clone https://github.com/ghdl/ghdl.git sources + + # Create build directory and configure GHDL + mkdir -p sources/build + cd sources/build + ../configure --prefix=/c/Tools/GHDL/3.0.0-dev + + # Build GHDL, run testsuite and install to ``prefix`` + make + make install + +The directory structure will look like this: + +.. code-block:: + + ├── Tools + │ ├── GHDL + │ │ ├── 3.0.0-dev + │ │ │ ├── bin + │ │ │ ├── include + │ │ │ ├── lib + │ │ │ │ ├── ghdl + │ │ ├── sources + │ │ │ ├── ... + │ │ │ ├── pyGHDL + │ │ │ ├── src + │ │ │ ├── ... + +In the next steps, some files from MSYS2/UCRT64 need to be copied into the installation directory, so +:file:`libghdl-3_0_0_dev.dll` can be used independently from MSYS2 environments. + +.. rubric:: Installing pyGHDL + +As a final setup step, pyGHDL needs to be installed via PIP by executing some commands in PowerShell. The dependencies +of pyGHDL will take care of installing all necessary requirements like pyVHDLModel. + +.. admonition:: PowerShell + + .. code-block:: powershell + + cd C:\Tools\GHDL\sources + pip install . + + +.. rubric:: Updating GHDL and libghdl + +If GHDL gets updated through new commits, start the UCRT64 console and execute these instructions to build a latest +:file:`libghdl-3_0_0_dev.dll`: + +.. admonition:: Bash + + .. code-block:: bash + + # Update Git reository + cd /c/Tools/GHDL/sources/build + git pull + + # Recompile GHDL + make + + # Overwrite file in installation directory + make install + +.. rubric:: Updating pyGHDL + +TBD + +On Linux +"""""""" + +.. todo:: Write how to get started on Linux with libghdl. + + +On Mac +"""""" + +.. todo:: Write how to get started on Mac with libghdl. + + +Using libghdl with Python +========================= + +An environment variable :envvar:`GHDL_PREFIX=C:\\Tools\\GHDL\\3.0.0-dev\\lib\\ghdl` is needed for libghdl. The path is +constructed from installation path plus ``lib\\ghdl``. + +.. admonition:: GettingStarted.py + + .. code-block:: Python + + from pathlib import Path + from pyGHDL.dom.NonStandard import Design, Document + + fileList = ( + ("libStopWatch", Path("Counter.vhdl")), # a list of 2-element tuples; library name and pat to the VHDL file + ... # just for this example to simply loop all files + ) + + design = Design() + design.LoadDefaultLibraries() # loads std.* and ieee.* (dummies for now to calculate dependencies) + for libName, file in fileList: + library = design.GetLibrary(libName) + document = Document(file) + design.AddDocument(document, library) + + # Analyzing dependencies and computing graphs + design.Analyze() + + # Accessing the TopLevel + design.TopLevel + + # Accessing graphs + design.DependencyGraph + design.HierarchyGraph + design.CompileOrderGraph diff --git a/_sources/Glossary.rst.txt b/_sources/Glossary.rst.txt new file mode 100644 index 000000000..65f0ad56d --- /dev/null +++ b/_sources/Glossary.rst.txt @@ -0,0 +1,16 @@ +Glossary +######## + +.. glossary:: + + LRM + IEEE Standard for VHDL Language Reference Manual + + * `1076-2019 `__. + * `1076-2008 `__ aka IEC 61691-1-1:2011. + * `1076-2002 `__ aka IEC 61691-1-1 Ed.1 (2004-10). + * `1076-2000 `__. + * `1076-1993 `__. + * `1076-1987 `__. + + See :ref:`VASG:About:Standards` for further details. diff --git a/_sources/Installation.rst.txt b/_sources/Installation.rst.txt new file mode 100644 index 000000000..19d04855e --- /dev/null +++ b/_sources/Installation.rst.txt @@ -0,0 +1,209 @@ +.. _INSTALL: + +Installation/Updates +#################### + +.. _INSTALL/pip: + +Using PIP to Install from PyPI +****************************** + +The following instruction are using PIP (Package Installer for Python) as a package manager and PyPI (Python Package +Index) as a source of Python packages. + + +.. _INSTALL/pip/install: + +Installing a Wheel Package from PyPI using PIP +============================================== + +Users of pyTooling can select if the want to install a basic variant of pyTooling. See :ref:`DEP` for more +details. + +.. tab-set:: + + .. tab-item:: Linux/MacOS + :sync: Linux + + .. code-block:: bash + + # Basic sphinx-reports package + pip3 install pyVHDLModel + + .. tab-item:: Windows + :sync: Windows + + .. code-block:: powershell + + # Basic sphinx-reports package + pip install pyVHDLModel + +Developers can install further dependencies for documentation generation (``doc``) or running unit tests (``test``) or +just all (``all``) dependencies. + +.. tab-set:: + + .. tab-item:: Linux/MacOS + :sync: Linux + + .. tab-set:: + + .. tab-item:: With Documentation Dependencies + :sync: Doc + + .. code-block:: bash + + # Install with dependencies to generate documentation + pip3 install pyVHDLModel[doc] + + .. tab-item:: With Unit Testing Dependencies + :sync: Unit + + .. code-block:: bash + + # Install with dependencies to run unit tests + pip3 install pyVHDLModel[test] + + .. tab-item:: All Developer Dependencies + :sync: All + + .. code-block:: bash + + # Install with all developer dependencies + pip install pyVHDLModel[all] + + .. tab-item:: Windows + :sync: Windows + + .. tab-set:: + + .. tab-item:: With Documentation Dependencies + :sync: Doc + + .. code-block:: powershell + + # Install with dependencies to generate documentation + pip install pyVHDLModel[doc] + + .. tab-item:: With Unit Testing Dependencies + :sync: Unit + + .. code-block:: powershell + + # Install with dependencies to run unit tests + pip install pyVHDLModel[test] + + .. tab-item:: All Developer Dependencies + :sync: All + + .. code-block:: powershell + + # Install with all developer dependencies + pip install pyVHDLModel[all] + + +.. _INSTALL/pip/update: + +Updating from PyPI using PIP +============================ + +.. tab-set:: + + .. tab-item:: Linux/MacOS + :sync: Linux + + .. code-block:: bash + + pip install -U pyVHDLModel + + .. tab-item:: Windows + :sync: Windows + + .. code-block:: powershell + + pip3 install -U pyVHDLModel + + +.. _INSTALL/pip/uninstall: + +Uninstallation using PIP +======================== + +.. tab-set:: + + .. tab-item:: Linux/MacOS + :sync: Linux + + .. code-block:: bash + + pip uninstall pyVHDLModel + + .. tab-item:: Windows + :sync: Windows + + .. code-block:: powershell + + pip3 uninstall pyVHDLModel + + +.. _INSTALL/setup: + +Using ``setup.py`` (legacy) +*************************** + +See sections above on how to use PIP. + +Installation using ``setup.py`` +=============================== + +.. code-block:: bash + + setup.py install + + +.. _INSTALL/building: + +Local Packaging and Installation via PIP +**************************************** + +For development and bug fixing it might be handy to create a local wheel package and also install it locally on the +development machine. The following instructions will create a local wheel package (``*.whl``) and then use PIP to +install it. As a user might have a sphinx-reports installation from PyPI, it's recommended to uninstall any previous +sphinx-reports packages. (This step is also needed if installing an updated local wheel file with same version number. PIP +will not detect a new version and thus not overwrite/reinstall the updated package contents.) + +Ensure :ref:`packaging requirements ` are installed. + +.. tab-set:: + + .. tab-item:: Linux/MacOS + :sync: Linux + + .. code-block:: bash + + cd + + # Package the code in a wheel (*.whl) + python -m build --wheel + + # Uninstall the old package + python -m pip uninstall -y pyVHDLModel + + # Install from wheel + python -m pip install ./dist/pyVHDLModel-0.28.0-py3-none-any.whl + + .. tab-item:: Windows + :sync: Windows + + .. code-block:: powershell + + cd + + # Package the code in a wheel (*.whl) + py -m build --wheel + + # Uninstall the old package + py -m pip uninstall -y pyVHDLModel + + # Install from wheel + py -m pip install .\dist\pyVHDLModel-0.28.0-py3-none-any.whl diff --git a/_sources/LanguageModel/ConcurrentStatements.rst.txt b/_sources/LanguageModel/ConcurrentStatements.rst.txt new file mode 100644 index 000000000..cb8e2a6d5 --- /dev/null +++ b/_sources/LanguageModel/ConcurrentStatements.rst.txt @@ -0,0 +1,294 @@ +.. _vhdlmodel-constm: + +Concurrent Statements +##################### + +.. contents:: Table of Content + :local: + +.. rubric:: Class Hierarchy + +.. inheritance-diagram:: pyVHDLModel.SyntaxModel.ConcurrentAssertStatement pyVHDLModel.SyntaxModel.ConcurrentSignalAssignment pyVHDLModel.SyntaxModel.ConcurrentBlockStatement pyVHDLModel.SyntaxModel.ProcessStatement pyVHDLModel.SyntaxModel.IfGenerateStatement pyVHDLModel.SyntaxModel.CaseGenerateStatement pyVHDLModel.SyntaxModel.ForGenerateStatement pyVHDLModel.SyntaxModel.ComponentInstantiation pyVHDLModel.SyntaxModel.ConfigurationInstantiation pyVHDLModel.SyntaxModel.EntityInstantiation pyVHDLModel.SyntaxModel.ConcurrentProcedureCall + :parts: 1 + +.. _vhdlmodel-con-assertstatement: + +Assert Statement +================ + +.. todo:: + + Write documentation. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.ConcurrentSignalAssignment`: + +.. code-block:: Python + + @export + class ConcurrentAssertStatement(ConcurrentStatement, MixinAssertStatement): + # inherited from ModelEntity + @property + def Parent(self) -> ModelEntity: + + # inherited from LabeledEntity + @property + def Label(self) -> str: + + # inherited from MixinReportStatement + @property + def Message(self) -> BaseExpression: + + @property + def Severity(self) -> BaseExpression: + + # inherited from MixinAssertStatement + @property + def Condition(self) -> BaseExpression: + + + +.. _vhdlmodel-con-signalassignment: + +Signal Assignment +================= + +.. todo:: + + Write documentation. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.ConcurrentSignalAssignment`: + +.. code-block:: Python + + @export + class ConcurrentSignalAssignment(ConcurrentStatement, SignalAssignment): + # inherited from ModelEntity + @property + def Parent(self) -> ModelEntity: + + # inherited from LabeledEntity + @property + def Label(self) -> str: + + # inherited from Assignment + @property + def Target(self) -> Object: + + @property + def BaseExpression(self) -> BaseExpression: + + + +.. _vhdlmodel-con-blockstatement: + +Concurrent Block Statement +========================== + +.. todo:: + + Write documentation. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.ConcurrentBlockStatement`: + +.. code-block:: Python + + @export + class ConcurrentBlockStatement(ConcurrentStatement, BlockStatement, ConcurrentDeclarations, ConcurrentStatements): + # inherited from ModelEntity + @property + def Parent(self) -> ModelEntity: + + # inherited from LabeledEntity + @property + def Label(self) -> str: + + # inherited from ConcurrentDeclarations + @property + def DeclaredItems(self) -> List: + + # inherited from ConcurrentStatements + @property + def Statements(self) -> List[ConcurrentStatement]: + + # from ConcurrentBlockStatement + @property + def PortItems(self) -> List[PortInterfaceItem]: + +.. _vhdlmodel-instantiations: + +Instantiations +============== + +.. todo:: + + Write documentation. + +.. _vhdlmodel-entityinstantiation: + +Entity Instantiation +-------------------- + +.. _vhdlmodel-componentinstantiation: + +Component Instantiation +----------------------- + +.. _vhdlmodel-configurationinstantiation: + +Configuration Instantiation +--------------------------- + +.. _vhdlmodel-generates: + +Generate Statements +=================== + +.. _vhdlmodel-ifgenerate: + +If Generate +----------- + +.. todo:: + + Write documentation. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.IfGenerateStatement`: + +.. code-block:: Python + + @export + class IfGenerateStatement(GenerateStatement): + # inherited from ModelEntity + @property + def Parent(self) -> ModelEntity: + + # inherited from LabeledEntity + @property + def Label(self) -> str: + + # from IfGenerateStatement + @property + def IfBranch(self) -> IfGenerateBranch: + + @property + def ElsifBranches(self) -> List[ElsifGenerateBranch]: + + @property + def ElseBranch(self) -> ElseGenerateBranch: + + + +.. _vhdlmodel-casegenerate: + +Case Generate +------------- + +.. todo:: + + Write documentation. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.CaseGenerateStatement`: + +.. code-block:: Python + + @export + class CaseGenerateStatement(GenerateStatement): + # inherited from ModelEntity + @property + def Parent(self) -> ModelEntity: + + # inherited from LabeledEntity + @property + def Label(self) -> str: + + # from CaseGenerateStatement + @property + def SelectExpression(self) -> BaseExpression: + + @property + def Cases(self) -> List[GenerateCase]: + + + +.. _vhdlmodel-forgenerate: + +For Generate +------------ + +.. todo:: + + Write documentation. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.ForGenerateStatement`: + +.. code-block:: Python + + @export + class ForGenerateStatement(GenerateStatement): + # inherited from ModelEntity + @property + def Parent(self) -> ModelEntity: + + # inherited from LabeledEntity + @property + def Label(self) -> str: + + # inherited from ConcurrentDeclarations + @property + def DeclaredItems(self) -> List: + + # inherited from ConcurrentStatements + @property + def Statements(self) -> List[ConcurrentStatement]: + + # from ForGenerateStatement + @property + def LoopIndex(self) -> Constant: + + @property + def Range(self) -> Range: + + + +.. _vhdlmodel-con-procedurecall: + +Procedure Call +============== + +.. todo:: + + Write documentation. + +.. _vhdlmodel-process: + +Process +======= + +.. todo:: + + Write documentation. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.ForGenerateStatement`: + +.. code-block:: Python + + class ProcessStatement(ConcurrentStatement, SequentialDeclarations, SequentialStatements): + # inherited from ModelEntity + @property + def Parent(self) -> ModelEntity: + + # inherited from LabeledEntity + @property + def Label(self) -> str: + + # inherited from SequentialDeclarations + @property + def DeclaredItems(self) -> List: + + # inherited from SequentialStatements + @property + def Statements(self) -> List[SequentialStatement]: + + # from ProcessStatement + @property + def SensitivityList(self) -> List[Signal]: diff --git a/_sources/LanguageModel/DesignUnits.rst.txt b/_sources/LanguageModel/DesignUnits.rst.txt new file mode 100644 index 000000000..bcfe2e3c7 --- /dev/null +++ b/_sources/LanguageModel/DesignUnits.rst.txt @@ -0,0 +1,224 @@ +.. _vhdlmodel-desuni: + +Design Units +############ + +A VHDL design (see :ref:`vhdlmodel-design`) is assembled from *design units*. VHDL distinguishes +between *primary* and *secondary* design units. + +.. contents:: Table of Content + :local: + +.. rubric:: Class Hierarchy + +.. inheritance-diagram:: pyVHDLModel.SyntaxModel.Architecture pyVHDLModel.SyntaxModel.Context pyVHDLModel.SyntaxModel.Configuration pyVHDLModel.SyntaxModel.Entity pyVHDLModel.SyntaxModel.Package pyVHDLModel.SyntaxModel.PackageBody + :parts: 1 + +.. _vhdlmodel-primary: + +Primary Units +============= + +.. _vhdlmodel-context: + +Context +------- + +.. todo:: + + Write documentation. + + + +.. _vhdlmodel-configuration: + +Configuration +------------- + +.. todo:: + + Write documentation. + + + +.. _vhdlmodel-entity: + +Entity +------ + +An ``Entity`` represents a VHDL entity declaration. Libraries and package +references declared ahead an entity are consumed by that entity and made +available as lists. An entities also provides lists of generic and port items. +The list of declared items (e.g. objects) also contains defined items (e.g. +types). An entity's list of statements is called body items. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.Entity`: + +.. code-block:: Python + + @export + class Entity(PrimaryUnit, MixinDesignUnitWithContext): + # inherited from ModelEntity + @property + def Parent(self) -> ModelEntity: + + # inherited from NamedEntity + @property + def Name(self) -> str: + + # inherited from MixinDesignUnitWithContext + @property + def LibraryReferences(self) -> List[LibraryClause]: + + @property + def PackageReferences(self) -> List[UseClause]: + + @property + def ContextReferences(self) -> List[Context]: + + # from Entity + @property + def GenericItems(self) -> List[GenericInterfaceItem]: + + @property + def PortItems(self) -> List[PortInterfaceItem]: + + @property + def DeclaredItems(self) -> List: + + @property + def BodyItems(self) -> List[ConcurrentStatement]: + + + +.. _vhdlmodel-package: + +Package +------- + +.. todo:: + + Write documentation. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.Package`: + +.. code-block:: Python + + @export + class Package(PrimaryUnit, MixinDesignUnitWithContext): + # inherited from ModelEntity + @property + def Parent(self) -> ModelEntity: + + # inherited from NamedEntity + @property + def Name(self) -> str: + + # inherited from MixinDesignUnitWithContext + @property + def LibraryReferences(self) -> List[LibraryClause]: + + @property + def PackageReferences(self) -> List[UseClause]: + + @property + def ContextReferences(self) -> List[Context]: + + # from Package + @property + def GenericItems(self) -> List[GenericInterfaceItem]: + + @property + def DeclaredItems(self) -> List: + + + +.. _vhdlmodel-secondary: + +Secondary Units +=============== + +.. _vhdlmodel-architeture: + +Architeture +----------- + +.. todo:: + + Write documentation. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.Architecture`: + +.. code-block:: Python + + @export + class Architecture(SecondaryUnit, MixinDesignUnitWithContext): + # inherited from ModelEntity + @property + def Parent(self) -> ModelEntity: + + # inherited from NamedEntity + @property + def Name(self) -> str: + + # inherited from MixinDesignUnitWithContext + @property + def LibraryReferences(self) -> List[LibraryClause]: + + @property + def PackageReferences(self) -> List[UseClause]: + + @property + def ContextReferences(self) -> List[Context]: + + # from Architecture + @property + def Entity(self) -> Entity: + + @property + def DeclaredItems(self) -> List: + + @property + def BodyItems(self) -> List[ConcurrentStatement]: + + + +.. _vhdlmodel-packagebody: + +Package Body +------------ + +.. todo:: + + Write documentation. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.PackageBody`: + +.. code-block:: Python + + @export + class PackageBody(SecondaryUnit, MixinDesignUnitWithContext): + # inherited from ModelEntity + @property + def Parent(self) -> ModelEntity: + + # inherited from NamedEntity + @property + def Name(self) -> str: + + # inherited from MixinDesignUnitWithContext + @property + def LibraryReferences(self) -> List[LibraryClause]: + + @property + def PackageReferences(self) -> List[UseClause]: + + @property + def ContextReferences(self) -> List[Context]: + + # from Package Body + @property + def Package(self) -> Package: + + @property + def DeclaredItems(self) -> List: diff --git a/_sources/LanguageModel/Enumerations.rst.txt b/_sources/LanguageModel/Enumerations.rst.txt new file mode 100644 index 000000000..8f13891bf --- /dev/null +++ b/_sources/LanguageModel/Enumerations.rst.txt @@ -0,0 +1,76 @@ +.. _vhdlmodel-enum: + +Enumerations +############ + +The language model contains some enumerations to express a *kind* of a models +entity. These are not enumerated types defined by VHDL itself, like ``boolean``. + +.. contents:: Table of Content + :local: + + +.. _vhdlmodel-direction: + +Direction +========= + +Ranges and slices have an ascending (``To``) or descending (``DownTo``) direction. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.Direction`: + +.. code-block:: Python + + @export + class Direction(Enum): + To = 0 + DownTo = 1 + + + +.. _vhdlmodel-mode: + +Mode +==== + +A *mode* describes the direction of data exchange e.g. for entity ports or subprogram parameters. +In addition to the modes defined by VHDL (``In``, ``Out``, ``InOut``, ``Buffer`` and ``Linkage``), ``Default`` +is a placeholder for omitted modes. The mode is then determined from the context. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.Mode`: + +.. code-block:: Python + + @export + class Mode(Enum): + Default = 0 + In = 1 + Out = 2 + InOut = 3 + Buffer = 4 + Linkage = 5 + + + +.. _vhdlmodel-objclass: + +Object ObjectClass +================== + +In addition to the 4 object classes defined by VHDL (`Constant`, `Variable`, +`Signal` and `File`), `Default` is used when no object class is defined. In +such a case, the object class is determined from the context. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.ObjectClass`: + +.. code-block:: Python + + @export + class ObjectClass(Enum): + Default = 0 + Constant = 1 + Variable = 2 + Signal = 3 + File = 4 + Type = 5 + Subprogram = 6 diff --git a/_sources/LanguageModel/Expressions.rst.txt b/_sources/LanguageModel/Expressions.rst.txt new file mode 100644 index 000000000..0f4d08573 --- /dev/null +++ b/_sources/LanguageModel/Expressions.rst.txt @@ -0,0 +1,198 @@ +.. _vhdlmodel-expr: + +Literals and Expressions +######################## + +.. contents:: Table of Content + :local: + +.. rubric:: Class Hierarchy + +.. inheritance-diagram:: pyVHDLModel.SyntaxModel.EnumerationLiteral pyVHDLModel.SyntaxModel.IntegerLiteral pyVHDLModel.SyntaxModel.FloatingPointLiteral pyVHDLModel.SyntaxModel.PhysicalLiteral pyVHDLModel.SyntaxModel.CharacterLiteral pyVHDLModel.SyntaxModel.StringLiteral pyVHDLModel.SyntaxModel.BitStringLiteral + :parts: 1 + +.. _vhdlmodel-literals: + +Literals +======== + +.. _vhdlmodel-enumerationliteral: + +Enumeration Literal +------------------- + +.. todo:: + + Write documentation. + + + +.. _vhdlmodel-integerliteral: + +Integer Literal +--------------- + +.. todo:: + + Write documentation. + + + +.. _vhdlmodel-realliteral: + +Floating Point Literal +---------------------- + +.. todo:: + + Write documentation. + + + +.. _vhdlmodel-physicalliteral: + +Physical Literal +---------------- + +.. todo:: + + Write documentation. + + + +.. _vhdlmodel-expressions: + +Expressions +=========== + +.. rubric:: Class Hierarchy + +.. inheritance-diagram:: pyVHDLModel.SyntaxModel.UnaryExpression pyVHDLModel.SyntaxModel.AddingExpression pyVHDLModel.SyntaxModel.MultiplyingExpression pyVHDLModel.SyntaxModel.LogicalExpression pyVHDLModel.SyntaxModel.ShiftExpression pyVHDLModel.SyntaxModel.TernaryExpression + :parts: 1 + +.. todo:: + + Write documentation. + + + +.. _vhdlmodel-unary: + +Unary Expressions +----------------- + +.. rubric:: Class Hierarchy + +.. inheritance-diagram:: pyVHDLModel.SyntaxModel.InverseExpression pyVHDLModel.SyntaxModel.IdentityExpression pyVHDLModel.SyntaxModel.NegationExpression pyVHDLModel.SyntaxModel.AbsoluteExpression pyVHDLModel.SyntaxModel.TypeConversion pyVHDLModel.SyntaxModel.FunctionCall pyVHDLModel.SyntaxModel.QualifiedExpression + :parts: 1 + +.. todo:: + + Write documentation. + + + +.. _vhdlmodel-binary: + +Binary Expressions +------------------ + +.. rubric:: Class Hierarchy + +.. inheritance-diagram:: pyVHDLModel.SyntaxModel.AddingExpression pyVHDLModel.SyntaxModel.MultiplyingExpression pyVHDLModel.SyntaxModel.LogicalExpression pyVHDLModel.SyntaxModel.RelationalExpression pyVHDLModel.SyntaxModel.ShiftExpression + :parts: 1 + +.. todo:: + + Write documentation. + + + +.. _vhdlmodel-addingexpression: + +Adding Expressions +~~~~~~~~~~~~~~~~~~ + +.. rubric:: Class Hierarchy + +.. inheritance-diagram:: pyVHDLModel.SyntaxModel.AdditionExpression pyVHDLModel.SyntaxModel.SubtractionExpression pyVHDLModel.SyntaxModel.ConcatenationExpression + :parts: 1 + +.. todo:: + + Write documentation. + + + +.. _vhdlmodel-multiplyingexpressions: + +Multiplying Expressions +~~~~~~~~~~~~~~~~~~~~~~~ + +.. rubric:: Class Hierarchy + +.. inheritance-diagram:: pyVHDLModel.SyntaxModel.MultiplyExpression pyVHDLModel.SyntaxModel.DivisionExpression pyVHDLModel.SyntaxModel.RemainderExpression pyVHDLModel.SyntaxModel.ModuloExpression pyVHDLModel.SyntaxModel.ExponentiationExpression + :parts: 1 + +.. todo:: + + Write documentation. + + + +.. _vhdlmodel-logicalexpressions: + +Logical Expressions +~~~~~~~~~~~~~~~~~~~ + +.. rubric:: Class Hierarchy + +.. inheritance-diagram:: pyVHDLModel.SyntaxModel.AndExpression pyVHDLModel.SyntaxModel.NandExpression pyVHDLModel.SyntaxModel.OrExpression pyVHDLModel.SyntaxModel.NorExpression pyVHDLModel.SyntaxModel.XorExpression pyVHDLModel.SyntaxModel.XnorExpression + :parts: 1 + +.. todo:: + + Write documentation. + + + +.. _vhdlmodel-relationalexpressions: + +Relational Expressions +~~~~~~~~~~~~~~~~~~~~~~ + +.. rubric:: Class Hierarchy + +.. inheritance-diagram:: pyVHDLModel.SyntaxModel.EqualExpression pyVHDLModel.SyntaxModel.UnequalExpression pyVHDLModel.SyntaxModel.GreaterThanExpression pyVHDLModel.SyntaxModel.GreaterEqualExpression pyVHDLModel.SyntaxModel.LessThanExpression + :parts: 1 + +.. todo:: + + Write documentation. + + + +.. _vhdlmodel-shiftingexpressions: + +Shifting Expressions +~~~~~~~~~~~~~~~~~~~~ + +.. rubric:: Class Hierarchy + +.. inheritance-diagram:: pyVHDLModel.SyntaxModel.ShiftRightLogicExpression pyVHDLModel.SyntaxModel.ShiftLeftLogicExpression pyVHDLModel.SyntaxModel.ShiftRightArithmeticExpression pyVHDLModel.SyntaxModel.ShiftLeftArithmeticExpression pyVHDLModel.SyntaxModel.RotateRightExpression pyVHDLModel.SyntaxModel.RotateLeftExpression + :parts: 1 + +.. todo:: + + Write documentation. + + + +.. _vhdlmodel-ternary: + +Ternary Expressions +------------------- + +.. todo:: + + Write documentation. diff --git a/_sources/LanguageModel/InterfaceItems.rst.txt b/_sources/LanguageModel/InterfaceItems.rst.txt new file mode 100644 index 000000000..34b2a2019 --- /dev/null +++ b/_sources/LanguageModel/InterfaceItems.rst.txt @@ -0,0 +1,301 @@ +.. _vhdlmodel-inter: + +Interface Items +################### + +Interface items are used in generic, port and parameter declarations. + +.. contents:: Table of Content + :local: + +.. rubric:: Class Hierarchy + +.. inheritance-diagram:: pyVHDLModel.SyntaxModel.GenericConstantInterfaceItem pyVHDLModel.SyntaxModel.GenericTypeInterfaceItem pyVHDLModel.SyntaxModel.GenericProcedureInterfaceItem pyVHDLModel.SyntaxModel.GenericFunctionInterfaceItem pyVHDLModel.SyntaxModel.PortSignalInterfaceItem pyVHDLModel.SyntaxModel.ParameterConstantInterfaceItem pyVHDLModel.SyntaxModel.ParameterVariableInterfaceItem pyVHDLModel.SyntaxModel.ParameterSignalInterfaceItem pyVHDLModel.SyntaxModel.ParameterFileInterfaceItem + :parts: 1 + + +.. _vhdlmodel-generics: + +Generic Interface Items +======================= + +.. _vhdlmodel-genericconstant: + +GenericConstantInterfaceItem +---------------------------- + +.. todo:: + + Write documentation. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.GenericConstantInterfaceItem`: + +.. code-block:: Python + + @export + class GenericConstantInterfaceItem(Constant, GenericInterfaceItem): + # inherited from ModelEntity + @property + def Parent(self) -> ModelEntity: + + # inherited from NamedEntity + @property + def Name(self) -> str: + + # inherited from Object + @property + def Subtype(self) -> Subtype: + + # inherited from WithDefaultExpressionMixin + @property + def DefaultExpression(self) -> BaseExpression: + + # inherited from InterfaceItem + @property + def Mode(self) -> Mode: + + + +.. _vhdlmodel-generictype: + +GenericTypeInterfaceItem +------------------------ + +.. todo:: + + Write documentation. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.GenericTypeInterfaceItem`: + +.. code-block:: Python + + @Export + class GenericTypeInterfaceItem(GenericInterfaceItem): + + +.. _vhdlmodel-genericprocedure: + +GenericProcedureInterfaceItem +----------------------------- + +.. todo:: + + Write documentation. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.GenericProcedureInterfaceItem`: + +.. code-block:: Python + + @Export + class GenericProcedureInterfaceItem(GenericSubprogramInterfaceItem): + + + +.. _vhdlmodel-genericfunction: + +GenericFunctionInterfaceItem +---------------------------- + +.. todo:: + + Write documentation. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.GenericFunctionInterfaceItem`: + +.. code-block:: Python + + @Export + class GenericFunctionInterfaceItem(GenericSubprogramInterfaceItem): + + + +.. _vhdlmodel-genericpackage: + +GenericPackageInterfaceItem +--------------------------- + +.. todo:: + + Write documentation. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.GenericPackageInterfaceItem`: + +.. code-block:: Python + + @Export + class GenericPackageInterfaceItem(GenericInterfaceItem): + + +.. _vhdlmodel-ports: + +Port Interface Item +=================== + +.. _vhdlmodel-portsignal: + +PortSignalInterfaceItem +----------------------- + +.. todo:: + + Write documentation. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.PortSignalInterfaceItem`: + +.. code-block:: Python + + @export + class PortSignalInterfaceItem(Signal, PortInterfaceItem): + # inherited from ModelEntity + @property + def Parent(self) -> ModelEntity: + + # inherited from NamedEntity + @property + def Name(self) -> str: + + # inherited from Object + @property + def Subtype(self) -> Subtype: + + # inherited from WithDefaultExpressionMixin + @property + def DefaultExpression(self) -> BaseExpression: + + # inherited from InterfaceItem + @property + def Mode(self) -> Mode: + + + +.. _vhdlmodel-parameters: + +Parameter Interface Item +========================= + +.. _vhdlmodel-parameterconstant: + +ParameterConstantInterfaceItem +------------------------------ + +.. todo:: + + Write documentation. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.ParameterConstantInterfaceItem`: + +.. code-block:: Python + + @export + class ParameterConstantInterfaceItem(Constant, ParameterInterfaceItem): + # inherited from ModelEntity + @property + def Parent(self) -> ModelEntity: + + # inherited from NamedEntity + @property + def Name(self) -> str: + + # inherited from Object + @property + def Subtype(self) -> Subtype: + + # inherited from WithDefaultExpressionMixin + @property + def DefaultExpression(self) -> BaseExpression: + + # inherited from InterfaceItem + @property + def Mode(self) -> Mode: + + + +.. _vhdlmodel-parametervariable: + +ParameterVariableInterfaceItem +------------------------------ + +.. todo:: + + Write documentation. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.ParameterVariableInterfaceItem`: + +.. code-block:: Python + + @export + class ParameterVariableInterfaceItem(Variable, ParameterInterfaceItem): + # inherited from ModelEntity + @property + def Parent(self) -> ModelEntity: + + # inherited from NamedEntity + @property + def Name(self) -> str: + + # inherited from Object + @property + def Subtype(self) -> Subtype: + + # inherited from WithDefaultExpressionMixin + @property + def DefaultExpression(self) -> BaseExpression: + + # inherited from InterfaceItem + @property + def Mode(self) -> Mode: + + + +.. _vhdlmodel-parametersignal: + +ParameterSignalInterfaceItem +---------------------------- + +.. todo:: + + Write documentation. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.ParameterSignalInterfaceItem`: + +.. code-block:: Python + + @export + class ParameterSignalInterfaceItem(Signal, ParameterInterfaceItem): + # inherited from ModelEntity + @property + def Parent(self) -> ModelEntity: + + # inherited from NamedEntity + @property + def Name(self) -> str: + + # inherited from Object + @property + def Subtype(self) -> Subtype: + + # inherited from WithDefaultExpressionMixin + @property + def DefaultExpression(self) -> BaseExpression: + + # inherited from InterfaceItem + @property + def Mode(self) -> Mode: + + + +.. _vhdlmodel-parameterfile: + +ParameterFileInterfaceItem +-------------------------- + +.. todo:: + + Write documentation. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.ParameterFileInterfaceItem`: + +.. code-block:: Python + + @Export + class ParameterFileInterfaceItem(ParameterInterfaceItem): diff --git a/_sources/LanguageModel/Miscellaneous.rst.txt b/_sources/LanguageModel/Miscellaneous.rst.txt new file mode 100644 index 000000000..6cb8926b7 --- /dev/null +++ b/_sources/LanguageModel/Miscellaneous.rst.txt @@ -0,0 +1,127 @@ +.. _vhdlmodel-misc: + +Concepts not defined by VHDL +############################ + +Some features required for a holistic language model are not defined in the VHDL +:term:`LRM` (IEEE Std. 1076). Other features are made explicitly implementation +specific to the implementer. This chapter will cover these parts. + +.. contents:: Table of Content + :local: + + +.. _vhdlmodel-design: + +Design +====== + +The root element in the language model is a design made out of multiple +sourcecode files (documents). Sourcecode files are compiled into libraries. Thus +a design has the two child nodes: :attr:`~pyVHDLModel.SyntaxModel.Design.Libraries` +and :attr:`~pyVHDLModel.SyntaxModel.Design.Documents`. Each is a :class:`list`. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.Design`: + +.. code-block:: Python + + @export + class Design(ModelEntity): + # inherited from ModelEntity + @property + def Parent(self) -> ModelEntity: + + # from Design + @property + def Libraries(self) -> Dict[str, Library]: + + @property + def Documents(self) -> List[Document]: + + def GetLibrary(self, libraryName: str) -> Library: + + def AddDocument(self, document: Document, library: Library): + + +.. _vhdlmodel-library: + +Library +======= + +A library contains multiple *design units*. Each design unit listed in a library +is a *primary* design unit like: :class:`~pyVHDLModel.SyntaxModel.Configuration`, +:class:`~pyVHDLModel.SyntaxModel.Entity`, :class:`~pyVHDLModel.SyntaxModel.Package` or +:class:`~pyVHDLModel.SyntaxModel.Context`. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.Library`: + +.. code-block:: Python + + @export + class Library(ModelEntity): + # inherited from ModelEntity + @property + def Parent(self) -> ModelEntity: + + # from Library + @property + def Contexts(self) -> List[Context]: + + @property + def Configurations(self) -> List[Configuration]: + + @property + def Entities(self) -> List[Entity]: + + @property + def Packages(self) -> List[Package]: + + + +.. _vhdlmodel-document: + +Document +======== + +A source file (document) contains multiple *design units*. Each design unit +listed in a sourcecode file is a *primary* or *secondary* design unit like: +``configuration``, ``entity``, ``architecture``, ``package``, ``package body`` +or ``context``. + +Design unit may be preceded by a context made of ``library``, ``use`` and +``context`` statements. These statements are not directly visible in the +``Document`` object, because design unit contexts are consumed by the design +units. See the ``Libraries`` and ``Uses`` fields of each design unit to +investigate the consumed contexts. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.Document`: + +.. code-block:: Python + + @export + class Document(ModelEntity): + # inherited from ModelEntity + @property + def Parent(self) -> ModelEntity: + + # from Document + @property + def Path(self) -> Path: + + @property + def Contexts(self) -> List[Context]: + + @property + def Configurations(self) -> List[Configuration]: + + @property + def Entities(self) -> List[Entity]: + + @property + def Architectures(self) -> List[Architecture]: + + @property + def Packages(self) -> List[Package]: + + @property + def PackageBodies(self) -> List[PackageBody]: diff --git a/_sources/LanguageModel/ObjectDeclarations.rst.txt b/_sources/LanguageModel/ObjectDeclarations.rst.txt new file mode 100644 index 000000000..369b7052c --- /dev/null +++ b/_sources/LanguageModel/ObjectDeclarations.rst.txt @@ -0,0 +1,270 @@ +.. _vhdlmodel-obj: + +Object Declarations +################### + +.. contents:: Table of Content + :local: + +.. #rubric:: Class Hierarchy + +.. #inheritance-diagram:: pyVHDLModel.SyntaxModel.Constant pyVHDLModel.SyntaxModel.DeferredConstant pyVHDLModel.SyntaxModel.GenericConstantInterfaceItem pyVHDLModel.SyntaxModel.ParameterConstantInterfaceItem pyVHDLModel.SyntaxModel.Variable pyVHDLModel.SyntaxModel.ParameterVariableInterfaceItem pyVHDLModel.SyntaxModel.Signal pyVHDLModel.SyntaxModel.PortSignalInterfaceItem pyVHDLModel.SyntaxModel.ParameterSignalInterfaceItem pyVHDLModel.SyntaxModel.File pyVHDLModel.SyntaxModel.ParameterFileInterfaceItem + :parts: 1 + + + +.. _vhdlmodel-constants: + +Constants +========= + +VHDL defines regular constants as an object. In addition, deferred constants are +supported in package declarations. Often generics to e.g. packages or entities +are constants. Also most *in* parameters to subprograms are constants. + +.. inheritance-diagram:: pyVHDLModel.SyntaxModel.Constant pyVHDLModel.SyntaxModel.DeferredConstant pyVHDLModel.SyntaxModel.GenericConstantInterfaceItem pyVHDLModel.SyntaxModel.ParameterConstantInterfaceItem + :parts: 1 + + + +.. _vhdlmodel-constant: + +Constant +-------- + +A constant represents immutable data. This data (value) must be assigned via a +default expression. If a constant's value is delayed in calculation, it's called +a deferred constant. See :ref:`vhdlmodel-deferredconstant` in next section. + + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.Constant`: + +.. code-block:: Python + + @export + class Constant(BaseConstant): + # inherited from ModelEntity + @property + def Parent(self) -> ModelEntity: + + # inherited from NamedEntity + @property + def Name(self) -> str: + + # inherited from Object + @property + def Subtype(self) -> Subtype: + + @property + def DefaultExpression(self) -> BaseExpression: + + + +.. _vhdlmodel-deferredconstant: + +Deferred Constant +----------------- + +If a constant's value is delayed in calculation, it's a deferred constant. Such +a deferred constant has a reference to the *regular* constant of the same name. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.DeferredConstant`: + +.. code-block:: Python + + @export + class DeferredConstant(BaseConstant): + # inherited from ModelEntity + @property + def Parent(self) -> ModelEntity: + + # inherited from NamedEntity + @property + def Name(self) -> str: + + # inherited from Object + @property + def Subtype(self) -> Subtype: + + # inherited from WithDefaultExpressionMixin + @property + def ConstantReference(self) -> Constant: + + + +.. _vhdlmodel-obj-genericconstant: + +Generic Constant +---------------- + +A generic without object class or a generic constant is a *regular* constant. + +.. seealso:: + + See :ref:`vhdlmodel-genericconstant` for details. + +.. _vhdlmodel-obj-parameterconstant: + +Constant as Parameter +--------------------- + +A subprogram parameter without object class of mode *in* or a parameter constant is a *regular* constant. + +.. seealso:: + + See :ref:`vhdlmodel-parameterconstant` for details. + + + +.. _vhdlmodel-variables: + +Variables +========= + +.. inheritance-diagram:: pyVHDLModel.SyntaxModel.Variable pyVHDLModel.SyntaxModel.ParameterVariableInterfaceItem + :parts: 1 + +.. _vhdlmodel-variable: + +Variable +-------- + +A variable represents mutable data in sequential regions. Assignments to +variables have no delay. The initial value can be assigned via a default +expression. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.Variable`: + +.. code-block:: Python + + @export + class Variable(Object): + # inherited from ModelEntity + @property + def Parent(self) -> ModelEntity: + + # inherited from NamedEntity + @property + def Name(self) -> str: + + # inherited from Object + @property + def Subtype(self) -> Subtype: + + # inherited from WithDefaultExpressionMixin + @property + def DefaultExpression(self) -> BaseExpression: + + + +.. _vhdlmodel-obj-parametervariable: + +Variable as Parameter +--------------------- + +A subprogram parameter without object class of mode *out* or a parameter variable is a *regular* variable. + +.. seealso:: + + See :ref:`vhdlmodel-parametervariable` for details. + + +.. _vhdlmodel-sharedvariable: + +Shared Variable +=============== + +.. todo:: + + Write documentation. + +.. _vhdlmodel-signals: + +Signals +======= + +.. inheritance-diagram:: pyVHDLModel.SyntaxModel.Signal pyVHDLModel.SyntaxModel.PortSignalInterfaceItem pyVHDLModel.SyntaxModel.ParameterSignalInterfaceItem + :parts: 1 + +.. _vhdlmodel-signal: + +Signal +------ + +A signal represents mutable data in concurrent regions. Assignments to signals +are delayed until next wait statement is executed. The initial value can be +assigned via a default expression. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.Signal`: + +.. code-block:: Python + + @export + class Signal(Object): + # inherited from ModelEntity + @property + def Parent(self) -> ModelEntity: + + # inherited from NamedEntity + @property + def Name(self) -> str: + + # inherited from Object + @property + def Subtype(self) -> Subtype: + + # inherited from WithDefaultExpressionMixin + @property + def DefaultExpression(self) -> BaseExpression: + + + +.. _vhdlmodel-obj-portsignal: + +Signal as Port +-------------- + +A port signal is a *regular* signal. + +.. seealso:: + + See :ref:`vhdlmodel-portsignal` for details. + +.. _vhdlmodel-obj-parametersignal: + +Signal as Parameter +------------------- + +A parameter signal is a *regular* signal. + +.. seealso:: + + See :ref:`vhdlmodel-parametersignal` for details. + +.. _vhdlmodel-files: + +Files +===== + +.. inheritance-diagram:: pyVHDLModel.SyntaxModel.File pyVHDLModel.SyntaxModel.ParameterFileInterfaceItem + :parts: 1 + +.. _vhdlmodel-file: + +File +---- + +.. todo:: + + Write documentation. + +.. _vhdlmodel-obj-parameterfile: + +File as Parameter +----------------- + +A parameter file is a *regular* file. + +.. seealso:: + + See :ref:`vhdlmodel-parameterfile` for details. diff --git a/_sources/LanguageModel/SequentialStatements.rst.txt b/_sources/LanguageModel/SequentialStatements.rst.txt new file mode 100644 index 000000000..5cb4394bf --- /dev/null +++ b/_sources/LanguageModel/SequentialStatements.rst.txt @@ -0,0 +1,451 @@ +.. _vhdlmodel-seqstm: + +Sequential Statements +##################### + +.. contents:: Table of Content + :local: + +.. rubric:: Class Hierarchy + +.. inheritance-diagram:: pyVHDLModel.SyntaxModel.SequentialAssertStatement pyVHDLModel.SyntaxModel.SequentialReportStatement pyVHDLModel.SyntaxModel.SequentialSignalAssignment pyVHDLModel.SyntaxModel.VariableAssignment pyVHDLModel.SyntaxModel.IfStatement pyVHDLModel.SyntaxModel.CaseStatement pyVHDLModel.SyntaxModel.EndlessLoopStatement pyVHDLModel.SyntaxModel.ForLoopStatement pyVHDLModel.SyntaxModel.WhileLoopStatement pyVHDLModel.SyntaxModel.NextStatement pyVHDLModel.SyntaxModel.ExitStatement pyVHDLModel.SyntaxModel.SequentialProcedureCall pyVHDLModel.SyntaxModel.WaitStatement pyVHDLModel.SyntaxModel.ReturnStatement + :parts: 1 + +.. _vhdlmodel-seq-assignments: + +Assignments +=========== + + + +.. _vhdlmodel-seq-signalassignment: + +Signal Assignment +----------------- + +.. todo:: + + Write documentation. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.SequentialSignalAssignment`: + +.. code-block:: Python + + @export + class SequentialSignalAssignment(SequentialStatement, SignalAssignment): + # inherited from ModelEntity + @property + def Parent(self) -> ModelEntity: + + # inherited from LabeledEntity + @property + def Label(self) -> str: + + # inherited from Assignment + @property + def Target(self) -> Object: + + @property + def BaseExpression(self) -> BaseExpression: + + + +.. _vhdlmodel-variableassignment: + +Variable Assignment +------------------- + +.. todo:: + + Write documentation. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.SequentialVariableAssignment`: + +.. code-block:: Python + + @export + class SequentialVariableAssignment(SequentialStatement, VariableAssignment): + # inherited from ModelEntity + @property + def Parent(self) -> ModelEntity: + + # inherited from LabeledEntity + @property + def Label(self) -> str: + + # inherited from Assignment + @property + def Target(self) -> Object: + + @property + def BaseExpression(self) -> BaseExpression: + + + +.. _vhdlmodel-branching: + +Branching +========= + +.. _vhdlmodel-ifstatement: + +If Statement +------------ + +.. todo:: + + Write documentation. + + + +.. _vhdlmodel-casestatement: + +Case Statement +-------------- + +.. todo:: + + Write documentation. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.CaseStatement`: + +.. code-block:: Python + + @export + class CaseStatement(CompoundStatement): + # inherited from ModelEntity + @property + def Parent(self) -> ModelEntity: + + # inherited from LabeledEntity + @property + def Label(self) -> str: + + # from CaseGenerateStatement + @property + def SelectExpression(self) -> BaseExpression: + + @property + def Cases(self) -> List[SequentialCase]: + + + +.. _vhdlmodel-loops: + +Loops +===== + +.. _vhdlmodel-endlessloop: + +Endless Loop +------------ + +.. todo:: + + Write documentation. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.EndlessLoopStatement`: + +.. code-block:: Python + + @export + class EndlessLoopStatement(LoopStatement): + # inherited from ModelEntity + @property + def Parent(self) -> ModelEntity: + + # inherited from LabeledEntity + @property + def Label(self) -> str: + + # inherited from SequentialStatements + @property + def Statements(self) -> List[SequentialStatement]: + + + +.. _vhdlmodel-forloop: + +For Loop +-------- + +.. todo:: + + Write documentation. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.ForLoopStatement`: + +.. code-block:: Python + + @export + class ForLoopStatement(LoopStatement): + # inherited from ModelEntity + @property + def Parent(self) -> ModelEntity: + + # inherited from LabeledEntity + @property + def Label(self) -> str: + + # inherited from SequentialStatements + @property + def Statements(self) -> List[SequentialStatement]: + + # from ForLoopStatement + @property + def LoopIndex(self) -> Constant: + + @property + def Range(self) -> Range: + + + +.. _vhdlmodel-whileloop: + +While Loop +---------- + +.. todo:: + + Write documentation. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.WhileLoopStatement`: + +.. code-block:: Python + + @export + class WhileLoopStatement(LoopStatement, BaseConditional): + # inherited from ModelEntity + @property + def Parent(self) -> ModelEntity: + + # inherited from LabeledEntity + @property + def Label(self) -> str: + + # inherited from SequentialStatements + @property + def Statements(self) -> List[SequentialStatement]: + + # inherited from BaseConditional + @property + def Condition(self) -> BaseExpression: + + +.. _vhdlmodel-nextstatement: + +Next Statement +-------------- + +.. todo:: + + Write documentation. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.NextStatement`: + +.. code-block:: Python + + @export + class NextStatement(SequentialStatement, BaseConditional): + # inherited from ModelEntity + @property + def Parent(self) -> ModelEntity: + + # inherited from LabeledEntity + @property + def Label(self) -> str: + + # inherited from BaseCondition + @property + def Condition(self) -> BaseExpression: + + # inherited from LoopControlStatement + @property + def LoopReference(self) -> LoopStatement: + + + +.. _vhdlmodel-exitstatement: + +Exit Statement +-------------- + +.. todo:: + + Write documentation. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.ExitStatement`: + +.. code-block:: Python + + @export + class ExitStatement(SequentialStatement, BaseConditional): + # inherited from ModelEntity + @property + def Parent(self) -> ModelEntity: + + # inherited from LabeledEntity + @property + def Label(self) -> str: + + # inherited from BaseCondition + @property + def Condition(self) -> BaseExpression: + + # inherited from LoopControlStatement + @property + def LoopReference(self) -> LoopStatement: + + + +.. _vhdlmodel-reporting: + +Reporting +========= + + +.. _vhdlmodel-seq-reportstatement: + +Report Statement +---------------- + +.. todo:: + + Write documentation. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.SequentialReportStatement`: + +.. code-block:: Python + + @export + class SequentialReportStatement(SequentialStatement, MixinReportStatement): + # inherited from ModelEntity + @property + def Parent(self) -> ModelEntity: + + # inherited from LabeledEntity + @property + def Label(self) -> str: + + # inherited from MixinReportStatement + @property + def Message(self) -> BaseExpression: + + @property + def Severity(self) -> BaseExpression: + + + +.. _vhdlmodel-seq-assertstatement: + +Assert Statement +---------------- + +.. todo:: + + Write documentation. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.SequentialAssertStatement`: + +.. code-block:: Python + + @export + class SequentialAssertStatement(SequentialStatement, MixinAssertStatement): + # inherited from ModelEntity + @property + def Parent(self) -> ModelEntity: + + # inherited from LabeledEntity + @property + def Label(self) -> str: + + # inherited from MixinReportStatement + @property + def Message(self) -> BaseExpression: + + @property + def Severity(self) -> BaseExpression: + + # inherited from MixinAssertStatement + @property + def Condition(self) -> BaseExpression: + + + +.. _vhdlmodel-seq-procedurecall: + +Procedure Call +============== + +.. todo:: + + Write documentation. + + + +.. _vhdlmodel-waitstatement: + +Wait Statement +============== + +.. todo:: + + Write documentation. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.WaitStatement`: + +.. code-block:: Python + + @export + class WaitStatement(SequentialStatement, BaseConditional): + # inherited from ModelEntity + @property + def Parent(self) -> ModelEntity: + + # inherited from LabeledEntity + @property + def Label(self) -> str: + + # inherited from BaseCondition + @property + def Condition(self) -> BaseExpression: + + # from WaitStatement + @property + def SensitivityList(self) -> List[Signal]: + + @property + def Timeout(self) -> BaseExpression: + + + +.. _vhdlmodel-returnstatement: + +Return Statement +================ + +.. todo:: + + Write documentation. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.ReturnStatement`: + +.. code-block:: Python + + @export + class ReturnStatement(SequentialStatement, BaseConditional): + # inherited from ModelEntity + @property + def Parent(self) -> ModelEntity: + + # inherited from LabeledEntity + @property + def Label(self) -> str: + + # inherited from BaseCondition + @property + def Condition(self) -> BaseExpression: + + # from ReturnStatement + @property + def ReturnValue(self) -> BaseExpression: diff --git a/_sources/LanguageModel/SubprogramDefinitions.rst.txt b/_sources/LanguageModel/SubprogramDefinitions.rst.txt new file mode 100644 index 000000000..08f41f7cb --- /dev/null +++ b/_sources/LanguageModel/SubprogramDefinitions.rst.txt @@ -0,0 +1,242 @@ +.. _vhdlmodel-subprog: + +Subprogram Declarations +######################## + +.. contents:: Table of Content + :local: + +.. #rubric:: Class Hierarchy + +.. #inheritance-diagram:: pyVHDLModel.SyntaxModel.Procedure pyVHDLModel.SyntaxModel.ProcedureMethod pyVHDLModel.SyntaxModel.GenericProcedureInterfaceItem pyVHDLModel.SyntaxModel.Function pyVHDLModel.SyntaxModel.FunctionMethod pyVHDLModel.SyntaxModel.GenericFunctionInterfaceItem + :parts: 1 + +.. _vhdlmodel-procedures: + +Procedures +========== + +.. inheritance-diagram:: pyVHDLModel.SyntaxModel.Procedure pyVHDLModel.SyntaxModel.ProcedureMethod pyVHDLModel.SyntaxModel.GenericProcedureInterfaceItem + :parts: 1 + + + +.. _vhdlmodel-procedure: + +Procedure +--------- + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.Procedure`: + +.. code-block:: Python + + @export + class Procedure(SubProgramm): + # inherited from ModelEntity + @property + def Parent(self) -> ModelEntity: + + # inherited from NamedEntity + @property + def Name(self) -> str: + + # inherited from Subprogram + @property + def GenericItems(self) -> List[GenericInterfaceItem]: + + @property + def ParameterItems(self) -> List[ParameterInterfaceItem]: + + @property + def DeclaredItems(self) -> List: + + @property + def BodyItems(self) -> List[SequentialStatement]: + + @property + def IsPure(self) -> bool: + + + +.. _vhdlmodel-procedureinstantiation: + +Procedure Instantiation +----------------------- + +.. todo:: + + Write documentation. + + + +.. _vhdlmodel-proceduremethod: + +Procedure as Method +------------------- + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.ProcedureMethod`: + +.. code-block:: Python + + @export + class ProcedureMethod(SubProgramm): + # inherited from ModelEntity + @property + def Parent(self) -> ModelEntity: + + # inherited from NamedEntity + @property + def Name(self) -> str: + + # inherited from Subprogram + @property + def GenericItems(self) -> List[GenericInterfaceItem]: + + @property + def ParameterItems(self) -> List[ParameterInterfaceItem]: + + @property + def DeclaredItems(self) -> List: + + @property + def BodyItems(self) -> List[SequentialStatement]: + + @property + def IsPure(self) -> bool: + + # inherited from Method + @property + def ProtectedType(self) -> ProtectedType: + + + +.. _vhdlmodel-sub-genericprocedure: + +Generic Procedure +----------------- + +A generic procedure is a *regular* procedure. + +.. seealso:: + + See :ref:`vhdlmodel-genericprocedure` for details. + + + +.. _vhdlmodel-functions: + +Functions +========= + +.. inheritance-diagram:: pyVHDLModel.SyntaxModel.Function pyVHDLModel.SyntaxModel.FunctionMethod pyVHDLModel.SyntaxModel.GenericFunctionInterfaceItem + :parts: 1 + + + +.. _vhdlmodel-function: + +Function +-------- + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.Function`: + +.. code-block:: Python + + @export + class Function(SubProgramm): + # inherited from ModelEntity + @property + def Parent(self) -> ModelEntity: + + # inherited from NamedEntity + @property + def Name(self) -> str: + + # inherited from Subprogram + @property + def GenericItems(self) -> List[GenericInterfaceItem]: + + @property + def ParameterItems(self) -> List[ParameterInterfaceItem]: + + @property + def DeclaredItems(self) -> List: + + @property + def BodyItems(self) -> List[SequentialStatement]: + + @property + def IsPure(self) -> bool: + + # from Function + @property + def ReturnType(self) -> Subtype: + + + +.. _vhdlmodel-functioninstantiation: + +Function Instantiation +---------------------- + +.. todo:: + + Write documentation. + + + +.. _vhdlmodel-functionmethod: + +Function as Method +------------------ + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.FunctionMethod`: + +.. code-block:: Python + + @export + class Function(SubProgramm): + # inherited from ModelEntity + @property + def Parent(self) -> ModelEntity: + + # inherited from NamedEntity + @property + def Name(self) -> str: + + # inherited from Subprogram + @property + def GenericItems(self) -> List[GenericInterfaceItem]: + + @property + def ParameterItems(self) -> List[ParameterInterfaceItem]: + + @property + def DeclaredItems(self) -> List: + + @property + def BodyItems(self) -> List[SequentialStatement]: + + @property + def IsPure(self) -> bool: + + # inherited from Function + @property + def ReturnType(self) -> Subtype: + + # inherited from Method + @property + def ProtectedType(self) -> ProtectedType: + + + +.. _vhdlmodel-sub-genericfunction: + +Generic Function +---------------- + +A generic function is a *regular* function. + +.. seealso:: + + See :ref:`vhdlmodel-genericfunction` for details. diff --git a/_sources/LanguageModel/SubtypeDefinitions.rst.txt b/_sources/LanguageModel/SubtypeDefinitions.rst.txt new file mode 100644 index 000000000..370886f6f --- /dev/null +++ b/_sources/LanguageModel/SubtypeDefinitions.rst.txt @@ -0,0 +1,18 @@ +.. _vhdlmodel-subtypes: + +Subtype Declarations +#################### + +VHDL has subtypes to constrain types. + +.. contents:: Table of Content + :local: + +.. rubric:: Class Hierarchy + +.. inheritance-diagram:: pyVHDLModel.SyntaxModel.Subtype + :parts: 1 + +.. todo:: + + Write documentation. diff --git a/_sources/LanguageModel/TypeDefinitions.rst.txt b/_sources/LanguageModel/TypeDefinitions.rst.txt new file mode 100644 index 000000000..5fb55c369 --- /dev/null +++ b/_sources/LanguageModel/TypeDefinitions.rst.txt @@ -0,0 +1,244 @@ +.. _vhdlmodel-types: + +Type Declarations +################# + +VHDL has types (also called a base type) and subtypes. The following shows VHDL's type hierarchy: + +.. contents:: Table of Content + :local: + +.. rubric:: Class Hierarchy + +.. inheritance-diagram:: pyVHDLModel.SyntaxModel.EnumeratedType pyVHDLModel.SyntaxModel.IntegerType pyVHDLModel.SyntaxModel.RealType pyVHDLModel.SyntaxModel.PhysicalType pyVHDLModel.SyntaxModel.ArrayType pyVHDLModel.SyntaxModel.RecordType pyVHDLModel.SyntaxModel.ProtectedType pyVHDLModel.SyntaxModel.AccessType pyVHDLModel.SyntaxModel.FileType + :parts: 1 + + +.. _vhdlmodel-scalartypes: + +Scalar Types +============ + +.. _vhdlmodel-enumeratedtypes: + +Enumeration +----------- + +.. todo:: + + Write documentation. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.EnumeratedType`: + +.. code-block:: Python + + @export + class EnumeratedType(ScalarType, DiscreteType): + # inherited from ModelEntity + @property + def Parent(self) -> ModelEntity: + + # inherited from NamedEntity + @property + def Name(self) -> str: + + # from EnumeratedType + @property + def Elements(self) -> List[str]: + + + +.. _vhdlmodel-integertypes: + +Integer +------- + +.. todo:: + + Write documentation. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.IntegerType`: + +.. code-block:: Python + + @export + class IntegerType(RangedScalarType, NumericType, DiscreteType): + # inherited from ModelEntity + @property + def Parent(self) -> ModelEntity: + + # inherited from NamedEntity + @property + def Name(self) -> str: + + # inherited from RangedScalarType + @property + def LeftBound(self) -> 'BaseExpression': + + @property + def RightBound(self) -> 'BaseExpression': + + + +.. _vhdlmodel-realtypes: + +Real +---- + +.. todo:: + + Write documentation. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.RealType`: + +.. code-block:: Python + + @export + class RealType(RangedScalarType, NumericType): + # inherited from ModelEntity + @property + def Parent(self) -> ModelEntity: + + # inherited from NamedEntity + @property + def Name(self) -> str: + + # inherited from RangedScalarType + @property + def LeftBound(self) -> 'BaseExpression': + + @property + def RightBound(self) -> 'BaseExpression': + + + +.. _vhdlmodel-physicaltypes: + +Physical +-------- + +.. todo:: + + Write documentation. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.PhysicalType`: + +.. code-block:: Python + + @export + class PhysicalType(RangedScalarType, NumericType): + # inherited from ModelEntity + @property + def Parent(self) -> ModelEntity: + + # inherited from NamedEntity + @property + def Name(self) -> str: + + # inherited from RangedScalarType + @property + def LeftBound(self) -> 'BaseExpression': + + @property + def RightBound(self) -> 'BaseExpression': + + # from PhysicalType + @property + def PrimaryUnit(self) -> str: + + @property + def SecondaryUnits(self) -> List[Tuple[int, str]]: + + + +.. _vhdlmodel-compositetypes: + +Composite Types +=============== + +.. _vhdlmodel-arraytypes: + +Array +----- + +.. todo:: + + Write documentation. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.ArrayType`: + +.. code-block:: Python + + @export + class ArrayType(CompositeType): + # inherited from ModelEntity + @property + def Parent(self) -> ModelEntity: + + # inherited from NamedEntity + @property + def Name(self) -> str: + + # from ArrayType + @property + def Dimensions(self) -> List[Range]: + + @property + def ElementType(self) -> Subtype: + + + +.. _vhdlmodel-recordtypes: + +Record +------ + +.. todo:: + + Write documentation. + +**Condensed definition of class** :class:`~pyVHDLModel.SyntaxModel.RecordType`: + +.. code-block:: Python + + @export + class RecordType(CompositeType): + # inherited from ModelEntity + @property + def Parent(self) -> ModelEntity: + + # inherited from NamedEntity + @property + def Name(self) -> str: + + # from RecordType + @property + def Members(self) -> List[RecordTypeElement]: + + +.. _vhdlmodel-protectedtypes: + +Protected +========= + +.. todo:: + + Write documentation. + +.. _vhdlmodel-accesstypes: + +Access +====== + +.. todo:: + + Write documentation. + +.. _vhdlmodel-filetypes: + +File +==== + +.. todo:: + + Write documentation. diff --git a/_sources/LanguageModel/index.rst.txt b/_sources/LanguageModel/index.rst.txt new file mode 100644 index 000000000..608f351b0 --- /dev/null +++ b/_sources/LanguageModel/index.rst.txt @@ -0,0 +1,31 @@ +.. _vhdlmodel: + +VHDL Language Model +################### + +.. rubric:: Design Goal + + * Clearly named classes that model the semantics of VHDL. + * All language constructs (statements, declarations, specifications, …) have + their own classes. |br| These classes are arranged in a logical hierarchy, + with a single common base-class. + * Child objects shall have a reference to their parent. + * Comments will be associated with a particular code object. + * Easy modifications of the object tree. + +.. rubric:: Elements of the Language Model + +.. toctree:: + :maxdepth: 1 + + Miscellaneous + Enumerations + DesignUnits + InterfaceItems + SubprogramDefinitions + TypeDefinitions + SubtypeDefinitions + ObjectDeclarations + ConcurrentStatements + SequentialStatements + Expressions diff --git a/_sources/License.rst.txt b/_sources/License.rst.txt new file mode 100644 index 000000000..fba66a206 --- /dev/null +++ b/_sources/License.rst.txt @@ -0,0 +1,140 @@ +.. _SRCLICENSE: + +.. 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We also recommend that a file or +class name and description of purpose be included on the same "printed page" as the copyright notice for easier identification within third-party archives. + +.. code-block:: none + + Copyright [yyyy] [name of copyright owner] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/_sources/TODO.rst.txt b/_sources/TODO.rst.txt new file mode 100644 index 000000000..3144da040 --- /dev/null +++ b/_sources/TODO.rst.txt @@ -0,0 +1,4 @@ +TODOs +##### + +.. todolist:: diff --git a/_sources/coverage/index.rst.txt b/_sources/coverage/index.rst.txt new file mode 100644 index 000000000..bad51b90a --- /dev/null +++ b/_sources/coverage/index.rst.txt @@ -0,0 +1,7 @@ +Code Coverage Report +#################### + +Code coverage report generated with `pytest `__ and `Coverage.py `__. + +.. report:code-coverage:: + :packageid: src diff --git a/_sources/index.rst.txt b/_sources/index.rst.txt new file mode 100644 index 000000000..69f206552 --- /dev/null +++ b/_sources/index.rst.txt @@ -0,0 +1,260 @@ +.. include:: shields.inc + +.. image:: _static/logo.svg + :height: 90 px + :align: center + :target: https://GitHub.com/VHDL/pyVHDLModel + +.. raw:: html + +
+ +.. raw:: latex + + \part{Introduction} + +.. only:: html + + | |SHIELD:svg:pyVHDLModel-github| |SHIELD:svg:pyVHDLModel-src-license| |SHIELD:svg:pyVHDLModel-ghp-doc| |SHIELD:svg:pyVHDLModel-doc-license| |SHIELD:svg:pyVHDLModel-gitter| + | |SHIELD:svg:pyVHDLModel-pypi-tag| |SHIELD:svg:pyVHDLModel-pypi-status| |SHIELD:svg:pyVHDLModel-pypi-python| + | |SHIELD:svg:pyVHDLModel-gha-test| |SHIELD:svg:pyVHDLModel-lib-status| |SHIELD:svg:pyVHDLModel-codacy-quality| |SHIELD:svg:pyVHDLModel-codacy-coverage| |SHIELD:svg:pyVHDLModel-codecov-coverage| + +.. Disabled shields: |SHIELD:svg:pyVHDLModel-lib-dep| |SHIELD:svg:pyVHDLModel-lib-rank| + +.. only:: latex + + |SHIELD:png:pyVHDLModel-github| |SHIELD:png:pyVHDLModel-src-license| |SHIELD:png:pyVHDLModel-ghp-doc| |SHIELD:png:pyVHDLModel-doc-license| |SHIELD:svg:pyVHDLModel-gitter| + |SHIELD:png:pyVHDLModel-pypi-tag| |SHIELD:png:pyVHDLModel-pypi-status| |SHIELD:png:pyVHDLModel-pypi-python| + |SHIELD:png:pyVHDLModel-gha-test| |SHIELD:png:pyVHDLModel-lib-status| |SHIELD:png:pyVHDLModel-codacy-quality| |SHIELD:png:pyVHDLModel-codacy-coverage| |SHIELD:png:pyVHDLModel-codecov-coverage| + +.. Disabled shields: |SHIELD:png:pyVHDLModel-lib-dep| |SHIELD:png:pyVHDLModel-lib-rank| + +The pyVHDLModel Documentation +############################# + +An abstract VHDL language model. + + +.. _goals: + +Main Goals +********** + +This package provides a unified abstract language model for VHDL. Projects reading +from source files can derive own classes and implement additional logic to create +a concrete language model for their tools. + +Projects consuming pre-processed VHDL data (parsed, analyzed or elaborated) can +build higher level features and services on such a model, while supporting multiple +frontends. + + +.. _usecase: + +Use Cases +********* + +* High-level API for `GHDL's `__ `libghdl` offered via `pyGHDL `__. +* Code Document-Object-Model (Code-DOM) in `pyVHDLParser `__. + + +.. _news: + +News +**** + +.. only:: html + + Jan. 2023 - Dependency, Hierarchy, Compile Order Analysis + ========================================================= + +.. only:: latex + + .. rubric:: Dependency, Hierarchy, Compile Order Analysis + +* Enhanced analysis of cross references. +* Enhanced dependency graphs: + + * Hierarchy graph and toplevel detection + * Compile order computation + +* Transformation from single module to >15 modules. +* Improved code coverage and test cases. + +.. only:: html + + Dec. 2022 - Added Documentation Property + ======================================== + +.. only:: latex + + .. rubric:: Added Documentation Property + +* `GHDL's `__ is now able to collect and associate (documentation) comments to language + constructs. This enhancement adds a ``Documentation`` property to many classes similar to a *doc-string* in Python. +* New -style of symbols merging a ``Name`` and a ``Symbol`` class. +* Finding relations between packages and its bodies, entities and its architectures. +* References to libraries, packages and contexts. +* Dependency graph for packages, contexts, and entities. + + * Package graph. + * Hierarchy graph. + * Compile order. + + +.. only:: html + + Jul. 2021 - First adoption and enhancements + =========================================== + +.. only:: latex + + .. rubric:: First adoption and enhancements + +* `GHDL's `__ is the first big adopter with `pyGHDL.dom `__ + to generate a network of instantiated classes derived from ``pyVHDLModel``. |br| + It uses `pyGHDL `__ as a backend (GHDL build as shared object and + loaded into CPython via C-binding API (``ctypes``). + + +.. only:: html + + Jun. 2021 - Model and documentation enhancements + ================================================ + +.. only:: latex + + .. rubric:: Model and documentation enhancements + +* Made generic, port, and parameter items a subclass of the matching object classes. +* Added missing object representations for language features. + + * Finalized literals, expressions and types. + * Added properties to empty placeholder classes. + +* Corrected class hierarchy according to LRM. +* Enhanced class documentation and cross references. +* New documentation chapter for literals and expressions. +* Added inheritance diagrams as overviews to documentation sections. +* Added condensed code snippets outlining the main interface of a model's object. +* New Single-File GitHub Action workflow (pipeline) including tests, documentation, packaging and publishing. +* Added Dependabot configuration file. +* Removed 2 dependencies to patched Sphinx extensions (now fixed in Sphinx). +* ... + +.. only:: html + + Jan. 2021 - Documentation enhancements + ====================================== + +.. only:: latex + + .. rubric:: Documentation enhancements + +* Enhanced class documentation. +* Changed test runner to ``pytest``. +* Dependency check and license clearance. |br| + See :ref:`dependency` for details. + + +.. only:: html + + Dec. 2020 - Split from pyVHDLParser + =================================== + +.. only:: latex + + .. rubric:: Split from pyVHDLParser + +* `pyVHDLModel` was split from `pyVHDLParser `__ (v0.6.0) as an independent Python package. + + +.. _CONTRIBUTORS: + +Contributors +************ + +* `Patrick Lehmann `__ (Maintainer) +* `Unai Martinez-Corral `__ +* `and more... `__ + + +.. _LICENSE: + +License +******* + +.. only:: html + + This Python package (source code) is licensed under `Apache License 2.0 `__. |br| + The accompanying documentation is licensed under `Creative Commons - Attribution 4.0 (CC-BY 4.0) `__. + +.. only:: latex + + This Python package (source code) is licensed under **Apache License 2.0**. |br| + The accompanying documentation is licensed under **Creative Commons - Attribution 4.0 (CC-BY 4.0)**. + + +.. only:: html + + This document was generated on |docdate|. + + +.. toctree:: + :hidden: + + Used as a layer of EDA² ➚ + + +.. toctree:: + :caption: Introduction + :hidden: + + GettingStarted + Installation + Dependency + + +.. raw:: latex + + \part{Main Documentation} + +.. toctree:: + :caption: Main Documentation + :hidden: + + LanguageModel/index + Analyze/index + DataStructure/index + + +.. raw:: latex + + \part{References and Reports} + +.. toctree:: + :caption: References and Reports + :hidden: + + Python Class Reference + unittests/index + coverage/index + Doc. Coverage Report + Static Type Check Report ➚ + + +.. raw:: latex + + \part{Appendix} + +.. toctree:: + :caption: Appendix + :hidden: + + ChangeLog/index + License + Doc-License + Glossary + genindex + Python Module Index + TODO diff --git a/_sources/pyVHDLModel/pyVHDLModel.Association.rst.txt b/_sources/pyVHDLModel/pyVHDLModel.Association.rst.txt new file mode 100644 index 000000000..614ee5605 --- /dev/null +++ b/_sources/pyVHDLModel/pyVHDLModel.Association.rst.txt @@ -0,0 +1,80 @@ +.. # Template modified by Patrick Lehmann + * removed automodule on top, because private members are activated for autodoc (no doubled documentation). + * Made sections like 'submodules' bold text, but no headlines to reduce number of ToC levels. + +======================= +pyVHDLModel.Association +======================= + +.. automodule:: pyVHDLModel.Association + + +.. currentmodule:: pyVHDLModel.Association + + +**Classes** + +- :py:class:`AssociationItem`: + A base-class for all association items. + +- :py:class:`GenericAssociationItem`: + A base-class for all generic association items used in generic map aspects. + +- :py:class:`PortAssociationItem`: + A base-class for all port association items used in port map aspects. + +- :py:class:`ParameterAssociationItem`: + A base-class for all parameter association items used in parameter map aspects. + + + +--------------------- + +**Classes** + + + + +.. autoclass:: AssociationItem + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: AssociationItem + :parts: 1 + +.. autoclass:: GenericAssociationItem + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: GenericAssociationItem + :parts: 1 + +.. autoclass:: PortAssociationItem + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: PortAssociationItem + :parts: 1 + +.. autoclass:: ParameterAssociationItem + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ParameterAssociationItem + :parts: 1 diff --git a/_sources/pyVHDLModel/pyVHDLModel.Base.rst.txt b/_sources/pyVHDLModel/pyVHDLModel.Base.rst.txt new file mode 100644 index 000000000..3de10235c --- /dev/null +++ b/_sources/pyVHDLModel/pyVHDLModel.Base.rst.txt @@ -0,0 +1,311 @@ +.. # Template modified by Patrick Lehmann + * removed automodule on top, because private members are activated for autodoc (no doubled documentation). + * Made sections like 'submodules' bold text, but no headlines to reduce number of ToC levels. + +================ +pyVHDLModel.Base +================ + +.. automodule:: pyVHDLModel.Base + + +.. currentmodule:: pyVHDLModel.Base + + +**Variables** + +- :py:data:`ExpressionUnion` + + + +**Classes** + +- :py:class:`Direction`: + An enumeration representing a direction in a range (``to`` or ``downto``). + +- :py:class:`Mode`: + A ``Mode`` is an enumeration. It represents the direction of data exchange (``in``, ``out``, ...) for objects in + +- :py:class:`ModelEntity`: + ``ModelEntity`` is the base-class for all classes in the VHDL language model, except for mixin classes (see multiple + +- :py:class:`NamedEntityMixin`: + A ``NamedEntityMixin`` is a mixin class for all VHDL entities that have identifiers. + +- :py:class:`MultipleNamedEntityMixin`: + A ``MultipleNamedEntityMixin`` is a mixin class for all VHDL entities that declare multiple instances at once by + +- :py:class:`LabeledEntityMixin`: + A ``LabeledEntityMixin`` is a mixin class for all VHDL entities that can have labels. + +- :py:class:`DocumentedEntityMixin`: + A ``DocumentedEntityMixin`` is a mixin class for all VHDL entities that can have an associated documentation. + +- :py:class:`ConditionalMixin`: + A ``ConditionalMixin`` is a mixin-class for all statements with a condition. + +- :py:class:`BranchMixin`: + A ``BranchMixin`` is a mixin-class for all statements with branches. + +- :py:class:`ConditionalBranchMixin`: + A ``BaseBranch`` is a mixin-class for all branch statements with a condition. + +- :py:class:`IfBranchMixin`: + A ``BaseIfBranch`` is a mixin-class for all if-branches. + +- :py:class:`ElsifBranchMixin`: + A ``BaseElsifBranch`` is a mixin-class for all elsif-branches. + +- :py:class:`ElseBranchMixin`: + A ``BaseElseBranch`` is a mixin-class for all else-branches. + +- :py:class:`ReportStatementMixin`: + A ``MixinReportStatement`` is a mixin-class for all report and assert statements. + +- :py:class:`AssertStatementMixin`: + A ``MixinAssertStatement`` is a mixin-class for all assert statements. + +- :py:class:`BaseChoice`: + A ``Choice`` is a base-class for all choices. + +- :py:class:`BaseCase`: + A ``Case`` is a base-class for all cases. + +- :py:class:`Range`: + ``ModelEntity`` is the base-class for all classes in the VHDL language model, except for mixin classes (see multiple + +- :py:class:`WaveformElement`: + ``ModelEntity`` is the base-class for all classes in the VHDL language model, except for mixin classes (see multiple + + + +--------------------- + +**Variables** + + + + +.. autodata:: ExpressionUnion + :annotation: + + .. code-block:: text + + typing.Union[ForwardRef('BaseExpression'), ForwardRef('QualifiedExpression'), ForwardRef('FunctionCall'), ForwardRef('TypeConversion'), ForwardRef('Literal')] + + +--------------------- + +**Classes** + + + + +.. autoclass:: Direction + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Direction + :parts: 1 + +.. autoclass:: Mode + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Mode + :parts: 1 + +.. autoclass:: ModelEntity + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ModelEntity + :parts: 1 + +.. autoclass:: NamedEntityMixin + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: NamedEntityMixin + :parts: 1 + +.. autoclass:: MultipleNamedEntityMixin + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: MultipleNamedEntityMixin + :parts: 1 + +.. autoclass:: LabeledEntityMixin + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: LabeledEntityMixin + :parts: 1 + +.. autoclass:: DocumentedEntityMixin + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: DocumentedEntityMixin + :parts: 1 + +.. autoclass:: ConditionalMixin + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ConditionalMixin + :parts: 1 + +.. autoclass:: BranchMixin + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: BranchMixin + :parts: 1 + +.. autoclass:: ConditionalBranchMixin + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ConditionalBranchMixin + :parts: 1 + +.. autoclass:: IfBranchMixin + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: IfBranchMixin + :parts: 1 + +.. autoclass:: ElsifBranchMixin + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ElsifBranchMixin + :parts: 1 + +.. autoclass:: ElseBranchMixin + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ElseBranchMixin + :parts: 1 + +.. autoclass:: ReportStatementMixin + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ReportStatementMixin + :parts: 1 + +.. autoclass:: AssertStatementMixin + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: AssertStatementMixin + :parts: 1 + +.. autoclass:: BaseChoice + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: BaseChoice + :parts: 1 + +.. autoclass:: BaseCase + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: BaseCase + :parts: 1 + +.. autoclass:: Range + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Range + :parts: 1 + +.. autoclass:: WaveformElement + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: WaveformElement + :parts: 1 diff --git a/_sources/pyVHDLModel/pyVHDLModel.Common.rst.txt b/_sources/pyVHDLModel/pyVHDLModel.Common.rst.txt new file mode 100644 index 000000000..f00553039 --- /dev/null +++ b/_sources/pyVHDLModel/pyVHDLModel.Common.rst.txt @@ -0,0 +1,94 @@ +.. # Template modified by Patrick Lehmann + * removed automodule on top, because private members are activated for autodoc (no doubled documentation). + * Made sections like 'submodules' bold text, but no headlines to reduce number of ToC levels. + +================== +pyVHDLModel.Common +================== + +.. automodule:: pyVHDLModel.Common + + +.. currentmodule:: pyVHDLModel.Common + + +**Classes** + +- :py:class:`Statement`: + A ``Statement`` is a base-class for all statements. + +- :py:class:`ProcedureCallMixin`: + Undocumented. + +- :py:class:`AssignmentMixin`: + A mixin-class for all assignment statements. + +- :py:class:`SignalAssignmentMixin`: + A mixin-class for all signal assignment statements. + +- :py:class:`VariableAssignmentMixin`: + A mixin-class for all variable assignment statements. + + + +--------------------- + +**Classes** + + + + +.. autoclass:: Statement + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Statement + :parts: 1 + +.. autoclass:: ProcedureCallMixin + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ProcedureCallMixin + :parts: 1 + +.. autoclass:: AssignmentMixin + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: AssignmentMixin + :parts: 1 + +.. autoclass:: SignalAssignmentMixin + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: SignalAssignmentMixin + :parts: 1 + +.. autoclass:: VariableAssignmentMixin + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: VariableAssignmentMixin + :parts: 1 diff --git a/_sources/pyVHDLModel/pyVHDLModel.Concurrent.rst.txt b/_sources/pyVHDLModel/pyVHDLModel.Concurrent.rst.txt new file mode 100644 index 000000000..e37c39271 --- /dev/null +++ b/_sources/pyVHDLModel/pyVHDLModel.Concurrent.rst.txt @@ -0,0 +1,416 @@ +.. # Template modified by Patrick Lehmann + * removed automodule on top, because private members are activated for autodoc (no doubled documentation). + * Made sections like 'submodules' bold text, but no headlines to reduce number of ToC levels. + +====================== +pyVHDLModel.Concurrent +====================== + +.. automodule:: pyVHDLModel.Concurrent + + +.. currentmodule:: pyVHDLModel.Concurrent + + +**Classes** + +- :py:class:`ConcurrentStatement`: + A base-class for all concurrent statements. + +- :py:class:`ConcurrentStatementsMixin`: + A mixin-class for all language constructs supporting concurrent statements. + +- :py:class:`Instantiation`: + A base-class for all (component) instantiations. + +- :py:class:`ComponentInstantiation`: + Represents a component instantiation by referring to a component name. + +- :py:class:`EntityInstantiation`: + Represents an entity instantiation by referring to an entity name with optional architecture name. + +- :py:class:`ConfigurationInstantiation`: + Represents a configuration instantiation by referring to a configuration name. + +- :py:class:`ProcessStatement`: + Represents a process statement with sensitivity list, sequential declaration region and sequential statements. + +- :py:class:`ConcurrentProcedureCall`: + A base-class for all concurrent statements. + +- :py:class:`ConcurrentBlockStatement`: + A base-class for all concurrent statements. + +- :py:class:`GenerateBranch`: + A base-class for all branches in a generate statements. + +- :py:class:`IfGenerateBranch`: + Represents if-generate branch in a generate statement with a concurrent declaration region and concurrent statements. + +- :py:class:`ElsifGenerateBranch`: + Represents elsif-generate branch in a generate statement with a concurrent declaration region and concurrent statements. + +- :py:class:`ElseGenerateBranch`: + Represents else-generate branch in a generate statement with a concurrent declaration region and concurrent statements. + +- :py:class:`GenerateStatement`: + A base-class for all generate statements. + +- :py:class:`IfGenerateStatement`: + Represents an if...generate statement. + +- :py:class:`ConcurrentChoice`: + A base-class for all concurrent choices (in case...generate statements). + +- :py:class:`IndexedGenerateChoice`: + A base-class for all concurrent choices (in case...generate statements). + +- :py:class:`RangedGenerateChoice`: + A base-class for all concurrent choices (in case...generate statements). + +- :py:class:`ConcurrentCase`: + A ``Case`` is a base-class for all cases. + +- :py:class:`GenerateCase`: + A ``Case`` is a base-class for all cases. + +- :py:class:`OthersGenerateCase`: + A ``Case`` is a base-class for all cases. + +- :py:class:`CaseGenerateStatement`: + Represents a case...generate statement. + +- :py:class:`ForGenerateStatement`: + Represents a for...generate statement. + +- :py:class:`ConcurrentSignalAssignment`: + A base-class for concurrent signal assignments. + +- :py:class:`ConcurrentSimpleSignalAssignment`: + A base-class for concurrent signal assignments. + +- :py:class:`ConcurrentSelectedSignalAssignment`: + A base-class for concurrent signal assignments. + +- :py:class:`ConcurrentConditionalSignalAssignment`: + A base-class for concurrent signal assignments. + +- :py:class:`ConcurrentAssertStatement`: + A base-class for all concurrent statements. + + + +--------------------- + +**Classes** + + + + +.. autoclass:: ConcurrentStatement + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ConcurrentStatement + :parts: 1 + +.. autoclass:: ConcurrentStatementsMixin + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ConcurrentStatementsMixin + :parts: 1 + +.. autoclass:: Instantiation + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Instantiation + :parts: 1 + +.. autoclass:: ComponentInstantiation + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ComponentInstantiation + :parts: 1 + +.. autoclass:: EntityInstantiation + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: EntityInstantiation + :parts: 1 + +.. autoclass:: ConfigurationInstantiation + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ConfigurationInstantiation + :parts: 1 + +.. autoclass:: ProcessStatement + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ProcessStatement + :parts: 1 + +.. autoclass:: ConcurrentProcedureCall + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ConcurrentProcedureCall + :parts: 1 + +.. autoclass:: ConcurrentBlockStatement + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ConcurrentBlockStatement + :parts: 1 + +.. autoclass:: GenerateBranch + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: GenerateBranch + :parts: 1 + +.. autoclass:: IfGenerateBranch + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: IfGenerateBranch + :parts: 1 + +.. autoclass:: ElsifGenerateBranch + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ElsifGenerateBranch + :parts: 1 + +.. autoclass:: ElseGenerateBranch + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ElseGenerateBranch + :parts: 1 + +.. autoclass:: GenerateStatement + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: GenerateStatement + :parts: 1 + +.. autoclass:: IfGenerateStatement + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: IfGenerateStatement + :parts: 1 + +.. autoclass:: ConcurrentChoice + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ConcurrentChoice + :parts: 1 + +.. autoclass:: IndexedGenerateChoice + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: IndexedGenerateChoice + :parts: 1 + +.. autoclass:: RangedGenerateChoice + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: RangedGenerateChoice + :parts: 1 + +.. autoclass:: ConcurrentCase + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ConcurrentCase + :parts: 1 + +.. autoclass:: GenerateCase + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: GenerateCase + :parts: 1 + +.. autoclass:: OthersGenerateCase + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: OthersGenerateCase + :parts: 1 + +.. autoclass:: CaseGenerateStatement + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: CaseGenerateStatement + :parts: 1 + +.. autoclass:: ForGenerateStatement + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ForGenerateStatement + :parts: 1 + +.. autoclass:: ConcurrentSignalAssignment + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ConcurrentSignalAssignment + :parts: 1 + +.. autoclass:: ConcurrentSimpleSignalAssignment + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ConcurrentSimpleSignalAssignment + :parts: 1 + +.. autoclass:: ConcurrentSelectedSignalAssignment + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ConcurrentSelectedSignalAssignment + :parts: 1 + +.. autoclass:: ConcurrentConditionalSignalAssignment + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ConcurrentConditionalSignalAssignment + :parts: 1 + +.. autoclass:: ConcurrentAssertStatement + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ConcurrentAssertStatement + :parts: 1 diff --git a/_sources/pyVHDLModel/pyVHDLModel.Declaration.rst.txt b/_sources/pyVHDLModel/pyVHDLModel.Declaration.rst.txt new file mode 100644 index 000000000..6d1e2367f --- /dev/null +++ b/_sources/pyVHDLModel/pyVHDLModel.Declaration.rst.txt @@ -0,0 +1,80 @@ +.. # Template modified by Patrick Lehmann + * removed automodule on top, because private members are activated for autodoc (no doubled documentation). + * Made sections like 'submodules' bold text, but no headlines to reduce number of ToC levels. + +======================= +pyVHDLModel.Declaration +======================= + +.. automodule:: pyVHDLModel.Declaration + + +.. currentmodule:: pyVHDLModel.Declaration + + +**Classes** + +- :py:class:`EntityClass`: + An ``EntityClass`` is an enumeration. It represents a VHDL language entity class (``entity``, ``label``, ...). + +- :py:class:`Attribute`: + Represents an attribute declaration. + +- :py:class:`AttributeSpecification`: + Represents an attribute specification. + +- :py:class:`Alias`: + ``ModelEntity`` is the base-class for all classes in the VHDL language model, except for mixin classes (see multiple + + + +--------------------- + +**Classes** + + + + +.. autoclass:: EntityClass + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: EntityClass + :parts: 1 + +.. autoclass:: Attribute + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Attribute + :parts: 1 + +.. autoclass:: AttributeSpecification + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: AttributeSpecification + :parts: 1 + +.. autoclass:: Alias + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Alias + :parts: 1 diff --git a/_sources/pyVHDLModel/pyVHDLModel.DesignUnit.rst.txt b/_sources/pyVHDLModel/pyVHDLModel.DesignUnit.rst.txt new file mode 100644 index 000000000..51e14cd40 --- /dev/null +++ b/_sources/pyVHDLModel/pyVHDLModel.DesignUnit.rst.txt @@ -0,0 +1,234 @@ +.. # Template modified by Patrick Lehmann + * removed automodule on top, because private members are activated for autodoc (no doubled documentation). + * Made sections like 'submodules' bold text, but no headlines to reduce number of ToC levels. + +====================== +pyVHDLModel.DesignUnit +====================== + +.. automodule:: pyVHDLModel.DesignUnit + + +.. currentmodule:: pyVHDLModel.DesignUnit + + +**Classes** + +- :py:class:`Reference`: + A base-class for all references. + +- :py:class:`LibraryClause`: + Represents a library clause. + +- :py:class:`UseClause`: + Represents a use clause. + +- :py:class:`ContextReference`: + Represents a context reference. + +- :py:class:`DesignUnitWithContextMixin`: + A mixin-class for all design units with a context. + +- :py:class:`DesignUnit`: + A base-class for all design units. + +- :py:class:`PrimaryUnit`: + A base-class for all primary design units. + +- :py:class:`SecondaryUnit`: + A base-class for all secondary design units. + +- :py:class:`Context`: + Represents a context declaration. + +- :py:class:`Package`: + Represents a package declaration. + +- :py:class:`PackageBody`: + Represents a package body declaration. + +- :py:class:`Entity`: + Represents an entity declaration. + +- :py:class:`Architecture`: + Represents an architecture declaration. + +- :py:class:`Component`: + Represents a configuration declaration. + +- :py:class:`Configuration`: + Represents a configuration declaration. + + + +--------------------- + +**Classes** + + + + +.. autoclass:: Reference + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Reference + :parts: 1 + +.. autoclass:: LibraryClause + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: LibraryClause + :parts: 1 + +.. autoclass:: UseClause + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: UseClause + :parts: 1 + +.. autoclass:: ContextReference + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ContextReference + :parts: 1 + +.. autoclass:: DesignUnitWithContextMixin + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: DesignUnitWithContextMixin + :parts: 1 + +.. autoclass:: DesignUnit + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: DesignUnit + :parts: 1 + +.. autoclass:: PrimaryUnit + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: PrimaryUnit + :parts: 1 + +.. autoclass:: SecondaryUnit + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: SecondaryUnit + :parts: 1 + +.. autoclass:: Context + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Context + :parts: 1 + +.. autoclass:: Package + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Package + :parts: 1 + +.. autoclass:: PackageBody + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: PackageBody + :parts: 1 + +.. autoclass:: Entity + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Entity + :parts: 1 + +.. autoclass:: Architecture + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Architecture + :parts: 1 + +.. autoclass:: Component + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Component + :parts: 1 + +.. autoclass:: Configuration + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Configuration + :parts: 1 diff --git a/_sources/pyVHDLModel/pyVHDLModel.Exception.rst.txt b/_sources/pyVHDLModel/pyVHDLModel.Exception.rst.txt new file mode 100644 index 000000000..184109325 --- /dev/null +++ b/_sources/pyVHDLModel/pyVHDLModel.Exception.rst.txt @@ -0,0 +1,123 @@ +.. # Template modified by Patrick Lehmann + * removed automodule on top, because private members are activated for autodoc (no doubled documentation). + * Made sections like 'submodules' bold text, but no headlines to reduce number of ToC levels. + +===================== +pyVHDLModel.Exception +===================== + +.. automodule:: pyVHDLModel.Exception + + +.. currentmodule:: pyVHDLModel.Exception + + +**Exceptions** + +- :py:exc:`VHDLModelException`: + Base-class for all exceptions (errors) raised by pyVHDLModel. + +- :py:exc:`LibraryExistsInDesignError`: + This exception is raised, when the library is already existing in the design. + +- :py:exc:`LibraryRegisteredToForeignDesignError`: + This exception is raised, when the library is already registered to a foreign design. + +- :py:exc:`LibraryNotRegisteredError`: + This exception is raised, when the library is not registered in the design. + +- :py:exc:`EntityExistsInLibraryError`: + This exception is raised, when the entity already existing in the library. + +- :py:exc:`ArchitectureExistsInLibraryError`: + This exception is raised, when the architecture already existing in the library. + +- :py:exc:`PackageExistsInLibraryError`: + This exception is raised, when the package already existing in the library. + +- :py:exc:`PackageBodyExistsError`: + This exception is raised, when the package body already existing in the library. + +- :py:exc:`ConfigurationExistsInLibraryError`: + This exception is raised, when the configuration already existing in the library. + +- :py:exc:`ContextExistsInLibraryError`: + This exception is raised, when the context already existing in the library. + +- :py:exc:`ReferencedLibraryNotExistingError`: + This exception is raised, when a library is referenced by a `library clause`, but doesn't exist in the design. + + + +--------------------- + +**Exceptions** + + + + +.. autoexception:: VHDLModelException + + .. rubric:: Inheritance + .. inheritance-diagram:: VHDLModelException + :parts: 1 + +.. autoexception:: LibraryExistsInDesignError + + .. rubric:: Inheritance + .. inheritance-diagram:: LibraryExistsInDesignError + :parts: 1 + +.. autoexception:: LibraryRegisteredToForeignDesignError + + .. rubric:: Inheritance + .. inheritance-diagram:: LibraryRegisteredToForeignDesignError + :parts: 1 + +.. autoexception:: LibraryNotRegisteredError + + .. rubric:: Inheritance + .. inheritance-diagram:: LibraryNotRegisteredError + :parts: 1 + +.. autoexception:: EntityExistsInLibraryError + + .. rubric:: Inheritance + .. inheritance-diagram:: EntityExistsInLibraryError + :parts: 1 + +.. autoexception:: ArchitectureExistsInLibraryError + + .. rubric:: Inheritance + .. inheritance-diagram:: ArchitectureExistsInLibraryError + :parts: 1 + +.. autoexception:: PackageExistsInLibraryError + + .. rubric:: Inheritance + .. inheritance-diagram:: PackageExistsInLibraryError + :parts: 1 + +.. autoexception:: PackageBodyExistsError + + .. rubric:: Inheritance + .. inheritance-diagram:: PackageBodyExistsError + :parts: 1 + +.. autoexception:: ConfigurationExistsInLibraryError + + .. rubric:: Inheritance + .. inheritance-diagram:: ConfigurationExistsInLibraryError + :parts: 1 + +.. autoexception:: ContextExistsInLibraryError + + .. rubric:: Inheritance + .. inheritance-diagram:: ContextExistsInLibraryError + :parts: 1 + +.. autoexception:: ReferencedLibraryNotExistingError + + .. rubric:: Inheritance + .. inheritance-diagram:: ReferencedLibraryNotExistingError + :parts: 1 diff --git a/_sources/pyVHDLModel/pyVHDLModel.Expression.rst.txt b/_sources/pyVHDLModel/pyVHDLModel.Expression.rst.txt new file mode 100644 index 000000000..79d00c04f --- /dev/null +++ b/_sources/pyVHDLModel/pyVHDLModel.Expression.rst.txt @@ -0,0 +1,1228 @@ +.. # Template modified by Patrick Lehmann + * removed automodule on top, because private members are activated for autodoc (no doubled documentation). + * Made sections like 'submodules' bold text, but no headlines to reduce number of ToC levels. + +====================== +pyVHDLModel.Expression +====================== + +.. automodule:: pyVHDLModel.Expression + + +.. currentmodule:: pyVHDLModel.Expression + + +**Classes** + +- :py:class:`BaseExpression`: + A ``BaseExpression`` is a base-class for all expressions. + +- :py:class:`Literal`: + A ``Literal`` is a base-class for all literals. + +- :py:class:`NullLiteral`: + A ``Literal`` is a base-class for all literals. + +- :py:class:`EnumerationLiteral`: + A ``Literal`` is a base-class for all literals. + +- :py:class:`NumericLiteral`: + A ``NumericLiteral`` is a base-class for all numeric literals. + +- :py:class:`IntegerLiteral`: + A ``NumericLiteral`` is a base-class for all numeric literals. + +- :py:class:`FloatingPointLiteral`: + A ``NumericLiteral`` is a base-class for all numeric literals. + +- :py:class:`PhysicalLiteral`: + A ``NumericLiteral`` is a base-class for all numeric literals. + +- :py:class:`PhysicalIntegerLiteral`: + A ``NumericLiteral`` is a base-class for all numeric literals. + +- :py:class:`PhysicalFloatingLiteral`: + A ``NumericLiteral`` is a base-class for all numeric literals. + +- :py:class:`CharacterLiteral`: + A ``Literal`` is a base-class for all literals. + +- :py:class:`StringLiteral`: + A ``Literal`` is a base-class for all literals. + +- :py:class:`BitStringLiteral`: + A ``Literal`` is a base-class for all literals. + +- :py:class:`ParenthesisExpression`: + Undocumented. + +- :py:class:`UnaryExpression`: + A ``UnaryExpression`` is a base-class for all unary expressions. + +- :py:class:`NegationExpression`: + A ``UnaryExpression`` is a base-class for all unary expressions. + +- :py:class:`IdentityExpression`: + A ``UnaryExpression`` is a base-class for all unary expressions. + +- :py:class:`InverseExpression`: + A ``UnaryExpression`` is a base-class for all unary expressions. + +- :py:class:`UnaryAndExpression`: + A ``UnaryExpression`` is a base-class for all unary expressions. + +- :py:class:`UnaryNandExpression`: + A ``UnaryExpression`` is a base-class for all unary expressions. + +- :py:class:`UnaryOrExpression`: + A ``UnaryExpression`` is a base-class for all unary expressions. + +- :py:class:`UnaryNorExpression`: + A ``UnaryExpression`` is a base-class for all unary expressions. + +- :py:class:`UnaryXorExpression`: + A ``UnaryExpression`` is a base-class for all unary expressions. + +- :py:class:`UnaryXnorExpression`: + A ``UnaryExpression`` is a base-class for all unary expressions. + +- :py:class:`AbsoluteExpression`: + A ``UnaryExpression`` is a base-class for all unary expressions. + +- :py:class:`TypeConversion`: + A ``UnaryExpression`` is a base-class for all unary expressions. + +- :py:class:`SubExpression`: + A ``UnaryExpression`` is a base-class for all unary expressions. + +- :py:class:`BinaryExpression`: + A ``BinaryExpression`` is a base-class for all binary expressions. + +- :py:class:`RangeExpression`: + A ``BinaryExpression`` is a base-class for all binary expressions. + +- :py:class:`AscendingRangeExpression`: + A ``BinaryExpression`` is a base-class for all binary expressions. + +- :py:class:`DescendingRangeExpression`: + A ``BinaryExpression`` is a base-class for all binary expressions. + +- :py:class:`AddingExpression`: + A ``AddingExpression`` is a base-class for all adding expressions. + +- :py:class:`AdditionExpression`: + A ``AddingExpression`` is a base-class for all adding expressions. + +- :py:class:`SubtractionExpression`: + A ``AddingExpression`` is a base-class for all adding expressions. + +- :py:class:`ConcatenationExpression`: + A ``AddingExpression`` is a base-class for all adding expressions. + +- :py:class:`MultiplyingExpression`: + A ``MultiplyingExpression`` is a base-class for all multiplying expressions. + +- :py:class:`MultiplyExpression`: + A ``MultiplyingExpression`` is a base-class for all multiplying expressions. + +- :py:class:`DivisionExpression`: + A ``MultiplyingExpression`` is a base-class for all multiplying expressions. + +- :py:class:`RemainderExpression`: + A ``MultiplyingExpression`` is a base-class for all multiplying expressions. + +- :py:class:`ModuloExpression`: + A ``MultiplyingExpression`` is a base-class for all multiplying expressions. + +- :py:class:`ExponentiationExpression`: + A ``MultiplyingExpression`` is a base-class for all multiplying expressions. + +- :py:class:`LogicalExpression`: + A ``LogicalExpression`` is a base-class for all logical expressions. + +- :py:class:`AndExpression`: + A ``LogicalExpression`` is a base-class for all logical expressions. + +- :py:class:`NandExpression`: + A ``LogicalExpression`` is a base-class for all logical expressions. + +- :py:class:`OrExpression`: + A ``LogicalExpression`` is a base-class for all logical expressions. + +- :py:class:`NorExpression`: + A ``LogicalExpression`` is a base-class for all logical expressions. + +- :py:class:`XorExpression`: + A ``LogicalExpression`` is a base-class for all logical expressions. + +- :py:class:`XnorExpression`: + A ``LogicalExpression`` is a base-class for all logical expressions. + +- :py:class:`RelationalExpression`: + A ``RelationalExpression`` is a base-class for all shifting expressions. + +- :py:class:`EqualExpression`: + A ``RelationalExpression`` is a base-class for all shifting expressions. + +- :py:class:`UnequalExpression`: + A ``RelationalExpression`` is a base-class for all shifting expressions. + +- :py:class:`GreaterThanExpression`: + A ``RelationalExpression`` is a base-class for all shifting expressions. + +- :py:class:`GreaterEqualExpression`: + A ``RelationalExpression`` is a base-class for all shifting expressions. + +- :py:class:`LessThanExpression`: + A ``RelationalExpression`` is a base-class for all shifting expressions. + +- :py:class:`LessEqualExpression`: + A ``RelationalExpression`` is a base-class for all shifting expressions. + +- :py:class:`MatchingRelationalExpression`: + A ``RelationalExpression`` is a base-class for all shifting expressions. + +- :py:class:`MatchingEqualExpression`: + A ``RelationalExpression`` is a base-class for all shifting expressions. + +- :py:class:`MatchingUnequalExpression`: + A ``RelationalExpression`` is a base-class for all shifting expressions. + +- :py:class:`MatchingGreaterThanExpression`: + A ``RelationalExpression`` is a base-class for all shifting expressions. + +- :py:class:`MatchingGreaterEqualExpression`: + A ``RelationalExpression`` is a base-class for all shifting expressions. + +- :py:class:`MatchingLessThanExpression`: + A ``RelationalExpression`` is a base-class for all shifting expressions. + +- :py:class:`MatchingLessEqualExpression`: + A ``RelationalExpression`` is a base-class for all shifting expressions. + +- :py:class:`ShiftExpression`: + A ``ShiftExpression`` is a base-class for all shifting expressions. + +- :py:class:`ShiftLogicExpression`: + A ``ShiftExpression`` is a base-class for all shifting expressions. + +- :py:class:`ShiftArithmeticExpression`: + A ``ShiftExpression`` is a base-class for all shifting expressions. + +- :py:class:`RotateExpression`: + A ``ShiftExpression`` is a base-class for all shifting expressions. + +- :py:class:`ShiftRightLogicExpression`: + A ``ShiftExpression`` is a base-class for all shifting expressions. + +- :py:class:`ShiftLeftLogicExpression`: + A ``ShiftExpression`` is a base-class for all shifting expressions. + +- :py:class:`ShiftRightArithmeticExpression`: + A ``ShiftExpression`` is a base-class for all shifting expressions. + +- :py:class:`ShiftLeftArithmeticExpression`: + A ``ShiftExpression`` is a base-class for all shifting expressions. + +- :py:class:`RotateRightExpression`: + A ``ShiftExpression`` is a base-class for all shifting expressions. + +- :py:class:`RotateLeftExpression`: + A ``ShiftExpression`` is a base-class for all shifting expressions. + +- :py:class:`QualifiedExpression`: + A ``BaseExpression`` is a base-class for all expressions. + +- :py:class:`TernaryExpression`: + A ``TernaryExpression`` is a base-class for all ternary expressions. + +- :py:class:`WhenElseExpression`: + A ``TernaryExpression`` is a base-class for all ternary expressions. + +- :py:class:`FunctionCall`: + A ``BaseExpression`` is a base-class for all expressions. + +- :py:class:`Allocation`: + A ``BaseExpression`` is a base-class for all expressions. + +- :py:class:`SubtypeAllocation`: + A ``BaseExpression`` is a base-class for all expressions. + +- :py:class:`QualifiedExpressionAllocation`: + A ``BaseExpression`` is a base-class for all expressions. + +- :py:class:`AggregateElement`: + A ``AggregateElement`` is a base-class for all aggregate elements. + +- :py:class:`SimpleAggregateElement`: + A ``AggregateElement`` is a base-class for all aggregate elements. + +- :py:class:`IndexedAggregateElement`: + A ``AggregateElement`` is a base-class for all aggregate elements. + +- :py:class:`RangedAggregateElement`: + A ``AggregateElement`` is a base-class for all aggregate elements. + +- :py:class:`NamedAggregateElement`: + A ``AggregateElement`` is a base-class for all aggregate elements. + +- :py:class:`OthersAggregateElement`: + A ``AggregateElement`` is a base-class for all aggregate elements. + +- :py:class:`Aggregate`: + A ``BaseExpression`` is a base-class for all expressions. + + + +--------------------- + +**Classes** + + + + +.. autoclass:: BaseExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: BaseExpression + :parts: 1 + +.. autoclass:: Literal + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Literal + :parts: 1 + +.. autoclass:: NullLiteral + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: NullLiteral + :parts: 1 + +.. autoclass:: EnumerationLiteral + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: EnumerationLiteral + :parts: 1 + +.. autoclass:: NumericLiteral + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: NumericLiteral + :parts: 1 + +.. autoclass:: IntegerLiteral + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: IntegerLiteral + :parts: 1 + +.. autoclass:: FloatingPointLiteral + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: FloatingPointLiteral + :parts: 1 + +.. autoclass:: PhysicalLiteral + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: PhysicalLiteral + :parts: 1 + +.. autoclass:: PhysicalIntegerLiteral + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: PhysicalIntegerLiteral + :parts: 1 + +.. autoclass:: PhysicalFloatingLiteral + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: PhysicalFloatingLiteral + :parts: 1 + +.. autoclass:: CharacterLiteral + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: CharacterLiteral + :parts: 1 + +.. autoclass:: StringLiteral + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: StringLiteral + :parts: 1 + +.. autoclass:: BitStringLiteral + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: BitStringLiteral + :parts: 1 + +.. autoclass:: ParenthesisExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ParenthesisExpression + :parts: 1 + +.. autoclass:: UnaryExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: UnaryExpression + :parts: 1 + +.. autoclass:: NegationExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: NegationExpression + :parts: 1 + +.. autoclass:: IdentityExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: IdentityExpression + :parts: 1 + +.. autoclass:: InverseExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: InverseExpression + :parts: 1 + +.. autoclass:: UnaryAndExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: UnaryAndExpression + :parts: 1 + +.. autoclass:: UnaryNandExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: UnaryNandExpression + :parts: 1 + +.. autoclass:: UnaryOrExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: UnaryOrExpression + :parts: 1 + +.. autoclass:: UnaryNorExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: UnaryNorExpression + :parts: 1 + +.. autoclass:: UnaryXorExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: UnaryXorExpression + :parts: 1 + +.. autoclass:: UnaryXnorExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: UnaryXnorExpression + :parts: 1 + +.. autoclass:: AbsoluteExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: AbsoluteExpression + :parts: 1 + +.. autoclass:: TypeConversion + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: TypeConversion + :parts: 1 + +.. autoclass:: SubExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: SubExpression + :parts: 1 + +.. autoclass:: BinaryExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: BinaryExpression + :parts: 1 + +.. autoclass:: RangeExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: RangeExpression + :parts: 1 + +.. autoclass:: AscendingRangeExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: AscendingRangeExpression + :parts: 1 + +.. autoclass:: DescendingRangeExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: DescendingRangeExpression + :parts: 1 + +.. autoclass:: AddingExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: AddingExpression + :parts: 1 + +.. autoclass:: AdditionExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: AdditionExpression + :parts: 1 + +.. autoclass:: SubtractionExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: SubtractionExpression + :parts: 1 + +.. autoclass:: ConcatenationExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ConcatenationExpression + :parts: 1 + +.. autoclass:: MultiplyingExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: MultiplyingExpression + :parts: 1 + +.. autoclass:: MultiplyExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: MultiplyExpression + :parts: 1 + +.. autoclass:: DivisionExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: DivisionExpression + :parts: 1 + +.. autoclass:: RemainderExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: RemainderExpression + :parts: 1 + +.. autoclass:: ModuloExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ModuloExpression + :parts: 1 + +.. autoclass:: ExponentiationExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ExponentiationExpression + :parts: 1 + +.. autoclass:: LogicalExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: LogicalExpression + :parts: 1 + +.. autoclass:: AndExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: AndExpression + :parts: 1 + +.. autoclass:: NandExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: NandExpression + :parts: 1 + +.. autoclass:: OrExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: OrExpression + :parts: 1 + +.. autoclass:: NorExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: NorExpression + :parts: 1 + +.. autoclass:: XorExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: XorExpression + :parts: 1 + +.. autoclass:: XnorExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: XnorExpression + :parts: 1 + +.. autoclass:: RelationalExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: RelationalExpression + :parts: 1 + +.. autoclass:: EqualExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: EqualExpression + :parts: 1 + +.. autoclass:: UnequalExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: UnequalExpression + :parts: 1 + +.. autoclass:: GreaterThanExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: GreaterThanExpression + :parts: 1 + +.. autoclass:: GreaterEqualExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: GreaterEqualExpression + :parts: 1 + +.. autoclass:: LessThanExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: LessThanExpression + :parts: 1 + +.. autoclass:: LessEqualExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: LessEqualExpression + :parts: 1 + +.. autoclass:: MatchingRelationalExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: MatchingRelationalExpression + :parts: 1 + +.. autoclass:: MatchingEqualExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: MatchingEqualExpression + :parts: 1 + +.. autoclass:: MatchingUnequalExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: MatchingUnequalExpression + :parts: 1 + +.. autoclass:: MatchingGreaterThanExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: MatchingGreaterThanExpression + :parts: 1 + +.. autoclass:: MatchingGreaterEqualExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: MatchingGreaterEqualExpression + :parts: 1 + +.. autoclass:: MatchingLessThanExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: MatchingLessThanExpression + :parts: 1 + +.. autoclass:: MatchingLessEqualExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: MatchingLessEqualExpression + :parts: 1 + +.. autoclass:: ShiftExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ShiftExpression + :parts: 1 + +.. autoclass:: ShiftLogicExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ShiftLogicExpression + :parts: 1 + +.. autoclass:: ShiftArithmeticExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ShiftArithmeticExpression + :parts: 1 + +.. autoclass:: RotateExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: RotateExpression + :parts: 1 + +.. autoclass:: ShiftRightLogicExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ShiftRightLogicExpression + :parts: 1 + +.. autoclass:: ShiftLeftLogicExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ShiftLeftLogicExpression + :parts: 1 + +.. autoclass:: ShiftRightArithmeticExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ShiftRightArithmeticExpression + :parts: 1 + +.. autoclass:: ShiftLeftArithmeticExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ShiftLeftArithmeticExpression + :parts: 1 + +.. autoclass:: RotateRightExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: RotateRightExpression + :parts: 1 + +.. autoclass:: RotateLeftExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: RotateLeftExpression + :parts: 1 + +.. autoclass:: QualifiedExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: QualifiedExpression + :parts: 1 + +.. autoclass:: TernaryExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: TernaryExpression + :parts: 1 + +.. autoclass:: WhenElseExpression + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: WhenElseExpression + :parts: 1 + +.. autoclass:: FunctionCall + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: FunctionCall + :parts: 1 + +.. autoclass:: Allocation + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Allocation + :parts: 1 + +.. autoclass:: SubtypeAllocation + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: SubtypeAllocation + :parts: 1 + +.. autoclass:: QualifiedExpressionAllocation + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: QualifiedExpressionAllocation + :parts: 1 + +.. autoclass:: AggregateElement + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: AggregateElement + :parts: 1 + +.. autoclass:: SimpleAggregateElement + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: SimpleAggregateElement + :parts: 1 + +.. autoclass:: IndexedAggregateElement + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: IndexedAggregateElement + :parts: 1 + +.. autoclass:: RangedAggregateElement + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: RangedAggregateElement + :parts: 1 + +.. autoclass:: NamedAggregateElement + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: NamedAggregateElement + :parts: 1 + +.. autoclass:: OthersAggregateElement + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: OthersAggregateElement + :parts: 1 + +.. autoclass:: Aggregate + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Aggregate + :parts: 1 diff --git a/_sources/pyVHDLModel/pyVHDLModel.IEEE.rst.txt b/_sources/pyVHDLModel/pyVHDLModel.IEEE.rst.txt new file mode 100644 index 000000000..0348abd80 --- /dev/null +++ b/_sources/pyVHDLModel/pyVHDLModel.IEEE.rst.txt @@ -0,0 +1,374 @@ +.. # Template modified by Patrick Lehmann + * removed automodule on top, because private members are activated for autodoc (no doubled documentation). + * Made sections like 'submodules' bold text, but no headlines to reduce number of ToC levels. + +================ +pyVHDLModel.IEEE +================ + +.. automodule:: pyVHDLModel.IEEE + + +.. currentmodule:: pyVHDLModel.IEEE + + +**Classes** + +- :py:class:`Ieee`: + Predefined VHDL library ``ieee``. + +- :py:class:`Math_Real`: + Predefined package ``ieee.math_real``. + +- :py:class:`Math_Real_Body`: + Predefined package body of package ``ieee.math_real``. + +- :py:class:`Math_Complex`: + Predefined package ``ieee.math_complex``. + +- :py:class:`Math_Complex_Body`: + Predefined package body of package ``ieee.math_complex``. + +- :py:class:`Std_logic_1164`: + Predefined package ``ieee.std_logic_1164``. + +- :py:class:`Std_logic_1164_Body`: + Predefined package body of package ``ieee.std_logic_1164``. + +- :py:class:`std_logic_textio`: + Predefined package ``ieee.std_logic_textio``. + +- :py:class:`Std_logic_misc`: + Predefined package ``ieee.std_logic_misc``. + +- :py:class:`Std_logic_misc_Body`: + Predefined package body of package ``ieee.std_logic_misc``. + +- :py:class:`Numeric_Bit`: + Predefined package ``ieee.numeric_bit``. + +- :py:class:`Numeric_Bit_Body`: + Predefined package body of package ``ieee.numeric_bit``. + +- :py:class:`Numeric_Bit_Unsigned`: + Predefined package ``ieee.numeric_bit_unsigned``. + +- :py:class:`Numeric_Bit_Unsigned_Body`: + Predefined package body of package ``ieee.numeric_bit_unsigned``. + +- :py:class:`Numeric_Std`: + Predefined package ``ieee.numeric_std``. + +- :py:class:`Numeric_Std_Body`: + Predefined package body of package ``ieee.numeric_std``. + +- :py:class:`Numeric_Std_Unsigned`: + Predefined package ``ieee.numeric_std_unsigned``. + +- :py:class:`Numeric_Std_Unsigned_Body`: + Predefined package body of package ``ieee.numeric_std_unsigned``. + +- :py:class:`Fixed_Float_Types`: + Predefined package ``ieee.fixed_float_types``. + +- :py:class:`Fixed_Generic_Pkg`: + Predefined package ``ieee.fixed_generic_pkg``. + +- :py:class:`Fixed_Generic_Pkg_Body`: + Predefined package body of package ``ieee.fixed_generic_pkg``. + +- :py:class:`Fixed_Pkg`: + Predefined package ``ieee.fixed_pkg``. + +- :py:class:`Float_Generic_Pkg`: + Predefined package ``ieee.float_generic_pkg``. + +- :py:class:`Float_Generic_Pkg_Body`: + Predefined package body of package ``ieee.float_generic_pkg``. + +- :py:class:`Float_Pkg`: + Predefined package ``ieee.float_pkg``. + + + +--------------------- + +**Classes** + + + + +.. autoclass:: Ieee + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Ieee + :parts: 1 + +.. autoclass:: Math_Real + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Math_Real + :parts: 1 + +.. autoclass:: Math_Real_Body + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Math_Real_Body + :parts: 1 + +.. autoclass:: Math_Complex + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Math_Complex + :parts: 1 + +.. autoclass:: Math_Complex_Body + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Math_Complex_Body + :parts: 1 + +.. autoclass:: Std_logic_1164 + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Std_logic_1164 + :parts: 1 + +.. autoclass:: Std_logic_1164_Body + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Std_logic_1164_Body + :parts: 1 + +.. autoclass:: std_logic_textio + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: std_logic_textio + :parts: 1 + +.. autoclass:: Std_logic_misc + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Std_logic_misc + :parts: 1 + +.. autoclass:: Std_logic_misc_Body + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Std_logic_misc_Body + :parts: 1 + +.. autoclass:: Numeric_Bit + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Numeric_Bit + :parts: 1 + +.. autoclass:: Numeric_Bit_Body + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Numeric_Bit_Body + :parts: 1 + +.. autoclass:: Numeric_Bit_Unsigned + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Numeric_Bit_Unsigned + :parts: 1 + +.. autoclass:: Numeric_Bit_Unsigned_Body + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Numeric_Bit_Unsigned_Body + :parts: 1 + +.. autoclass:: Numeric_Std + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Numeric_Std + :parts: 1 + +.. autoclass:: Numeric_Std_Body + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Numeric_Std_Body + :parts: 1 + +.. autoclass:: Numeric_Std_Unsigned + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Numeric_Std_Unsigned + :parts: 1 + +.. autoclass:: Numeric_Std_Unsigned_Body + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Numeric_Std_Unsigned_Body + :parts: 1 + +.. autoclass:: Fixed_Float_Types + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Fixed_Float_Types + :parts: 1 + +.. autoclass:: Fixed_Generic_Pkg + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Fixed_Generic_Pkg + :parts: 1 + +.. autoclass:: Fixed_Generic_Pkg_Body + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Fixed_Generic_Pkg_Body + :parts: 1 + +.. autoclass:: Fixed_Pkg + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Fixed_Pkg + :parts: 1 + +.. autoclass:: Float_Generic_Pkg + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Float_Generic_Pkg + :parts: 1 + +.. autoclass:: Float_Generic_Pkg_Body + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Float_Generic_Pkg_Body + :parts: 1 + +.. autoclass:: Float_Pkg + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Float_Pkg + :parts: 1 diff --git a/_sources/pyVHDLModel/pyVHDLModel.Instantiation.rst.txt b/_sources/pyVHDLModel/pyVHDLModel.Instantiation.rst.txt new file mode 100644 index 000000000..d653a79f6 --- /dev/null +++ b/_sources/pyVHDLModel/pyVHDLModel.Instantiation.rst.txt @@ -0,0 +1,108 @@ +.. # Template modified by Patrick Lehmann + * removed automodule on top, because private members are activated for autodoc (no doubled documentation). + * Made sections like 'submodules' bold text, but no headlines to reduce number of ToC levels. + +========================= +pyVHDLModel.Instantiation +========================= + +.. automodule:: pyVHDLModel.Instantiation + + +.. currentmodule:: pyVHDLModel.Instantiation + + +**Classes** + +- :py:class:`GenericInstantiationMixin`: + Undocumented. + +- :py:class:`GenericEntityInstantiationMixin`: + Undocumented. + +- :py:class:`SubprogramInstantiationMixin`: + Undocumented. + +- :py:class:`ProcedureInstantiation`: + ``ModelEntity`` is the base-class for all classes in the VHDL language model, except for mixin classes (see multiple + +- :py:class:`FunctionInstantiation`: + ``ModelEntity`` is the base-class for all classes in the VHDL language model, except for mixin classes (see multiple + +- :py:class:`PackageInstantiation`: + A base-class for all primary design units. + + + +--------------------- + +**Classes** + + + + +.. autoclass:: GenericInstantiationMixin + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: GenericInstantiationMixin + :parts: 1 + +.. autoclass:: GenericEntityInstantiationMixin + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: GenericEntityInstantiationMixin + :parts: 1 + +.. autoclass:: SubprogramInstantiationMixin + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: SubprogramInstantiationMixin + :parts: 1 + +.. autoclass:: ProcedureInstantiation + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ProcedureInstantiation + :parts: 1 + +.. autoclass:: FunctionInstantiation + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: FunctionInstantiation + :parts: 1 + +.. autoclass:: PackageInstantiation + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: PackageInstantiation + :parts: 1 diff --git a/_sources/pyVHDLModel/pyVHDLModel.Interface.rst.txt b/_sources/pyVHDLModel/pyVHDLModel.Interface.rst.txt new file mode 100644 index 000000000..36170295b --- /dev/null +++ b/_sources/pyVHDLModel/pyVHDLModel.Interface.rst.txt @@ -0,0 +1,248 @@ +.. # Template modified by Patrick Lehmann + * removed automodule on top, because private members are activated for autodoc (no doubled documentation). + * Made sections like 'submodules' bold text, but no headlines to reduce number of ToC levels. + +===================== +pyVHDLModel.Interface +===================== + +.. automodule:: pyVHDLModel.Interface + + +.. currentmodule:: pyVHDLModel.Interface + + +**Classes** + +- :py:class:`InterfaceItemMixin`: + An ``InterfaceItem`` is a base-class for all mixin-classes for all interface items. + +- :py:class:`InterfaceItemWithModeMixin`: + An ``InterfaceItemWithMode`` is a mixin-class to provide a ``Mode`` to interface items. + +- :py:class:`GenericInterfaceItemMixin`: + A ``GenericInterfaceItem`` is a mixin class for all generic interface items. + +- :py:class:`PortInterfaceItemMixin`: + A ``PortInterfaceItem`` is a mixin class for all port interface items. + +- :py:class:`ParameterInterfaceItemMixin`: + A ``ParameterInterfaceItem`` is a mixin class for all parameter interface items. + +- :py:class:`GenericConstantInterfaceItem`: + Represents a constant. + +- :py:class:`GenericTypeInterfaceItem`: + ``BaseType`` is the base-class of all type entities in this model. + +- :py:class:`GenericSubprogramInterfaceItem`: + A ``GenericInterfaceItem`` is a mixin class for all generic interface items. + +- :py:class:`GenericProcedureInterfaceItem`: + ``ModelEntity`` is the base-class for all classes in the VHDL language model, except for mixin classes (see multiple + +- :py:class:`GenericFunctionInterfaceItem`: + ``ModelEntity`` is the base-class for all classes in the VHDL language model, except for mixin classes (see multiple + +- :py:class:`GenericPackageInterfaceItem`: + A ``GenericInterfaceItem`` is a mixin class for all generic interface items. + +- :py:class:`PortSignalInterfaceItem`: + Represents a signal. + +- :py:class:`ParameterConstantInterfaceItem`: + Represents a constant. + +- :py:class:`ParameterVariableInterfaceItem`: + Represents a variable. + +- :py:class:`ParameterSignalInterfaceItem`: + Represents a signal. + +- :py:class:`ParameterFileInterfaceItem`: + Represents a file. + + + +--------------------- + +**Classes** + + + + +.. autoclass:: InterfaceItemMixin + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: InterfaceItemMixin + :parts: 1 + +.. autoclass:: InterfaceItemWithModeMixin + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: InterfaceItemWithModeMixin + :parts: 1 + +.. autoclass:: GenericInterfaceItemMixin + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: GenericInterfaceItemMixin + :parts: 1 + +.. autoclass:: PortInterfaceItemMixin + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: PortInterfaceItemMixin + :parts: 1 + +.. autoclass:: ParameterInterfaceItemMixin + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ParameterInterfaceItemMixin + :parts: 1 + +.. autoclass:: GenericConstantInterfaceItem + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: GenericConstantInterfaceItem + :parts: 1 + +.. autoclass:: GenericTypeInterfaceItem + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: GenericTypeInterfaceItem + :parts: 1 + +.. autoclass:: GenericSubprogramInterfaceItem + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: GenericSubprogramInterfaceItem + :parts: 1 + +.. autoclass:: GenericProcedureInterfaceItem + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: GenericProcedureInterfaceItem + :parts: 1 + +.. autoclass:: GenericFunctionInterfaceItem + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: GenericFunctionInterfaceItem + :parts: 1 + +.. autoclass:: GenericPackageInterfaceItem + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: GenericPackageInterfaceItem + :parts: 1 + +.. autoclass:: PortSignalInterfaceItem + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: PortSignalInterfaceItem + :parts: 1 + +.. autoclass:: ParameterConstantInterfaceItem + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ParameterConstantInterfaceItem + :parts: 1 + +.. autoclass:: ParameterVariableInterfaceItem + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ParameterVariableInterfaceItem + :parts: 1 + +.. autoclass:: ParameterSignalInterfaceItem + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ParameterSignalInterfaceItem + :parts: 1 + +.. autoclass:: ParameterFileInterfaceItem + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ParameterFileInterfaceItem + :parts: 1 diff --git a/_sources/pyVHDLModel/pyVHDLModel.Name.rst.txt b/_sources/pyVHDLModel/pyVHDLModel.Name.rst.txt new file mode 100644 index 000000000..a1d4481fc --- /dev/null +++ b/_sources/pyVHDLModel/pyVHDLModel.Name.rst.txt @@ -0,0 +1,150 @@ +.. # Template modified by Patrick Lehmann + * removed automodule on top, because private members are activated for autodoc (no doubled documentation). + * Made sections like 'submodules' bold text, but no headlines to reduce number of ToC levels. + +================ +pyVHDLModel.Name +================ + +.. automodule:: pyVHDLModel.Name + + +.. currentmodule:: pyVHDLModel.Name + + +**Classes** + +- :py:class:`Name`: + ``Name`` is the base-class for all *names* in the VHDL language model. + +- :py:class:`SimpleName`: + A *simple name* is a name made from a single word. + +- :py:class:`ParenthesisName`: + ``Name`` is the base-class for all *names* in the VHDL language model. + +- :py:class:`IndexedName`: + ``Name`` is the base-class for all *names* in the VHDL language model. + +- :py:class:`SlicedName`: + ``Name`` is the base-class for all *names* in the VHDL language model. + +- :py:class:`SelectedName`: + A *selected name* is a name made from multiple words separated by a dot (``.``). + +- :py:class:`AttributeName`: + ``Name`` is the base-class for all *names* in the VHDL language model. + +- :py:class:`AllName`: + The *all name* represents the reserved word ``all`` used in names. + +- :py:class:`OpenName`: + The *open name* represents the reserved word ``open``. + + + +--------------------- + +**Classes** + + + + +.. autoclass:: Name + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Name + :parts: 1 + +.. autoclass:: SimpleName + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: SimpleName + :parts: 1 + +.. autoclass:: ParenthesisName + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ParenthesisName + :parts: 1 + +.. autoclass:: IndexedName + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: IndexedName + :parts: 1 + +.. autoclass:: SlicedName + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: SlicedName + :parts: 1 + +.. autoclass:: SelectedName + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: SelectedName + :parts: 1 + +.. autoclass:: AttributeName + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: AttributeName + :parts: 1 + +.. autoclass:: AllName + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: AllName + :parts: 1 + +.. autoclass:: OpenName + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: OpenName + :parts: 1 diff --git a/_sources/pyVHDLModel/pyVHDLModel.Namespace.rst.txt b/_sources/pyVHDLModel/pyVHDLModel.Namespace.rst.txt new file mode 100644 index 000000000..42c465675 --- /dev/null +++ b/_sources/pyVHDLModel/pyVHDLModel.Namespace.rst.txt @@ -0,0 +1,12 @@ +.. # Template modified by Patrick Lehmann + * removed automodule on top, because private members are activated for autodoc (no doubled documentation). + * Made sections like 'submodules' bold text, but no headlines to reduce number of ToC levels. + +===================== +pyVHDLModel.Namespace +===================== + +.. automodule:: pyVHDLModel.Namespace + + +.. currentmodule:: pyVHDLModel.Namespace diff --git a/_sources/pyVHDLModel/pyVHDLModel.Object.rst.txt b/_sources/pyVHDLModel/pyVHDLModel.Object.rst.txt new file mode 100644 index 000000000..44c8f2750 --- /dev/null +++ b/_sources/pyVHDLModel/pyVHDLModel.Object.rst.txt @@ -0,0 +1,150 @@ +.. # Template modified by Patrick Lehmann + * removed automodule on top, because private members are activated for autodoc (no doubled documentation). + * Made sections like 'submodules' bold text, but no headlines to reduce number of ToC levels. + +================== +pyVHDLModel.Object +================== + +.. automodule:: pyVHDLModel.Object + + +.. currentmodule:: pyVHDLModel.Object + + +**Classes** + +- :py:class:`Obj`: + Base-class for all objects (constants, signals, variables and files) in VHDL. + +- :py:class:`WithDefaultExpressionMixin`: + A ``WithDefaultExpression`` is a mixin-class for all objects declarations accepting default expressions. + +- :py:class:`BaseConstant`: + Base-class for all constants (normal and deferred constants) in VHDL. + +- :py:class:`Constant`: + Represents a constant. + +- :py:class:`DeferredConstant`: + Represents a deferred constant. + +- :py:class:`Variable`: + Represents a variable. + +- :py:class:`SharedVariable`: + Represents a shared variable. + +- :py:class:`Signal`: + Represents a signal. + +- :py:class:`File`: + Represents a file. + + + +--------------------- + +**Classes** + + + + +.. autoclass:: Obj + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Obj + :parts: 1 + +.. autoclass:: WithDefaultExpressionMixin + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: WithDefaultExpressionMixin + :parts: 1 + +.. autoclass:: BaseConstant + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: BaseConstant + :parts: 1 + +.. autoclass:: Constant + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Constant + :parts: 1 + +.. autoclass:: DeferredConstant + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: DeferredConstant + :parts: 1 + +.. autoclass:: Variable + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Variable + :parts: 1 + +.. autoclass:: SharedVariable + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: SharedVariable + :parts: 1 + +.. autoclass:: Signal + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Signal + :parts: 1 + +.. autoclass:: File + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: File + :parts: 1 diff --git a/_sources/pyVHDLModel/pyVHDLModel.PSLModel.rst.txt b/_sources/pyVHDLModel/pyVHDLModel.PSLModel.rst.txt new file mode 100644 index 000000000..1750c7c96 --- /dev/null +++ b/_sources/pyVHDLModel/pyVHDLModel.PSLModel.rst.txt @@ -0,0 +1,108 @@ +.. # Template modified by Patrick Lehmann + * removed automodule on top, because private members are activated for autodoc (no doubled documentation). + * Made sections like 'submodules' bold text, but no headlines to reduce number of ToC levels. + +==================== +pyVHDLModel.PSLModel +==================== + +.. automodule:: pyVHDLModel.PSLModel + + +.. currentmodule:: pyVHDLModel.PSLModel + + +**Classes** + +- :py:class:`PSLEntity`: + ``ModelEntity`` is the base-class for all classes in the VHDL language model, except for mixin classes (see multiple + +- :py:class:`PSLPrimaryUnit`: + A base-class for all primary design units. + +- :py:class:`VerificationUnit`: + A base-class for all primary design units. + +- :py:class:`VerificationProperty`: + A base-class for all primary design units. + +- :py:class:`VerificationMode`: + A base-class for all primary design units. + +- :py:class:`DefaultClock`: + ``ModelEntity`` is the base-class for all classes in the VHDL language model, except for mixin classes (see multiple + + + +--------------------- + +**Classes** + + + + +.. autoclass:: PSLEntity + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: PSLEntity + :parts: 1 + +.. autoclass:: PSLPrimaryUnit + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: PSLPrimaryUnit + :parts: 1 + +.. autoclass:: VerificationUnit + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: VerificationUnit + :parts: 1 + +.. autoclass:: VerificationProperty + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: VerificationProperty + :parts: 1 + +.. autoclass:: VerificationMode + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: VerificationMode + :parts: 1 + +.. autoclass:: DefaultClock + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: DefaultClock + :parts: 1 diff --git a/_sources/pyVHDLModel/pyVHDLModel.Predefined.rst.txt b/_sources/pyVHDLModel/pyVHDLModel.Predefined.rst.txt new file mode 100644 index 000000000..de2111825 --- /dev/null +++ b/_sources/pyVHDLModel/pyVHDLModel.Predefined.rst.txt @@ -0,0 +1,80 @@ +.. # Template modified by Patrick Lehmann + * removed automodule on top, because private members are activated for autodoc (no doubled documentation). + * Made sections like 'submodules' bold text, but no headlines to reduce number of ToC levels. + +====================== +pyVHDLModel.Predefined +====================== + +.. automodule:: pyVHDLModel.Predefined + + +.. currentmodule:: pyVHDLModel.Predefined + + +**Classes** + +- :py:class:`PredefinedLibrary`: + A base-class for predefined VHDL libraries. + +- :py:class:`PredefinedPackageMixin`: + A mixin-class for predefined VHDL packages and package bodies. + +- :py:class:`PredefinedPackage`: + A base-class for predefined VHDL packages. + +- :py:class:`PredefinedPackageBody`: + A base-class for predefined VHDL package bodies. + + + +--------------------- + +**Classes** + + + + +.. autoclass:: PredefinedLibrary + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: PredefinedLibrary + :parts: 1 + +.. autoclass:: PredefinedPackageMixin + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: PredefinedPackageMixin + :parts: 1 + +.. autoclass:: PredefinedPackage + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: PredefinedPackage + :parts: 1 + +.. autoclass:: PredefinedPackageBody + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: PredefinedPackageBody + :parts: 1 diff --git a/_sources/pyVHDLModel/pyVHDLModel.Regions.rst.txt b/_sources/pyVHDLModel/pyVHDLModel.Regions.rst.txt new file mode 100644 index 000000000..3fac86f27 --- /dev/null +++ b/_sources/pyVHDLModel/pyVHDLModel.Regions.rst.txt @@ -0,0 +1,38 @@ +.. # Template modified by Patrick Lehmann + * removed automodule on top, because private members are activated for autodoc (no doubled documentation). + * Made sections like 'submodules' bold text, but no headlines to reduce number of ToC levels. + +=================== +pyVHDLModel.Regions +=================== + +.. automodule:: pyVHDLModel.Regions + + +.. currentmodule:: pyVHDLModel.Regions + + +**Classes** + +- :py:class:`ConcurrentDeclarationRegionMixin`: + Undocumented. + + + +--------------------- + +**Classes** + + + + +.. autoclass:: ConcurrentDeclarationRegionMixin + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ConcurrentDeclarationRegionMixin + :parts: 1 diff --git a/_sources/pyVHDLModel/pyVHDLModel.STD.rst.txt b/_sources/pyVHDLModel/pyVHDLModel.STD.rst.txt new file mode 100644 index 000000000..f9fbeadc9 --- /dev/null +++ b/_sources/pyVHDLModel/pyVHDLModel.STD.rst.txt @@ -0,0 +1,122 @@ +.. # Template modified by Patrick Lehmann + * removed automodule on top, because private members are activated for autodoc (no doubled documentation). + * Made sections like 'submodules' bold text, but no headlines to reduce number of ToC levels. + +=============== +pyVHDLModel.STD +=============== + +.. automodule:: pyVHDLModel.STD + + +.. currentmodule:: pyVHDLModel.STD + + +**Classes** + +- :py:class:`Std`: + Predefined VHDL library ``std``. + +- :py:class:`Standard`: + Predefined package ``std.standard``. + +- :py:class:`Standard_Body`: + Predefined package body of package ``std.standard``. + +- :py:class:`TextIO`: + Predefined package ``std.textio``. + +- :py:class:`TextIO_Body`: + Predefined package body of package ``std.textio``. + +- :py:class:`Env`: + Predefined package ``std.env``. + +- :py:class:`Env_Body`: + Predefined package body of package ``std.env``. + + + +--------------------- + +**Classes** + + + + +.. autoclass:: Std + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Std + :parts: 1 + +.. autoclass:: Standard + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Standard + :parts: 1 + +.. autoclass:: Standard_Body + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Standard_Body + :parts: 1 + +.. autoclass:: TextIO + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: TextIO + :parts: 1 + +.. autoclass:: TextIO_Body + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: TextIO_Body + :parts: 1 + +.. autoclass:: Env + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Env + :parts: 1 + +.. autoclass:: Env_Body + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Env_Body + :parts: 1 diff --git a/_sources/pyVHDLModel/pyVHDLModel.Sequential.rst.txt b/_sources/pyVHDLModel/pyVHDLModel.Sequential.rst.txt new file mode 100644 index 000000000..c1edfac75 --- /dev/null +++ b/_sources/pyVHDLModel/pyVHDLModel.Sequential.rst.txt @@ -0,0 +1,472 @@ +.. # Template modified by Patrick Lehmann + * removed automodule on top, because private members are activated for autodoc (no doubled documentation). + * Made sections like 'submodules' bold text, but no headlines to reduce number of ToC levels. + +====================== +pyVHDLModel.Sequential +====================== + +.. automodule:: pyVHDLModel.Sequential + + +.. currentmodule:: pyVHDLModel.Sequential + + +**Classes** + +- :py:class:`SequentialStatement`: + A ``SequentialStatement`` is a base-class for all sequential statements. + +- :py:class:`SequentialStatementsMixin`: + Undocumented. + +- :py:class:`SequentialProcedureCall`: + A ``SequentialStatement`` is a base-class for all sequential statements. + +- :py:class:`SequentialSignalAssignment`: + A ``SequentialStatement`` is a base-class for all sequential statements. + +- :py:class:`SequentialSimpleSignalAssignment`: + A ``SequentialStatement`` is a base-class for all sequential statements. + +- :py:class:`SequentialVariableAssignment`: + A ``SequentialStatement`` is a base-class for all sequential statements. + +- :py:class:`SequentialReportStatement`: + A ``SequentialStatement`` is a base-class for all sequential statements. + +- :py:class:`SequentialAssertStatement`: + A ``SequentialStatement`` is a base-class for all sequential statements. + +- :py:class:`CompoundStatement`: + A ``CompoundStatement`` is a base-class for all compound statements. + +- :py:class:`Branch`: + A ``Branch`` is a base-class for all branches in a if statement. + +- :py:class:`IfBranch`: + A ``Branch`` is a base-class for all branches in a if statement. + +- :py:class:`ElsifBranch`: + A ``Branch`` is a base-class for all branches in a if statement. + +- :py:class:`ElseBranch`: + A ``Branch`` is a base-class for all branches in a if statement. + +- :py:class:`IfStatement`: + A ``CompoundStatement`` is a base-class for all compound statements. + +- :py:class:`SequentialChoice`: + A ``SequentialChoice`` is a base-class for all sequential choices (in case statements). + +- :py:class:`IndexedChoice`: + A ``SequentialChoice`` is a base-class for all sequential choices (in case statements). + +- :py:class:`RangedChoice`: + A ``SequentialChoice`` is a base-class for all sequential choices (in case statements). + +- :py:class:`SequentialCase`: + A ``Case`` is a base-class for all cases. + +- :py:class:`Case`: + A ``Case`` is a base-class for all cases. + +- :py:class:`OthersCase`: + A ``Case`` is a base-class for all cases. + +- :py:class:`CaseStatement`: + A ``CompoundStatement`` is a base-class for all compound statements. + +- :py:class:`LoopStatement`: + A ``LoopStatement`` is a base-class for all loop statements. + +- :py:class:`EndlessLoopStatement`: + A ``LoopStatement`` is a base-class for all loop statements. + +- :py:class:`ForLoopStatement`: + A ``LoopStatement`` is a base-class for all loop statements. + +- :py:class:`WhileLoopStatement`: + A ``LoopStatement`` is a base-class for all loop statements. + +- :py:class:`LoopControlStatement`: + A ``LoopControlStatement`` is a base-class for all loop controlling statements. + +- :py:class:`NextStatement`: + A ``LoopControlStatement`` is a base-class for all loop controlling statements. + +- :py:class:`ExitStatement`: + A ``LoopControlStatement`` is a base-class for all loop controlling statements. + +- :py:class:`NullStatement`: + A ``SequentialStatement`` is a base-class for all sequential statements. + +- :py:class:`ReturnStatement`: + A ``SequentialStatement`` is a base-class for all sequential statements. + +- :py:class:`WaitStatement`: + A ``SequentialStatement`` is a base-class for all sequential statements. + +- :py:class:`SequentialDeclarationsMixin`: + Undocumented. + + + +--------------------- + +**Classes** + + + + +.. autoclass:: SequentialStatement + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: SequentialStatement + :parts: 1 + +.. autoclass:: SequentialStatementsMixin + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: SequentialStatementsMixin + :parts: 1 + +.. autoclass:: SequentialProcedureCall + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: SequentialProcedureCall + :parts: 1 + +.. autoclass:: SequentialSignalAssignment + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: SequentialSignalAssignment + :parts: 1 + +.. autoclass:: SequentialSimpleSignalAssignment + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: SequentialSimpleSignalAssignment + :parts: 1 + +.. autoclass:: SequentialVariableAssignment + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: SequentialVariableAssignment + :parts: 1 + +.. autoclass:: SequentialReportStatement + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: SequentialReportStatement + :parts: 1 + +.. autoclass:: SequentialAssertStatement + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: SequentialAssertStatement + :parts: 1 + +.. autoclass:: CompoundStatement + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: CompoundStatement + :parts: 1 + +.. autoclass:: Branch + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Branch + :parts: 1 + +.. autoclass:: IfBranch + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: IfBranch + :parts: 1 + +.. autoclass:: ElsifBranch + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ElsifBranch + :parts: 1 + +.. autoclass:: ElseBranch + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ElseBranch + :parts: 1 + +.. autoclass:: IfStatement + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: IfStatement + :parts: 1 + +.. autoclass:: SequentialChoice + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: SequentialChoice + :parts: 1 + +.. autoclass:: IndexedChoice + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: IndexedChoice + :parts: 1 + +.. autoclass:: RangedChoice + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: RangedChoice + :parts: 1 + +.. autoclass:: SequentialCase + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: SequentialCase + :parts: 1 + +.. autoclass:: Case + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Case + :parts: 1 + +.. autoclass:: OthersCase + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: OthersCase + :parts: 1 + +.. autoclass:: CaseStatement + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: CaseStatement + :parts: 1 + +.. autoclass:: LoopStatement + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: LoopStatement + :parts: 1 + +.. autoclass:: EndlessLoopStatement + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: EndlessLoopStatement + :parts: 1 + +.. autoclass:: ForLoopStatement + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ForLoopStatement + :parts: 1 + +.. autoclass:: WhileLoopStatement + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: WhileLoopStatement + :parts: 1 + +.. autoclass:: LoopControlStatement + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: LoopControlStatement + :parts: 1 + +.. autoclass:: NextStatement + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: NextStatement + :parts: 1 + +.. autoclass:: ExitStatement + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ExitStatement + :parts: 1 + +.. autoclass:: NullStatement + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: NullStatement + :parts: 1 + +.. autoclass:: ReturnStatement + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ReturnStatement + :parts: 1 + +.. autoclass:: WaitStatement + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: WaitStatement + :parts: 1 + +.. autoclass:: SequentialDeclarationsMixin + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: SequentialDeclarationsMixin + :parts: 1 diff --git a/_sources/pyVHDLModel/pyVHDLModel.Subprogram.rst.txt b/_sources/pyVHDLModel/pyVHDLModel.Subprogram.rst.txt new file mode 100644 index 000000000..2c6b5d305 --- /dev/null +++ b/_sources/pyVHDLModel/pyVHDLModel.Subprogram.rst.txt @@ -0,0 +1,108 @@ +.. # Template modified by Patrick Lehmann + * removed automodule on top, because private members are activated for autodoc (no doubled documentation). + * Made sections like 'submodules' bold text, but no headlines to reduce number of ToC levels. + +====================== +pyVHDLModel.Subprogram +====================== + +.. automodule:: pyVHDLModel.Subprogram + + +.. currentmodule:: pyVHDLModel.Subprogram + + +**Classes** + +- :py:class:`Subprogram`: + ``ModelEntity`` is the base-class for all classes in the VHDL language model, except for mixin classes (see multiple + +- :py:class:`Procedure`: + ``ModelEntity`` is the base-class for all classes in the VHDL language model, except for mixin classes (see multiple + +- :py:class:`Function`: + ``ModelEntity`` is the base-class for all classes in the VHDL language model, except for mixin classes (see multiple + +- :py:class:`MethodMixin`: + A ``Method`` is a mixin class for all subprograms in a protected type. + +- :py:class:`ProcedureMethod`: + ``ModelEntity`` is the base-class for all classes in the VHDL language model, except for mixin classes (see multiple + +- :py:class:`FunctionMethod`: + ``ModelEntity`` is the base-class for all classes in the VHDL language model, except for mixin classes (see multiple + + + +--------------------- + +**Classes** + + + + +.. autoclass:: Subprogram + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Subprogram + :parts: 1 + +.. autoclass:: Procedure + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Procedure + :parts: 1 + +.. autoclass:: Function + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Function + :parts: 1 + +.. autoclass:: MethodMixin + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: MethodMixin + :parts: 1 + +.. autoclass:: ProcedureMethod + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ProcedureMethod + :parts: 1 + +.. autoclass:: FunctionMethod + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: FunctionMethod + :parts: 1 diff --git a/_sources/pyVHDLModel/pyVHDLModel.Symbol.rst.txt b/_sources/pyVHDLModel/pyVHDLModel.Symbol.rst.txt new file mode 100644 index 000000000..453f13e9d --- /dev/null +++ b/_sources/pyVHDLModel/pyVHDLModel.Symbol.rst.txt @@ -0,0 +1,332 @@ +.. # Template modified by Patrick Lehmann + * removed automodule on top, because private members are activated for autodoc (no doubled documentation). + * Made sections like 'submodules' bold text, but no headlines to reduce number of ToC levels. + +================== +pyVHDLModel.Symbol +================== + +.. automodule:: pyVHDLModel.Symbol + + +.. currentmodule:: pyVHDLModel.Symbol + + +**Classes** + +- :py:class:`PossibleReference`: + Is an enumeration, representing possible targets for a reference in a :class:`~pyVHDLModel.Symbol`. + +- :py:class:`Symbol`: + Base-class for all symbol classes. + +- :py:class:`LibraryReferenceSymbol`: + Represents a reference (name) to a library. + +- :py:class:`PackageReferenceSymbol`: + Represents a reference (name) to a package. + +- :py:class:`ContextReferenceSymbol`: + Represents a reference (name) to a context. + +- :py:class:`PackageMemberReferenceSymbol`: + Represents a reference (name) to a package member. + +- :py:class:`AllPackageMembersReferenceSymbol`: + Represents a reference (name) to all package members. + +- :py:class:`EntityInstantiationSymbol`: + Represents a reference (name) to an entity in a direct entity instantiation. + +- :py:class:`ComponentInstantiationSymbol`: + Represents a reference (name) to an entity in a component instantiation. + +- :py:class:`ConfigurationInstantiationSymbol`: + Represents a reference (name) to an entity in a configuration instantiation. + +- :py:class:`EntitySymbol`: + Represents a reference (name) to an entity in an architecture declaration. + +- :py:class:`ArchitectureSymbol`: + An entity reference in an entity instantiation with architecture name. + +- :py:class:`PackageSymbol`: + Represents a reference (name) to a package in a package body declaration. + +- :py:class:`RecordElementSymbol`: + Base-class for all symbol classes. + +- :py:class:`SubtypeSymbol`: + Base-class for all symbol classes. + +- :py:class:`SimpleSubtypeSymbol`: + Base-class for all symbol classes. + +- :py:class:`ConstrainedScalarSubtypeSymbol`: + Base-class for all symbol classes. + +- :py:class:`ConstrainedCompositeSubtypeSymbol`: + Base-class for all symbol classes. + +- :py:class:`ConstrainedArraySubtypeSymbol`: + Base-class for all symbol classes. + +- :py:class:`ConstrainedRecordSubtypeSymbol`: + Base-class for all symbol classes. + +- :py:class:`SimpleObjectOrFunctionCallSymbol`: + Base-class for all symbol classes. + +- :py:class:`IndexedObjectOrFunctionCallSymbol`: + Base-class for all symbol classes. + + + +--------------------- + +**Classes** + + + + +.. autoclass:: PossibleReference + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: PossibleReference + :parts: 1 + +.. autoclass:: Symbol + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Symbol + :parts: 1 + +.. autoclass:: LibraryReferenceSymbol + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: LibraryReferenceSymbol + :parts: 1 + +.. autoclass:: PackageReferenceSymbol + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: PackageReferenceSymbol + :parts: 1 + +.. autoclass:: ContextReferenceSymbol + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ContextReferenceSymbol + :parts: 1 + +.. autoclass:: PackageMemberReferenceSymbol + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: PackageMemberReferenceSymbol + :parts: 1 + +.. autoclass:: AllPackageMembersReferenceSymbol + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: AllPackageMembersReferenceSymbol + :parts: 1 + +.. autoclass:: EntityInstantiationSymbol + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: EntityInstantiationSymbol + :parts: 1 + +.. autoclass:: ComponentInstantiationSymbol + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ComponentInstantiationSymbol + :parts: 1 + +.. autoclass:: ConfigurationInstantiationSymbol + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ConfigurationInstantiationSymbol + :parts: 1 + +.. autoclass:: EntitySymbol + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: EntitySymbol + :parts: 1 + +.. autoclass:: ArchitectureSymbol + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ArchitectureSymbol + :parts: 1 + +.. autoclass:: PackageSymbol + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: PackageSymbol + :parts: 1 + +.. autoclass:: RecordElementSymbol + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: RecordElementSymbol + :parts: 1 + +.. autoclass:: SubtypeSymbol + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: SubtypeSymbol + :parts: 1 + +.. autoclass:: SimpleSubtypeSymbol + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: SimpleSubtypeSymbol + :parts: 1 + +.. autoclass:: ConstrainedScalarSubtypeSymbol + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ConstrainedScalarSubtypeSymbol + :parts: 1 + +.. autoclass:: ConstrainedCompositeSubtypeSymbol + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ConstrainedCompositeSubtypeSymbol + :parts: 1 + +.. autoclass:: ConstrainedArraySubtypeSymbol + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ConstrainedArraySubtypeSymbol + :parts: 1 + +.. autoclass:: ConstrainedRecordSubtypeSymbol + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ConstrainedRecordSubtypeSymbol + :parts: 1 + +.. autoclass:: SimpleObjectOrFunctionCallSymbol + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: SimpleObjectOrFunctionCallSymbol + :parts: 1 + +.. autoclass:: IndexedObjectOrFunctionCallSymbol + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: IndexedObjectOrFunctionCallSymbol + :parts: 1 diff --git a/_sources/pyVHDLModel/pyVHDLModel.Type.rst.txt b/_sources/pyVHDLModel/pyVHDLModel.Type.rst.txt new file mode 100644 index 000000000..13eaa7230 --- /dev/null +++ b/_sources/pyVHDLModel/pyVHDLModel.Type.rst.txt @@ -0,0 +1,318 @@ +.. # Template modified by Patrick Lehmann + * removed automodule on top, because private members are activated for autodoc (no doubled documentation). + * Made sections like 'submodules' bold text, but no headlines to reduce number of ToC levels. + +================ +pyVHDLModel.Type +================ + +.. automodule:: pyVHDLModel.Type + + +.. currentmodule:: pyVHDLModel.Type + + +**Classes** + +- :py:class:`BaseType`: + ``BaseType`` is the base-class of all type entities in this model. + +- :py:class:`Type`: + ``BaseType`` is the base-class of all type entities in this model. + +- :py:class:`AnonymousType`: + ``BaseType`` is the base-class of all type entities in this model. + +- :py:class:`FullType`: + ``BaseType`` is the base-class of all type entities in this model. + +- :py:class:`Subtype`: + ``BaseType`` is the base-class of all type entities in this model. + +- :py:class:`ScalarType`: + A ``ScalarType`` is a base-class for all scalar types. + +- :py:class:`RangedScalarType`: + A ``RangedScalarType`` is a base-class for all scalar types with a range. + +- :py:class:`NumericTypeMixin`: + A ``NumericType`` is a mixin class for all numeric types. + +- :py:class:`DiscreteTypeMixin`: + A ``DiscreteType`` is a mixin class for all discrete types. + +- :py:class:`EnumeratedType`: + A ``ScalarType`` is a base-class for all scalar types. + +- :py:class:`IntegerType`: + A ``RangedScalarType`` is a base-class for all scalar types with a range. + +- :py:class:`RealType`: + A ``RangedScalarType`` is a base-class for all scalar types with a range. + +- :py:class:`PhysicalType`: + A ``RangedScalarType`` is a base-class for all scalar types with a range. + +- :py:class:`CompositeType`: + A ``CompositeType`` is a base-class for all composite types. + +- :py:class:`ArrayType`: + A ``CompositeType`` is a base-class for all composite types. + +- :py:class:`RecordTypeElement`: + ``ModelEntity`` is the base-class for all classes in the VHDL language model, except for mixin classes (see multiple + +- :py:class:`RecordType`: + A ``CompositeType`` is a base-class for all composite types. + +- :py:class:`ProtectedType`: + ``BaseType`` is the base-class of all type entities in this model. + +- :py:class:`ProtectedTypeBody`: + ``BaseType`` is the base-class of all type entities in this model. + +- :py:class:`AccessType`: + ``BaseType`` is the base-class of all type entities in this model. + +- :py:class:`FileType`: + ``BaseType`` is the base-class of all type entities in this model. + + + +--------------------- + +**Classes** + + + + +.. autoclass:: BaseType + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: BaseType + :parts: 1 + +.. autoclass:: Type + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Type + :parts: 1 + +.. autoclass:: AnonymousType + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: AnonymousType + :parts: 1 + +.. autoclass:: FullType + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: FullType + :parts: 1 + +.. autoclass:: Subtype + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Subtype + :parts: 1 + +.. autoclass:: ScalarType + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ScalarType + :parts: 1 + +.. autoclass:: RangedScalarType + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: RangedScalarType + :parts: 1 + +.. autoclass:: NumericTypeMixin + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: NumericTypeMixin + :parts: 1 + +.. autoclass:: DiscreteTypeMixin + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: DiscreteTypeMixin + :parts: 1 + +.. autoclass:: EnumeratedType + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: EnumeratedType + :parts: 1 + +.. autoclass:: IntegerType + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: IntegerType + :parts: 1 + +.. autoclass:: RealType + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: RealType + :parts: 1 + +.. autoclass:: PhysicalType + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: PhysicalType + :parts: 1 + +.. autoclass:: CompositeType + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: CompositeType + :parts: 1 + +.. autoclass:: ArrayType + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ArrayType + :parts: 1 + +.. autoclass:: RecordTypeElement + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: RecordTypeElement + :parts: 1 + +.. autoclass:: RecordType + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: RecordType + :parts: 1 + +.. autoclass:: ProtectedType + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ProtectedType + :parts: 1 + +.. autoclass:: ProtectedTypeBody + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ProtectedTypeBody + :parts: 1 + +.. autoclass:: AccessType + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: AccessType + :parts: 1 + +.. autoclass:: FileType + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: FileType + :parts: 1 diff --git a/_sources/pyVHDLModel/pyVHDLModel.rst.txt b/_sources/pyVHDLModel/pyVHDLModel.rst.txt new file mode 100644 index 000000000..b74838402 --- /dev/null +++ b/_sources/pyVHDLModel/pyVHDLModel.rst.txt @@ -0,0 +1,193 @@ +.. # Template modified by Patrick Lehmann + * removed automodule on top, because private members are activated for autodoc (no doubled documentation). + * Made sections like 'submodules' bold text, but no headlines to reduce number of ToC levels. + +=========== +pyVHDLModel +=========== + +.. automodule:: pyVHDLModel + + + +**Submodules** + +.. toctree:: + :maxdepth: 1 + + pyVHDLModel.Association + pyVHDLModel.Base + pyVHDLModel.Common + pyVHDLModel.Concurrent + pyVHDLModel.Declaration + pyVHDLModel.DesignUnit + pyVHDLModel.Exception + pyVHDLModel.Expression + pyVHDLModel.IEEE + pyVHDLModel.Instantiation + pyVHDLModel.Interface + pyVHDLModel.Name + pyVHDLModel.Namespace + pyVHDLModel.Object + pyVHDLModel.PSLModel + pyVHDLModel.Predefined + pyVHDLModel.Regions + pyVHDLModel.STD + pyVHDLModel.Sequential + pyVHDLModel.Subprogram + pyVHDLModel.Symbol + pyVHDLModel.Type + +.. currentmodule:: pyVHDLModel + + +**Classes** + +- :py:class:`VHDLVersion`: + An enumeration for all possible version numbers for VHDL and VHDL-AMS. + +- :py:class:`ObjectClass`: + An ``ObjectClass`` is an enumeration and represents an object's class (``constant``, ``signal``, ...). + +- :py:class:`DesignUnitKind`: + A ``DesignUnitKind`` is an enumeration and represents the kind of design unit (``Entity``, ``Architecture``, ...). + +- :py:class:`DependencyGraphVertexKind`: + A ``DependencyGraphVertexKind`` is an enumeration and represents the kind of vertex in the dependency graph. + +- :py:class:`DependencyGraphEdgeKind`: + A ``DependencyGraphEdgeKind`` is an enumeration and represents the kind of edge in the dependency graph. + +- :py:class:`ObjectGraphVertexKind`: + A ``ObjectGraphVertexKind`` is an enumeration and represents the kind of vertex in the object graph. + +- :py:class:`ObjectGraphEdgeKind`: + A ``ObjectGraphEdgeKind`` is an enumeration and represents the kind of edge in the object graph. + +- :py:class:`Design`: + A ``Design`` represents set of VHDL libraries as well as all loaded and analysed source files (see :class:`~pyVHDLModel.Document`). + +- :py:class:`Library`: + A ``Library`` represents a VHDL library. It contains all *primary* and *secondary* design units. + +- :py:class:`Document`: + A ``Document`` represents a sourcefile. It contains *primary* and *secondary* design units. + + + +--------------------- + +**Classes** + + + + +.. autoclass:: VHDLVersion + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: VHDLVersion + :parts: 1 + +.. autoclass:: ObjectClass + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ObjectClass + :parts: 1 + +.. autoclass:: DesignUnitKind + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: DesignUnitKind + :parts: 1 + +.. autoclass:: DependencyGraphVertexKind + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: DependencyGraphVertexKind + :parts: 1 + +.. autoclass:: DependencyGraphEdgeKind + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: DependencyGraphEdgeKind + :parts: 1 + +.. autoclass:: ObjectGraphVertexKind + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ObjectGraphVertexKind + :parts: 1 + +.. autoclass:: ObjectGraphEdgeKind + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: ObjectGraphEdgeKind + :parts: 1 + +.. autoclass:: Design + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Design + :parts: 1 + +.. autoclass:: Library + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Library + :parts: 1 + +.. autoclass:: Document + :members: + :private-members: + :special-members: + :inherited-members: + :exclude-members: __weakref__ + + .. rubric:: Inheritance + .. inheritance-diagram:: Document + :parts: 1 diff --git a/_sources/typing/index.rst.txt b/_sources/typing/index.rst.txt new file mode 100644 index 000000000..97d4ae2aa --- /dev/null +++ b/_sources/typing/index.rst.txt @@ -0,0 +1,4 @@ +Static Type Checking Report +########################### + +*Placeholder for the Static Type Checking report generated with* ``mypy``. diff --git a/_sources/unittests/index.rst.txt b/_sources/unittests/index.rst.txt new file mode 100644 index 000000000..8b840ee66 --- /dev/null +++ b/_sources/unittests/index.rst.txt @@ -0,0 +1,7 @@ +Unittest Summary Report +####################### + +Unittest report generated with `pytest `__. + +.. report:unittest-summary:: + :reportid: src diff --git a/_sphinx_design_static/design-tabs.js b/_sphinx_design_static/design-tabs.js new file mode 100644 index 000000000..b25bd6a4f --- /dev/null +++ b/_sphinx_design_static/design-tabs.js @@ -0,0 +1,101 @@ +// @ts-check + +// Extra JS capability for selected tabs to be synced +// The selection is stored in local storage so that it persists across page loads. + +/** + * @type {Record} + */ +let sd_id_to_elements = {}; +const storageKeyPrefix = "sphinx-design-tab-id-"; + +/** + * Create a key for a tab element. + * @param {HTMLElement} el - The tab element. + * @returns {[string, string, string] | null} - The key. + * + */ +function create_key(el) { + let syncId = el.getAttribute("data-sync-id"); + let syncGroup = el.getAttribute("data-sync-group"); + if (!syncId || !syncGroup) return null; + return [syncGroup, syncId, syncGroup + "--" + syncId]; +} + +/** + * Initialize the tab selection. + * + */ +function ready() { + // Find all tabs with sync data + + /** @type {string[]} */ + let groups = []; + + document.querySelectorAll(".sd-tab-label").forEach((label) => { + if (label instanceof HTMLElement) { + let data = create_key(label); + if (data) { + let [group, id, key] = data; + + // add click event listener + // @ts-ignore + label.onclick = onSDLabelClick; + + // store map of key to elements + if (!sd_id_to_elements[key]) { + sd_id_to_elements[key] = []; + } + sd_id_to_elements[key].push(label); + + if (groups.indexOf(group) === -1) { + groups.push(group); + // Check if a specific tab has been selected via URL parameter + const tabParam = new URLSearchParams(window.location.search).get( + group + ); + if (tabParam) { + console.log( + "sphinx-design: Selecting tab id for group '" + + group + + "' from URL parameter: " + + tabParam + ); + window.sessionStorage.setItem(storageKeyPrefix + group, tabParam); + } + } + + // Check is a specific tab has been selected previously + let previousId = window.sessionStorage.getItem( + storageKeyPrefix + group + ); + if (previousId === id) { + // console.log( + // "sphinx-design: Selecting tab from session storage: " + id + // ); + // @ts-ignore + label.previousElementSibling.checked = true; + } + } + } + }); +} + +/** + * Activate other tabs with the same sync id. + * + * @this {HTMLElement} - The element that was clicked. + */ +function onSDLabelClick() { + let data = create_key(this); + if (!data) return; + let [group, id, key] = data; + for (const label of sd_id_to_elements[key]) { + if (label === this) continue; + // @ts-ignore + label.previousElementSibling.checked = true; + } + window.sessionStorage.setItem(storageKeyPrefix + group, id); +} + +document.addEventListener("DOMContentLoaded", ready, false); diff --git a/_sphinx_design_static/sphinx-design.min.css b/_sphinx_design_static/sphinx-design.min.css new file mode 100644 index 000000000..860c36da0 --- /dev/null +++ b/_sphinx_design_static/sphinx-design.min.css @@ -0,0 +1 @@ +.sd-bg-primary{background-color:var(--sd-color-primary) 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b/_static/_sphinx_javascript_frameworks_compat.js @@ -0,0 +1,123 @@ +/* Compatability shim for jQuery and underscores.js. + * + * Copyright Sphinx contributors + * Released under the two clause BSD licence + */ + +/** + * small helper function to urldecode strings + * + * See https://developer.mozilla.org/en-US/docs/Web/JavaScript/Reference/Global_Objects/decodeURIComponent#Decoding_query_parameters_from_a_URL + */ +jQuery.urldecode = function(x) { + if (!x) { + return x + } + return decodeURIComponent(x.replace(/\+/g, ' ')); +}; + +/** + * small helper function to urlencode strings + */ +jQuery.urlencode = encodeURIComponent; + +/** + * This function returns the parsed url parameters of the + * current request. Multiple values per key are supported, + * it will always return arrays of strings for the value parts. + */ +jQuery.getQueryParameters = function(s) { + if (typeof s === 'undefined') + s = document.location.search; + var parts = s.substr(s.indexOf('?') + 1).split('&'); + var result = {}; + for (var i = 0; i < parts.length; i++) { + var tmp = parts[i].split('=', 2); + var key = jQuery.urldecode(tmp[0]); + var value = jQuery.urldecode(tmp[1]); + if (key in result) + result[key].push(value); + else + result[key] = [value]; + } + return result; +}; + +/** + * highlight a given string on a jquery object by wrapping it in + * span elements with the given class name. + */ +jQuery.fn.highlightText = function(text, className) { + function highlight(node, addItems) { + if (node.nodeType === 3) { + var val = node.nodeValue; + var pos = val.toLowerCase().indexOf(text); + if (pos >= 0 && + !jQuery(node.parentNode).hasClass(className) && + !jQuery(node.parentNode).hasClass("nohighlight")) { + var span; + var isInSVG = jQuery(node).closest("body, svg, foreignObject").is("svg"); + if (isInSVG) { + span = document.createElementNS("http://www.w3.org/2000/svg", "tspan"); + } else { + span = document.createElement("span"); + span.className = className; + } + span.appendChild(document.createTextNode(val.substr(pos, text.length))); + node.parentNode.insertBefore(span, node.parentNode.insertBefore( + document.createTextNode(val.substr(pos + text.length)), + node.nextSibling)); + node.nodeValue = val.substr(0, pos); + if (isInSVG) { + var rect = document.createElementNS("http://www.w3.org/2000/svg", "rect"); + var bbox = node.parentElement.getBBox(); + rect.x.baseVal.value = bbox.x; + rect.y.baseVal.value = bbox.y; + rect.width.baseVal.value = bbox.width; + rect.height.baseVal.value = bbox.height; + rect.setAttribute('class', className); + addItems.push({ + "parent": node.parentNode, + "target": rect}); + } + } + } + else if (!jQuery(node).is("button, select, textarea")) { + jQuery.each(node.childNodes, function() { + highlight(this, addItems); + }); + } + } + var addItems = []; + var result = this.each(function() { + highlight(this, addItems); + }); + for (var i = 0; i < addItems.length; ++i) { + jQuery(addItems[i].parent).before(addItems[i].target); + } + return result; +}; + +/* + * backward compatibility for jQuery.browser + * This will be supported until firefox bug is fixed. + */ +if (!jQuery.browser) { + jQuery.uaMatch = function(ua) { + ua = ua.toLowerCase(); + + var match = /(chrome)[ \/]([\w.]+)/.exec(ua) || + /(webkit)[ \/]([\w.]+)/.exec(ua) || + /(opera)(?:.*version|)[ \/]([\w.]+)/.exec(ua) || + /(msie) ([\w.]+)/.exec(ua) || + ua.indexOf("compatible") < 0 && /(mozilla)(?:.*? rv:([\w.]+)|)/.exec(ua) || + []; + + return { + browser: match[ 1 ] || "", + version: match[ 2 ] || "0" + }; + }; + jQuery.browser = {}; + jQuery.browser[jQuery.uaMatch(navigator.userAgent).browser] = true; +} diff --git a/_static/basic.css b/_static/basic.css new file mode 100644 index 000000000..f316efcb4 --- /dev/null +++ b/_static/basic.css @@ -0,0 +1,925 @@ +/* + * basic.css + * ~~~~~~~~~ + * + * Sphinx stylesheet -- basic theme. + * + * :copyright: Copyright 2007-2024 by the Sphinx team, see AUTHORS. + * :license: BSD, see LICENSE for details. + * + */ + +/* -- main layout ----------------------------------------------------------- */ + +div.clearer { + clear: both; +} + +div.section::after { + display: block; + content: ''; + clear: left; +} + +/* -- relbar ---------------------------------------------------------------- */ + +div.related { + width: 100%; + font-size: 90%; +} + +div.related h3 { + display: none; +} + +div.related ul { + margin: 0; + padding: 0 0 0 10px; + list-style: none; +} + +div.related li { + display: inline; +} + +div.related li.right { + float: right; + margin-right: 5px; +} + +/* -- sidebar --------------------------------------------------------------- */ + +div.sphinxsidebarwrapper { + padding: 10px 5px 0 10px; +} + +div.sphinxsidebar { + float: left; + width: 230px; + margin-left: -100%; + font-size: 90%; + word-wrap: break-word; + overflow-wrap : break-word; +} + +div.sphinxsidebar ul { + list-style: none; +} + +div.sphinxsidebar ul ul, +div.sphinxsidebar ul.want-points { + margin-left: 20px; + list-style: square; +} + +div.sphinxsidebar ul ul { + margin-top: 0; + margin-bottom: 0; +} + +div.sphinxsidebar form { + margin-top: 10px; +} + +div.sphinxsidebar input { + border: 1px solid #98dbcc; + font-family: sans-serif; + font-size: 1em; +} + +div.sphinxsidebar #searchbox form.search { + overflow: hidden; +} + +div.sphinxsidebar #searchbox input[type="text"] { + float: left; + width: 80%; + padding: 0.25em; + box-sizing: border-box; +} + +div.sphinxsidebar #searchbox input[type="submit"] { + float: left; + width: 20%; + border-left: none; + padding: 0.25em; + box-sizing: border-box; +} + + +img { + border: 0; + max-width: 100%; +} + +/* -- search page ----------------------------------------------------------- */ + +ul.search { + margin: 10px 0 0 20px; + padding: 0; +} + +ul.search li { + padding: 5px 0 5px 20px; + background-image: url(file.png); + background-repeat: no-repeat; + background-position: 0 7px; +} + +ul.search li a { + font-weight: bold; +} + +ul.search li p.context { + color: #888; + margin: 2px 0 0 30px; + text-align: left; +} + +ul.keywordmatches li.goodmatch a { + font-weight: bold; +} + +/* -- index page ------------------------------------------------------------ */ + +table.contentstable { + width: 90%; + margin-left: auto; + margin-right: auto; +} + +table.contentstable p.biglink { + line-height: 150%; +} + +a.biglink { + font-size: 1.3em; +} + +span.linkdescr { + font-style: italic; + padding-top: 5px; + font-size: 90%; +} + +/* -- general index --------------------------------------------------------- */ + +table.indextable { + width: 100%; +} + +table.indextable td { + text-align: left; + vertical-align: top; +} + +table.indextable ul { + margin-top: 0; + margin-bottom: 0; + list-style-type: none; +} + +table.indextable > tbody > tr > td > ul { + padding-left: 0em; +} + +table.indextable tr.pcap { + height: 10px; +} + +table.indextable tr.cap { + margin-top: 10px; + background-color: #f2f2f2; +} + +img.toggler { + margin-right: 3px; + margin-top: 3px; + cursor: pointer; +} + +div.modindex-jumpbox { + border-top: 1px solid #ddd; + border-bottom: 1px solid #ddd; + margin: 1em 0 1em 0; + padding: 0.4em; +} + +div.genindex-jumpbox { + border-top: 1px solid #ddd; + border-bottom: 1px solid #ddd; + margin: 1em 0 1em 0; + padding: 0.4em; +} + +/* -- domain module index --------------------------------------------------- */ + +table.modindextable td { + padding: 2px; + border-collapse: collapse; +} + +/* -- general body styles --------------------------------------------------- */ + +div.body { + min-width: 360px; + max-width: 800px; +} + +div.body p, div.body dd, div.body li, div.body blockquote { + -moz-hyphens: auto; + -ms-hyphens: auto; + -webkit-hyphens: auto; + hyphens: auto; +} + +a.headerlink { + visibility: hidden; +} + +a:visited { + color: #551A8B; +} + +h1:hover > a.headerlink, +h2:hover > a.headerlink, +h3:hover > a.headerlink, +h4:hover > a.headerlink, +h5:hover > a.headerlink, +h6:hover > a.headerlink, +dt:hover > a.headerlink, +caption:hover > a.headerlink, +p.caption:hover > a.headerlink, +div.code-block-caption:hover > a.headerlink { + visibility: visible; +} + +div.body p.caption { + text-align: inherit; +} + +div.body td { + text-align: left; +} + +.first { + margin-top: 0 !important; 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+ float: right; + clear: right; + overflow-x: auto; +} + +p.sidebar-title { + font-weight: bold; +} + +nav.contents, +aside.topic, +div.admonition, div.topic, blockquote { + clear: left; +} + +/* -- topics ---------------------------------------------------------------- */ + +nav.contents, +aside.topic, +div.topic { + border: 1px solid #ccc; + padding: 7px; + margin: 10px 0 10px 0; +} + +p.topic-title { + font-size: 1.1em; + font-weight: bold; + margin-top: 10px; +} + +/* -- admonitions ----------------------------------------------------------- */ + +div.admonition { + margin-top: 10px; + margin-bottom: 10px; + padding: 7px; +} + +div.admonition dt { + font-weight: bold; +} + +p.admonition-title { + margin: 0px 10px 5px 0px; + font-weight: bold; +} + +div.body p.centered { + text-align: center; + margin-top: 25px; +} + +/* -- content of sidebars/topics/admonitions -------------------------------- */ + +div.sidebar > :last-child, +aside.sidebar > :last-child, +nav.contents > :last-child, +aside.topic > :last-child, +div.topic > :last-child, +div.admonition > :last-child { + margin-bottom: 0; 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+} + +.sig-name, code.descname { + background-color: transparent; + font-weight: bold; +} + +.sig-name { + font-size: 1.1em; +} + +code.descname { + font-size: 1.2em; +} + +.sig-prename, code.descclassname { + background-color: transparent; +} + +.optional { + font-size: 1.3em; +} + +.sig-paren { + font-size: larger; +} + +.sig-param.n { + font-style: italic; +} + +/* C++ specific styling */ + +.sig-inline.c-texpr, +.sig-inline.cpp-texpr { + font-family: unset; +} + +.sig.c .k, .sig.c .kt, +.sig.cpp .k, .sig.cpp .kt { + color: #0033B3; +} + +.sig.c .m, +.sig.cpp .m { + color: #1750EB; +} + +.sig.c .s, .sig.c .sc, +.sig.cpp .s, .sig.cpp .sc { + color: #067D17; +} + + +/* -- other body styles ----------------------------------------------------- */ + +ol.arabic { + list-style: decimal; +} + +ol.loweralpha { + list-style: lower-alpha; +} + +ol.upperalpha { + list-style: upper-alpha; +} + +ol.lowerroman { + list-style: lower-roman; +} + +ol.upperroman { + list-style: upper-roman; +} + +:not(li) > ol > li:first-child > :first-child, +:not(li) > ul > li:first-child > :first-child { + margin-top: 0px; +} + +:not(li) > ol > li:last-child > :last-child, +:not(li) > ul > li:last-child > :last-child { + margin-bottom: 0px; +} + +ol.simple ol p, +ol.simple ul p, +ul.simple ol p, +ul.simple ul p { + margin-top: 0; +} + +ol.simple > li:not(:first-child) > p, +ul.simple > li:not(:first-child) > p { + margin-top: 0; +} + +ol.simple p, +ul.simple p { + margin-bottom: 0; +} + +aside.footnote > span, +div.citation > span { + float: left; +} +aside.footnote > span:last-of-type, +div.citation > span:last-of-type { + padding-right: 0.5em; +} +aside.footnote > p { + margin-left: 2em; +} +div.citation > p { + margin-left: 4em; +} +aside.footnote > p:last-of-type, +div.citation > p:last-of-type { + margin-bottom: 0em; +} +aside.footnote > p:last-of-type:after, +div.citation > p:last-of-type:after { + content: ""; + clear: both; +} + +dl.field-list { + display: grid; + grid-template-columns: fit-content(30%) auto; +} + +dl.field-list > dt { + font-weight: bold; + word-break: break-word; + padding-left: 0.5em; + padding-right: 5px; +} + +dl.field-list > dd { + padding-left: 0.5em; + margin-top: 0em; + margin-left: 0em; + margin-bottom: 0em; +} + +dl { + margin-bottom: 15px; +} + +dd > :first-child { + margin-top: 0px; +} + +dd ul, dd table { + margin-bottom: 10px; +} + +dd { + margin-top: 3px; + margin-bottom: 10px; + margin-left: 30px; +} + +.sig dd { + margin-top: 0px; + margin-bottom: 0px; +} + +.sig dl { + margin-top: 0px; + margin-bottom: 0px; +} + +dl > dd:last-child, +dl > dd:last-child > :last-child { + margin-bottom: 0; +} + +dt:target, span.highlighted { + background-color: #fbe54e; +} + +rect.highlighted { + fill: #fbe54e; +} + +dl.glossary dt { + font-weight: bold; + font-size: 1.1em; +} + +.versionmodified { + font-style: italic; +} + +.system-message { + background-color: #fda; + padding: 5px; + border: 3px solid red; +} + +.footnote:target { + background-color: #ffa; +} + +.line-block { + display: block; + margin-top: 1em; + margin-bottom: 1em; +} + +.line-block .line-block { + margin-top: 0; + margin-bottom: 0; + margin-left: 1.5em; +} + +.guilabel, .menuselection { + font-family: sans-serif; +} + +.accelerator { + text-decoration: underline; +} + +.classifier { + font-style: oblique; +} + +.classifier:before { + font-style: normal; + margin: 0 0.5em; + content: ":"; + display: inline-block; +} + +abbr, acronym { + border-bottom: dotted 1px; + cursor: help; +} + +.translated { + background-color: rgba(207, 255, 207, 0.2) +} + +.untranslated { + background-color: rgba(255, 207, 207, 0.2) +} + +/* -- code displays --------------------------------------------------------- */ + +pre { + overflow: auto; + overflow-y: hidden; /* fixes display issues on Chrome browsers */ +} + +pre, div[class*="highlight-"] { + clear: both; +} + +span.pre { + -moz-hyphens: none; + -ms-hyphens: none; + -webkit-hyphens: none; + hyphens: none; + white-space: nowrap; +} + +div[class*="highlight-"] { + margin: 1em 0; +} + +td.linenos pre { + border: 0; + background-color: transparent; + color: #aaa; +} + +table.highlighttable { + display: block; +} + +table.highlighttable tbody { + display: block; +} + +table.highlighttable tr { + display: flex; +} + +table.highlighttable td { + margin: 0; + padding: 0; +} + +table.highlighttable td.linenos { + padding-right: 0.5em; +} + +table.highlighttable td.code { + flex: 1; + overflow: hidden; +} + +.highlight .hll { + display: block; +} + +div.highlight pre, +table.highlighttable pre { + margin: 0; +} + +div.code-block-caption + div { + margin-top: 0; +} + +div.code-block-caption { + margin-top: 1em; + padding: 2px 5px; + font-size: small; +} + +div.code-block-caption code { + background-color: transparent; +} + +table.highlighttable td.linenos, +span.linenos, +div.highlight span.gp { /* gp: Generic.Prompt */ + user-select: none; + -webkit-user-select: text; /* Safari fallback only */ + -webkit-user-select: none; /* Chrome/Safari */ + -moz-user-select: none; /* Firefox */ + -ms-user-select: none; /* IE10+ */ +} + +div.code-block-caption span.caption-number { + padding: 0.1em 0.3em; + font-style: italic; +} + +div.code-block-caption span.caption-text { +} + +div.literal-block-wrapper { + margin: 1em 0; +} + +code.xref, a code { + background-color: transparent; + font-weight: bold; +} + +h1 code, h2 code, h3 code, h4 code, h5 code, h6 code { + background-color: transparent; +} + +.viewcode-link { + float: right; +} + +.viewcode-back { + float: right; + font-family: sans-serif; +} + +div.viewcode-block:target { + margin: -1px -10px; + padding: 0 10px; +} + +/* -- math display ---------------------------------------------------------- */ + +img.math { + vertical-align: middle; +} + +div.body div.math p { + text-align: center; +} + +span.eqno { + float: right; +} + +span.eqno a.headerlink { + position: absolute; + z-index: 1; +} + +div.math:hover a.headerlink { + visibility: visible; +} + +/* -- printout stylesheet --------------------------------------------------- */ + +@media print { + div.document, + div.documentwrapper, + div.bodywrapper { + margin: 0 !important; + width: 100%; + } + + div.sphinxsidebar, + div.related, + div.footer, + #top-link { + display: none; + } +} \ No newline at end of file diff --git a/_static/check-solid.svg b/_static/check-solid.svg new file mode 100644 index 000000000..92fad4b5c --- /dev/null +++ b/_static/check-solid.svg @@ -0,0 +1,4 @@ + + + + diff --git a/_static/clipboard.min.js b/_static/clipboard.min.js new file mode 100644 index 000000000..54b3c4638 --- /dev/null +++ b/_static/clipboard.min.js @@ -0,0 +1,7 @@ +/*! + * clipboard.js v2.0.8 + * https://clipboardjs.com/ + * + * Licensed MIT © Zeno Rocha + */ +!function(t,e){"object"==typeof exports&&"object"==typeof module?module.exports=e():"function"==typeof define&&define.amd?define([],e):"object"==typeof exports?exports.ClipboardJS=e():t.ClipboardJS=e()}(this,function(){return n={686:function(t,e,n){"use strict";n.d(e,{default:function(){return o}});var e=n(279),i=n.n(e),e=n(370),u=n.n(e),e=n(817),c=n.n(e);function a(t){try{return document.execCommand(t)}catch(t){return}}var f=function(t){t=c()(t);return a("cut"),t};var l=function(t){var e,n,o,r=1 + + + + diff --git a/_static/copybutton.css b/_static/copybutton.css new file mode 100644 index 000000000..f1916ec7d --- /dev/null +++ b/_static/copybutton.css @@ -0,0 +1,94 @@ +/* Copy buttons */ +button.copybtn { + position: absolute; + display: flex; + top: .3em; + right: .3em; + width: 1.7em; + height: 1.7em; + opacity: 0; + transition: opacity 0.3s, border .3s, background-color .3s; + user-select: none; + padding: 0; + border: none; + outline: none; + border-radius: 0.4em; + /* The colors that GitHub uses */ + border: #1b1f2426 1px solid; + background-color: #f6f8fa; + color: #57606a; +} + +button.copybtn.success { + border-color: #22863a; + color: #22863a; +} + +button.copybtn svg { + stroke: currentColor; + width: 1.5em; + height: 1.5em; + padding: 0.1em; +} + +div.highlight { + position: relative; +} + +/* Show the copybutton */ +.highlight:hover button.copybtn, button.copybtn.success { + opacity: 1; +} + +.highlight button.copybtn:hover { + background-color: rgb(235, 235, 235); +} + +.highlight button.copybtn:active { + background-color: rgb(187, 187, 187); +} + +/** + * A minimal CSS-only tooltip copied from: + * https://codepen.io/mildrenben/pen/rVBrpK + * + * To use, write HTML like the following: + * + *

Short

+ */ + .o-tooltip--left { + position: relative; + } + + .o-tooltip--left:after { + opacity: 0; + visibility: hidden; + position: absolute; + content: attr(data-tooltip); + padding: .2em; + font-size: .8em; + left: -.2em; + background: grey; + color: white; + white-space: nowrap; + z-index: 2; + border-radius: 2px; + transform: translateX(-102%) translateY(0); + transition: opacity 0.2s cubic-bezier(0.64, 0.09, 0.08, 1), transform 0.2s cubic-bezier(0.64, 0.09, 0.08, 1); +} + +.o-tooltip--left:hover:after { + display: block; + opacity: 1; + visibility: visible; + transform: translateX(-100%) translateY(0); + transition: opacity 0.2s cubic-bezier(0.64, 0.09, 0.08, 1), transform 0.2s cubic-bezier(0.64, 0.09, 0.08, 1); + transition-delay: .5s; +} + +/* By default the copy button shouldn't show up when printing a page */ +@media print { + button.copybtn { + display: none; + } +} diff --git a/_static/copybutton.js b/_static/copybutton.js new file mode 100644 index 000000000..2ea7ff3e2 --- /dev/null +++ b/_static/copybutton.js @@ -0,0 +1,248 @@ +// Localization support +const messages = { + 'en': { + 'copy': 'Copy', + 'copy_to_clipboard': 'Copy to clipboard', + 'copy_success': 'Copied!', + 'copy_failure': 'Failed to copy', + }, + 'es' : { + 'copy': 'Copiar', + 'copy_to_clipboard': 'Copiar al portapapeles', + 'copy_success': '¡Copiado!', + 'copy_failure': 'Error al copiar', + }, + 'de' : { + 'copy': 'Kopieren', + 'copy_to_clipboard': 'In die Zwischenablage kopieren', + 'copy_success': 'Kopiert!', + 'copy_failure': 'Fehler beim Kopieren', + }, + 'fr' : { + 'copy': 'Copier', + 'copy_to_clipboard': 'Copier dans le presse-papier', + 'copy_success': 'Copié !', + 'copy_failure': 'Échec de la copie', + }, + 'ru': { + 'copy': 'Скопировать', + 'copy_to_clipboard': 'Скопировать в буфер', + 'copy_success': 'Скопировано!', + 'copy_failure': 'Не удалось скопировать', + }, + 'zh-CN': { + 'copy': '复制', + 'copy_to_clipboard': '复制到剪贴板', + 'copy_success': '复制成功!', + 'copy_failure': '复制失败', + }, + 'it' : { + 'copy': 'Copiare', + 'copy_to_clipboard': 'Copiato negli appunti', + 'copy_success': 'Copiato!', + 'copy_failure': 'Errore durante la copia', + } +} + +let locale = 'en' +if( document.documentElement.lang !== undefined + && messages[document.documentElement.lang] !== undefined ) { + locale = document.documentElement.lang +} + +let doc_url_root = DOCUMENTATION_OPTIONS.URL_ROOT; +if (doc_url_root == '#') { + doc_url_root = ''; +} + +/** + * SVG files for our copy buttons + */ +let iconCheck = ` + ${messages[locale]['copy_success']} + + +` + +// If the user specified their own SVG use that, otherwise use the default +let iconCopy = ``; +if (!iconCopy) { + iconCopy = ` + ${messages[locale]['copy_to_clipboard']} + + + +` +} + +/** + * Set up copy/paste for code blocks + */ + +const runWhenDOMLoaded = cb => { + if (document.readyState != 'loading') { + cb() + } else if (document.addEventListener) { + document.addEventListener('DOMContentLoaded', cb) + } else { + document.attachEvent('onreadystatechange', function() { + if (document.readyState == 'complete') cb() + }) + } +} + +const codeCellId = index => `codecell${index}` + +// Clears selected text since ClipboardJS will select the text when copying +const clearSelection = () => { + if (window.getSelection) { + window.getSelection().removeAllRanges() + } else if (document.selection) { + document.selection.empty() + } +} + +// Changes tooltip text for a moment, then changes it back +// We want the timeout of our `success` class to be a bit shorter than the +// tooltip and icon change, so that we can hide the icon before changing back. +var timeoutIcon = 2000; +var timeoutSuccessClass = 1500; + +const temporarilyChangeTooltip = (el, oldText, newText) => { + el.setAttribute('data-tooltip', newText) + el.classList.add('success') + // Remove success a little bit sooner than we change the tooltip + // So that we can use CSS to hide the copybutton first + setTimeout(() => el.classList.remove('success'), timeoutSuccessClass) + setTimeout(() => el.setAttribute('data-tooltip', oldText), timeoutIcon) +} + +// Changes the copy button icon for two seconds, then changes it back +const temporarilyChangeIcon = (el) => { + el.innerHTML = iconCheck; + setTimeout(() => {el.innerHTML = iconCopy}, timeoutIcon) +} + +const addCopyButtonToCodeCells = () => { + // If ClipboardJS hasn't loaded, wait a bit and try again. This + // happens because we load ClipboardJS asynchronously. + if (window.ClipboardJS === undefined) { + setTimeout(addCopyButtonToCodeCells, 250) + return + } + + // Add copybuttons to all of our code cells + const COPYBUTTON_SELECTOR = 'div.highlight pre'; + const codeCells = document.querySelectorAll(COPYBUTTON_SELECTOR) + codeCells.forEach((codeCell, index) => { + const id = codeCellId(index) + codeCell.setAttribute('id', id) + + const clipboardButton = id => + `` + codeCell.insertAdjacentHTML('afterend', clipboardButton(id)) + }) + +function escapeRegExp(string) { + return string.replace(/[.*+?^${}()|[\]\\]/g, '\\$&'); // $& means the whole matched string +} + +/** + * Removes excluded text from a Node. + * + * @param {Node} target Node to filter. + * @param {string} exclude CSS selector of nodes to exclude. + * @returns {DOMString} Text from `target` with text removed. + */ +function filterText(target, exclude) { + const clone = target.cloneNode(true); // clone as to not modify the live DOM + if (exclude) { + // remove excluded nodes + clone.querySelectorAll(exclude).forEach(node => node.remove()); + } + return clone.innerText; +} + +// Callback when a copy button is clicked. Will be passed the node that was clicked +// should then grab the text and replace pieces of text that shouldn't be used in output +function formatCopyText(textContent, copybuttonPromptText, isRegexp = false, onlyCopyPromptLines = true, removePrompts = true, copyEmptyLines = true, lineContinuationChar = "", hereDocDelim = "") { + var regexp; + var match; + + // Do we check for line continuation characters and "HERE-documents"? + var useLineCont = !!lineContinuationChar + var useHereDoc = !!hereDocDelim + + // create regexp to capture prompt and remaining line + if (isRegexp) { + regexp = new RegExp('^(' + copybuttonPromptText + ')(.*)') + } else { + regexp = new RegExp('^(' + escapeRegExp(copybuttonPromptText) + ')(.*)') + } + + const outputLines = []; + var promptFound = false; + var gotLineCont = false; + var gotHereDoc = false; + const lineGotPrompt = []; + for (const line of textContent.split('\n')) { + match = line.match(regexp) + if (match || gotLineCont || gotHereDoc) { + promptFound = regexp.test(line) + lineGotPrompt.push(promptFound) + if (removePrompts && promptFound) { + outputLines.push(match[2]) + } else { + outputLines.push(line) + } + gotLineCont = line.endsWith(lineContinuationChar) & useLineCont + if (line.includes(hereDocDelim) & useHereDoc) + gotHereDoc = !gotHereDoc + } else if (!onlyCopyPromptLines) { + outputLines.push(line) + } else if (copyEmptyLines && line.trim() === '') { + outputLines.push(line) + } + } + + // If no lines with the prompt were found then just use original lines + if (lineGotPrompt.some(v => v === true)) { + textContent = outputLines.join('\n'); + } + + // Remove a trailing newline to avoid auto-running when pasting + if (textContent.endsWith("\n")) { + textContent = textContent.slice(0, -1) + } + return textContent +} + + +var copyTargetText = (trigger) => { + var target = document.querySelector(trigger.attributes['data-clipboard-target'].value); + + // get filtered text + let exclude = '.linenos'; + + let text = filterText(target, exclude); + return formatCopyText(text, '', false, true, true, true, '', '') +} + + // Initialize with a callback so we can modify the text before copy + const clipboard = new ClipboardJS('.copybtn', {text: copyTargetText}) + + // Update UI with error/success messages + clipboard.on('success', event => { + clearSelection() + temporarilyChangeTooltip(event.trigger, messages[locale]['copy'], messages[locale]['copy_success']) + temporarilyChangeIcon(event.trigger) + }) + + clipboard.on('error', event => { + temporarilyChangeTooltip(event.trigger, messages[locale]['copy'], messages[locale]['copy_failure']) + }) +} + +runWhenDOMLoaded(addCopyButtonToCodeCells) \ No newline at end of file diff --git a/_static/copybutton_funcs.js b/_static/copybutton_funcs.js new file mode 100644 index 000000000..dbe1aaad7 --- /dev/null +++ b/_static/copybutton_funcs.js @@ -0,0 +1,73 @@ +function escapeRegExp(string) { + return string.replace(/[.*+?^${}()|[\]\\]/g, '\\$&'); // $& means the whole matched string +} + +/** + * Removes excluded text from a Node. + * + * @param {Node} target Node to filter. + * @param {string} exclude CSS selector of nodes to exclude. + * @returns {DOMString} Text from `target` with text removed. + */ +export function filterText(target, exclude) { + const clone = target.cloneNode(true); // clone as to not modify the live DOM + if (exclude) { + // remove excluded nodes + clone.querySelectorAll(exclude).forEach(node => node.remove()); + } + return clone.innerText; +} + +// Callback when a copy button is clicked. Will be passed the node that was clicked +// should then grab the text and replace pieces of text that shouldn't be used in output +export function formatCopyText(textContent, copybuttonPromptText, isRegexp = false, onlyCopyPromptLines = true, removePrompts = true, copyEmptyLines = true, lineContinuationChar = "", hereDocDelim = "") { + var regexp; + var match; + + // Do we check for line continuation characters and "HERE-documents"? + var useLineCont = !!lineContinuationChar + var useHereDoc = !!hereDocDelim + + // create regexp to capture prompt and remaining line + if (isRegexp) { + regexp = new RegExp('^(' + copybuttonPromptText + ')(.*)') + } else { + regexp = new RegExp('^(' + escapeRegExp(copybuttonPromptText) + ')(.*)') + } + + const outputLines = []; + var promptFound = false; + var gotLineCont = false; + var gotHereDoc = false; + const lineGotPrompt = []; + for (const line of textContent.split('\n')) { + match = line.match(regexp) + if (match || gotLineCont || gotHereDoc) { + promptFound = regexp.test(line) + lineGotPrompt.push(promptFound) + if (removePrompts && promptFound) { + outputLines.push(match[2]) + } else { + outputLines.push(line) + } + gotLineCont = line.endsWith(lineContinuationChar) & useLineCont + if (line.includes(hereDocDelim) & useHereDoc) + gotHereDoc = !gotHereDoc + } else if (!onlyCopyPromptLines) { + outputLines.push(line) + } else if (copyEmptyLines && line.trim() === '') { + outputLines.push(line) + } + } + + // If no lines with the prompt were found then just use original lines + if (lineGotPrompt.some(v => v === true)) { + textContent = outputLines.join('\n'); + } + + // Remove a trailing newline to avoid auto-running when pasting + if (textContent.endsWith("\n")) { + textContent = textContent.slice(0, -1) + } + return textContent +} diff --git a/_static/css/badge_only.css b/_static/css/badge_only.css new file mode 100644 index 000000000..c718cee44 --- /dev/null +++ b/_static/css/badge_only.css @@ -0,0 +1 @@ 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// [C]VC[V] is m=1 + var mgr1 = "^(" + C + ")?" + V + C + V + C; // [C]VCVC... is m>1 + var s_v = "^(" + C + ")?" + v; // vowel in stem + + this.stemWord = function (w) { + var stem; + var suffix; + var firstch; + var origword = w; + + if (w.length < 3) + return w; + + var re; + var re2; + var re3; + var re4; + + firstch = w.substr(0,1); + if (firstch == "y") + w = firstch.toUpperCase() + w.substr(1); + + // Step 1a + re = /^(.+?)(ss|i)es$/; + re2 = /^(.+?)([^s])s$/; + + if (re.test(w)) + w = w.replace(re,"$1$2"); + else if (re2.test(w)) + w = w.replace(re2,"$1$2"); + + // Step 1b + re = /^(.+?)eed$/; + re2 = /^(.+?)(ed|ing)$/; + if (re.test(w)) { + var fp = re.exec(w); + re = new RegExp(mgr0); + if (re.test(fp[1])) { + re = /.$/; + w = w.replace(re,""); + } + } + else if (re2.test(w)) { + var fp = re2.exec(w); + stem = fp[1]; + re2 = new RegExp(s_v); + if (re2.test(stem)) { + w = stem; + re2 = /(at|bl|iz)$/; + re3 = new RegExp("([^aeiouylsz])\\1$"); + re4 = new RegExp("^" + C + v + "[^aeiouwxy]$"); + if (re2.test(w)) + w = w + "e"; + else if (re3.test(w)) { + re = /.$/; + w = w.replace(re,""); + } + else if (re4.test(w)) + w = w + "e"; + } + } + + // Step 1c + re = /^(.+?)y$/; + if (re.test(w)) { + var fp = re.exec(w); + stem = fp[1]; + re = new RegExp(s_v); + if (re.test(stem)) + w = stem + "i"; + } + + // Step 2 + re = /^(.+?)(ational|tional|enci|anci|izer|bli|alli|entli|eli|ousli|ization|ation|ator|alism|iveness|fulness|ousness|aliti|iviti|biliti|logi)$/; + if (re.test(w)) { + var fp = re.exec(w); + stem = fp[1]; + suffix = fp[2]; + re = new RegExp(mgr0); + if (re.test(stem)) + w = stem + step2list[suffix]; + } + + // Step 3 + re = /^(.+?)(icate|ative|alize|iciti|ical|ful|ness)$/; + if (re.test(w)) { + var fp = re.exec(w); + stem = fp[1]; + suffix = fp[2]; + re = new RegExp(mgr0); + if (re.test(stem)) + w = stem + step3list[suffix]; + } + + // Step 4 + re = /^(.+?)(al|ance|ence|er|ic|able|ible|ant|ement|ment|ent|ou|ism|ate|iti|ous|ive|ize)$/; + re2 = /^(.+?)(s|t)(ion)$/; + if (re.test(w)) { + var fp = re.exec(w); + stem = fp[1]; + re = new RegExp(mgr1); + if (re.test(stem)) + w = stem; + } + else if (re2.test(w)) { + var fp = re2.exec(w); + stem = fp[1] + fp[2]; + re2 = new RegExp(mgr1); + if (re2.test(stem)) + w = stem; + } + + // Step 5 + re = /^(.+?)e$/; + if (re.test(w)) { + var fp = re.exec(w); + stem = fp[1]; + re = new RegExp(mgr1); + re2 = new RegExp(meq1); + re3 = new RegExp("^" + C + v + "[^aeiouwxy]$"); + if (re.test(stem) || (re2.test(stem) && !(re3.test(stem)))) + w = stem; + } + re = /ll$/; + re2 = new RegExp(mgr1); + if (re.test(w) && re2.test(w)) { + re = /.$/; + w = w.replace(re,""); + } + + // and turn initial Y back to y + if (firstch == "y") + w = firstch.toLowerCase() + w.substr(1); + return w; + } +} + diff --git a/_static/logo.svg b/_static/logo.svg new file mode 100644 index 000000000..62d264f79 --- /dev/null +++ b/_static/logo.svg @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/_static/minus.png b/_static/minus.png new file mode 100644 index 000000000..d96755fda Binary files /dev/null and b/_static/minus.png differ diff --git a/_static/plus.png b/_static/plus.png new file mode 100644 index 000000000..7107cec93 Binary files /dev/null and b/_static/plus.png differ diff --git a/_static/pygments.css b/_static/pygments.css new file mode 100644 index 000000000..3f7c12800 --- /dev/null +++ b/_static/pygments.css @@ -0,0 +1,75 @@ +pre { line-height: 125%; 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+ +/** + * Simple result scoring code. + */ +if (typeof Scorer === "undefined") { + var Scorer = { + // Implement the following function to further tweak the score for each result + // The function takes a result array [docname, title, anchor, descr, score, filename] + // and returns the new score. + /* + score: result => { + const [docname, title, anchor, descr, score, filename] = result + return score + }, + */ + + // query matches the full name of an object + objNameMatch: 11, + // or matches in the last dotted part of the object name + objPartialMatch: 6, + // Additive scores depending on the priority of the object + objPrio: { + 0: 15, // used to be importantResults + 1: 5, // used to be objectResults + 2: -5, // used to be unimportantResults + }, + // Used when the priority is not in the mapping. + objPrioDefault: 0, + + // query found in title + title: 15, + partialTitle: 7, + // query found in terms + term: 5, + partialTerm: 2, + }; +} + +const _removeChildren = (element) => { + while (element && element.lastChild) element.removeChild(element.lastChild); +}; + +/** + * See https://developer.mozilla.org/en-US/docs/Web/JavaScript/Guide/Regular_Expressions#escaping + */ +const _escapeRegExp = (string) => + string.replace(/[.*+\-?^${}()|[\]\\]/g, "\\$&"); // $& means the whole matched string + +const _displayItem = (item, searchTerms, highlightTerms) => { + const docBuilder = DOCUMENTATION_OPTIONS.BUILDER; + const docFileSuffix = DOCUMENTATION_OPTIONS.FILE_SUFFIX; + const docLinkSuffix = DOCUMENTATION_OPTIONS.LINK_SUFFIX; + const showSearchSummary = DOCUMENTATION_OPTIONS.SHOW_SEARCH_SUMMARY; + const contentRoot = document.documentElement.dataset.content_root; + + const [docName, title, anchor, descr, score, _filename] = item; + + let listItem = document.createElement("li"); + let requestUrl; + let linkUrl; + if (docBuilder === "dirhtml") { + // dirhtml builder + let dirname = docName + "/"; + if (dirname.match(/\/index\/$/)) + dirname = dirname.substring(0, dirname.length - 6); + else if (dirname === "index/") dirname = ""; + requestUrl = contentRoot + dirname; + linkUrl = requestUrl; + } else { + // normal html builders + requestUrl = contentRoot + docName + docFileSuffix; + linkUrl = docName + docLinkSuffix; + } + let linkEl = listItem.appendChild(document.createElement("a")); + linkEl.href = linkUrl + anchor; + linkEl.dataset.score = score; + linkEl.innerHTML = title; + if (descr) { + listItem.appendChild(document.createElement("span")).innerHTML = + " (" + descr + ")"; + // highlight search terms in the description + if (SPHINX_HIGHLIGHT_ENABLED) // set in sphinx_highlight.js + highlightTerms.forEach((term) => _highlightText(listItem, term, "highlighted")); + } + else if (showSearchSummary) + fetch(requestUrl) + .then((responseData) => responseData.text()) + .then((data) => { + if (data) + listItem.appendChild( + Search.makeSearchSummary(data, searchTerms, anchor) + ); + // highlight search terms in the summary + if (SPHINX_HIGHLIGHT_ENABLED) // set in sphinx_highlight.js + highlightTerms.forEach((term) => _highlightText(listItem, term, "highlighted")); + }); + Search.output.appendChild(listItem); +}; +const _finishSearch = (resultCount) => { + Search.stopPulse(); + Search.title.innerText = _("Search Results"); + if (!resultCount) + Search.status.innerText = Documentation.gettext( + "Your search did not match any documents. Please make sure that all words are spelled correctly and that you've selected enough categories." + ); + else + Search.status.innerText = _( + "Search finished, found ${resultCount} page(s) matching the search query." + ).replace('${resultCount}', resultCount); +}; +const _displayNextItem = ( + results, + resultCount, + searchTerms, + highlightTerms, +) => { + // results left, load the summary and display it + // this is intended to be dynamic (don't sub resultsCount) + if (results.length) { + _displayItem(results.pop(), searchTerms, highlightTerms); + setTimeout( + () => _displayNextItem(results, resultCount, searchTerms, highlightTerms), + 5 + ); + } + // search finished, update title and status message + else _finishSearch(resultCount); +}; +// Helper function used by query() to order search results. +// Each input is an array of [docname, title, anchor, descr, score, filename]. +// Order the results by score (in opposite order of appearance, since the +// `_displayNextItem` function uses pop() to retrieve items) and then alphabetically. +const _orderResultsByScoreThenName = (a, b) => { + const leftScore = a[4]; + const rightScore = b[4]; + if (leftScore === rightScore) { + // same score: sort alphabetically + const leftTitle = a[1].toLowerCase(); + const rightTitle = b[1].toLowerCase(); + if (leftTitle === rightTitle) return 0; + return leftTitle > rightTitle ? -1 : 1; // inverted is intentional + } + return leftScore > rightScore ? 1 : -1; +}; + +/** + * Default splitQuery function. Can be overridden in ``sphinx.search`` with a + * custom function per language. + * + * The regular expression works by splitting the string on consecutive characters + * that are not Unicode letters, numbers, underscores, or emoji characters. + * This is the same as ``\W+`` in Python, preserving the surrogate pair area. + */ +if (typeof splitQuery === "undefined") { + var splitQuery = (query) => query + .split(/[^\p{Letter}\p{Number}_\p{Emoji_Presentation}]+/gu) + .filter(term => term) // remove remaining empty strings +} + +/** + * Search Module + */ +const Search = { + _index: null, + _queued_query: null, + _pulse_status: -1, + + htmlToText: (htmlString, anchor) => { + const htmlElement = new DOMParser().parseFromString(htmlString, 'text/html'); + for (const removalQuery of [".headerlink", "script", "style"]) { + htmlElement.querySelectorAll(removalQuery).forEach((el) => { el.remove() }); + } + if (anchor) { + const anchorContent = htmlElement.querySelector(`[role="main"] ${anchor}`); + if (anchorContent) return anchorContent.textContent; + + console.warn( + `Anchored content block not found. Sphinx search tries to obtain it via DOM query '[role=main] ${anchor}'. Check your theme or template.` + ); + } + + // if anchor not specified or not found, fall back to main content + const docContent = htmlElement.querySelector('[role="main"]'); + if (docContent) return docContent.textContent; + + console.warn( + "Content block not found. Sphinx search tries to obtain it via DOM query '[role=main]'. Check your theme or template." + ); + return ""; + }, + + init: () => { + const query = new URLSearchParams(window.location.search).get("q"); + document + .querySelectorAll('input[name="q"]') + .forEach((el) => (el.value = query)); + if (query) Search.performSearch(query); + }, + + loadIndex: (url) => + (document.body.appendChild(document.createElement("script")).src = url), + + setIndex: (index) => { + Search._index = index; + if (Search._queued_query !== null) { + const query = Search._queued_query; + Search._queued_query = null; + Search.query(query); + } + }, + + hasIndex: () => Search._index !== null, + + deferQuery: (query) => (Search._queued_query = query), + + stopPulse: () => (Search._pulse_status = -1), + + startPulse: () => { + if (Search._pulse_status >= 0) return; + + const pulse = () => { + Search._pulse_status = (Search._pulse_status + 1) % 4; + Search.dots.innerText = ".".repeat(Search._pulse_status); + if (Search._pulse_status >= 0) window.setTimeout(pulse, 500); + }; + pulse(); + }, + + /** + * perform a search for something (or wait until index is loaded) + */ + performSearch: (query) => { + // create the required interface elements + const searchText = document.createElement("h2"); + searchText.textContent = _("Searching"); + const searchSummary = document.createElement("p"); + searchSummary.classList.add("search-summary"); + searchSummary.innerText = ""; + const searchList = document.createElement("ul"); + searchList.classList.add("search"); + + const out = document.getElementById("search-results"); + Search.title = out.appendChild(searchText); + Search.dots = Search.title.appendChild(document.createElement("span")); + Search.status = out.appendChild(searchSummary); + Search.output = out.appendChild(searchList); + + const searchProgress = document.getElementById("search-progress"); + // Some themes don't use the search progress node + if (searchProgress) { + searchProgress.innerText = _("Preparing search..."); + } + Search.startPulse(); + + // index already loaded, the browser was quick! + if (Search.hasIndex()) Search.query(query); + else Search.deferQuery(query); + }, + + _parseQuery: (query) => { + // stem the search terms and add them to the correct list + const stemmer = new Stemmer(); + const searchTerms = new Set(); + const excludedTerms = new Set(); + const highlightTerms = new Set(); + const objectTerms = new Set(splitQuery(query.toLowerCase().trim())); + splitQuery(query.trim()).forEach((queryTerm) => { + const queryTermLower = queryTerm.toLowerCase(); + + // maybe skip this "word" + // stopwords array is from language_data.js + if ( + stopwords.indexOf(queryTermLower) !== -1 || + queryTerm.match(/^\d+$/) + ) + return; + + // stem the word + let word = stemmer.stemWord(queryTermLower); + // select the correct list + if (word[0] === "-") excludedTerms.add(word.substr(1)); + else { + searchTerms.add(word); + highlightTerms.add(queryTermLower); + } + }); + + if (SPHINX_HIGHLIGHT_ENABLED) { // set in sphinx_highlight.js + localStorage.setItem("sphinx_highlight_terms", [...highlightTerms].join(" ")) + } + + // console.debug("SEARCH: searching for:"); + // console.info("required: ", [...searchTerms]); + // console.info("excluded: ", [...excludedTerms]); + + return [query, searchTerms, excludedTerms, highlightTerms, objectTerms]; + }, + + /** + * execute search (requires search index to be loaded) + */ + _performSearch: (query, searchTerms, excludedTerms, highlightTerms, objectTerms) => { + const filenames = Search._index.filenames; + const docNames = Search._index.docnames; + const titles = Search._index.titles; + const allTitles = Search._index.alltitles; + const indexEntries = Search._index.indexentries; + + // Collect multiple result groups to be sorted separately and then ordered. + // Each is an array of [docname, title, anchor, descr, score, filename]. + const normalResults = []; + const nonMainIndexResults = []; + + _removeChildren(document.getElementById("search-progress")); + + const queryLower = query.toLowerCase().trim(); + for (const [title, foundTitles] of Object.entries(allTitles)) { + if (title.toLowerCase().trim().includes(queryLower) && (queryLower.length >= title.length/2)) { + for (const [file, id] of foundTitles) { + const score = Math.round(Scorer.title * queryLower.length / title.length); + const boost = titles[file] === title ? 1 : 0; // add a boost for document titles + normalResults.push([ + docNames[file], + titles[file] !== title ? `${titles[file]} > ${title}` : title, + id !== null ? "#" + id : "", + null, + score + boost, + filenames[file], + ]); + } + } + } + + // search for explicit entries in index directives + for (const [entry, foundEntries] of Object.entries(indexEntries)) { + if (entry.includes(queryLower) && (queryLower.length >= entry.length/2)) { + for (const [file, id, isMain] of foundEntries) { + const score = Math.round(100 * queryLower.length / entry.length); + const result = [ + docNames[file], + titles[file], + id ? "#" + id : "", + null, + score, + filenames[file], + ]; + if (isMain) { + normalResults.push(result); + } else { + nonMainIndexResults.push(result); + } + } + } + } + + // lookup as object + objectTerms.forEach((term) => + normalResults.push(...Search.performObjectSearch(term, objectTerms)) + ); + + // lookup as search terms in fulltext + normalResults.push(...Search.performTermsSearch(searchTerms, excludedTerms)); + + // let the scorer override scores with a custom scoring function + if (Scorer.score) { + normalResults.forEach((item) => (item[4] = Scorer.score(item))); + nonMainIndexResults.forEach((item) => (item[4] = Scorer.score(item))); + } + + // Sort each group of results by score and then alphabetically by name. + normalResults.sort(_orderResultsByScoreThenName); + nonMainIndexResults.sort(_orderResultsByScoreThenName); + + // Combine the result groups in (reverse) order. + // Non-main index entries are typically arbitrary cross-references, + // so display them after other results. + let results = [...nonMainIndexResults, ...normalResults]; + + // remove duplicate search results + // note the reversing of results, so that in the case of duplicates, the highest-scoring entry is kept + let seen = new Set(); + results = results.reverse().reduce((acc, result) => { + let resultStr = result.slice(0, 4).concat([result[5]]).map(v => String(v)).join(','); + if (!seen.has(resultStr)) { + acc.push(result); + seen.add(resultStr); + } + return acc; + }, []); + + return results.reverse(); + }, + + query: (query) => { + const [searchQuery, searchTerms, excludedTerms, highlightTerms, objectTerms] = Search._parseQuery(query); + const results = Search._performSearch(searchQuery, searchTerms, excludedTerms, highlightTerms, objectTerms); + + // for debugging + //Search.lastresults = results.slice(); // a copy + // console.info("search results:", Search.lastresults); + + // print the results + _displayNextItem(results, results.length, searchTerms, highlightTerms); + }, + + /** + * search for object names + */ + performObjectSearch: (object, objectTerms) => { + const filenames = Search._index.filenames; + const docNames = Search._index.docnames; + const objects = Search._index.objects; + const objNames = Search._index.objnames; + const titles = Search._index.titles; + + const results = []; + + const objectSearchCallback = (prefix, match) => { + const name = match[4] + const fullname = (prefix ? prefix + "." : "") + name; + const fullnameLower = fullname.toLowerCase(); + if (fullnameLower.indexOf(object) < 0) return; + + let score = 0; + const parts = fullnameLower.split("."); + + // check for different match types: exact matches of full name or + // "last name" (i.e. last dotted part) + if (fullnameLower === object || parts.slice(-1)[0] === object) + score += Scorer.objNameMatch; + else if (parts.slice(-1)[0].indexOf(object) > -1) + score += Scorer.objPartialMatch; // matches in last name + + const objName = objNames[match[1]][2]; + const title = titles[match[0]]; + + // If more than one term searched for, we require other words to be + // found in the name/title/description + const otherTerms = new Set(objectTerms); + otherTerms.delete(object); + if (otherTerms.size > 0) { + const haystack = `${prefix} ${name} ${objName} ${title}`.toLowerCase(); + if ( + [...otherTerms].some((otherTerm) => haystack.indexOf(otherTerm) < 0) + ) + return; + } + + let anchor = match[3]; + if (anchor === "") anchor = fullname; + else if (anchor === "-") anchor = objNames[match[1]][1] + "-" + fullname; + + const descr = objName + _(", in ") + title; + + // add custom score for some objects according to scorer + if (Scorer.objPrio.hasOwnProperty(match[2])) + score += Scorer.objPrio[match[2]]; + else score += Scorer.objPrioDefault; + + results.push([ + docNames[match[0]], + fullname, + "#" + anchor, + descr, + score, + filenames[match[0]], + ]); + }; + Object.keys(objects).forEach((prefix) => + objects[prefix].forEach((array) => + objectSearchCallback(prefix, array) + ) + ); + return results; + }, + + /** + * search for full-text terms in the index + */ + performTermsSearch: (searchTerms, excludedTerms) => { + // prepare search + const terms = Search._index.terms; + const titleTerms = Search._index.titleterms; + const filenames = Search._index.filenames; + const docNames = Search._index.docnames; + const titles = Search._index.titles; + + const scoreMap = new Map(); + const fileMap = new Map(); + + // perform the search on the required terms + searchTerms.forEach((word) => { + const files = []; + const arr = [ + { files: terms[word], score: Scorer.term }, + { files: titleTerms[word], score: Scorer.title }, + ]; + // add support for partial matches + if (word.length > 2) { + const escapedWord = _escapeRegExp(word); + if (!terms.hasOwnProperty(word)) { + Object.keys(terms).forEach((term) => { + if (term.match(escapedWord)) + arr.push({ files: terms[term], score: Scorer.partialTerm }); + }); + } + if (!titleTerms.hasOwnProperty(word)) { + Object.keys(titleTerms).forEach((term) => { + if (term.match(escapedWord)) + arr.push({ files: titleTerms[term], score: Scorer.partialTitle }); + }); + } + } + + // no match but word was a required one + if (arr.every((record) => record.files === undefined)) return; + + // found search word in contents + arr.forEach((record) => { + if (record.files === undefined) return; + + let recordFiles = record.files; + if (recordFiles.length === undefined) recordFiles = [recordFiles]; + files.push(...recordFiles); + + // set score for the word in each file + recordFiles.forEach((file) => { + if (!scoreMap.has(file)) scoreMap.set(file, {}); + scoreMap.get(file)[word] = record.score; + }); + }); + + // create the mapping + files.forEach((file) => { + if (!fileMap.has(file)) fileMap.set(file, [word]); + else if (fileMap.get(file).indexOf(word) === -1) fileMap.get(file).push(word); + }); + }); + + // now check if the files don't contain excluded terms + const results = []; + for (const [file, wordList] of fileMap) { + // check if all requirements are matched + + // as search terms with length < 3 are discarded + const filteredTermCount = [...searchTerms].filter( + (term) => term.length > 2 + ).length; + if ( + wordList.length !== searchTerms.size && + wordList.length !== filteredTermCount + ) + continue; + + // ensure that none of the excluded terms is in the search result + if ( + [...excludedTerms].some( + (term) => + terms[term] === file || + titleTerms[term] === file || + (terms[term] || []).includes(file) || + (titleTerms[term] || []).includes(file) + ) + ) + break; + + // select one (max) score for the file. + const score = Math.max(...wordList.map((w) => scoreMap.get(file)[w])); + // add result to the result list + results.push([ + docNames[file], + titles[file], + "", + null, + score, + filenames[file], + ]); + } + return results; + }, + + /** + * helper function to return a node containing the + * search summary for a given text. keywords is a list + * of stemmed words. + */ + makeSearchSummary: (htmlText, keywords, anchor) => { + const text = Search.htmlToText(htmlText, anchor); + if (text === "") return null; + + const textLower = text.toLowerCase(); + const actualStartPosition = [...keywords] + .map((k) => textLower.indexOf(k.toLowerCase())) + .filter((i) => i > -1) + .slice(-1)[0]; + const startWithContext = Math.max(actualStartPosition - 120, 0); + + const top = startWithContext === 0 ? "" : "..."; + const tail = startWithContext + 240 < text.length ? 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' + + '' + + _("Hide Search Matches") + + "

" + ) + ); + }, + + /** + * helper function to hide the search marks again + */ + hideSearchWords: () => { + document + .querySelectorAll("#searchbox .highlight-link") + .forEach((el) => el.remove()); + document + .querySelectorAll("span.highlighted") + .forEach((el) => el.classList.remove("highlighted")); + localStorage.removeItem("sphinx_highlight_terms") + }, + + initEscapeListener: () => { + // only install a listener if it is really needed + if (!DOCUMENTATION_OPTIONS.ENABLE_SEARCH_SHORTCUTS) return; + + document.addEventListener("keydown", (event) => { + // bail for input elements + if (BLACKLISTED_KEY_CONTROL_ELEMENTS.has(document.activeElement.tagName)) return; + // bail with special keys + if (event.shiftKey || event.altKey || event.ctrlKey || event.metaKey) return; + if (DOCUMENTATION_OPTIONS.ENABLE_SEARCH_SHORTCUTS && (event.key === "Escape")) { + SphinxHighlight.hideSearchWords(); + event.preventDefault(); + } + }); + }, +}; + +_ready(() => { + /* Do not call highlightSearchWords() when we are on the search page. + * It will highlight words from the *previous* search query. + */ + if (typeof Search === "undefined") SphinxHighlight.highlightSearchWords(); + SphinxHighlight.initEscapeListener(); +}); diff --git a/coverage/index.html b/coverage/index.html new file mode 100644 index 000000000..dfe9036d4 --- /dev/null +++ b/coverage/index.html @@ -0,0 +1,467 @@ + + + + + + + Code Coverage Report — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

Code Coverage Report

+

Code coverage report generated with pytest and Coverage.py.

+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Package

Statments

Branches

Coverage

 Module

Total

Excluded

Covered

Missing

Total

Covered

Partial

Missing

in %

📦pyVHDLModel

1075

25

843

232

540

415

55

125

77.9%

   Association

32

0

22

10

16

12

0

4

70.8%

   Base

178

0

144

34

86

76

0

10

83.3%

   Common

52

0

36

16

22

18

0

4

73.0%

   Concurrent

363

2

211

152

168

114

6

54

61.2%

   DesignUnit

315

0

242

73

142

115

5

27

78.1%

   Exception

137

6

95

42

58

58

0

0

78.5%

   Expression

453

0

366

87

226

224

0

2

86.9%

   IEEE

152

0

152

0

50

50

0

0

100.0%

   Instantiation

43

0

33

10

16

16

0

0

83.1%

   Interface

86

0

57

29

34

34

0

0

75.8%

   Name

92

0

76

16

42

34

0

8

82.1%

   Namespace

84

0

37

47

38

13

3

25

41.0%

   Object

64

0

55

9

28

27

1

1

89.1%

   PSLModel

26

0

21

5

12

12

0

0

86.8%

   Predefined

48

0

47

1

16

15

1

1

96.9%

   Regions

93

0

58

35

54

26

2

28

57.1%

   STD

82

0

82

0

14

14

0

0

100.0%

   Sequential

270

0

158

112

134

100

0

34

63.9%

   Subprogram

68

0

45

23

26

26

0

0

75.5%

   Symbol

220

0

207

13

102

102

0

0

96.0%

   Type

216

0

170

46

102

89

3

13

81.4%

Overall (1 files):

+

Legend

+ + + + + + + + + + + + + + + + + + + + + + + +

%

Coverage Level

≤30%

almost undocumented

≤50%

poorly documented

≤80%

roughly documented

≤90%

well documented

≤100%

excellent documented

+
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/genindex.html b/genindex.html new file mode 100644 index 000000000..6393dedad --- /dev/null +++ b/genindex.html @@ -0,0 +1,9983 @@ + + + + + + Index — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+
    +
    • +
  • Index
    • +
  • +
    • +
+
+
+
+
+ + +

Index

+ +
+ _ + | A + | B + | C + | D + | E + | F + | G + | H + | I + | L + | M + | N + | O + | P + | Q + | R + | S + | T + | U + | V + | W + | X + +
+

_

+ + + +
+ +

A

+ + + +
+ +

B

+ + + +
+ +

C

+ + + +
+ +

D

+ + + +
+ +

E

+ + + +
+ +

F

+ + + +
+ +

G

+ + + +
+ +

H

+ + + +
+ +

I

+ + + +
+ +

L

+ + + +
+ +

M

+ + + +
+ +

N

+ + + +
+ +

O

+ + + +
+ +

P

+ + + +
+ +

Q

+ + + +
+ +

R

+ + + +
+ +

S

+ + + +
+ +

T

+ + + +
+ +

U

+ + + +
+ +

V

+ + + +
+ +

W

+ + + +
+ +

X

+ + + +
+ + + +
+
+
+ +
+ +
+

© Copyright 2016-2024, Patrick Lehmann. + Last updated on 27.09.2024. +

+
+ + Built with Sphinx using a + theme + provided by Read the Docs. + + +
+
+
+
+
+ + + + \ No newline at end of file diff --git a/index.html b/index.html new file mode 100644 index 000000000..d72b521f7 --- /dev/null +++ b/index.html @@ -0,0 +1,288 @@ + + + + + + + The pyVHDLModel Documentation — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ + _images/logo.svg +
+
Sourcecode on GitHub Code license Documentation - Read Now! Documentation License Documentation License
+
PyPI - Tag PyPI - Status PyPI - Python Version
+
GitHub Workflow - Build and Test Status Libraries.io status for latest release Codacy - Quality Codacy - Line Coverage Codecov - Branch Coverage
+
+
+

The pyVHDLModel Documentation

+

An abstract VHDL language model.

+
+

Main Goals

+

This package provides a unified abstract language model for VHDL. Projects reading +from source files can derive own classes and implement additional logic to create +a concrete language model for their tools.

+

Projects consuming pre-processed VHDL data (parsed, analyzed or elaborated) can +build higher level features and services on such a model, while supporting multiple +frontends.

+
+
+

Use Cases

+ +
+
+

News

+
+

Jan. 2023 - Dependency, Hierarchy, Compile Order Analysis

+
+
    +

  • Enhanced analysis of cross references.

    • +

  • Enhanced dependency graphs:

    +
      +

    • Hierarchy graph and toplevel detection

      • +

    • Compile order computation

      • +
    +
    • +

  • Transformation from single module to >15 modules.

    • +

  • Improved code coverage and test cases.

    • +
+
+

Dec. 2022 - Added Documentation Property

+
+
    +

  • GHDL’s is now able to collect and associate (documentation) comments to language +constructs. This enhancement adds a Documentation property to many classes similar to a doc-string in Python.

    • +

  • New -style of symbols merging a Name and a Symbol class.

    • +

  • Finding relations between packages and its bodies, entities and its architectures.

    • +

  • References to libraries, packages and contexts.

    • +

  • Dependency graph for packages, contexts, and entities.

    +
      +

    • Package graph.

      • +

    • Hierarchy graph.

      • +

    • Compile order.

      • +
    +
    • +
+
+

Jul. 2021 - First adoption and enhancements

+
+
    +

  • GHDL’s is the first big adopter with pyGHDL.dom +to generate a network of instantiated classes derived from pyVHDLModel.
    +It uses pyGHDL as a backend (GHDL build as shared object and +loaded into CPython via C-binding API (ctypes).

    • +
+
+

Jun. 2021 - Model and documentation enhancements

+
+
    +

  • Made generic, port, and parameter items a subclass of the matching object classes.

    • +

  • Added missing object representations for language features.

    +
      +

    • Finalized literals, expressions and types.

      • +

    • Added properties to empty placeholder classes.

      • +
    +
    • +

  • Corrected class hierarchy according to LRM.

    • +

  • Enhanced class documentation and cross references.

    • +

  • New documentation chapter for literals and expressions.

    • +

  • Added inheritance diagrams as overviews to documentation sections.

    • +

  • Added condensed code snippets outlining the main interface of a model’s object.

    • +

  • New Single-File GitHub Action workflow (pipeline) including tests, documentation, packaging and publishing.

    • +

  • Added Dependabot configuration file.

    • +

  • Removed 2 dependencies to patched Sphinx extensions (now fixed in Sphinx).

    • +

  • …

    • +
+
+

Jan. 2021 - Documentation enhancements

+
+
    +

  • Enhanced class documentation.

    • +

  • Changed test runner to pytest.

    • +

  • Dependency check and license clearance.
    +See Dependency for details.

    • +
+
+

Dec. 2020 - Split from pyVHDLParser

+
+
    +

  • pyVHDLModel was split from pyVHDLParser (v0.6.0) as an independent Python package.

    • +
+
+
+

Contributors

+ +
+
+

License

+

This Python package (source code) is licensed under Apache License 2.0.
+The accompanying documentation is licensed under Creative Commons - Attribution 4.0 (CC-BY 4.0).

+

This document was generated on |docdate|.

+
+
+
+
+
+
+
+
+
+
+
+
+ + +
+
+
+ +
+ +
+

© Copyright 2016-2024, Patrick Lehmann. + Last updated on 27.09.2024. +

+
+ + Built with Sphinx using a + theme + provided by Read the Docs. + + +
+
+
+
+
+ + + + \ No newline at end of file diff --git a/objects.inv b/objects.inv new file mode 100644 index 000000000..93f46a12b Binary files /dev/null and b/objects.inv differ diff --git a/py-modindex.html b/py-modindex.html new file mode 100644 index 000000000..7679fe6a8 --- /dev/null +++ b/py-modindex.html @@ -0,0 +1,325 @@ + + + + + + Python Module Index — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+
    +
    • +
  • Python Module Index
    • +
  • +
    • +
+
+
+
+
+ + +

Python Module Index

+ +
+ a | + b | + c | + d | + e | + i | + n | + o | + p | + r | + s | + t +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
 
+ a
+ pyVHDLModel.Association +
 
+ b
+ pyVHDLModel.Base +
 
+ c
+ pyVHDLModel.Common +
+ pyVHDLModel.Concurrent +
 
+ d
+ pyVHDLModel.Declaration +
+ pyVHDLModel.DesignUnit +
 
+ e
+ pyVHDLModel.Exception +
+ pyVHDLModel.Expression +
 
+ i
+ pyVHDLModel.IEEE +
+ pyVHDLModel.Instantiation +
+ pyVHDLModel.Interface +
 
+ n
+ pyVHDLModel.Name +
+ pyVHDLModel.Namespace +
 
+ o
+ pyVHDLModel.Object +
 
+ p
+ pyVHDLModel +
+ pyVHDLModel.Predefined +
+ pyVHDLModel.PSLModel +
 
+ r
+ pyVHDLModel.Regions +
 
+ s
+ pyVHDLModel.Sequential +
+ pyVHDLModel.STD +
+ pyVHDLModel.Subprogram +
+ pyVHDLModel.Symbol +
 
+ t
+ pyVHDLModel.Type +
+ + +
+
+
+ +
+ +
+

© Copyright 2016-2024, Patrick Lehmann. + Last updated on 27.09.2024. +

+
+ + Built with Sphinx using a + theme + provided by Read the Docs. + + +
+
+
+
+
+ + + + \ No newline at end of file diff --git a/pyVHDLModel/pyVHDLModel.Association.html b/pyVHDLModel/pyVHDLModel.Association.html new file mode 100644 index 000000000..35c8ec9ba --- /dev/null +++ b/pyVHDLModel/pyVHDLModel.Association.html @@ -0,0 +1,592 @@ + + + + + + + pyVHDLModel.Association — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

pyVHDLModel.Association

+

This module contains parts of an abstract document language model for VHDL.

+

Associations are used in generic maps, port maps and parameter maps.

+

Classes

+ +
+

Classes

+
+
+class pyVHDLModel.Association.AssociationItem(actual, formal=None)[source]
+

A base-class for all association items.

+

Inheritance

+
+

Inheritance diagram of AssociationItem

+
+
Parameters:
+
+
+
+
+
+__init__(actual, formal=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Association.GenericAssociationItem(actual, formal=None)[source]
+

A base-class for all generic association items used in generic map aspects.

+

Inheritance

+
+

Inheritance diagram of GenericAssociationItem

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(actual, formal=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Association.PortAssociationItem(actual, formal=None)[source]
+

A base-class for all port association items used in port map aspects.

+

Inheritance

+
+

Inheritance diagram of PortAssociationItem

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(actual, formal=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Association.ParameterAssociationItem(actual, formal=None)[source]
+

A base-class for all parameter association items used in parameter map aspects.

+

Inheritance

+
+

Inheritance diagram of ParameterAssociationItem

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(actual, formal=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/pyVHDLModel/pyVHDLModel.Base.html b/pyVHDLModel/pyVHDLModel.Base.html new file mode 100644 index 000000000..3c14838c4 --- /dev/null +++ b/pyVHDLModel/pyVHDLModel.Base.html @@ -0,0 +1,1658 @@ + + + + + + + pyVHDLModel.Base — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

pyVHDLModel.Base

+

This module contains parts of an abstract document language model for VHDL.

+

Base-classes for the VHDL language model.

+

Variables

+ +

Classes

+
    +

  • Direction: +An enumeration representing a direction in a range (to or downto).

    • +

  • Mode: +A Mode is an enumeration. It represents the direction of data exchange (in, out, …) for objects in

    • +

  • ModelEntity: +ModelEntity is the base-class for all classes in the VHDL language model, except for mixin classes (see multiple

    • +

  • NamedEntityMixin: +A NamedEntityMixin is a mixin class for all VHDL entities that have identifiers.

    • +

  • MultipleNamedEntityMixin: +A MultipleNamedEntityMixin is a mixin class for all VHDL entities that declare multiple instances at once by

    • +

  • LabeledEntityMixin: +A LabeledEntityMixin is a mixin class for all VHDL entities that can have labels.

    • +

  • DocumentedEntityMixin: +A DocumentedEntityMixin is a mixin class for all VHDL entities that can have an associated documentation.

    • +

  • ConditionalMixin: +A ConditionalMixin is a mixin-class for all statements with a condition.

    • +

  • BranchMixin: +A BranchMixin is a mixin-class for all statements with branches.

    • +

  • ConditionalBranchMixin: +A BaseBranch is a mixin-class for all branch statements with a condition.

    • +

  • IfBranchMixin: +A BaseIfBranch is a mixin-class for all if-branches.

    • +

  • ElsifBranchMixin: +A BaseElsifBranch is a mixin-class for all elsif-branches.

    • +

  • ElseBranchMixin: +A BaseElseBranch is a mixin-class for all else-branches.

    • +

  • ReportStatementMixin: +A MixinReportStatement is a mixin-class for all report and assert statements.

    • +

  • AssertStatementMixin: +A MixinAssertStatement is a mixin-class for all assert statements.

    • +

  • BaseChoice: +A Choice is a base-class for all choices.

    • +

  • BaseCase: +A Case is a base-class for all cases.

    • +

  • Range: +ModelEntity is the base-class for all classes in the VHDL language model, except for mixin classes (see multiple

    • +

  • WaveformElement: +ModelEntity is the base-class for all classes in the VHDL language model, except for mixin classes (see multiple

    • +
+
+

Variables

+
+
+pyVHDLModel.Base.ExpressionUnion
+
typing.Union[ForwardRef('BaseExpression'), ForwardRef('QualifiedExpression'), ForwardRef('FunctionCall'), ForwardRef('TypeConversion'), ForwardRef('Literal')]
+
+
+

alias of BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal

+
+ +
+

Classes

+
+
+class pyVHDLModel.Base.Direction(value, names=<not given>, *values, module=None, qualname=None, type=None, start=1, boundary=None)[source]
+

An enumeration representing a direction in a range (to or downto).

+

Inheritance

+
+

Inheritance diagram of Direction

+
+
+To = 0
+

Ascending direction

+
+ +
+
+DownTo = 1
+

Descending direction

+
+ +
+
+__str__()[source]
+

Formats the direction to to or downto.

+
+
Return type:
+

str

+
+
Returns:
+

Formatted direction.

+
+
+
+ +
+ +
+
+class pyVHDLModel.Base.Mode(value, names=<not given>, *values, module=None, qualname=None, type=None, start=1, boundary=None)[source]
+

A Mode is an enumeration. It represents the direction of data exchange (in, out, …) for objects in +generic, port or parameter lists.

+

In case no mode is defined, Default is used, so the mode is inferred from context.

+

Inheritance

+
+

Inheritance diagram of Mode

+
+
+Default = 0
+

Mode not defined, thus it’s context dependent.

+
+ +
+
+In = 1
+

Input

+
+ +
+
+Out = 2
+

Output

+
+ +
+
+InOut = 3
+

Bi-directional

+
+ +
+
+Buffer = 4
+

Buffered output

+
+ +
+
+Linkage = 5
+

undocumented

+
+ +
+
+__str__()[source]
+

Formats the direction.

+
+
Return type:
+

str

+
+
Returns:
+

Formatted direction.

+
+
+
+ +
+ +
+
+class pyVHDLModel.Base.ModelEntity(parent=None)[source]
+

ModelEntity is the base-class for all classes in the VHDL language model, except for mixin classes (see multiple +inheritance) and enumerations.

+

Each entity in this model has a reference to its parent entity. Therefore, a protected variable _parent is +available and a readonly property Parent.

+

Inheritance

+
+

Inheritance diagram of ModelEntity

+
+
Parameters:
+

parent (ModelEntity | None)

+
+
+
+
+__init__(parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+

parent (Optional[ModelEntity]) – The parent model entity of this entity.

+
+
Return type:
+

None

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+ +
+
+class pyVHDLModel.Base.NamedEntityMixin(identifier)[source]
+

A NamedEntityMixin is a mixin class for all VHDL entities that have identifiers.

+

Protected variables _identifier and _normalizedIdentifier are available to derived classes as well as +two readonly properties Identifier and NormalizedIdentifier for public access.

+

Inheritance

+
+

Inheritance diagram of NamedEntityMixin

+
+
Parameters:
+

identifier (str)

+
+
+
+
+__init__(identifier)[source]
+

Initializes a named entity.

+
+
Parameters:
+

identifier (str) – Identifier (name) of the model entity.

+
+
Return type:
+

None

+
+
+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+ +
+
+class pyVHDLModel.Base.MultipleNamedEntityMixin(identifiers)[source]
+

A MultipleNamedEntityMixin is a mixin class for all VHDL entities that declare multiple instances at once by +defining multiple identifiers.

+

Protected variables _identifiers and _normalizedIdentifiers are available to derived classes as well +as two readonly properties Identifiers and NormalizedIdentifiers for public access.

+

Inheritance

+
+

Inheritance diagram of MultipleNamedEntityMixin

+
+
Parameters:
+

identifiers (Iterable[str])

+
+
+
+
+__init__(identifiers)[source]
+

Initializes a multiple-named entity.

+
+
Parameters:
+

identifiers (Iterable[str]) – Sequence of identifiers (names) of the model entity.

+
+
Return type:
+

None

+
+
+
+ +
+
+_identifiers: Tuple[str]
+

A list of identifiers.

+
+ +
+
+_normalizedIdentifiers: Tuple[str]
+

A list of normalized (lower case) identifiers.

+
+ +
+
+property Identifiers: Tuple[str]
+

Returns a model entity’s tuple of identifiers (names).

+
+
Returns:
+

Tuple of identifiers.

+
+
+
+ +
+
+property NormalizedIdentifiers: Tuple[str]
+

Returns a model entity’s tuple of normalized identifiers (lower case names).

+
+
Returns:
+

Tuple of normalized identifiers.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+ +
+
+class pyVHDLModel.Base.LabeledEntityMixin(label)[source]
+

A LabeledEntityMixin is a mixin class for all VHDL entities that can have labels.

+

protected variables _label and _normalizedLabel are available to derived classes as well as two +readonly properties Label and NormalizedLabel for public access.

+

Inheritance

+
+

Inheritance diagram of LabeledEntityMixin

+
+
Parameters:
+

label (str | None)

+
+
+
+
+__init__(label)[source]
+

Initializes a labeled entity.

+
+
Parameters:
+

label (Optional[str]) – Label of the model entity.

+
+
Return type:
+

None

+
+
+
+ +
+
+_label: Optional[str]
+

The label of a model entity.

+
+ +
+
+_normalizedLabel: Optional[str]
+

The normalized (lower case) label of a model entity.

+
+ +
+
+property Label: str | None
+

Returns a model entity’s label.

+
+
Returns:
+

Label of a model entity.

+
+
+
+ +
+
+property NormalizedLabel: str | None
+

Returns a model entity’s normalized (lower case) label.

+
+
Returns:
+

Normalized label of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+ +
+
+class pyVHDLModel.Base.DocumentedEntityMixin(documentation)[source]
+

A DocumentedEntityMixin is a mixin class for all VHDL entities that can have an associated documentation.

+

A protected variable _documentation is available to derived classes as well as a readonly property +Documentation for public access.

+

Inheritance

+
+

Inheritance diagram of DocumentedEntityMixin

+
+
Parameters:
+

documentation (str | None)

+
+
+
+
+__init__(documentation)[source]
+

Initializes a documented entity.

+
+
Parameters:
+

documentation (Optional[str]) – Documentation of a model entity.

+
+
Return type:
+

None

+
+
+
+ +
+
+_documentation: Optional[str]
+

The associated documentation of a model entity.

+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+ +
+
+class pyVHDLModel.Base.ConditionalMixin(condition=None)[source]
+

A ConditionalMixin is a mixin-class for all statements with a condition.

+

Inheritance

+
+

Inheritance diagram of ConditionalMixin

+
+
Parameters:
+

condition (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal | None)

+
+
+
+
+__init__(condition=None)[source]
+

Initializes a statement with a condition.

+

When the condition is not None, the condition’s parent reference is set to this statement.

+
+
Parameters:
+

condition (Union[BaseExpression, QualifiedExpression, FunctionCall, TypeConversion, Literal, None]) – The expression representing the condition.

+
+
Return type:
+

None

+
+
+
+ +
+
+property Condition: BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal
+

Read-only property to access the condition of a statement (_condition).

+
+
Returns:
+

The expression representing the condition of a statement.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+ +
+
+class pyVHDLModel.Base.BranchMixin[source]
+

A BranchMixin is a mixin-class for all statements with branches.

+

Inheritance

+
+

Inheritance diagram of BranchMixin

+
+
+
+
+__init__()[source]
+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+ +
+
+class pyVHDLModel.Base.ConditionalBranchMixin(condition)[source]
+

A BaseBranch is a mixin-class for all branch statements with a condition.

+

Inheritance

+
+

Inheritance diagram of ConditionalBranchMixin

+
+
Parameters:
+

condition (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal)

+
+
+
+
+__init__(condition)[source]
+

Initializes a statement with a condition.

+

When the condition is not None, the condition’s parent reference is set to this statement.

+
+
Parameters:
+

condition (Union[BaseExpression, QualifiedExpression, FunctionCall, TypeConversion, Literal]) – The expression representing the condition.

+
+
Return type:
+

None

+
+
+
+ +
+
+property Condition: BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal
+

Read-only property to access the condition of a statement (_condition).

+
+
Returns:
+

The expression representing the condition of a statement.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+ +
+
+class pyVHDLModel.Base.IfBranchMixin(condition)[source]
+

A BaseIfBranch is a mixin-class for all if-branches.

+

Inheritance

+
+

Inheritance diagram of IfBranchMixin

+
+
Parameters:
+

condition (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal)

+
+
+
+
+property Condition: BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal
+

Read-only property to access the condition of a statement (_condition).

+
+
Returns:
+

The expression representing the condition of a statement.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+__init__(condition)
+

Initializes a statement with a condition.

+

When the condition is not None, the condition’s parent reference is set to this statement.

+
+
Parameters:
+

condition (Union[BaseExpression, QualifiedExpression, FunctionCall, TypeConversion, Literal]) – The expression representing the condition.

+
+
Return type:
+

None

+
+
+
+ +
+ +
+
+class pyVHDLModel.Base.ElsifBranchMixin(condition)[source]
+

A BaseElsifBranch is a mixin-class for all elsif-branches.

+

Inheritance

+
+

Inheritance diagram of ElsifBranchMixin

+
+
Parameters:
+

condition (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal)

+
+
+
+
+property Condition: BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal
+

Read-only property to access the condition of a statement (_condition).

+
+
Returns:
+

The expression representing the condition of a statement.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+__init__(condition)
+

Initializes a statement with a condition.

+

When the condition is not None, the condition’s parent reference is set to this statement.

+
+
Parameters:
+

condition (Union[BaseExpression, QualifiedExpression, FunctionCall, TypeConversion, Literal]) – The expression representing the condition.

+
+
Return type:
+

None

+
+
+
+ +
+ +
+
+class pyVHDLModel.Base.ElseBranchMixin[source]
+

A BaseElseBranch is a mixin-class for all else-branches.

+

Inheritance

+
+

Inheritance diagram of ElseBranchMixin

+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+__init__()
+
+
Return type:
+

None

+
+
+
+ +
+ +
+
+class pyVHDLModel.Base.ReportStatementMixin(message=None, severity=None)[source]
+

A MixinReportStatement is a mixin-class for all report and assert statements.

+

Inheritance

+
+

Inheritance diagram of ReportStatementMixin

+
+
Parameters:
+
+
+
+
+
+__init__(message=None, severity=None)[source]
+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+ +
+
+class pyVHDLModel.Base.AssertStatementMixin(condition, message=None, severity=None)[source]
+

A MixinAssertStatement is a mixin-class for all assert statements.

+

Inheritance

+
+

Inheritance diagram of AssertStatementMixin

+
+
Parameters:
+
+
+
+
+
+__init__(condition, message=None, severity=None)[source]
+

Initializes a statement with a condition.

+

When the condition is not None, the condition’s parent reference is set to this statement.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+property Condition: BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal
+

Read-only property to access the condition of a statement (_condition).

+
+
Returns:
+

The expression representing the condition of a statement.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+ +
+
+class pyVHDLModel.Base.BaseChoice(parent=None)[source]
+

A Choice is a base-class for all choices.

+

Inheritance

+
+

Inheritance diagram of BaseChoice

+
+
Parameters:
+

parent (ModelEntity | None)

+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+

parent (Optional[ModelEntity]) – The parent model entity of this entity.

+
+
Return type:
+

None

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Base.BaseCase(parent=None)[source]
+

A Case is a base-class for all cases.

+

Inheritance

+
+

Inheritance diagram of BaseCase

+
+
Parameters:
+

parent (ModelEntity | None)

+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+

parent (Optional[ModelEntity]) – The parent model entity of this entity.

+
+
Return type:
+

None

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Base.Range(leftBound, rightBound, direction, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of Range

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(leftBound, rightBound, direction, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+ +
+
+class pyVHDLModel.Base.WaveformElement(expression, after=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of WaveformElement

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+__init__(expression, after=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+ +
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/pyVHDLModel/pyVHDLModel.Common.html b/pyVHDLModel/pyVHDLModel.Common.html new file mode 100644 index 000000000..72abe55f1 --- /dev/null +++ b/pyVHDLModel/pyVHDLModel.Common.html @@ -0,0 +1,565 @@ + + + + + + + pyVHDLModel.Common — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

pyVHDLModel.Common

+

This module contains parts of an abstract document language model for VHDL.

+

Common definitions and Mixins are used by many classes in the model as base-classes.

+

Classes

+ +
+

Classes

+
+
+class pyVHDLModel.Common.Statement(label=None, parent=None)[source]
+

A Statement is a base-class for all statements.

+

Inheritance

+
+

Inheritance diagram of Statement

+
+
Parameters:
+

label (str | None)

+
+
+
+
+__init__(label=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
    +

  • parent – The parent model entity of this entity.

    • +

  • label (str | None)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+_label: Optional[str]
+

The label of a model entity.

+
+ +
+
+_normalizedLabel: Optional[str]
+

The normalized (lower case) label of a model entity.

+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Label: str | None
+

Returns a model entity’s label.

+
+
Returns:
+

Label of a model entity.

+
+
+
+ +
+
+property NormalizedLabel: str | None
+

Returns a model entity’s normalized (lower case) label.

+
+
Returns:
+

Normalized label of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Common.ProcedureCallMixin(procedureName, parameterMappings=None)[source]
+

Inheritance

+
+

Inheritance diagram of ProcedureCallMixin

+
+
Parameters:
+
+
+
+
+
+__init__(procedureName, parameterMappings=None)[source]
+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+ +
+
+class pyVHDLModel.Common.AssignmentMixin(target)[source]
+

A mixin-class for all assignment statements.

+

Inheritance

+
+

Inheritance diagram of AssignmentMixin

+
+
Parameters:
+

target (Symbol)

+
+
+
+
+__init__(target)[source]
+
+
Parameters:
+

target (Symbol)

+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+ +
+
+class pyVHDLModel.Common.SignalAssignmentMixin(target)[source]
+

A mixin-class for all signal assignment statements.

+

Inheritance

+
+

Inheritance diagram of SignalAssignmentMixin

+
+
Parameters:
+

target (Symbol)

+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+__init__(target)
+
+
Parameters:
+

target (Symbol)

+
+
Return type:
+

None

+
+
+
+ +
+ +
+
+class pyVHDLModel.Common.VariableAssignmentMixin(target, expression)[source]
+

A mixin-class for all variable assignment statements.

+

Inheritance

+
+

Inheritance diagram of VariableAssignmentMixin

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+__init__(target, expression)[source]
+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+ +
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/pyVHDLModel/pyVHDLModel.Concurrent.html b/pyVHDLModel/pyVHDLModel.Concurrent.html new file mode 100644 index 000000000..fa0d2521a --- /dev/null +++ b/pyVHDLModel/pyVHDLModel.Concurrent.html @@ -0,0 +1,4584 @@ + + + + + + + pyVHDLModel.Concurrent — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

pyVHDLModel.Concurrent

+

This module contains parts of an abstract document language model for VHDL.

+

Concurrent defines all concurrent statements used in entities, architectures, generates and block statements.

+

Classes

+ +
+

Classes

+
+
+class pyVHDLModel.Concurrent.ConcurrentStatement(label=None, parent=None)[source]
+

A base-class for all concurrent statements.

+

Inheritance

+
+

Inheritance diagram of ConcurrentStatement

+
+
Parameters:
+

label (str | None)

+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Label: str | None
+

Returns a model entity’s label.

+
+
Returns:
+

Label of a model entity.

+
+
+
+ +
+
+property NormalizedLabel: str | None
+

Returns a model entity’s normalized (lower case) label.

+
+
Returns:
+

Normalized label of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(label=None, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
    +

  • parent – The parent model entity of this entity.

    • +

  • label (str | None)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+_label: Optional[str]
+

The label of a model entity.

+
+ +
+
+_normalizedLabel: Optional[str]
+

The normalized (lower case) label of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Concurrent.ConcurrentStatementsMixin(statements=None)[source]
+

A mixin-class for all language constructs supporting concurrent statements.

+
+

See also

+
+

Todo

+

concurrent declaration region

+
+
+

Inheritance

+
+

Inheritance diagram of ConcurrentStatementsMixin

+
+
Parameters:
+

statements (Iterable[ConcurrentStatement] | None)

+
+
+
+
+__init__(statements=None)[source]
+
+
Parameters:
+

statements (Iterable[ConcurrentStatement] | None)

+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+ +
+
+class pyVHDLModel.Concurrent.Instantiation(label, genericAssociations=None, portAssociations=None, parent=None)[source]
+

A base-class for all (component) instantiations.

+

Inheritance

+
+

Inheritance diagram of Instantiation

+
+
Parameters:
+
+
+
+
+
+__init__(label, genericAssociations=None, portAssociations=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Label: str | None
+

Returns a model entity’s label.

+
+
Returns:
+

Label of a model entity.

+
+
+
+ +
+
+property NormalizedLabel: str | None
+

Returns a model entity’s normalized (lower case) label.

+
+
Returns:
+

Normalized label of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_label: Optional[str]
+

The label of a model entity.

+
+ +
+
+_normalizedLabel: Optional[str]
+

The normalized (lower case) label of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Concurrent.ComponentInstantiation(label, componentSymbol, genericAssociations=None, portAssociations=None, parent=None)[source]
+

Represents a component instantiation by referring to a component name.

+
+

Example

+
inst : component Counter;
+
+
+
+

Inheritance

+
+

Inheritance diagram of ComponentInstantiation

+
+
Parameters:
+
+
+
+
+
+__init__(label, componentSymbol, genericAssociations=None, portAssociations=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Label: str | None
+

Returns a model entity’s label.

+
+
Returns:
+

Label of a model entity.

+
+
+
+ +
+
+property NormalizedLabel: str | None
+

Returns a model entity’s normalized (lower case) label.

+
+
Returns:
+

Normalized label of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_label: Optional[str]
+

The label of a model entity.

+
+ +
+
+_normalizedLabel: Optional[str]
+

The normalized (lower case) label of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Concurrent.EntityInstantiation(label, entitySymbol, architectureSymbol=None, genericAssociations=None, portAssociations=None, parent=None)[source]
+

Represents an entity instantiation by referring to an entity name with optional architecture name.

+
+

Example

+
inst : entity work. Counter;
+
+
+
+

Inheritance

+
+

Inheritance diagram of EntityInstantiation

+
+
Parameters:
+
+
+
+
+
+__init__(label, entitySymbol, architectureSymbol=None, genericAssociations=None, portAssociations=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Label: str | None
+

Returns a model entity’s label.

+
+
Returns:
+

Label of a model entity.

+
+
+
+ +
+
+property NormalizedLabel: str | None
+

Returns a model entity’s normalized (lower case) label.

+
+
Returns:
+

Normalized label of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_label: Optional[str]
+

The label of a model entity.

+
+ +
+
+_normalizedLabel: Optional[str]
+

The normalized (lower case) label of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Concurrent.ConfigurationInstantiation(label, configurationSymbol, genericAssociations=None, portAssociations=None, parent=None)[source]
+

Represents a configuration instantiation by referring to a configuration name.

+
+

Example

+
inst : configuration Counter;
+
+
+
+

Inheritance

+
+

Inheritance diagram of ConfigurationInstantiation

+
+
Parameters:
+
+
+
+
+
+__init__(label, configurationSymbol, genericAssociations=None, portAssociations=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Label: str | None
+

Returns a model entity’s label.

+
+
Returns:
+

Label of a model entity.

+
+
+
+ +
+
+property NormalizedLabel: str | None
+

Returns a model entity’s normalized (lower case) label.

+
+
Returns:
+

Normalized label of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_label: Optional[str]
+

The label of a model entity.

+
+ +
+
+_normalizedLabel: Optional[str]
+

The normalized (lower case) label of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Concurrent.ProcessStatement(label=None, declaredItems=None, statements=None, sensitivityList=None, documentation=None, parent=None)[source]
+

Represents a process statement with sensitivity list, sequential declaration region and sequential statements.

+
+

Example

+
proc: process(Clock)
+  -- sequential declarations
+begin
+  -- sequential statements
+end process;
+
+
+
+

Inheritance

+
+

Inheritance diagram of ProcessStatement

+
+
Parameters:
+
+
+
+
+
+__init__(label=None, declaredItems=None, statements=None, sensitivityList=None, documentation=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+_documentation: Optional[str]
+

The associated documentation of a model entity.

+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Label: str | None
+

Returns a model entity’s label.

+
+
Returns:
+

Label of a model entity.

+
+
+
+ +
+
+property NormalizedLabel: str | None
+

Returns a model entity’s normalized (lower case) label.

+
+
Returns:
+

Normalized label of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+property Statements: List[SequentialStatement]
+

Read-only property to access the list of sequential statements (_statements).

+
+
Returns:
+

A list of sequential statements.

+
+
+
+ +
+
+_label: Optional[str]
+

The label of a model entity.

+
+ +
+
+_normalizedLabel: Optional[str]
+

The normalized (lower case) label of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Concurrent.ConcurrentProcedureCall(label, procedureName, parameterMappings=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of ConcurrentProcedureCall

+
+
Parameters:
+
+
+
+
+
+__init__(label, procedureName, parameterMappings=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Label: str | None
+

Returns a model entity’s label.

+
+
Returns:
+

Label of a model entity.

+
+
+
+ +
+
+property NormalizedLabel: str | None
+

Returns a model entity’s normalized (lower case) label.

+
+
Returns:
+

Normalized label of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_label: Nullable[str]
+

The label of a model entity.

+
+ +
+
+_normalizedLabel: Nullable[str]
+

The normalized (lower case) label of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Concurrent.ConcurrentBlockStatement(label, portItems=None, declaredItems=None, statements=None, documentation=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of ConcurrentBlockStatement

+
+
Parameters:
+
+
+
+
+
+__init__(label, portItems=None, declaredItems=None, statements=None, documentation=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+_label: Nullable[str]
+

The label of a model entity.

+
+ +
+
+_normalizedLabel: Nullable[str]
+

The normalized (lower case) label of a model entity.

+
+ +
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+IndexDeclaredItems()
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+
+property Label: str | None
+

Returns a model entity’s label.

+
+
Returns:
+

Label of a model entity.

+
+
+
+ +
+
+property NormalizedLabel: str | None
+

Returns a model entity’s normalized (lower case) label.

+
+
Returns:
+

Normalized label of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Concurrent.GenerateBranch(declaredItems=None, statements=None, alternativeLabel=None, parent=None)[source]
+

A base-class for all branches in a generate statements.

+
+

See also

+ +
+

Inheritance

+
+

Inheritance diagram of GenerateBranch

+
+
Parameters:
+
+
+
+
+
+__init__(declaredItems=None, statements=None, alternativeLabel=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+IndexDeclaredItems()
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Concurrent.IfGenerateBranch(condition, declaredItems=None, statements=None, alternativeLabel=None, parent=None)[source]
+

Represents if-generate branch in a generate statement with a concurrent declaration region and concurrent statements.

+
+

Example

+
gen: if condition generate
+  -- concurrent declarations
+begin
+  -- concurrent statements
+elsif condition generate
+  -- ...
+else generate
+  -- ...
+end generate;
+
+
+
+

Inheritance

+
+

Inheritance diagram of IfGenerateBranch

+
+
Parameters:
+
+
+
+
+
+__init__(condition, declaredItems=None, statements=None, alternativeLabel=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+property Condition: BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal
+

Read-only property to access the condition of a statement (_condition).

+
+
Returns:
+

The expression representing the condition of a statement.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+IndexDeclaredItems()
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+ +
+
+class pyVHDLModel.Concurrent.ElsifGenerateBranch(condition, declaredItems=None, statements=None, alternativeLabel=None, parent=None)[source]
+

Represents elsif-generate branch in a generate statement with a concurrent declaration region and concurrent statements.

+
+

Example

+
gen: if condition generate
+  -- ...
+elsif condition generate
+  -- concurrent declarations
+begin
+  -- concurrent statements
+else generate
+  -- ...
+end generate;
+
+
+
+

Inheritance

+
+

Inheritance diagram of ElsifGenerateBranch

+
+
Parameters:
+
+
+
+
+
+__init__(condition, declaredItems=None, statements=None, alternativeLabel=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+property Condition: BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal
+

Read-only property to access the condition of a statement (_condition).

+
+
Returns:
+

The expression representing the condition of a statement.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+IndexDeclaredItems()
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+ +
+
+class pyVHDLModel.Concurrent.ElseGenerateBranch(declaredItems=None, statements=None, alternativeLabel=None, parent=None)[source]
+

Represents else-generate branch in a generate statement with a concurrent declaration region and concurrent statements.

+
+

Example

+
gen: if condition generate
+  -- ...
+elsif condition generate
+  -- ...
+else generate
+  -- concurrent declarations
+begin
+  -- concurrent statements
+end generate;
+
+
+
+

Inheritance

+
+

Inheritance diagram of ElseGenerateBranch

+
+
Parameters:
+
+
+
+
+
+__init__(declaredItems=None, statements=None, alternativeLabel=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+IndexDeclaredItems()
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+ +
+
+class pyVHDLModel.Concurrent.GenerateStatement(label=None, parent=None)[source]
+

A base-class for all generate statements.

+
+

See also

+ +
+

Inheritance

+
+

Inheritance diagram of GenerateStatement

+
+
Parameters:
+
+
+
+
+
+__init__(label=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
    +

  • parent (ModelEntity) – The parent model entity of this entity.

    • +

  • label (str | None)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Label: str | None
+

Returns a model entity’s label.

+
+
Returns:
+

Label of a model entity.

+
+
+
+ +
+
+property NormalizedLabel: str | None
+

Returns a model entity’s normalized (lower case) label.

+
+
Returns:
+

Normalized label of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_label: Optional[str]
+

The label of a model entity.

+
+ +
+
+_normalizedLabel: Optional[str]
+

The normalized (lower case) label of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Concurrent.IfGenerateStatement(label, ifBranch, elsifBranches=None, elseBranch=None, parent=None)[source]
+

Represents an if…generate statement.

+
+

Example

+
gen: if condition generate
+  -- ...
+elsif condition generate
+  -- ...
+else generate
+  -- ...
+end generate;
+
+
+
+
+

See also

+ +
+

Inheritance

+
+

Inheritance diagram of IfGenerateStatement

+
+
Parameters:
+
+
+
+
+
+__init__(label, ifBranch, elsifBranches=None, elseBranch=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Label: str | None
+

Returns a model entity’s label.

+
+
Returns:
+

Label of a model entity.

+
+
+
+ +
+
+property NormalizedLabel: str | None
+

Returns a model entity’s normalized (lower case) label.

+
+
Returns:
+

Normalized label of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_label: Optional[str]
+

The label of a model entity.

+
+ +
+
+_normalizedLabel: Optional[str]
+

The normalized (lower case) label of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Concurrent.ConcurrentChoice(parent=None)[source]
+

A base-class for all concurrent choices (in case…generate statements).

+

Inheritance

+
+

Inheritance diagram of ConcurrentChoice

+
+
Parameters:
+

parent (ModelEntity | None)

+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+

parent (Optional[ModelEntity]) – The parent model entity of this entity.

+
+
Return type:
+

None

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Concurrent.IndexedGenerateChoice(expression, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of IndexedGenerateChoice

+
+
Parameters:
+
+
+
+
+
+__init__(expression, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Concurrent.RangedGenerateChoice(rng, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of RangedGenerateChoice

+
+
Parameters:
+
+
+
+
+
+__init__(rng, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
    +

  • parent (ModelEntity) – The parent model entity of this entity.

    • +

  • rng (Range)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Concurrent.ConcurrentCase(declaredItems=None, statements=None, alternativeLabel=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of ConcurrentCase

+
+
Parameters:
+
+
+
+
+
+__init__(declaredItems=None, statements=None, alternativeLabel=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+_label: Nullable[str]
+

The label of a model entity.

+
+ +
+
+_normalizedLabel: Nullable[str]
+

The normalized (lower case) label of a model entity.

+
+ +
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+IndexDeclaredItems()
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+
+property Label: str | None
+

Returns a model entity’s label.

+
+
Returns:
+

Label of a model entity.

+
+
+
+ +
+
+property NormalizedLabel: str | None
+

Returns a model entity’s normalized (lower case) label.

+
+
Returns:
+

Normalized label of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Concurrent.GenerateCase(choices, declaredItems=None, statements=None, alternativeLabel=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of GenerateCase

+
+
Parameters:
+
+
+
+
+
+__init__(choices, declaredItems=None, statements=None, alternativeLabel=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+IndexDeclaredItems()
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+
+property Label: str | None
+

Returns a model entity’s label.

+
+
Returns:
+

Label of a model entity.

+
+
+
+ +
+
+property NormalizedLabel: str | None
+

Returns a model entity’s normalized (lower case) label.

+
+
Returns:
+

Normalized label of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_label: Nullable[str]
+

The label of a model entity.

+
+ +
+
+_normalizedLabel: Nullable[str]
+

The normalized (lower case) label of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+ +
+
+class pyVHDLModel.Concurrent.OthersGenerateCase(declaredItems=None, statements=None, alternativeLabel=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of OthersGenerateCase

+
+
Parameters:
+
+
+
+
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+IndexDeclaredItems()
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+
+property Label: str | None
+

Returns a model entity’s label.

+
+
Returns:
+

Label of a model entity.

+
+
+
+ +
+
+property NormalizedLabel: str | None
+

Returns a model entity’s normalized (lower case) label.

+
+
Returns:
+

Normalized label of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(declaredItems=None, statements=None, alternativeLabel=None, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_label: Nullable[str]
+

The label of a model entity.

+
+ +
+
+_normalizedLabel: Nullable[str]
+

The normalized (lower case) label of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+ +
+
+class pyVHDLModel.Concurrent.CaseGenerateStatement(label, expression, cases, parent=None)[source]
+

Represents a case…generate statement.

+
+

Example

+
gen: case selector generate
+  case choice1 =>
+    -- ...
+  case choice2 =>
+    -- ...
+  case others =>
+    -- ...
+end generate;
+
+
+
+

Inheritance

+
+

Inheritance diagram of CaseGenerateStatement

+
+
Parameters:
+
+
+
+
+
+__init__(label, expression, cases, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Label: str | None
+

Returns a model entity’s label.

+
+
Returns:
+

Label of a model entity.

+
+
+
+ +
+
+property NormalizedLabel: str | None
+

Returns a model entity’s normalized (lower case) label.

+
+
Returns:
+

Normalized label of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_label: Optional[str]
+

The label of a model entity.

+
+ +
+
+_normalizedLabel: Optional[str]
+

The normalized (lower case) label of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Concurrent.ForGenerateStatement(label, loopIndex, rng, declaredItems=None, statements=None, parent=None)[source]
+

Represents a for…generate statement.

+
+

Example

+
gen: for i in 0 to 3 generate
+  -- ...
+end generate;
+
+
+
+

Inheritance

+
+

Inheritance diagram of ForGenerateStatement

+
+
Parameters:
+
+
+
+
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+IndexDeclaredItems()
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+
+property Label: str | None
+

Returns a model entity’s label.

+
+
Returns:
+

Label of a model entity.

+
+
+
+ +
+
+property NormalizedLabel: str | None
+

Returns a model entity’s normalized (lower case) label.

+
+
Returns:
+

Normalized label of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_label: Nullable[str]
+

The label of a model entity.

+
+ +
+
+_normalizedLabel: Nullable[str]
+

The normalized (lower case) label of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+__init__(label, loopIndex, rng, declaredItems=None, statements=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+ +
+
+class pyVHDLModel.Concurrent.ConcurrentSignalAssignment(label, target, parent=None)[source]
+

A base-class for concurrent signal assignments.

+
+

See also

+ +
+

Inheritance

+
+

Inheritance diagram of ConcurrentSignalAssignment

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Label: str | None
+

Returns a model entity’s label.

+
+
Returns:
+

Label of a model entity.

+
+
+
+ +
+
+property NormalizedLabel: str | None
+

Returns a model entity’s normalized (lower case) label.

+
+
Returns:
+

Normalized label of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_label: Nullable[str]
+

The label of a model entity.

+
+ +
+
+_normalizedLabel: Nullable[str]
+

The normalized (lower case) label of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+__init__(label, target, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
    +

  • parent (ModelEntity) – The parent model entity of this entity.

    • +

  • label (str)

    • +

  • target (Name)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+ +
+
+class pyVHDLModel.Concurrent.ConcurrentSimpleSignalAssignment(label, target, waveform, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of ConcurrentSimpleSignalAssignment

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Label: str | None
+

Returns a model entity’s label.

+
+
Returns:
+

Label of a model entity.

+
+
+
+ +
+
+property NormalizedLabel: str | None
+

Returns a model entity’s normalized (lower case) label.

+
+
Returns:
+

Normalized label of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_label: Nullable[str]
+

The label of a model entity.

+
+ +
+
+_normalizedLabel: Nullable[str]
+

The normalized (lower case) label of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+__init__(label, target, waveform, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+ +
+
+class pyVHDLModel.Concurrent.ConcurrentSelectedSignalAssignment(label, target, expression, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of ConcurrentSelectedSignalAssignment

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Label: str | None
+

Returns a model entity’s label.

+
+
Returns:
+

Label of a model entity.

+
+
+
+ +
+
+property NormalizedLabel: str | None
+

Returns a model entity’s normalized (lower case) label.

+
+
Returns:
+

Normalized label of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_label: Nullable[str]
+

The label of a model entity.

+
+ +
+
+_normalizedLabel: Nullable[str]
+

The normalized (lower case) label of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+__init__(label, target, expression, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+ +
+
+class pyVHDLModel.Concurrent.ConcurrentConditionalSignalAssignment(label, target, expression, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of ConcurrentConditionalSignalAssignment

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Label: str | None
+

Returns a model entity’s label.

+
+
Returns:
+

Label of a model entity.

+
+
+
+ +
+
+property NormalizedLabel: str | None
+

Returns a model entity’s normalized (lower case) label.

+
+
Returns:
+

Normalized label of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_label: Nullable[str]
+

The label of a model entity.

+
+ +
+
+_normalizedLabel: Nullable[str]
+

The normalized (lower case) label of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+__init__(label, target, expression, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+ +
+
+class pyVHDLModel.Concurrent.ConcurrentAssertStatement(condition, message, severity=None, label=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of ConcurrentAssertStatement

+
+
Parameters:
+
+
+
+
+
+property Condition: BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal
+

Read-only property to access the condition of a statement (_condition).

+
+
Returns:
+

The expression representing the condition of a statement.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Label: str | None
+

Returns a model entity’s label.

+
+
Returns:
+

Label of a model entity.

+
+
+
+ +
+
+property NormalizedLabel: str | None
+

Returns a model entity’s normalized (lower case) label.

+
+
Returns:
+

Normalized label of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_label: Nullable[str]
+

The label of a model entity.

+
+ +
+
+_normalizedLabel: Nullable[str]
+

The normalized (lower case) label of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+__init__(condition, message, severity=None, label=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+ +
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/pyVHDLModel/pyVHDLModel.Declaration.html b/pyVHDLModel/pyVHDLModel.Declaration.html new file mode 100644 index 000000000..d6a6361ae --- /dev/null +++ b/pyVHDLModel/pyVHDLModel.Declaration.html @@ -0,0 +1,775 @@ + + + + + + + pyVHDLModel.Declaration — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

pyVHDLModel.Declaration

+

This module contains parts of an abstract document language model for VHDL.

+

Classes

+
    +

  • EntityClass: +An EntityClass is an enumeration. It represents a VHDL language entity class (entity, label, …).

    • +

  • Attribute: +Represents an attribute declaration.

    • +

  • AttributeSpecification: +Represents an attribute specification.

    • +

  • Alias: +ModelEntity is the base-class for all classes in the VHDL language model, except for mixin classes (see multiple

    • +
+
+

Classes

+
+
+class pyVHDLModel.Declaration.EntityClass(value, names=<not given>, *values, module=None, qualname=None, type=None, start=1, boundary=None)[source]
+

An EntityClass is an enumeration. It represents a VHDL language entity class (entity, label, …).

+

Inheritance

+
+

Inheritance diagram of EntityClass

+
+
+Entity = 0
+

Entity

+
+ +
+
+Architecture = 1
+

Architecture

+
+ +
+
+Configuration = 2
+

Configuration

+
+ +
+
+Procedure = 3
+

Procedure

+
+ +
+
+Function = 4
+

Function

+
+ +
+
+Package = 5
+

Package

+
+ +
+
+Type = 6
+

Type

+
+ +
+
+Subtype = 7
+

Subtype

+
+ +
+
+Constant = 8
+

Constant

+
+ +
+
+Signal = 9
+

Signal

+
+ +
+
+Variable = 10
+

Variable

+
+ +
+
+Component = 11
+

Component

+
+ +
+
+Label = 12
+

Label

+
+ +
+
+Literal = 13
+

Literal

+
+ +
+
+Units = 14
+

Units

+
+ +
+
+Group = 15
+

Group

+
+ +
+
+File = 16
+

File

+
+ +
+
+Property = 17
+

Property

+
+ +
+
+Sequence = 18
+

Sequence

+
+ +
+
+View = 19
+

View

+
+ +
+
+Others = 20
+

Others

+
+ +
+ +
+
+class pyVHDLModel.Declaration.Attribute(identifier, subtype, documentation=None, parent=None)[source]
+

Represents an attribute declaration.

+
+

Example

+
attribute TotalBits : natural;
+
+
+
+

Inheritance

+
+

Inheritance diagram of Attribute

+
+
Parameters:
+
+
+
+
+
+__init__(identifier, subtype, documentation=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
    +

  • parent (ModelEntity) – The parent model entity of this entity.

    • +

  • identifier (str)

    • +

  • subtype (Symbol)

    • +

  • documentation (str | None)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_documentation: Optional[str]
+

The associated documentation of a model entity.

+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Declaration.AttributeSpecification(identifiers, attribute, entityClass, expression, documentation=None, parent=None)[source]
+

Represents an attribute specification.

+
+

Example

+
attribute TotalBits of BusType : subtype is 32;
+
+
+
+

Inheritance

+
+

Inheritance diagram of AttributeSpecification

+
+
Parameters:
+
+
+
+
+
+__init__(identifiers, attribute, entityClass, expression, documentation=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+_documentation: Optional[str]
+

The associated documentation of a model entity.

+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Declaration.Alias(identifier, documentation=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of Alias

+
+
Parameters:
+
+
+
+
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_documentation: Optional[str]
+

The associated documentation of a model entity.

+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+__init__(identifier, documentation=None, parent=None)[source]
+

Initializes underlying BaseType.

+
+
Parameters:
+
    +

  • identifier (str) – Name of the type.

    • +

  • documentation (str | None)

    • +

  • parent (ModelEntity)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+ +
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/pyVHDLModel/pyVHDLModel.DesignUnit.html b/pyVHDLModel/pyVHDLModel.DesignUnit.html new file mode 100644 index 000000000..cfe6ae85b --- /dev/null +++ b/pyVHDLModel/pyVHDLModel.DesignUnit.html @@ -0,0 +1,4087 @@ + + + + + + + pyVHDLModel.DesignUnit — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

pyVHDLModel.DesignUnit

+

This module contains parts of an abstract document language model for VHDL.

+

Design units are contexts, entities, architectures, packages and their bodies as well as configurations.

+

Classes

+ +
+

Classes

+
+
+class pyVHDLModel.DesignUnit.Reference(symbols, parent=None)[source]
+

A base-class for all references.

+
+

See also

+ +
+

Inheritance

+
+

Inheritance diagram of Reference

+
+
Parameters:
+
+
+
+
+
+__init__(symbols, parent=None)[source]
+

Initializes a reference by taking a list of symbols and a parent reference.

+
+
Parameters:
+
    +

  • symbols (Iterable[Symbol]) – A list of symbols this reference references to.

    • +

  • parent (ModelEntity) – Reference to the logical parent in the model hierarchy.

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+property Symbols: List[Symbol]
+

Read-only property to access the symbols this reference references to (_symbols).

+
+
Returns:
+

A list of symbols.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.DesignUnit.LibraryClause(symbols, parent=None)[source]
+

Represents a library clause.

+
+

Example

+
library std, ieee;
+
+
+
+

Inheritance

+
+

Inheritance diagram of LibraryClause

+
+
Parameters:
+
+
+
+
+
+property Symbols: List[LibraryReferenceSymbol]
+

Read-only property to access the symbols this library clause references to (_symbols).

+
+
Returns:
+

A list of library reference symbols.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(symbols, parent=None)
+

Initializes a reference by taking a list of symbols and a parent reference.

+
+
Parameters:
+
    +

  • symbols (Iterable[Symbol]) – A list of symbols this reference references to.

    • +

  • parent (ModelEntity) – Reference to the logical parent in the model hierarchy.

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.DesignUnit.UseClause(symbols, parent=None)[source]
+

Represents a use clause.

+
+

Example

+
use std.text_io.all, ieee.numeric_std.all;
+
+
+
+

Inheritance

+
+

Inheritance diagram of UseClause

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+property Symbols: List[Symbol]
+

Read-only property to access the symbols this reference references to (_symbols).

+
+
Returns:
+

A list of symbols.

+
+
+
+ +
+
+__init__(symbols, parent=None)
+

Initializes a reference by taking a list of symbols and a parent reference.

+
+
Parameters:
+
    +

  • symbols (Iterable[Symbol]) – A list of symbols this reference references to.

    • +

  • parent (ModelEntity) – Reference to the logical parent in the model hierarchy.

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.DesignUnit.ContextReference(symbols, parent=None)[source]
+

Represents a context reference.

+
+

Hint

+

It’s called context reference not context clause by the LRM.

+
+
+

Example

+
context ieee.ieee_std_context;
+
+
+
+

Inheritance

+
+

Inheritance diagram of ContextReference

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+property Symbols: List[Symbol]
+

Read-only property to access the symbols this reference references to (_symbols).

+
+
Returns:
+

A list of symbols.

+
+
+
+ +
+
+__init__(symbols, parent=None)
+

Initializes a reference by taking a list of symbols and a parent reference.

+
+
Parameters:
+
    +

  • symbols (Iterable[Symbol]) – A list of symbols this reference references to.

    • +

  • parent (ModelEntity) – Reference to the logical parent in the model hierarchy.

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.DesignUnit.DesignUnitWithContextMixin[source]
+

A mixin-class for all design units with a context.

+

Inheritance

+
+

Inheritance diagram of DesignUnitWithContextMixin

+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+ +
+
+class pyVHDLModel.DesignUnit.DesignUnit(identifier, contextItems=None, documentation=None, parent=None)[source]
+

A base-class for all design units.

+
+

See also

+ +
+

Inheritance

+
+

Inheritance diagram of DesignUnit

+
+
Parameters:
+
+
+
+
+
+__init__(identifier, contextItems=None, documentation=None, parent=None)[source]
+

Initializes a design unit.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_contextItems: List[ContextUnion]
+

List of all context items (library, use and context clauses).

+
+ +
+
+_libraryReferences: List[LibraryClause]
+

List of library clauses.

+
+ +
+
+_packageReferences: List[UseClause]
+

List of use clauses.

+
+ +
+
+_contextReferences: List[ContextReference]
+

List of context clauses.

+
+ +
+
+_referencedLibraries: Dict[str, Library]
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, Package]]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+
+_referencedContexts: Dict[str, Context]
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, DesignUnit, None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, DesignUnit, None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.DesignUnit.PrimaryUnit(identifier, contextItems=None, documentation=None, parent=None)[source]
+

A base-class for all primary design units.

+
+

See also

+ +
+

Inheritance

+
+

Inheritance diagram of PrimaryUnit

+
+
Parameters:
+
+
+
+
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(identifier, contextItems=None, documentation=None, parent=None)
+

Initializes a design unit.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+_contextItems: List['ContextUnion']
+

List of all context items (library, use and context clauses).

+
+ +
+
+_contextReferences: List['ContextReference']
+

List of context clauses.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_libraryReferences: List['LibraryClause']
+

List of library clauses.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageReferences: List['UseClause']
+

List of use clauses.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_referencedContexts: Dict[str, 'Context']
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_referencedLibraries: Dict[str, 'Library']
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, 'Package']]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+ +
+
+class pyVHDLModel.DesignUnit.SecondaryUnit(identifier, contextItems=None, documentation=None, parent=None)[source]
+

A base-class for all secondary design units.

+
+

See also

+ +
+

Inheritance

+
+

Inheritance diagram of SecondaryUnit

+
+
Parameters:
+
+
+
+
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(identifier, contextItems=None, documentation=None, parent=None)
+

Initializes a design unit.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+_contextItems: List['ContextUnion']
+

List of all context items (library, use and context clauses).

+
+ +
+
+_contextReferences: List['ContextReference']
+

List of context clauses.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_libraryReferences: List['LibraryClause']
+

List of library clauses.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageReferences: List['UseClause']
+

List of use clauses.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_referencedContexts: Dict[str, 'Context']
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_referencedLibraries: Dict[str, 'Library']
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, 'Package']]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+ +
+
+class pyVHDLModel.DesignUnit.Context(identifier, references=None, documentation=None, parent=None)[source]
+

Represents a context declaration.

+

A context contains a generic list of all its items (library clauses, use clauses and context references) in +_references.

+

Furthermore, when a context gets initialized, the item kinds get separated into individual lists:

+ +

When pyVHDLModel.Design.LinkContexts() got called, these lists were processed and the fields:

+ +

are populated.

+
+

Example

+
context ctx is
+  -- ...
+end context;
+
+
+
+

Inheritance

+
+

Inheritance diagram of Context

+
+
Parameters:
+
+
+
+
+
+__init__(identifier, references=None, documentation=None, parent=None)[source]
+

Initializes a design unit.

+
+
Parameters:
+
    +

  • identifier (str) – Identifier (name) of the design unit.

    • +

  • contextItems – A sequence of library, use or context clauses.

    • +

  • documentation (Optional[str]) – Associated documentation of the design unit.

    • +

  • parent (ModelEntity) – Reference to the logical parent in the model hierarchy.

    • +

  • references (Iterable[LibraryClause | UseClause | ContextReference] | None)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+_libraryReferences: List['LibraryClause']
+

List of library clauses.

+
+ +
+
+_packageReferences: List['UseClause']
+

List of use clauses.

+
+ +
+
+_contextReferences: List['ContextReference']
+

List of context clauses.

+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_contextItems: List['ContextUnion']
+

List of all context items (library, use and context clauses).

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_referencedContexts: Dict[str, 'Context']
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_referencedLibraries: Dict[str, 'Library']
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, 'Package']]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+ +
+
+class pyVHDLModel.DesignUnit.Package(identifier, contextItems=None, genericItems=None, declaredItems=None, documentation=None, parent=None)[source]
+

Represents a package declaration.

+
+

Example

+
package pkg is
+  -- ...
+end package;
+
+
+
+

Inheritance

+
+

Inheritance diagram of Package

+
+
Parameters:
+
+
+
+
+
+__init__(identifier, contextItems=None, genericItems=None, declaredItems=None, documentation=None, parent=None)[source]
+

Initializes a design unit.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__repr__()[source]
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+IndexDeclaredItems()
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_contextItems: List['ContextUnion']
+

List of all context items (library, use and context clauses).

+
+ +
+
+_contextReferences: List['ContextReference']
+

List of context clauses.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_libraryReferences: List['LibraryClause']
+

List of library clauses.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageReferences: List['UseClause']
+

List of use clauses.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_referencedContexts: Dict[str, 'Context']
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_referencedLibraries: Dict[str, 'Library']
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, 'Package']]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+ +
+
+class pyVHDLModel.DesignUnit.PackageBody(packageSymbol, contextItems=None, declaredItems=None, documentation=None, parent=None)[source]
+

Represents a package body declaration.

+
+

Example

+
package body pkg is
+  -- ...
+end package body;
+
+
+
+

Inheritance

+
+

Inheritance diagram of PackageBody

+
+
Parameters:
+
+
+
+
+
+__init__(packageSymbol, contextItems=None, declaredItems=None, documentation=None, parent=None)[source]
+

Initializes a design unit.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__repr__()[source]
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+IndexDeclaredItems()
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_contextItems: List['ContextUnion']
+

List of all context items (library, use and context clauses).

+
+ +
+
+_contextReferences: List['ContextReference']
+

List of context clauses.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_libraryReferences: List['LibraryClause']
+

List of library clauses.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageReferences: List['UseClause']
+

List of use clauses.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_referencedContexts: Dict[str, 'Context']
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_referencedLibraries: Dict[str, 'Library']
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, 'Package']]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+ +
+
+class pyVHDLModel.DesignUnit.Entity(identifier, contextItems=None, genericItems=None, portItems=None, declaredItems=None, statements=None, documentation=None, parent=None)[source]
+

Represents an entity declaration.

+
+

Example

+
entity ent is
+  -- ...
+end entity;
+
+
+
+

Inheritance

+
+

Inheritance diagram of Entity

+
+
Parameters:
+
+
+
+
+
+__init__(identifier, contextItems=None, genericItems=None, portItems=None, declaredItems=None, statements=None, documentation=None, parent=None)[source]
+

Initializes a design unit.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+IndexDeclaredItems()
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_contextItems: List['ContextUnion']
+

List of all context items (library, use and context clauses).

+
+ +
+
+_contextReferences: List['ContextReference']
+

List of context clauses.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_libraryReferences: List['LibraryClause']
+

List of library clauses.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageReferences: List['UseClause']
+

List of use clauses.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_referencedContexts: Dict[str, 'Context']
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_referencedLibraries: Dict[str, 'Library']
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, 'Package']]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__repr__()[source]
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+ +
+
+class pyVHDLModel.DesignUnit.Architecture(identifier, entity, contextItems=None, declaredItems=None, statements=None, documentation=None, parent=None)[source]
+

Represents an architecture declaration.

+
+

Example

+
architecture rtl of ent is
+  -- ...
+begin
+  -- ...
+end architecture;
+
+
+
+

Inheritance

+
+

Inheritance diagram of Architecture

+
+
Parameters:
+
+
+
+
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+IndexDeclaredItems()
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_contextItems: List['ContextUnion']
+

List of all context items (library, use and context clauses).

+
+ +
+
+_contextReferences: List['ContextReference']
+

List of context clauses.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_libraryReferences: List['LibraryClause']
+

List of library clauses.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageReferences: List['UseClause']
+

List of use clauses.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_referencedContexts: Dict[str, 'Context']
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_referencedLibraries: Dict[str, 'Library']
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, 'Package']]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+
+__init__(identifier, entity, contextItems=None, declaredItems=None, statements=None, documentation=None, parent=None)[source]
+

Initializes a design unit.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__repr__()[source]
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+ +
+
+class pyVHDLModel.DesignUnit.Component(identifier, genericItems=None, portItems=None, documentation=None, parent=None)[source]
+

Represents a configuration declaration.

+
+

Example

+
component ent is
+  -- ...
+end component;
+
+
+
+

Inheritance

+
+

Inheritance diagram of Component

+
+
Parameters:
+
+
+
+
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_documentation: Optional[str]
+

The associated documentation of a model entity.

+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+__init__(identifier, genericItems=None, portItems=None, documentation=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+ +
+
+class pyVHDLModel.DesignUnit.Configuration(identifier, contextItems=None, documentation=None, parent=None)[source]
+

Represents a configuration declaration.

+
+

Example

+
configuration cfg of ent is
+  for rtl
+    -- ...
+  end for;
+end configuration;
+
+
+
+

Inheritance

+
+

Inheritance diagram of Configuration

+
+
Parameters:
+
+
+
+
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_contextItems: List['ContextUnion']
+

List of all context items (library, use and context clauses).

+
+ +
+
+_contextReferences: List['ContextReference']
+

List of context clauses.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_libraryReferences: List['LibraryClause']
+

List of library clauses.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageReferences: List['UseClause']
+

List of use clauses.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_referencedContexts: Dict[str, 'Context']
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_referencedLibraries: Dict[str, 'Library']
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, 'Package']]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+
+__init__(identifier, contextItems=None, documentation=None, parent=None)[source]
+

Initializes a design unit.

+
+
Parameters:
+
    +

  • identifier (str) – Identifier (name) of the design unit.

    • +

  • contextItems (Optional[Iterable[Context]]) – A sequence of library, use or context clauses.

    • +

  • documentation (Optional[str]) – Associated documentation of the design unit.

    • +

  • parent (ModelEntity) – Reference to the logical parent in the model hierarchy.

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__repr__()[source]
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+ +
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/pyVHDLModel/pyVHDLModel.Exception.html b/pyVHDLModel/pyVHDLModel.Exception.html new file mode 100644 index 000000000..0ecf96fa3 --- /dev/null +++ b/pyVHDLModel/pyVHDLModel.Exception.html @@ -0,0 +1,453 @@ + + + + + + + pyVHDLModel.Exception — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

pyVHDLModel.Exception

+

This module contains parts of an abstract document language model for VHDL.

+

The module Exceptions contains all structured errors that are raised by pyVHDLModel. Besides a default error +message in english, each exception object contains one or multiple references to the exception’s context.

+

Exceptions

+ +
+

Exceptions

+
+
+exception pyVHDLModel.Exception.VHDLModelException[source]
+

Base-class for all exceptions (errors) raised by pyVHDLModel.

+

Inheritance

+
+

Inheritance diagram of VHDLModelException

+
+ +
+
+exception pyVHDLModel.Exception.LibraryExistsInDesignError(library)[source]
+

This exception is raised, when the library is already existing in the design.

+

Message: f"Library '{library._identifier}' already exists in design."

+

Inheritance

+
+

Inheritance diagram of LibraryExistsInDesignError

+
+
Parameters:
+

library (Library)

+
+
Return type:
+

None

+
+
+
+ +
+
+exception pyVHDLModel.Exception.LibraryRegisteredToForeignDesignError(library)[source]
+

This exception is raised, when the library is already registered to a foreign design.

+

Message: f"Library '{library._identifier}' already registered in design '{library.Parent}'."

+

Inheritance

+
+

Inheritance diagram of LibraryRegisteredToForeignDesignError

+
+
Parameters:
+

library (Library)

+
+
Return type:
+

None

+
+
+
+ +
+
+exception pyVHDLModel.Exception.LibraryNotRegisteredError(library)[source]
+

This exception is raised, when the library is not registered in the design.

+

Message: f"Library '{library._identifier}' is not registered in the design."

+

Inheritance

+
+

Inheritance diagram of LibraryNotRegisteredError

+
+
Parameters:
+

library (Library)

+
+
Return type:
+

None

+
+
+
+ +
+
+exception pyVHDLModel.Exception.EntityExistsInLibraryError(entity, library)[source]
+

This exception is raised, when the entity already existing in the library.

+

Message: f"Entity '{entity._identifier}' already exists in library '{library._identifier}'."

+

Inheritance

+
+

Inheritance diagram of EntityExistsInLibraryError

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+exception pyVHDLModel.Exception.ArchitectureExistsInLibraryError(architecture, entity, library)[source]
+

This exception is raised, when the architecture already existing in the library.

+

Message: f"Architecture '{architecture._identifier}' for entity '{entity._identifier}' already exists in library '{library._identifier}'."

+

Inheritance

+
+

Inheritance diagram of ArchitectureExistsInLibraryError

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+exception pyVHDLModel.Exception.PackageExistsInLibraryError(package, library)[source]
+

This exception is raised, when the package already existing in the library.

+

Message: f"Package '{package._identifier}' already exists in library '{library._identifier}'."

+

Inheritance

+
+

Inheritance diagram of PackageExistsInLibraryError

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+exception pyVHDLModel.Exception.PackageBodyExistsError(packageBody, library)[source]
+

This exception is raised, when the package body already existing in the library.

+

Message: f"Package body '{packageBody._identifier}' already exists in library '{library._identifier}'."

+

Inheritance

+
+

Inheritance diagram of PackageBodyExistsError

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+exception pyVHDLModel.Exception.ConfigurationExistsInLibraryError(configuration, library)[source]
+

This exception is raised, when the configuration already existing in the library.

+

Message: f"Configuration '{configuration._identifier}' already exists in library '{library._identifier}'."

+

Inheritance

+
+

Inheritance diagram of ConfigurationExistsInLibraryError

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+exception pyVHDLModel.Exception.ContextExistsInLibraryError(context, library)[source]
+

This exception is raised, when the context already existing in the library.

+

Message: f"Context '{context._identifier}' already exists in library '{library._identifier}'."

+

Inheritance

+
+

Inheritance diagram of ContextExistsInLibraryError

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+exception pyVHDLModel.Exception.ReferencedLibraryNotExistingError(context, librarySymbol)[source]
+

This exception is raised, when a library is referenced by a library clause, but doesn’t exist in the design.

+

Message: f"Library '{librarySymbol.Name._identifier}' referenced by library clause of context '{context._identifier}' doesn't exist in design."

+

Inheritance

+
+

Inheritance diagram of ReferencedLibraryNotExistingError

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/pyVHDLModel/pyVHDLModel.Expression.html b/pyVHDLModel/pyVHDLModel.Expression.html new file mode 100644 index 000000000..31ba39c2b --- /dev/null +++ b/pyVHDLModel/pyVHDLModel.Expression.html @@ -0,0 +1,8183 @@ + + + + + + + pyVHDLModel.Expression — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

pyVHDLModel.Expression

+

This module contains parts of an abstract document language model for VHDL.

+

All declarations for literals, aggregates, operators forming an expressions.

+

Classes

+ +
+

Classes

+
+
+class pyVHDLModel.Expression.BaseExpression(parent=None)[source]
+

A BaseExpression is a base-class for all expressions.

+

Inheritance

+
+

Inheritance diagram of BaseExpression

+
+
Parameters:
+

parent (ModelEntity | None)

+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+

parent (Optional[ModelEntity]) – The parent model entity of this entity.

+
+
Return type:
+

None

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.Literal(parent=None)[source]
+

A Literal is a base-class for all literals.

+

Inheritance

+
+

Inheritance diagram of Literal

+
+
Parameters:
+

parent (ModelEntity | None)

+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+

parent (Optional[ModelEntity]) – The parent model entity of this entity.

+
+
Return type:
+

None

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.NullLiteral(parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of NullLiteral

+
+
Parameters:
+

parent (ModelEntity | None)

+
+
+
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+

parent (Optional[ModelEntity]) – The parent model entity of this entity.

+
+
Return type:
+

None

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.EnumerationLiteral(value, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of EnumerationLiteral

+
+
Parameters:
+
+
+
+
+
+__init__(value, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
    +

  • parent (ModelEntity) – The parent model entity of this entity.

    • +

  • value (str)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.NumericLiteral(parent=None)[source]
+

A NumericLiteral is a base-class for all numeric literals.

+

Inheritance

+
+

Inheritance diagram of NumericLiteral

+
+
Parameters:
+

parent (ModelEntity | None)

+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+

parent (Optional[ModelEntity]) – The parent model entity of this entity.

+
+
Return type:
+

None

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.IntegerLiteral(value)[source]
+

Inheritance

+
+

Inheritance diagram of IntegerLiteral

+
+
Parameters:
+

value (int)

+
+
+
+
+__init__(value)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
    +

  • parent – The parent model entity of this entity.

    • +

  • value (int)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.FloatingPointLiteral(value)[source]
+

Inheritance

+
+

Inheritance diagram of FloatingPointLiteral

+
+
Parameters:
+

value (float)

+
+
+
+
+__init__(value)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
    +

  • parent – The parent model entity of this entity.

    • +

  • value (float)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.PhysicalLiteral(unitName)[source]
+

Inheritance

+
+

Inheritance diagram of PhysicalLiteral

+
+
Parameters:
+

unitName (str)

+
+
+
+
+__init__(unitName)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
    +

  • parent – The parent model entity of this entity.

    • +

  • unitName (str)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.PhysicalIntegerLiteral(value, unitName)[source]
+

Inheritance

+
+

Inheritance diagram of PhysicalIntegerLiteral

+
+
Parameters:
+
    +

  • value (int)

    • +

  • unitName (str)

    • +
+
+
+
+
+__init__(value, unitName)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
    +

  • parent – The parent model entity of this entity.

    • +

  • value (int)

    • +

  • unitName (str)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.PhysicalFloatingLiteral(value, unitName)[source]
+

Inheritance

+
+

Inheritance diagram of PhysicalFloatingLiteral

+
+
Parameters:
+
+
+
+
+
+__init__(value, unitName)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
    +

  • parent – The parent model entity of this entity.

    • +

  • value (float)

    • +

  • unitName (str)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.CharacterLiteral(value)[source]
+

Inheritance

+
+

Inheritance diagram of CharacterLiteral

+
+
Parameters:
+

value (str)

+
+
+
+
+__init__(value)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
    +

  • parent – The parent model entity of this entity.

    • +

  • value (str)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.StringLiteral(value)[source]
+

Inheritance

+
+

Inheritance diagram of StringLiteral

+
+
Parameters:
+

value (str)

+
+
+
+
+__init__(value)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
    +

  • parent – The parent model entity of this entity.

    • +

  • value (str)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.BitStringLiteral(value)[source]
+

Inheritance

+
+

Inheritance diagram of BitStringLiteral

+
+
Parameters:
+

value (str)

+
+
+
+
+__init__(value)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
    +

  • parent – The parent model entity of this entity.

    • +

  • value (str)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.ParenthesisExpression[source]
+

Inheritance

+
+

Inheritance diagram of ParenthesisExpression

+
+ +
+
+class pyVHDLModel.Expression.UnaryExpression(operand, parent=None)[source]
+

A UnaryExpression is a base-class for all unary expressions.

+

Inheritance

+
+

Inheritance diagram of UnaryExpression

+
+
Parameters:
+
+
+
+
+
+__init__(operand, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.NegationExpression(operand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of NegationExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(operand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.IdentityExpression(operand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of IdentityExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(operand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.InverseExpression(operand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of InverseExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(operand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.UnaryAndExpression(operand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of UnaryAndExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(operand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.UnaryNandExpression(operand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of UnaryNandExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(operand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.UnaryOrExpression(operand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of UnaryOrExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(operand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.UnaryNorExpression(operand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of UnaryNorExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(operand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.UnaryXorExpression(operand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of UnaryXorExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(operand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.UnaryXnorExpression(operand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of UnaryXnorExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(operand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.AbsoluteExpression(operand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of AbsoluteExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(operand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.TypeConversion(operand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of TypeConversion

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(operand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.SubExpression(operand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of SubExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(operand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.BinaryExpression(leftOperand, rightOperand, parent=None)[source]
+

A BinaryExpression is a base-class for all binary expressions.

+

Inheritance

+
+

Inheritance diagram of BinaryExpression

+
+
Parameters:
+
+
+
+
+
+__init__(leftOperand, rightOperand, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.RangeExpression(leftOperand, rightOperand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of RangeExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(leftOperand, rightOperand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.AscendingRangeExpression(leftOperand, rightOperand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of AscendingRangeExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(leftOperand, rightOperand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.DescendingRangeExpression(leftOperand, rightOperand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of DescendingRangeExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(leftOperand, rightOperand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.AddingExpression(leftOperand, rightOperand, parent=None)[source]
+

A AddingExpression is a base-class for all adding expressions.

+

Inheritance

+
+

Inheritance diagram of AddingExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(leftOperand, rightOperand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.AdditionExpression(leftOperand, rightOperand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of AdditionExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(leftOperand, rightOperand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.SubtractionExpression(leftOperand, rightOperand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of SubtractionExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(leftOperand, rightOperand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.ConcatenationExpression(leftOperand, rightOperand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of ConcatenationExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(leftOperand, rightOperand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.MultiplyingExpression(leftOperand, rightOperand, parent=None)[source]
+

A MultiplyingExpression is a base-class for all multiplying expressions.

+

Inheritance

+
+

Inheritance diagram of MultiplyingExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(leftOperand, rightOperand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.MultiplyExpression(leftOperand, rightOperand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of MultiplyExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(leftOperand, rightOperand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.DivisionExpression(leftOperand, rightOperand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of DivisionExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(leftOperand, rightOperand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.RemainderExpression(leftOperand, rightOperand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of RemainderExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(leftOperand, rightOperand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.ModuloExpression(leftOperand, rightOperand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of ModuloExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(leftOperand, rightOperand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.ExponentiationExpression(leftOperand, rightOperand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of ExponentiationExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(leftOperand, rightOperand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.LogicalExpression(leftOperand, rightOperand, parent=None)[source]
+

A LogicalExpression is a base-class for all logical expressions.

+

Inheritance

+
+

Inheritance diagram of LogicalExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(leftOperand, rightOperand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.AndExpression(leftOperand, rightOperand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of AndExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(leftOperand, rightOperand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.NandExpression(leftOperand, rightOperand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of NandExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(leftOperand, rightOperand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.OrExpression(leftOperand, rightOperand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of OrExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(leftOperand, rightOperand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.NorExpression(leftOperand, rightOperand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of NorExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(leftOperand, rightOperand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.XorExpression(leftOperand, rightOperand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of XorExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(leftOperand, rightOperand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.XnorExpression(leftOperand, rightOperand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of XnorExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(leftOperand, rightOperand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.RelationalExpression(leftOperand, rightOperand, parent=None)[source]
+

A RelationalExpression is a base-class for all shifting expressions.

+

Inheritance

+
+

Inheritance diagram of RelationalExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(leftOperand, rightOperand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.EqualExpression(leftOperand, rightOperand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of EqualExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(leftOperand, rightOperand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.UnequalExpression(leftOperand, rightOperand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of UnequalExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(leftOperand, rightOperand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.GreaterThanExpression(leftOperand, rightOperand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of GreaterThanExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(leftOperand, rightOperand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.GreaterEqualExpression(leftOperand, rightOperand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of GreaterEqualExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(leftOperand, rightOperand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.LessThanExpression(leftOperand, rightOperand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of LessThanExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(leftOperand, rightOperand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.LessEqualExpression(leftOperand, rightOperand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of LessEqualExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(leftOperand, rightOperand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.MatchingRelationalExpression(leftOperand, rightOperand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of MatchingRelationalExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(leftOperand, rightOperand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.MatchingEqualExpression(leftOperand, rightOperand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of MatchingEqualExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(leftOperand, rightOperand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.MatchingUnequalExpression(leftOperand, rightOperand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of MatchingUnequalExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(leftOperand, rightOperand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.MatchingGreaterThanExpression(leftOperand, rightOperand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of MatchingGreaterThanExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(leftOperand, rightOperand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.MatchingGreaterEqualExpression(leftOperand, rightOperand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of MatchingGreaterEqualExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(leftOperand, rightOperand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.MatchingLessThanExpression(leftOperand, rightOperand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of MatchingLessThanExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(leftOperand, rightOperand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.MatchingLessEqualExpression(leftOperand, rightOperand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of MatchingLessEqualExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(leftOperand, rightOperand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.ShiftExpression(leftOperand, rightOperand, parent=None)[source]
+

A ShiftExpression is a base-class for all shifting expressions.

+

Inheritance

+
+

Inheritance diagram of ShiftExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(leftOperand, rightOperand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.ShiftLogicExpression(leftOperand, rightOperand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of ShiftLogicExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(leftOperand, rightOperand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.ShiftArithmeticExpression(leftOperand, rightOperand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of ShiftArithmeticExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(leftOperand, rightOperand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.RotateExpression(leftOperand, rightOperand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of RotateExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(leftOperand, rightOperand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.ShiftRightLogicExpression(leftOperand, rightOperand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of ShiftRightLogicExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(leftOperand, rightOperand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.ShiftLeftLogicExpression(leftOperand, rightOperand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of ShiftLeftLogicExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(leftOperand, rightOperand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.ShiftRightArithmeticExpression(leftOperand, rightOperand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of ShiftRightArithmeticExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(leftOperand, rightOperand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.ShiftLeftArithmeticExpression(leftOperand, rightOperand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of ShiftLeftArithmeticExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(leftOperand, rightOperand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.RotateRightExpression(leftOperand, rightOperand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of RotateRightExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(leftOperand, rightOperand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.RotateLeftExpression(leftOperand, rightOperand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of RotateLeftExpression

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(leftOperand, rightOperand, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.QualifiedExpression(subtype, operand, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of QualifiedExpression

+
+
Parameters:
+
+
+
+
+
+__init__(subtype, operand, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.TernaryExpression(parent=None)[source]
+

A TernaryExpression is a base-class for all ternary expressions.

+

Inheritance

+
+

Inheritance diagram of TernaryExpression

+
+
Parameters:
+

parent (ModelEntity)

+
+
+
+
+__init__(parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+

parent (ModelEntity) – The parent model entity of this entity.

+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.WhenElseExpression(parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of WhenElseExpression

+
+
Parameters:
+

parent (ModelEntity)

+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+

parent (ModelEntity) – The parent model entity of this entity.

+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.FunctionCall(parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of FunctionCall

+
+
Parameters:
+

parent (ModelEntity | None)

+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+

parent (Optional[ModelEntity]) – The parent model entity of this entity.

+
+
Return type:
+

None

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.Allocation(parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of Allocation

+
+
Parameters:
+

parent (ModelEntity | None)

+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+

parent (Optional[ModelEntity]) – The parent model entity of this entity.

+
+
Return type:
+

None

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.SubtypeAllocation(subtype, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of SubtypeAllocation

+
+
Parameters:
+
+
+
+
+
+__init__(subtype, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
    +

  • parent (ModelEntity) – The parent model entity of this entity.

    • +

  • subtype (Symbol)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.QualifiedExpressionAllocation(qualifiedExpression, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of QualifiedExpressionAllocation

+
+
Parameters:
+
+
+
+
+
+__init__(qualifiedExpression, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.AggregateElement(expression, parent=None)[source]
+

A AggregateElement is a base-class for all aggregate elements.

+

Inheritance

+
+

Inheritance diagram of AggregateElement

+
+
Parameters:
+
+
+
+
+
+__init__(expression, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.SimpleAggregateElement(expression, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of SimpleAggregateElement

+
+
Parameters:
+
+
+
+
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(expression, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.IndexedAggregateElement(index, expression, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of IndexedAggregateElement

+
+
Parameters:
+
+
+
+
+
+__init__(index, expression, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Expression.RangedAggregateElement(rng, expression, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of RangedAggregateElement

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+__init__(rng, expression, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+ +
+
+class pyVHDLModel.Expression.NamedAggregateElement(name, expression, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of NamedAggregateElement

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+__init__(name, expression, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+ +
+
+class pyVHDLModel.Expression.OthersAggregateElement(expression, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of OthersAggregateElement

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(expression, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+ +
+
+class pyVHDLModel.Expression.Aggregate(elements, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of Aggregate

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+__init__(elements, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+ +
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/pyVHDLModel/pyVHDLModel.IEEE.html b/pyVHDLModel/pyVHDLModel.IEEE.html new file mode 100644 index 000000000..f71653be7 --- /dev/null +++ b/pyVHDLModel/pyVHDLModel.IEEE.html @@ -0,0 +1,10599 @@ + + + + + + + pyVHDLModel.IEEE — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

pyVHDLModel.IEEE

+

This module contains library and package declarations for VHDL library IEEE.

+

Classes

+ +
+

Classes

+
+
+class pyVHDLModel.IEEE.Ieee[source]
+

Predefined VHDL library ieee.

+

The following predefined packages are in this library:

+ +
+

See also

+
+
Other predefined libraries:
    +

  • Library Std

    • +
+
+
+
+

Inheritance

+
+

Inheritance diagram of Ieee

+
+
+
+
+__init__()[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+

parent – The parent model entity of this entity.

+
+
Return type:
+

None

+
+
+
+ +
+
+property Architectures: Dict[str, Dict[str, Architecture]]
+

Returns a list of all architectures declarations declared in this library.

+
+ +
+
+property Configurations: Dict[str, Configuration]
+

Returns a list of all configuration declarations declared in this library.

+
+ +
+
+property Contexts: Dict[str, Context]
+

Returns a list of all context declarations declared in this library.

+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this library by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Entities: Dict[str, Entity]
+

Returns a list of all entity declarations declared in this library.

+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+IndexArchitectures()
+

Index declared items in all architectures.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all architectures:

    + +
    2. +
+
+

See also

+
+
IndexPackages()

Index all declared items in a package.

+
+
IndexPackageBodies()

Index all declared items in a package body.

+
+
IndexEntities()

Index all declared items in an entity.

+
+
+
+
+ +
+
+IndexEntities()
+

Index declared items in all entities.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all entities:

    + +
    2. +
+
+

See also

+
+
IndexPackages()

Index all declared items in a package.

+
+
IndexPackageBodies()

Index all declared items in a package body.

+
+
IndexArchitectures()

Index all declared items in an architecture.

+
+
+
+
+ +
+
+IndexPackageBodies()
+

Index declared items in all package bodies.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all package bodies:

    + +
    2. +
+
+

See also

+
+
IndexPackages()

Index all declared items in a package.

+
+
IndexEntities()

Index all declared items in an entity.

+
+
IndexArchitectures()

Index all declared items in an architecture.

+
+
+
+
+ +
+
+IndexPackages()
+

Index declared items in all packages.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all packages:

    + +
    2. +
+
+

See also

+
+
IndexPackageBodies()

Index all declared items in a package body.

+
+
IndexEntities()

Index all declared items in an entity.

+
+
IndexArchitectures()

Index all declared items in an architecture.

+
+
+
+
+ +
+
+IterateDesignUnits(filter=<DesignUnitKind.All: 63>)
+

Iterate all design units in the library.

+

A union of DesignUnitKind values can be given to filter the returned result for suitable design units.

+

Algorithm

+
    +

  1. Iterate all contexts in that library.

    2. +

  2. Iterate all packages in that library.

    3. +

  3. Iterate all package bodies in that library.

    4. +

  4. Iterate all entites in that library.

    5. +

  5. Iterate all architectures in that library.

    6. +

  6. Iterate all configurations in that library.

    7. +
+
+
Parameters:
+

filter (DesignUnitKind) – An enumeration with possibly multiple flags to filter the returned design units.

+
+
Return type:
+

Generator[DesignUnit, None, None]

+
+
Returns:
+

A generator to iterate all matched design units in the library.

+
+
+
+

See also

+
+
pyVHDLModel.Design.IterateDesignUnits()

Iterate all design units in the design.

+
+
pyVHDLModel.Document.IterateDesignUnits()

Iterate all design units in the document.

+
+
+
+
+ +
+
+LinkArchitectures()
+

Link all architectures to corresponding entities.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all architecture groups (grouped per entity symbol’s name).

    +
      +

    • Check if entity symbol’s name exists as an entity in this library.

      • +
    +
      +

    1. For each architecture in the same architecture group:

      +
        +

      • Add architecture to entities architecture dictionary pyVHDLModel.DesignUnit.Entity._architectures.

        • +

      • Assign found entity to architecture’s entity symbol pyVHDLModel.DesignUnit.Architecture._entity

        • +

      • Set parent namespace of architecture’s namespace to the entitie’s namespace.

        • +

      • Add an edge in the dependency graph from the architecture’s corresponding dependency vertex to the entity’s corresponding dependency vertex.

        • +
      +
      2. +
    +
    2. +
+
+
Raises:
+
+
+
Return type:
+

None

+
+
+
+

See also

+
+
LinkPackageBodies()

Link all package bodies to corresponding packages.

+
+
+
+
+ +
+
+LinkPackageBodies()
+

Link all package bodies to corresponding packages.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all package bodies.

    +
      +

    • Check if package body symbol’s name exists as a package in this library.

      • +

    • Add package body to package pyVHDLModel.DesignUnit.Package._packageBody.

      • +

    • Assign found package to package body’s package symbol pyVHDLModel.DesignUnit.PackageBody._package

      • +

    • Set parent namespace of package body’s namespace to the package’s namespace.

      • +

    • Add an edge in the dependency graph from the package body’s corresponding dependency vertex to the package’s corresponding dependency vertex.

      • +
    +
    2. +
+
+
Raises:
+

VHDLModelException – If package name doesn’t exist.

+
+
Return type:
+

None

+
+
+
+

See also

+
+
LinkArchitectures()

Link all architectures to corresponding entities.

+
+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageBodies: Dict[str, PackageBody]
+

Returns a list of all package body declarations declared in this library.

+
+ +
+
+property Packages: Dict[str, Package]
+

Returns a list of all package declarations declared in this library.

+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__repr__()
+

Formats a representation of the library.

+

Format: Library: 'my_library'

+
+
Return type:
+

str

+
+
Returns:
+

String representation of the library.

+
+
+
+ +
+
+__str__()
+

Formats a representation of the library.

+

Format: Library: 'my_library'

+
+
Return type:
+

str

+
+
Returns:
+

String representation of the library.

+
+
+
+ +
+
+_architectures: Dict[str, Dict[str, Architecture]]
+

Dictionary of all architectures defined in a library.

+
+ +
+
+_configurations: Dict[str, Configuration]
+

Dictionary of all configurations defined in a library.

+
+ +
+
+_contexts: Dict[str, Context]
+

Dictionary of all contexts defined in a library.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, Union['Library', DesignUnit], None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the library.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_entities: Dict[str, Entity]
+

Dictionary of all entities defined in a library.

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageBodies: Dict[str, PackageBody]
+

Dictionary of all package bodies defined in a library.

+
+ +
+
+_packages: Dict[str, Package]
+

Dictionary of all packages defined in a library.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.IEEE.Math_Real[source]
+

Predefined package ieee.math_real.

+

Inheritance

+
+

Inheritance diagram of Math_Real

+
+
+
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+IndexDeclaredItems()
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__()
+

Initializes a design unit.

+
+
Parameters:
+
    +

  • identifier – Identifier (name) of the design unit.

    • +

  • contextItems – A sequence of library, use or context clauses.

    • +

  • documentation – Associated documentation of the design unit.

    • +

  • parent – Reference to the logical parent in the model hierarchy.

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_contextItems: List['ContextUnion']
+

List of all context items (library, use and context clauses).

+
+ +
+
+_contextReferences: List['ContextReference']
+

List of context clauses.

+
+ +
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_libraryReferences: List['LibraryClause']
+

List of library clauses.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageReferences: List['UseClause']
+

List of use clauses.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+_referencedContexts: Dict[str, 'Context']
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_referencedLibraries: Dict[str, 'Library']
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, 'Package']]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+ +
+
+class pyVHDLModel.IEEE.Math_Real_Body[source]
+

Predefined package body of package ieee.math_real.

+

Inheritance

+
+

Inheritance diagram of Math_Real_Body

+
+
+
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+IndexDeclaredItems()
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__()
+

Initializes a design unit.

+
+
Parameters:
+
    +

  • identifier – Identifier (name) of the design unit.

    • +

  • contextItems – A sequence of library, use or context clauses.

    • +

  • documentation – Associated documentation of the design unit.

    • +

  • parent – Reference to the logical parent in the model hierarchy.

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_contextItems: List['ContextUnion']
+

List of all context items (library, use and context clauses).

+
+ +
+
+_contextReferences: List['ContextReference']
+

List of context clauses.

+
+ +
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_libraryReferences: List['LibraryClause']
+

List of library clauses.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageReferences: List['UseClause']
+

List of use clauses.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+_referencedContexts: Dict[str, 'Context']
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_referencedLibraries: Dict[str, 'Library']
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, 'Package']]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+ +
+
+class pyVHDLModel.IEEE.Math_Complex[source]
+

Predefined package ieee.math_complex.

+

Inheritance

+
+

Inheritance diagram of Math_Complex

+
+
+
+
+__init__()[source]
+

Initializes a design unit.

+
+
Parameters:
+
    +

  • identifier – Identifier (name) of the design unit.

    • +

  • contextItems – A sequence of library, use or context clauses.

    • +

  • documentation – Associated documentation of the design unit.

    • +

  • parent – Reference to the logical parent in the model hierarchy.

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+IndexDeclaredItems()
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_contextItems: List['ContextUnion']
+

List of all context items (library, use and context clauses).

+
+ +
+
+_contextReferences: List['ContextReference']
+

List of context clauses.

+
+ +
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_libraryReferences: List['LibraryClause']
+

List of library clauses.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageReferences: List['UseClause']
+

List of use clauses.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+_referencedContexts: Dict[str, 'Context']
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_referencedLibraries: Dict[str, 'Library']
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, 'Package']]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+ +
+
+class pyVHDLModel.IEEE.Math_Complex_Body[source]
+

Predefined package body of package ieee.math_complex.

+

Inheritance

+
+

Inheritance diagram of Math_Complex_Body

+
+
+
+
+__init__()[source]
+

Initializes a design unit.

+
+
Parameters:
+
    +

  • identifier – Identifier (name) of the design unit.

    • +

  • contextItems – A sequence of library, use or context clauses.

    • +

  • documentation – Associated documentation of the design unit.

    • +

  • parent – Reference to the logical parent in the model hierarchy.

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+IndexDeclaredItems()
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_contextItems: List['ContextUnion']
+

List of all context items (library, use and context clauses).

+
+ +
+
+_contextReferences: List['ContextReference']
+

List of context clauses.

+
+ +
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_libraryReferences: List['LibraryClause']
+

List of library clauses.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageReferences: List['UseClause']
+

List of use clauses.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+_referencedContexts: Dict[str, 'Context']
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_referencedLibraries: Dict[str, 'Library']
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, 'Package']]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+ +
+
+class pyVHDLModel.IEEE.Std_logic_1164[source]
+

Predefined package ieee.std_logic_1164.

+

Predefined types:

+
    +

  • std_ulogic, std_ulogic_vector

    • +

  • std_logic, std_logic_vector

    • +
+

Inheritance

+
+

Inheritance diagram of Std_logic_1164

+
+
+
+
+__init__()[source]
+

Initializes a design unit.

+
+
Parameters:
+
    +

  • identifier – Identifier (name) of the design unit.

    • +

  • contextItems – A sequence of library, use or context clauses.

    • +

  • documentation – Associated documentation of the design unit.

    • +

  • parent – Reference to the logical parent in the model hierarchy.

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+IndexDeclaredItems()
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_contextItems: List['ContextUnion']
+

List of all context items (library, use and context clauses).

+
+ +
+
+_contextReferences: List['ContextReference']
+

List of context clauses.

+
+ +
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_libraryReferences: List['LibraryClause']
+

List of library clauses.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageReferences: List['UseClause']
+

List of use clauses.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+_referencedContexts: Dict[str, 'Context']
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_referencedLibraries: Dict[str, 'Library']
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, 'Package']]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+ +
+
+class pyVHDLModel.IEEE.Std_logic_1164_Body[source]
+

Predefined package body of package ieee.std_logic_1164.

+

Inheritance

+
+

Inheritance diagram of Std_logic_1164_Body

+
+
+
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+IndexDeclaredItems()
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__()
+

Initializes a design unit.

+
+
Parameters:
+
    +

  • identifier – Identifier (name) of the design unit.

    • +

  • contextItems – A sequence of library, use or context clauses.

    • +

  • documentation – Associated documentation of the design unit.

    • +

  • parent – Reference to the logical parent in the model hierarchy.

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_contextItems: List['ContextUnion']
+

List of all context items (library, use and context clauses).

+
+ +
+
+_contextReferences: List['ContextReference']
+

List of context clauses.

+
+ +
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_libraryReferences: List['LibraryClause']
+

List of library clauses.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageReferences: List['UseClause']
+

List of use clauses.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+_referencedContexts: Dict[str, 'Context']
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_referencedLibraries: Dict[str, 'Library']
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, 'Package']]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+ +
+
+class pyVHDLModel.IEEE.std_logic_textio[source]
+

Predefined package ieee.std_logic_textio.

+

Inheritance

+
+

Inheritance diagram of std_logic_textio

+
+
+
+
+__init__()[source]
+

Initializes a design unit.

+
+
Parameters:
+
    +

  • identifier – Identifier (name) of the design unit.

    • +

  • contextItems – A sequence of library, use or context clauses.

    • +

  • documentation – Associated documentation of the design unit.

    • +

  • parent – Reference to the logical parent in the model hierarchy.

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+IndexDeclaredItems()
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_contextItems: List['ContextUnion']
+

List of all context items (library, use and context clauses).

+
+ +
+
+_contextReferences: List['ContextReference']
+

List of context clauses.

+
+ +
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_libraryReferences: List['LibraryClause']
+

List of library clauses.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageReferences: List['UseClause']
+

List of use clauses.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+_referencedContexts: Dict[str, 'Context']
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_referencedLibraries: Dict[str, 'Library']
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, 'Package']]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+ +
+
+class pyVHDLModel.IEEE.Std_logic_misc[source]
+

Predefined package ieee.std_logic_misc.

+

Inheritance

+
+

Inheritance diagram of Std_logic_misc

+
+
+
+
+__init__()[source]
+

Initializes a design unit.

+
+
Parameters:
+
    +

  • identifier – Identifier (name) of the design unit.

    • +

  • contextItems – A sequence of library, use or context clauses.

    • +

  • documentation – Associated documentation of the design unit.

    • +

  • parent – Reference to the logical parent in the model hierarchy.

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+IndexDeclaredItems()
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_contextItems: List['ContextUnion']
+

List of all context items (library, use and context clauses).

+
+ +
+
+_contextReferences: List['ContextReference']
+

List of context clauses.

+
+ +
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_libraryReferences: List['LibraryClause']
+

List of library clauses.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageReferences: List['UseClause']
+

List of use clauses.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+_referencedContexts: Dict[str, 'Context']
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_referencedLibraries: Dict[str, 'Library']
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, 'Package']]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+ +
+
+class pyVHDLModel.IEEE.Std_logic_misc_Body[source]
+

Predefined package body of package ieee.std_logic_misc.

+

Inheritance

+
+

Inheritance diagram of Std_logic_misc_Body

+
+
+
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+IndexDeclaredItems()
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__()
+

Initializes a design unit.

+
+
Parameters:
+
    +

  • identifier – Identifier (name) of the design unit.

    • +

  • contextItems – A sequence of library, use or context clauses.

    • +

  • documentation – Associated documentation of the design unit.

    • +

  • parent – Reference to the logical parent in the model hierarchy.

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_contextItems: List['ContextUnion']
+

List of all context items (library, use and context clauses).

+
+ +
+
+_contextReferences: List['ContextReference']
+

List of context clauses.

+
+ +
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_libraryReferences: List['LibraryClause']
+

List of library clauses.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageReferences: List['UseClause']
+

List of use clauses.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+_referencedContexts: Dict[str, 'Context']
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_referencedLibraries: Dict[str, 'Library']
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, 'Package']]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+ +
+
+class pyVHDLModel.IEEE.Numeric_Bit[source]
+

Predefined package ieee.numeric_bit.

+

Inheritance

+
+

Inheritance diagram of Numeric_Bit

+
+
+
+
+__init__()[source]
+

Initializes a design unit.

+
+
Parameters:
+
    +

  • identifier – Identifier (name) of the design unit.

    • +

  • contextItems – A sequence of library, use or context clauses.

    • +

  • documentation – Associated documentation of the design unit.

    • +

  • parent – Reference to the logical parent in the model hierarchy.

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+IndexDeclaredItems()
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_contextItems: List['ContextUnion']
+

List of all context items (library, use and context clauses).

+
+ +
+
+_contextReferences: List['ContextReference']
+

List of context clauses.

+
+ +
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_libraryReferences: List['LibraryClause']
+

List of library clauses.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageReferences: List['UseClause']
+

List of use clauses.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+_referencedContexts: Dict[str, 'Context']
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_referencedLibraries: Dict[str, 'Library']
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, 'Package']]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+ +
+
+class pyVHDLModel.IEEE.Numeric_Bit_Body[source]
+

Predefined package body of package ieee.numeric_bit.

+

Inheritance

+
+

Inheritance diagram of Numeric_Bit_Body

+
+
+
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+IndexDeclaredItems()
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__()
+

Initializes a design unit.

+
+
Parameters:
+
    +

  • identifier – Identifier (name) of the design unit.

    • +

  • contextItems – A sequence of library, use or context clauses.

    • +

  • documentation – Associated documentation of the design unit.

    • +

  • parent – Reference to the logical parent in the model hierarchy.

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_contextItems: List['ContextUnion']
+

List of all context items (library, use and context clauses).

+
+ +
+
+_contextReferences: List['ContextReference']
+

List of context clauses.

+
+ +
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_libraryReferences: List['LibraryClause']
+

List of library clauses.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageReferences: List['UseClause']
+

List of use clauses.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+_referencedContexts: Dict[str, 'Context']
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_referencedLibraries: Dict[str, 'Library']
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, 'Package']]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+ +
+
+class pyVHDLModel.IEEE.Numeric_Bit_Unsigned[source]
+

Predefined package ieee.numeric_bit_unsigned.

+

Inheritance

+
+

Inheritance diagram of Numeric_Bit_Unsigned

+
+
+
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+IndexDeclaredItems()
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__()
+

Initializes a design unit.

+
+
Parameters:
+
    +

  • identifier – Identifier (name) of the design unit.

    • +

  • contextItems – A sequence of library, use or context clauses.

    • +

  • documentation – Associated documentation of the design unit.

    • +

  • parent – Reference to the logical parent in the model hierarchy.

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_contextItems: List['ContextUnion']
+

List of all context items (library, use and context clauses).

+
+ +
+
+_contextReferences: List['ContextReference']
+

List of context clauses.

+
+ +
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_libraryReferences: List['LibraryClause']
+

List of library clauses.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageReferences: List['UseClause']
+

List of use clauses.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+_referencedContexts: Dict[str, 'Context']
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_referencedLibraries: Dict[str, 'Library']
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, 'Package']]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+ +
+
+class pyVHDLModel.IEEE.Numeric_Bit_Unsigned_Body[source]
+

Predefined package body of package ieee.numeric_bit_unsigned.

+

Inheritance

+
+

Inheritance diagram of Numeric_Bit_Unsigned_Body

+
+
+
+
+__init__()[source]
+

Initializes a design unit.

+
+
Parameters:
+
    +

  • identifier – Identifier (name) of the design unit.

    • +

  • contextItems – A sequence of library, use or context clauses.

    • +

  • documentation – Associated documentation of the design unit.

    • +

  • parent – Reference to the logical parent in the model hierarchy.

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+IndexDeclaredItems()
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_contextItems: List['ContextUnion']
+

List of all context items (library, use and context clauses).

+
+ +
+
+_contextReferences: List['ContextReference']
+

List of context clauses.

+
+ +
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_libraryReferences: List['LibraryClause']
+

List of library clauses.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageReferences: List['UseClause']
+

List of use clauses.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+_referencedContexts: Dict[str, 'Context']
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_referencedLibraries: Dict[str, 'Library']
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, 'Package']]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+ +
+
+class pyVHDLModel.IEEE.Numeric_Std[source]
+

Predefined package ieee.numeric_std.

+

Predefined types:

+
    +

  • unresolved_unsigned, unsigned

    • +

  • unresolved_signed, signed

    • +
+

Inheritance

+
+

Inheritance diagram of Numeric_Std

+
+
+
+
+__init__()[source]
+

Initializes a design unit.

+
+
Parameters:
+
    +

  • identifier – Identifier (name) of the design unit.

    • +

  • contextItems – A sequence of library, use or context clauses.

    • +

  • documentation – Associated documentation of the design unit.

    • +

  • parent – Reference to the logical parent in the model hierarchy.

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+IndexDeclaredItems()
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_contextItems: List['ContextUnion']
+

List of all context items (library, use and context clauses).

+
+ +
+
+_contextReferences: List['ContextReference']
+

List of context clauses.

+
+ +
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_libraryReferences: List['LibraryClause']
+

List of library clauses.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageReferences: List['UseClause']
+

List of use clauses.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+_referencedContexts: Dict[str, 'Context']
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_referencedLibraries: Dict[str, 'Library']
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, 'Package']]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+ +
+
+class pyVHDLModel.IEEE.Numeric_Std_Body[source]
+

Predefined package body of package ieee.numeric_std.

+

Inheritance

+
+

Inheritance diagram of Numeric_Std_Body

+
+
+
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+IndexDeclaredItems()
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__()
+

Initializes a design unit.

+
+
Parameters:
+
    +

  • identifier – Identifier (name) of the design unit.

    • +

  • contextItems – A sequence of library, use or context clauses.

    • +

  • documentation – Associated documentation of the design unit.

    • +

  • parent – Reference to the logical parent in the model hierarchy.

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_contextItems: List['ContextUnion']
+

List of all context items (library, use and context clauses).

+
+ +
+
+_contextReferences: List['ContextReference']
+

List of context clauses.

+
+ +
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_libraryReferences: List['LibraryClause']
+

List of library clauses.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageReferences: List['UseClause']
+

List of use clauses.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+_referencedContexts: Dict[str, 'Context']
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_referencedLibraries: Dict[str, 'Library']
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, 'Package']]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+ +
+
+class pyVHDLModel.IEEE.Numeric_Std_Unsigned[source]
+

Predefined package ieee.numeric_std_unsigned.

+

Inheritance

+
+

Inheritance diagram of Numeric_Std_Unsigned

+
+
+
+
+__init__()[source]
+

Initializes a design unit.

+
+
Parameters:
+
    +

  • identifier – Identifier (name) of the design unit.

    • +

  • contextItems – A sequence of library, use or context clauses.

    • +

  • documentation – Associated documentation of the design unit.

    • +

  • parent – Reference to the logical parent in the model hierarchy.

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+IndexDeclaredItems()
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_contextItems: List['ContextUnion']
+

List of all context items (library, use and context clauses).

+
+ +
+
+_contextReferences: List['ContextReference']
+

List of context clauses.

+
+ +
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_libraryReferences: List['LibraryClause']
+

List of library clauses.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageReferences: List['UseClause']
+

List of use clauses.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+_referencedContexts: Dict[str, 'Context']
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_referencedLibraries: Dict[str, 'Library']
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, 'Package']]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+ +
+
+class pyVHDLModel.IEEE.Numeric_Std_Unsigned_Body[source]
+

Predefined package body of package ieee.numeric_std_unsigned.

+

Inheritance

+
+

Inheritance diagram of Numeric_Std_Unsigned_Body

+
+
+
+
+__init__()[source]
+

Initializes a design unit.

+
+
Parameters:
+
    +

  • identifier – Identifier (name) of the design unit.

    • +

  • contextItems – A sequence of library, use or context clauses.

    • +

  • documentation – Associated documentation of the design unit.

    • +

  • parent – Reference to the logical parent in the model hierarchy.

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+IndexDeclaredItems()
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_contextItems: List['ContextUnion']
+

List of all context items (library, use and context clauses).

+
+ +
+
+_contextReferences: List['ContextReference']
+

List of context clauses.

+
+ +
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_libraryReferences: List['LibraryClause']
+

List of library clauses.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageReferences: List['UseClause']
+

List of use clauses.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+_referencedContexts: Dict[str, 'Context']
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_referencedLibraries: Dict[str, 'Library']
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, 'Package']]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+ +
+
+class pyVHDLModel.IEEE.Fixed_Float_Types[source]
+

Predefined package ieee.fixed_float_types.

+

Inheritance

+
+

Inheritance diagram of Fixed_Float_Types

+
+
+
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+IndexDeclaredItems()
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__()
+

Initializes a design unit.

+
+
Parameters:
+
    +

  • identifier – Identifier (name) of the design unit.

    • +

  • contextItems – A sequence of library, use or context clauses.

    • +

  • documentation – Associated documentation of the design unit.

    • +

  • parent – Reference to the logical parent in the model hierarchy.

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_contextItems: List['ContextUnion']
+

List of all context items (library, use and context clauses).

+
+ +
+
+_contextReferences: List['ContextReference']
+

List of context clauses.

+
+ +
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_libraryReferences: List['LibraryClause']
+

List of library clauses.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageReferences: List['UseClause']
+

List of use clauses.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+_referencedContexts: Dict[str, 'Context']
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_referencedLibraries: Dict[str, 'Library']
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, 'Package']]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+ +
+
+class pyVHDLModel.IEEE.Fixed_Generic_Pkg[source]
+

Predefined package ieee.fixed_generic_pkg.

+

Inheritance

+
+

Inheritance diagram of Fixed_Generic_Pkg

+
+
+
+
+__init__()[source]
+

Initializes a design unit.

+
+
Parameters:
+
    +

  • identifier – Identifier (name) of the design unit.

    • +

  • contextItems – A sequence of library, use or context clauses.

    • +

  • documentation – Associated documentation of the design unit.

    • +

  • parent – Reference to the logical parent in the model hierarchy.

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+IndexDeclaredItems()
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_contextItems: List['ContextUnion']
+

List of all context items (library, use and context clauses).

+
+ +
+
+_contextReferences: List['ContextReference']
+

List of context clauses.

+
+ +
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_libraryReferences: List['LibraryClause']
+

List of library clauses.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageReferences: List['UseClause']
+

List of use clauses.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+_referencedContexts: Dict[str, 'Context']
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_referencedLibraries: Dict[str, 'Library']
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, 'Package']]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+ +
+
+class pyVHDLModel.IEEE.Fixed_Generic_Pkg_Body[source]
+

Predefined package body of package ieee.fixed_generic_pkg.

+

Inheritance

+
+

Inheritance diagram of Fixed_Generic_Pkg_Body

+
+
+
+
+__init__()[source]
+

Initializes a design unit.

+
+
Parameters:
+
    +

  • identifier – Identifier (name) of the design unit.

    • +

  • contextItems – A sequence of library, use or context clauses.

    • +

  • documentation – Associated documentation of the design unit.

    • +

  • parent – Reference to the logical parent in the model hierarchy.

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+IndexDeclaredItems()
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_contextItems: List['ContextUnion']
+

List of all context items (library, use and context clauses).

+
+ +
+
+_contextReferences: List['ContextReference']
+

List of context clauses.

+
+ +
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_libraryReferences: List['LibraryClause']
+

List of library clauses.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageReferences: List['UseClause']
+

List of use clauses.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+_referencedContexts: Dict[str, 'Context']
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_referencedLibraries: Dict[str, 'Library']
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, 'Package']]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+ +
+
+class pyVHDLModel.IEEE.Fixed_Pkg[source]
+

Predefined package ieee.fixed_pkg.

+

Inheritance

+
+

Inheritance diagram of Fixed_Pkg

+
+
+
+
+__init__()[source]
+

Initializes a design unit.

+
+
Parameters:
+
    +

  • identifier – Identifier (name) of the design unit.

    • +

  • contextItems – A sequence of library, use or context clauses.

    • +

  • documentation – Associated documentation of the design unit.

    • +

  • parent – Reference to the logical parent in the model hierarchy.

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+IndexDeclaredItems()
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_contextItems: List['ContextUnion']
+

List of all context items (library, use and context clauses).

+
+ +
+
+_contextReferences: List['ContextReference']
+

List of context clauses.

+
+ +
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_libraryReferences: List['LibraryClause']
+

List of library clauses.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageReferences: List['UseClause']
+

List of use clauses.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+_referencedContexts: Dict[str, 'Context']
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_referencedLibraries: Dict[str, 'Library']
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, 'Package']]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+ +
+
+class pyVHDLModel.IEEE.Float_Generic_Pkg[source]
+

Predefined package ieee.float_generic_pkg.

+

Inheritance

+
+

Inheritance diagram of Float_Generic_Pkg

+
+
+
+
+__init__()[source]
+

Initializes a design unit.

+
+
Parameters:
+
    +

  • identifier – Identifier (name) of the design unit.

    • +

  • contextItems – A sequence of library, use or context clauses.

    • +

  • documentation – Associated documentation of the design unit.

    • +

  • parent – Reference to the logical parent in the model hierarchy.

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+IndexDeclaredItems()
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_contextItems: List['ContextUnion']
+

List of all context items (library, use and context clauses).

+
+ +
+
+_contextReferences: List['ContextReference']
+

List of context clauses.

+
+ +
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_libraryReferences: List['LibraryClause']
+

List of library clauses.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageReferences: List['UseClause']
+

List of use clauses.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+_referencedContexts: Dict[str, 'Context']
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_referencedLibraries: Dict[str, 'Library']
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, 'Package']]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+ +
+
+class pyVHDLModel.IEEE.Float_Generic_Pkg_Body[source]
+

Predefined package body of package ieee.float_generic_pkg.

+

Inheritance

+
+

Inheritance diagram of Float_Generic_Pkg_Body

+
+
+
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+IndexDeclaredItems()
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__()
+

Initializes a design unit.

+
+
Parameters:
+
    +

  • identifier – Identifier (name) of the design unit.

    • +

  • contextItems – A sequence of library, use or context clauses.

    • +

  • documentation – Associated documentation of the design unit.

    • +

  • parent – Reference to the logical parent in the model hierarchy.

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_contextItems: List['ContextUnion']
+

List of all context items (library, use and context clauses).

+
+ +
+
+_contextReferences: List['ContextReference']
+

List of context clauses.

+
+ +
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_libraryReferences: List['LibraryClause']
+

List of library clauses.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageReferences: List['UseClause']
+

List of use clauses.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+_referencedContexts: Dict[str, 'Context']
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_referencedLibraries: Dict[str, 'Library']
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, 'Package']]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+ +
+
+class pyVHDLModel.IEEE.Float_Pkg[source]
+

Predefined package ieee.float_pkg.

+

Inheritance

+
+

Inheritance diagram of Float_Pkg

+
+
+
+
+__init__()[source]
+

Initializes a design unit.

+
+
Parameters:
+
    +

  • identifier – Identifier (name) of the design unit.

    • +

  • contextItems – A sequence of library, use or context clauses.

    • +

  • documentation – Associated documentation of the design unit.

    • +

  • parent – Reference to the logical parent in the model hierarchy.

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+IndexDeclaredItems()
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_contextItems: List['ContextUnion']
+

List of all context items (library, use and context clauses).

+
+ +
+
+_contextReferences: List['ContextReference']
+

List of context clauses.

+
+ +
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_libraryReferences: List['LibraryClause']
+

List of library clauses.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageReferences: List['UseClause']
+

List of use clauses.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+_referencedContexts: Dict[str, 'Context']
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_referencedLibraries: Dict[str, 'Library']
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, 'Package']]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+ +
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/pyVHDLModel/pyVHDLModel.Instantiation.html b/pyVHDLModel/pyVHDLModel.Instantiation.html new file mode 100644 index 000000000..5eefe6479 --- /dev/null +++ b/pyVHDLModel/pyVHDLModel.Instantiation.html @@ -0,0 +1,931 @@ + + + + + + + pyVHDLModel.Instantiation — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

pyVHDLModel.Instantiation

+

This module contains parts of an abstract document language model for VHDL.

+

Instantiations of packages, procedures, functions and protected types.

+

Classes

+ +
+

Classes

+
+
+class pyVHDLModel.Instantiation.GenericInstantiationMixin[source]
+

Inheritance

+
+

Inheritance diagram of GenericInstantiationMixin

+
+
+
+
+__init__()[source]
+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+ +
+
+class pyVHDLModel.Instantiation.GenericEntityInstantiationMixin[source]
+

Inheritance

+
+

Inheritance diagram of GenericEntityInstantiationMixin

+
+
+
+
+__init__()[source]
+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+ +
+
+class pyVHDLModel.Instantiation.SubprogramInstantiationMixin[source]
+

Inheritance

+
+

Inheritance diagram of SubprogramInstantiationMixin

+
+
+
+
+__init__()[source]
+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+ +
+
+class pyVHDLModel.Instantiation.ProcedureInstantiation(identifier, documentation=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of ProcedureInstantiation

+
+
Parameters:
+
+
+
+
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(identifier, documentation=None, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
    +

  • parent (ModelEntity) – The parent model entity of this entity.

    • +

  • identifier (str)

    • +

  • documentation (str | None)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Instantiation.FunctionInstantiation(identifier, isPure=True, documentation=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of FunctionInstantiation

+
+
Parameters:
+
+
+
+
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(identifier, isPure=True, documentation=None, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
    +

  • parent (ModelEntity) – The parent model entity of this entity.

    • +

  • identifier (str)

    • +

  • isPure (bool)

    • +

  • documentation (str | None)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Instantiation.PackageInstantiation(identifier, uninstantiatedPackage, documentation=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of PackageInstantiation

+
+
Parameters:
+
+
+
+
+
+__init__(identifier, uninstantiatedPackage, documentation=None, parent=None)[source]
+

Initializes a design unit.

+
+
Parameters:
+
    +

  • identifier (str) – Identifier (name) of the design unit.

    • +

  • contextItems – A sequence of library, use or context clauses.

    • +

  • documentation (Optional[str]) – Associated documentation of the design unit.

    • +

  • parent (ModelEntity) – Reference to the logical parent in the model hierarchy.

    • +

  • uninstantiatedPackage (PackageReferenceSymbol)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_contextItems: List['ContextUnion']
+

List of all context items (library, use and context clauses).

+
+ +
+
+_contextReferences: List['ContextReference']
+

List of context clauses.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_libraryReferences: List['LibraryClause']
+

List of library clauses.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageReferences: List['UseClause']
+

List of use clauses.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_referencedContexts: Dict[str, 'Context']
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_referencedLibraries: Dict[str, 'Library']
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, 'Package']]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+ +
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/pyVHDLModel/pyVHDLModel.Interface.html b/pyVHDLModel/pyVHDLModel.Interface.html new file mode 100644 index 000000000..8d6f041c9 --- /dev/null +++ b/pyVHDLModel/pyVHDLModel.Interface.html @@ -0,0 +1,2115 @@ + + + + + + + pyVHDLModel.Interface — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

pyVHDLModel.Interface

+

This module contains parts of an abstract document language model for VHDL.

+

Interface items are used in generic, port and parameter declarations.

+

Classes

+ +
+

Classes

+
+
+class pyVHDLModel.Interface.InterfaceItemMixin(documentation=None)[source]
+

An InterfaceItem is a base-class for all mixin-classes for all interface items.

+

Inheritance

+
+

Inheritance diagram of InterfaceItemMixin

+
+
Parameters:
+

documentation (str | None)

+
+
+
+
+__init__(documentation=None)[source]
+

Initializes a documented entity.

+
+
Parameters:
+

documentation (Optional[str]) – Documentation of a model entity.

+
+
Return type:
+

None

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+_documentation: Optional[str]
+

The associated documentation of a model entity.

+
+ +
+ +
+
+class pyVHDLModel.Interface.InterfaceItemWithModeMixin(mode)[source]
+

An InterfaceItemWithMode is a mixin-class to provide a Mode to interface items.

+

Inheritance

+
+

Inheritance diagram of InterfaceItemWithModeMixin

+
+
Parameters:
+

mode (Mode)

+
+
+
+
+__init__(mode)[source]
+
+
Parameters:
+

mode (Mode)

+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+ +
+
+class pyVHDLModel.Interface.GenericInterfaceItemMixin(documentation=None)[source]
+

A GenericInterfaceItem is a mixin class for all generic interface items.

+

Inheritance

+
+

Inheritance diagram of GenericInterfaceItemMixin

+
+
Parameters:
+

documentation (str | None)

+
+
+
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+__init__(documentation=None)
+

Initializes a documented entity.

+
+
Parameters:
+

documentation (Optional[str]) – Documentation of a model entity.

+
+
Return type:
+

None

+
+
+
+ +
+
+_documentation: Optional[str]
+

The associated documentation of a model entity.

+
+ +
+ +
+
+class pyVHDLModel.Interface.PortInterfaceItemMixin(mode)[source]
+

A PortInterfaceItem is a mixin class for all port interface items.

+

Inheritance

+
+

Inheritance diagram of PortInterfaceItemMixin

+
+
Parameters:
+

mode (Mode)

+
+
+
+
+__init__(mode)[source]
+

Initializes a documented entity.

+
+
Parameters:
+
    +

  • documentation – Documentation of a model entity.

    • +

  • mode (Mode)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+_documentation: Optional[str]
+

The associated documentation of a model entity.

+
+ +
+ +
+
+class pyVHDLModel.Interface.ParameterInterfaceItemMixin(documentation=None)[source]
+

A ParameterInterfaceItem is a mixin class for all parameter interface items.

+

Inheritance

+
+

Inheritance diagram of ParameterInterfaceItemMixin

+
+
Parameters:
+

documentation (str | None)

+
+
+
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+__init__(documentation=None)
+

Initializes a documented entity.

+
+
Parameters:
+

documentation (Optional[str]) – Documentation of a model entity.

+
+
Return type:
+

None

+
+
+
+ +
+
+_documentation: Optional[str]
+

The associated documentation of a model entity.

+
+ +
+ +
+
+class pyVHDLModel.Interface.GenericConstantInterfaceItem(identifiers, mode, subtype, defaultExpression=None, documentation=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of GenericConstantInterfaceItem

+
+
Parameters:
+
+
+
+
+
+__init__(identifiers, mode, subtype, defaultExpression=None, documentation=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifiers: Tuple[str]
+

Returns a model entity’s tuple of identifiers (names).

+
+
Returns:
+

Tuple of identifiers.

+
+
+
+ +
+
+property NormalizedIdentifiers: Tuple[str]
+

Returns a model entity’s tuple of normalized identifiers (lower case names).

+
+
Returns:
+

Tuple of normalized identifiers.

+
+
+
+ +
+
+property ObjectVertex: Vertex | None
+

Read-only property to access the corresponding object vertex (_objectVertex).

+

The object vertex references this Object by its value field.

+
+
Returns:
+

The corresponding object vertex.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_identifiers: Tuple[str]
+

A list of identifiers.

+
+ +
+
+_normalizedIdentifiers: Tuple[str]
+

A list of normalized (lower case) identifiers.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Interface.GenericTypeInterfaceItem(identifier, documentation=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of GenericTypeInterfaceItem

+
+
Parameters:
+
+
+
+
+
+__init__(identifier, documentation=None, parent=None)[source]
+

Initializes underlying BaseType.

+
+
Parameters:
+
    +

  • identifier (str) – Name of the type.

    • +

  • parent (ModelEntity) – Reference to the logical parent in the model hierarchy.

    • +

  • documentation (str | None)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Interface.GenericSubprogramInterfaceItem(documentation=None)[source]
+

Inheritance

+
+

Inheritance diagram of GenericSubprogramInterfaceItem

+
+
Parameters:
+

documentation (str | None)

+
+
+
+
+_documentation: Optional[str]
+

The associated documentation of a model entity.

+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+__init__(documentation=None)
+

Initializes a documented entity.

+
+
Parameters:
+

documentation (Optional[str]) – Documentation of a model entity.

+
+
Return type:
+

None

+
+
+
+ +
+ +
+
+class pyVHDLModel.Interface.GenericProcedureInterfaceItem(identifier, documentation=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of GenericProcedureInterfaceItem

+
+
Parameters:
+
+
+
+
+
+__init__(identifier, documentation=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
    +

  • parent (ModelEntity) – The parent model entity of this entity.

    • +

  • identifier (str)

    • +

  • documentation (str | None)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Interface.GenericFunctionInterfaceItem(identifier, documentation=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of GenericFunctionInterfaceItem

+
+
Parameters:
+
+
+
+
+
+__init__(identifier, documentation=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
    +

  • parent (ModelEntity) – The parent model entity of this entity.

    • +

  • identifier (str)

    • +

  • documentation (str | None)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Interface.GenericPackageInterfaceItem(identifier, documentation=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of GenericPackageInterfaceItem

+
+
Parameters:
+
+
+
+
+
+__init__(identifier, documentation=None, parent=None)[source]
+

Initializes a documented entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+_documentation: Optional[str]
+

The associated documentation of a model entity.

+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+ +
+
+class pyVHDLModel.Interface.PortSignalInterfaceItem(identifiers, mode, subtype, defaultExpression=None, documentation=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of PortSignalInterfaceItem

+
+
Parameters:
+
+
+
+
+
+__init__(identifiers, mode, subtype, defaultExpression=None, documentation=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifiers: Tuple[str]
+

Returns a model entity’s tuple of identifiers (names).

+
+
Returns:
+

Tuple of identifiers.

+
+
+
+ +
+
+property NormalizedIdentifiers: Tuple[str]
+

Returns a model entity’s tuple of normalized identifiers (lower case names).

+
+
Returns:
+

Tuple of normalized identifiers.

+
+
+
+ +
+
+property ObjectVertex: Vertex | None
+

Read-only property to access the corresponding object vertex (_objectVertex).

+

The object vertex references this Object by its value field.

+
+
Returns:
+

The corresponding object vertex.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_identifiers: Tuple[str]
+

A list of identifiers.

+
+ +
+
+_normalizedIdentifiers: Tuple[str]
+

A list of normalized (lower case) identifiers.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Interface.ParameterConstantInterfaceItem(identifiers, mode, subtype, defaultExpression=None, documentation=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of ParameterConstantInterfaceItem

+
+
Parameters:
+
+
+
+
+
+__init__(identifiers, mode, subtype, defaultExpression=None, documentation=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifiers: Tuple[str]
+

Returns a model entity’s tuple of identifiers (names).

+
+
Returns:
+

Tuple of identifiers.

+
+
+
+ +
+
+property NormalizedIdentifiers: Tuple[str]
+

Returns a model entity’s tuple of normalized identifiers (lower case names).

+
+
Returns:
+

Tuple of normalized identifiers.

+
+
+
+ +
+
+property ObjectVertex: Vertex | None
+

Read-only property to access the corresponding object vertex (_objectVertex).

+

The object vertex references this Object by its value field.

+
+
Returns:
+

The corresponding object vertex.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_identifiers: Tuple[str]
+

A list of identifiers.

+
+ +
+
+_normalizedIdentifiers: Tuple[str]
+

A list of normalized (lower case) identifiers.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Interface.ParameterVariableInterfaceItem(identifiers, mode, subtype, defaultExpression=None, documentation=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of ParameterVariableInterfaceItem

+
+
Parameters:
+
+
+
+
+
+__init__(identifiers, mode, subtype, defaultExpression=None, documentation=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifiers: Tuple[str]
+

Returns a model entity’s tuple of identifiers (names).

+
+
Returns:
+

Tuple of identifiers.

+
+
+
+ +
+
+property NormalizedIdentifiers: Tuple[str]
+

Returns a model entity’s tuple of normalized identifiers (lower case names).

+
+
Returns:
+

Tuple of normalized identifiers.

+
+
+
+ +
+
+property ObjectVertex: Vertex | None
+

Read-only property to access the corresponding object vertex (_objectVertex).

+

The object vertex references this Object by its value field.

+
+
Returns:
+

The corresponding object vertex.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_identifiers: Tuple[str]
+

A list of identifiers.

+
+ +
+
+_normalizedIdentifiers: Tuple[str]
+

A list of normalized (lower case) identifiers.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Interface.ParameterSignalInterfaceItem(identifiers, mode, subtype, defaultExpression=None, documentation=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of ParameterSignalInterfaceItem

+
+
Parameters:
+
+
+
+
+
+__init__(identifiers, mode, subtype, defaultExpression=None, documentation=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifiers: Tuple[str]
+

Returns a model entity’s tuple of identifiers (names).

+
+
Returns:
+

Tuple of identifiers.

+
+
+
+ +
+
+property NormalizedIdentifiers: Tuple[str]
+

Returns a model entity’s tuple of normalized identifiers (lower case names).

+
+
Returns:
+

Tuple of normalized identifiers.

+
+
+
+ +
+
+property ObjectVertex: Vertex | None
+

Read-only property to access the corresponding object vertex (_objectVertex).

+

The object vertex references this Object by its value field.

+
+
Returns:
+

The corresponding object vertex.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_identifiers: Tuple[str]
+

A list of identifiers.

+
+ +
+
+_normalizedIdentifiers: Tuple[str]
+

A list of normalized (lower case) identifiers.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Interface.ParameterFileInterfaceItem(identifiers, subtype, documentation=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of ParameterFileInterfaceItem

+
+
Parameters:
+
+
+
+
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifiers: Tuple[str]
+

Returns a model entity’s tuple of identifiers (names).

+
+
Returns:
+

Tuple of identifiers.

+
+
+
+ +
+
+property NormalizedIdentifiers: Tuple[str]
+

Returns a model entity’s tuple of normalized identifiers (lower case names).

+
+
Returns:
+

Tuple of normalized identifiers.

+
+
+
+ +
+
+property ObjectVertex: Vertex | None
+

Read-only property to access the corresponding object vertex (_objectVertex).

+

The object vertex references this Object by its value field.

+
+
Returns:
+

The corresponding object vertex.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(identifiers, subtype, documentation=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+_identifiers: Tuple[str]
+

A list of identifiers.

+
+ +
+
+_normalizedIdentifiers: Tuple[str]
+

A list of normalized (lower case) identifiers.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/pyVHDLModel/pyVHDLModel.Name.html b/pyVHDLModel/pyVHDLModel.Name.html new file mode 100644 index 000000000..eb4df7efb --- /dev/null +++ b/pyVHDLModel/pyVHDLModel.Name.html @@ -0,0 +1,1743 @@ + + + + + + + pyVHDLModel.Name — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

pyVHDLModel.Name

+

This module contains parts of an abstract document language model for VHDL.

+

VHDL uses names to express cross-references from usage locations to declarations. Here, names are single or +combined identifiers. Symbols are structures representing a name and a reference +(pointer) to the referenced vhdl language entity.

+

Classes

+
    +

  • Name: +Name is the base-class for all names in the VHDL language model.

    • +

  • SimpleName: +A simple name is a name made from a single word.

    • +

  • ParenthesisName: +Name is the base-class for all names in the VHDL language model.

    • +

  • IndexedName: +Name is the base-class for all names in the VHDL language model.

    • +

  • SlicedName: +Name is the base-class for all names in the VHDL language model.

    • +

  • SelectedName: +A selected name is a name made from multiple words separated by a dot (.).

    • +

  • AttributeName: +Name is the base-class for all names in the VHDL language model.

    • +

  • AllName: +The all name represents the reserved word all used in names.

    • +

  • OpenName: +The open name represents the reserved word open.

    • +
+
+

Classes

+
+
+class pyVHDLModel.Name.Name(identifier, prefix=None, parent=None)[source]
+

Name is the base-class for all names in the VHDL language model.

+

Inheritance

+
+

Inheritance diagram of Name

+
+
Parameters:
+
+
+
+
+
+__init__(identifier, prefix=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
    +

  • parent (ModelEntity) – The parent model entity of this entity.

    • +

  • identifier (str)

    • +

  • prefix (Name | None)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+property Identifier: str
+

The identifier the name is referencing.

+
+
Returns:
+

The referenced identifier.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

The normalized identifier the name is referencing.

+
+
Returns:
+

The referenced identifier (normalized).

+
+
+
+ +
+
+property Root: Name
+

The root (left-most) element in a chain of names.

+

In case the name is a simple name, the root points to the name itself.

+
+
Returns:
+

The name’s root element.

+
+
+
+ +
+
+property Prefix: Name | None
+

The name’s prefix in a chain of names.

+
+
Returns:
+

The name left from current name, if not a simple name, otherwise None.

+
+
+
+ +
+
+property HasPrefix: bool
+

Returns true, if the name has a prefix.

+

This is true for all names except simple names.

+
+
Returns:
+

True, if the name as a prefix.

+
+
+
+ +
+
+__repr__()[source]
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Name.SimpleName(identifier, prefix=None, parent=None)[source]
+

A simple name is a name made from a single word.

+

For example, the entity name in an architecture declaration is a simple name, while the name of the architecture +itself is an identifier. The simple name references is again an identifier in the entity declaration, thus names +reference other (already) declared language entities.

+

Inheritance

+
+

Inheritance diagram of SimpleName

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HasPrefix: bool
+

Returns true, if the name has a prefix.

+

This is true for all names except simple names.

+
+
Returns:
+

True, if the name as a prefix.

+
+
+
+ +
+
+property Identifier: str
+

The identifier the name is referencing.

+
+
Returns:
+

The referenced identifier.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

The normalized identifier the name is referencing.

+
+
Returns:
+

The referenced identifier (normalized).

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+property Prefix: Name | None
+

The name’s prefix in a chain of names.

+
+
Returns:
+

The name left from current name, if not a simple name, otherwise None.

+
+
+
+ +
+
+property Root: Name
+

The root (left-most) element in a chain of names.

+

In case the name is a simple name, the root points to the name itself.

+
+
Returns:
+

The name’s root element.

+
+
+
+ +
+
+__init__(identifier, prefix=None, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
    +

  • parent (ModelEntity) – The parent model entity of this entity.

    • +

  • identifier (str)

    • +

  • prefix (Name | None)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Name.ParenthesisName(prefix, associations, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of ParenthesisName

+
+
Parameters:
+
+
+
+
+
+__init__(prefix, associations, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HasPrefix: bool
+

Returns true, if the name has a prefix.

+

This is true for all names except simple names.

+
+
Returns:
+

True, if the name as a prefix.

+
+
+
+ +
+
+property Identifier: str
+

The identifier the name is referencing.

+
+
Returns:
+

The referenced identifier.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

The normalized identifier the name is referencing.

+
+
Returns:
+

The referenced identifier (normalized).

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+property Prefix: Name | None
+

The name’s prefix in a chain of names.

+
+
Returns:
+

The name left from current name, if not a simple name, otherwise None.

+
+
+
+ +
+
+property Root: Name
+

The root (left-most) element in a chain of names.

+

In case the name is a simple name, the root points to the name itself.

+
+
Returns:
+

The name’s root element.

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Name.IndexedName(prefix, indices, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of IndexedName

+
+
Parameters:
+
+
+
+
+
+__init__(prefix, indices, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HasPrefix: bool
+

Returns true, if the name has a prefix.

+

This is true for all names except simple names.

+
+
Returns:
+

True, if the name as a prefix.

+
+
+
+ +
+
+property Identifier: str
+

The identifier the name is referencing.

+
+
Returns:
+

The referenced identifier.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

The normalized identifier the name is referencing.

+
+
Returns:
+

The referenced identifier (normalized).

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+property Prefix: Name | None
+

The name’s prefix in a chain of names.

+
+
Returns:
+

The name left from current name, if not a simple name, otherwise None.

+
+
+
+ +
+
+property Root: Name
+

The root (left-most) element in a chain of names.

+

In case the name is a simple name, the root points to the name itself.

+
+
Returns:
+

The name’s root element.

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Name.SlicedName(identifier, prefix=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of SlicedName

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HasPrefix: bool
+

Returns true, if the name has a prefix.

+

This is true for all names except simple names.

+
+
Returns:
+

True, if the name as a prefix.

+
+
+
+ +
+
+property Identifier: str
+

The identifier the name is referencing.

+
+
Returns:
+

The referenced identifier.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

The normalized identifier the name is referencing.

+
+
Returns:
+

The referenced identifier (normalized).

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+property Prefix: Name | None
+

The name’s prefix in a chain of names.

+
+
Returns:
+

The name left from current name, if not a simple name, otherwise None.

+
+
+
+ +
+
+property Root: Name
+

The root (left-most) element in a chain of names.

+

In case the name is a simple name, the root points to the name itself.

+
+
Returns:
+

The name’s root element.

+
+
+
+ +
+
+__init__(identifier, prefix=None, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
    +

  • parent (ModelEntity) – The parent model entity of this entity.

    • +

  • identifier (str)

    • +

  • prefix (Name | None)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Name.SelectedName(identifier, prefix, parent=None)[source]
+

A selected name is a name made from multiple words separated by a dot (.).

+

For example, the library and entity name in a direct entity instantiation is a selected name. Here the entity +identifier is a selected name. The library identifier is a simple name, which is +referenced by the selected name via the Prefix property.

+

Inheritance

+
+

Inheritance diagram of SelectedName

+
+
Parameters:
+
+
+
+
+
+__init__(identifier, prefix, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
    +

  • parent (ModelEntity) – The parent model entity of this entity.

    • +

  • identifier (str)

    • +

  • prefix (Name)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HasPrefix: bool
+

Returns true, if the name has a prefix.

+

This is true for all names except simple names.

+
+
Returns:
+

True, if the name as a prefix.

+
+
+
+ +
+
+property Identifier: str
+

The identifier the name is referencing.

+
+
Returns:
+

The referenced identifier.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

The normalized identifier the name is referencing.

+
+
Returns:
+

The referenced identifier (normalized).

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+property Prefix: Name | None
+

The name’s prefix in a chain of names.

+
+
Returns:
+

The name left from current name, if not a simple name, otherwise None.

+
+
+
+ +
+
+property Root: Name
+

The root (left-most) element in a chain of names.

+

In case the name is a simple name, the root points to the name itself.

+
+
Returns:
+

The name’s root element.

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Name.AttributeName(identifier, prefix, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of AttributeName

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HasPrefix: bool
+

Returns true, if the name has a prefix.

+

This is true for all names except simple names.

+
+
Returns:
+

True, if the name as a prefix.

+
+
+
+ +
+
+property Identifier: str
+

The identifier the name is referencing.

+
+
Returns:
+

The referenced identifier.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

The normalized identifier the name is referencing.

+
+
Returns:
+

The referenced identifier (normalized).

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+property Prefix: Name | None
+

The name’s prefix in a chain of names.

+
+
Returns:
+

The name left from current name, if not a simple name, otherwise None.

+
+
+
+ +
+
+property Root: Name
+

The root (left-most) element in a chain of names.

+

In case the name is a simple name, the root points to the name itself.

+
+
Returns:
+

The name’s root element.

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+__init__(identifier, prefix, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
    +

  • parent (ModelEntity) – The parent model entity of this entity.

    • +

  • identifier (str)

    • +

  • prefix (Name)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+ +
+
+class pyVHDLModel.Name.AllName(prefix, parent=None)[source]
+

The all name represents the reserved word all used in names.

+

Most likely this name is used in use-statements.

+

Inheritance

+
+

Inheritance diagram of AllName

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HasPrefix: bool
+

Returns true, if the name has a prefix.

+

This is true for all names except simple names.

+
+
Returns:
+

True, if the name as a prefix.

+
+
+
+ +
+
+property Identifier: str
+

The identifier the name is referencing.

+
+
Returns:
+

The referenced identifier.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

The normalized identifier the name is referencing.

+
+
Returns:
+

The referenced identifier (normalized).

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+property Prefix: Name | None
+

The name’s prefix in a chain of names.

+
+
Returns:
+

The name left from current name, if not a simple name, otherwise None.

+
+
+
+ +
+
+property Root: Name
+

The root (left-most) element in a chain of names.

+

In case the name is a simple name, the root points to the name itself.

+
+
Returns:
+

The name’s root element.

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+__init__(prefix, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
    +

  • parent (ModelEntity) – The parent model entity of this entity.

    • +

  • prefix (Name)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+ +
+
+class pyVHDLModel.Name.OpenName(parent=None)[source]
+

The open name represents the reserved word open.

+

Most likely this name is used in port associations.

+

Inheritance

+
+

Inheritance diagram of OpenName

+
+
Parameters:
+

parent (ModelEntity)

+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HasPrefix: bool
+

Returns true, if the name has a prefix.

+

This is true for all names except simple names.

+
+
Returns:
+

True, if the name as a prefix.

+
+
+
+ +
+
+property Identifier: str
+

The identifier the name is referencing.

+
+
Returns:
+

The referenced identifier.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

The normalized identifier the name is referencing.

+
+
Returns:
+

The referenced identifier (normalized).

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+property Prefix: Name | None
+

The name’s prefix in a chain of names.

+
+
Returns:
+

The name left from current name, if not a simple name, otherwise None.

+
+
+
+ +
+
+property Root: Name
+

The root (left-most) element in a chain of names.

+

In case the name is a simple name, the root points to the name itself.

+
+
Returns:
+

The name’s root element.

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+__init__(parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+

parent (ModelEntity) – The parent model entity of this entity.

+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+ +
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/pyVHDLModel/pyVHDLModel.Namespace.html b/pyVHDLModel/pyVHDLModel.Namespace.html new file mode 100644 index 000000000..8080a572f --- /dev/null +++ b/pyVHDLModel/pyVHDLModel.Namespace.html @@ -0,0 +1,201 @@ + + + + + + + pyVHDLModel.Namespace — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

pyVHDLModel.Namespace

+

This module contains parts of an abstract document language model for VHDL.

+

A helper class to implement namespaces and scopes.

+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/pyVHDLModel/pyVHDLModel.Object.html b/pyVHDLModel/pyVHDLModel.Object.html new file mode 100644 index 000000000..b27b6d12e --- /dev/null +++ b/pyVHDLModel/pyVHDLModel.Object.html @@ -0,0 +1,1584 @@ + + + + + + + pyVHDLModel.Object — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

pyVHDLModel.Object

+

This module contains parts of an abstract document language model for VHDL.

+

Objects are constants, variables, signals and files.

+

Classes

+
    +

  • Obj: +Base-class for all objects (constants, signals, variables and files) in VHDL.

    • +

  • WithDefaultExpressionMixin: +A WithDefaultExpression is a mixin-class for all objects declarations accepting default expressions.

    • +

  • BaseConstant: +Base-class for all constants (normal and deferred constants) in VHDL.

    • +

  • Constant: +Represents a constant.

    • +

  • DeferredConstant: +Represents a deferred constant.

    • +

  • Variable: +Represents a variable.

    • +

  • SharedVariable: +Represents a shared variable.

    • +

  • Signal: +Represents a signal.

    • +

  • File: +Represents a file.

    • +
+
+

Classes

+
+
+class pyVHDLModel.Object.Obj(identifiers, subtype, documentation=None, parent=None)[source]
+

Base-class for all objects (constants, signals, variables and files) in VHDL.

+

An object (syntax element) can define multiple objects (semantic elements) in a single declaration, thus +MultipleNamedEntityMixin is inherited. All objects can be documented, thus +DocumentedEntityMixin is inherited too.

+

Each object references a subtype via _subtype.

+

Objects are elements in the type and object graph, thus a reference to a vertex in that graph is stored in +__objectVertex.

+

Inheritance

+
+

Inheritance diagram of Obj

+
+
Parameters:
+
+
+
+
+
+__init__(identifiers, subtype, documentation=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+property ObjectVertex: Vertex | None
+

Read-only property to access the corresponding object vertex (_objectVertex).

+

The object vertex references this Object by its value field.

+
+
Returns:
+

The corresponding object vertex.

+
+
+
+ +
+
+_identifiers: Tuple[str]
+

A list of identifiers.

+
+ +
+
+_normalizedIdentifiers: Tuple[str]
+

A list of normalized (lower case) identifiers.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifiers: Tuple[str]
+

Returns a model entity’s tuple of identifiers (names).

+
+
Returns:
+

Tuple of identifiers.

+
+
+
+ +
+
+property NormalizedIdentifiers: Tuple[str]
+

Returns a model entity’s tuple of normalized identifiers (lower case names).

+
+
Returns:
+

Tuple of normalized identifiers.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Object.WithDefaultExpressionMixin(defaultExpression=None)[source]
+

A WithDefaultExpression is a mixin-class for all objects declarations accepting default expressions.

+

The default expression is referenced by __defaultExpression. If no default expression is present, this field +is None.

+

Inheritance

+
+

Inheritance diagram of WithDefaultExpressionMixin

+
+
Parameters:
+

defaultExpression (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal | None)

+
+
+
+
+__init__(defaultExpression=None)[source]
+
+
Parameters:
+

defaultExpression (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal | None)

+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+ +
+
+class pyVHDLModel.Object.BaseConstant(identifiers, subtype, documentation=None, parent=None)[source]
+

Base-class for all constants (normal and deferred constants) in VHDL.

+

Inheritance

+
+

Inheritance diagram of BaseConstant

+
+
Parameters:
+
+
+
+
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifiers: Tuple[str]
+

Returns a model entity’s tuple of identifiers (names).

+
+
Returns:
+

Tuple of identifiers.

+
+
+
+ +
+
+property NormalizedIdentifiers: Tuple[str]
+

Returns a model entity’s tuple of normalized identifiers (lower case names).

+
+
Returns:
+

Tuple of normalized identifiers.

+
+
+
+ +
+
+property ObjectVertex: Vertex | None
+

Read-only property to access the corresponding object vertex (_objectVertex).

+

The object vertex references this Object by its value field.

+
+
Returns:
+

The corresponding object vertex.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(identifiers, subtype, documentation=None, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_identifiers: Tuple[str]
+

A list of identifiers.

+
+ +
+
+_normalizedIdentifiers: Tuple[str]
+

A list of normalized (lower case) identifiers.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Object.Constant(identifiers, subtype, defaultExpression=None, documentation=None, parent=None)[source]
+

Represents a constant.

+

As constants (always) have a default expression, the class WithDefaultExpressionMixin is inherited.

+
+

Example

+
constant BITS : positive := 8;
+
+
+
+

Inheritance

+
+

Inheritance diagram of Constant

+
+
Parameters:
+
+
+
+
+
+__init__(identifiers, subtype, defaultExpression=None, documentation=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifiers: Tuple[str]
+

Returns a model entity’s tuple of identifiers (names).

+
+
Returns:
+

Tuple of identifiers.

+
+
+
+ +
+
+property NormalizedIdentifiers: Tuple[str]
+

Returns a model entity’s tuple of normalized identifiers (lower case names).

+
+
Returns:
+

Tuple of normalized identifiers.

+
+
+
+ +
+
+property ObjectVertex: Vertex | None
+

Read-only property to access the corresponding object vertex (_objectVertex).

+

The object vertex references this Object by its value field.

+
+
Returns:
+

The corresponding object vertex.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_identifiers: Tuple[str]
+

A list of identifiers.

+
+ +
+
+_normalizedIdentifiers: Tuple[str]
+

A list of normalized (lower case) identifiers.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Object.DeferredConstant(identifiers, subtype, documentation=None, parent=None)[source]
+

Represents a deferred constant.

+

Deferred constants are forward declarations for a (complete) constant declaration, thus it contains a +field __constantReference to the complete constant declaration.

+
+

Example

+
constant BITS : positive;
+
+
+
+

Inheritance

+
+

Inheritance diagram of DeferredConstant

+
+
Parameters:
+
+
+
+
+
+__init__(identifiers, subtype, documentation=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifiers: Tuple[str]
+

Returns a model entity’s tuple of identifiers (names).

+
+
Returns:
+

Tuple of identifiers.

+
+
+
+ +
+
+property NormalizedIdentifiers: Tuple[str]
+

Returns a model entity’s tuple of normalized identifiers (lower case names).

+
+
Returns:
+

Tuple of normalized identifiers.

+
+
+
+ +
+
+property ObjectVertex: Vertex | None
+

Read-only property to access the corresponding object vertex (_objectVertex).

+

The object vertex references this Object by its value field.

+
+
Returns:
+

The corresponding object vertex.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_identifiers: Tuple[str]
+

A list of identifiers.

+
+ +
+
+_normalizedIdentifiers: Tuple[str]
+

A list of normalized (lower case) identifiers.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Object.Variable(identifiers, subtype, defaultExpression=None, documentation=None, parent=None)[source]
+

Represents a variable.

+

As variables might have a default expression, the class WithDefaultExpressionMixin is inherited.

+
+

Example

+
variable result : natural := 0;
+
+
+
+

Inheritance

+
+

Inheritance diagram of Variable

+
+
Parameters:
+
+
+
+
+
+__init__(identifiers, subtype, defaultExpression=None, documentation=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifiers: Tuple[str]
+

Returns a model entity’s tuple of identifiers (names).

+
+
Returns:
+

Tuple of identifiers.

+
+
+
+ +
+
+property NormalizedIdentifiers: Tuple[str]
+

Returns a model entity’s tuple of normalized identifiers (lower case names).

+
+
Returns:
+

Tuple of normalized identifiers.

+
+
+
+ +
+
+property ObjectVertex: Vertex | None
+

Read-only property to access the corresponding object vertex (_objectVertex).

+

The object vertex references this Object by its value field.

+
+
Returns:
+

The corresponding object vertex.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_identifiers: Tuple[str]
+

A list of identifiers.

+
+ +
+
+_normalizedIdentifiers: Tuple[str]
+

A list of normalized (lower case) identifiers.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Object.SharedVariable(identifiers, subtype, documentation=None, parent=None)[source]
+

Represents a shared variable.

+
+

Todo

+

Shared variable object not implemented.

+
+

Inheritance

+
+

Inheritance diagram of SharedVariable

+
+
Parameters:
+
+
+
+
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifiers: Tuple[str]
+

Returns a model entity’s tuple of identifiers (names).

+
+
Returns:
+

Tuple of identifiers.

+
+
+
+ +
+
+property NormalizedIdentifiers: Tuple[str]
+

Returns a model entity’s tuple of normalized identifiers (lower case names).

+
+
Returns:
+

Tuple of normalized identifiers.

+
+
+
+ +
+
+property ObjectVertex: Vertex | None
+

Read-only property to access the corresponding object vertex (_objectVertex).

+

The object vertex references this Object by its value field.

+
+
Returns:
+

The corresponding object vertex.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(identifiers, subtype, documentation=None, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_identifiers: Tuple[str]
+

A list of identifiers.

+
+ +
+
+_normalizedIdentifiers: Tuple[str]
+

A list of normalized (lower case) identifiers.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Object.Signal(identifiers, subtype, defaultExpression=None, documentation=None, parent=None)[source]
+

Represents a signal.

+

As signals might have a default expression, the class WithDefaultExpressionMixin is inherited.

+
+

Example

+
signal counter : unsigned(7 downto 0) := '0';
+
+
+
+

Inheritance

+
+

Inheritance diagram of Signal

+
+
Parameters:
+
+
+
+
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifiers: Tuple[str]
+

Returns a model entity’s tuple of identifiers (names).

+
+
Returns:
+

Tuple of identifiers.

+
+
+
+ +
+
+property NormalizedIdentifiers: Tuple[str]
+

Returns a model entity’s tuple of normalized identifiers (lower case names).

+
+
Returns:
+

Tuple of normalized identifiers.

+
+
+
+ +
+
+property ObjectVertex: Vertex | None
+

Read-only property to access the corresponding object vertex (_objectVertex).

+

The object vertex references this Object by its value field.

+
+
Returns:
+

The corresponding object vertex.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_identifiers: Tuple[str]
+

A list of identifiers.

+
+ +
+
+_normalizedIdentifiers: Tuple[str]
+

A list of normalized (lower case) identifiers.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+__init__(identifiers, subtype, defaultExpression=None, documentation=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+ +
+
+class pyVHDLModel.Object.File(identifiers, subtype, documentation=None, parent=None)[source]
+

Represents a file.

+
+

Todo

+

File object not implemented.

+
+

Inheritance

+
+

Inheritance diagram of File

+
+
Parameters:
+
+
+
+
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifiers: Tuple[str]
+

Returns a model entity’s tuple of identifiers (names).

+
+
Returns:
+

Tuple of identifiers.

+
+
+
+ +
+
+property NormalizedIdentifiers: Tuple[str]
+

Returns a model entity’s tuple of normalized identifiers (lower case names).

+
+
Returns:
+

Tuple of normalized identifiers.

+
+
+
+ +
+
+property ObjectVertex: Vertex | None
+

Read-only property to access the corresponding object vertex (_objectVertex).

+

The object vertex references this Object by its value field.

+
+
Returns:
+

The corresponding object vertex.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(identifiers, subtype, documentation=None, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_identifiers: Tuple[str]
+

A list of identifiers.

+
+ +
+
+_normalizedIdentifiers: Tuple[str]
+

A list of normalized (lower case) identifiers.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/pyVHDLModel/pyVHDLModel.PSLModel.html b/pyVHDLModel/pyVHDLModel.PSLModel.html new file mode 100644 index 000000000..15389c515 --- /dev/null +++ b/pyVHDLModel/pyVHDLModel.PSLModel.html @@ -0,0 +1,1537 @@ + + + + + + + pyVHDLModel.PSLModel — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

pyVHDLModel.PSLModel

+

This module contains an abstract document language model for PSL in VHDL.

+

Classes

+
    +

  • PSLEntity: +ModelEntity is the base-class for all classes in the VHDL language model, except for mixin classes (see multiple

    • +

  • PSLPrimaryUnit: +A base-class for all primary design units.

    • +

  • VerificationUnit: +A base-class for all primary design units.

    • +

  • VerificationProperty: +A base-class for all primary design units.

    • +

  • VerificationMode: +A base-class for all primary design units.

    • +

  • DefaultClock: +ModelEntity is the base-class for all classes in the VHDL language model, except for mixin classes (see multiple

    • +
+
+

Classes

+
+
+class pyVHDLModel.PSLModel.PSLEntity(parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of PSLEntity

+
+
Parameters:
+

parent (ModelEntity | None)

+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+

parent (Optional[ModelEntity]) – The parent model entity of this entity.

+
+
Return type:
+

None

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.PSLModel.PSLPrimaryUnit(identifier, contextItems=None, documentation=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of PSLPrimaryUnit

+
+
Parameters:
+
+
+
+
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(identifier, contextItems=None, documentation=None, parent=None)
+

Initializes a design unit.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+_contextItems: List['ContextUnion']
+

List of all context items (library, use and context clauses).

+
+ +
+
+_contextReferences: List['ContextReference']
+

List of context clauses.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_libraryReferences: List['LibraryClause']
+

List of library clauses.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageReferences: List['UseClause']
+

List of use clauses.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_referencedContexts: Dict[str, 'Context']
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_referencedLibraries: Dict[str, 'Library']
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, 'Package']]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+ +
+
+class pyVHDLModel.PSLModel.VerificationUnit(identifier)[source]
+

Inheritance

+
+

Inheritance diagram of VerificationUnit

+
+
Parameters:
+

identifier (str)

+
+
+
+
+__init__(identifier)[source]
+

Initializes a design unit.

+
+
Parameters:
+
    +

  • identifier (str) – Identifier (name) of the design unit.

    • +

  • contextItems – A sequence of library, use or context clauses.

    • +

  • documentation – Associated documentation of the design unit.

    • +

  • parent – Reference to the logical parent in the model hierarchy.

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_contextItems: List['ContextUnion']
+

List of all context items (library, use and context clauses).

+
+ +
+
+_contextReferences: List['ContextReference']
+

List of context clauses.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_libraryReferences: List['LibraryClause']
+

List of library clauses.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageReferences: List['UseClause']
+

List of use clauses.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_referencedContexts: Dict[str, 'Context']
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_referencedLibraries: Dict[str, 'Library']
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, 'Package']]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+ +
+
+class pyVHDLModel.PSLModel.VerificationProperty(identifier)[source]
+

Inheritance

+
+

Inheritance diagram of VerificationProperty

+
+
Parameters:
+

identifier (str)

+
+
+
+
+__init__(identifier)[source]
+

Initializes a design unit.

+
+
Parameters:
+
    +

  • identifier (str) – Identifier (name) of the design unit.

    • +

  • contextItems – A sequence of library, use or context clauses.

    • +

  • documentation – Associated documentation of the design unit.

    • +

  • parent – Reference to the logical parent in the model hierarchy.

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_contextItems: List['ContextUnion']
+

List of all context items (library, use and context clauses).

+
+ +
+
+_contextReferences: List['ContextReference']
+

List of context clauses.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_libraryReferences: List['LibraryClause']
+

List of library clauses.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageReferences: List['UseClause']
+

List of use clauses.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_referencedContexts: Dict[str, 'Context']
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_referencedLibraries: Dict[str, 'Library']
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, 'Package']]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+ +
+
+class pyVHDLModel.PSLModel.VerificationMode(identifier)[source]
+

Inheritance

+
+

Inheritance diagram of VerificationMode

+
+
Parameters:
+

identifier (str)

+
+
+
+
+__init__(identifier)[source]
+

Initializes a design unit.

+
+
Parameters:
+
    +

  • identifier (str) – Identifier (name) of the design unit.

    • +

  • contextItems – A sequence of library, use or context clauses.

    • +

  • documentation – Associated documentation of the design unit.

    • +

  • parent – Reference to the logical parent in the model hierarchy.

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_contextItems: List['ContextUnion']
+

List of all context items (library, use and context clauses).

+
+ +
+
+_contextReferences: List['ContextReference']
+

List of context clauses.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_libraryReferences: List['LibraryClause']
+

List of library clauses.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageReferences: List['UseClause']
+

List of use clauses.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_referencedContexts: Dict[str, 'Context']
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_referencedLibraries: Dict[str, 'Library']
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, 'Package']]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+ +
+
+class pyVHDLModel.PSLModel.DefaultClock(identifier)[source]
+

Inheritance

+
+

Inheritance diagram of DefaultClock

+
+
Parameters:
+

identifier (str)

+
+
+
+
+__init__(identifier)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
    +

  • parent – The parent model entity of this entity.

    • +

  • identifier (str)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/pyVHDLModel/pyVHDLModel.Predefined.html b/pyVHDLModel/pyVHDLModel.Predefined.html new file mode 100644 index 000000000..f840af525 --- /dev/null +++ b/pyVHDLModel/pyVHDLModel.Predefined.html @@ -0,0 +1,1570 @@ + + + + + + + pyVHDLModel.Predefined — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

pyVHDLModel.Predefined

+

This module contains base-classes for predefined library and package declarations.

+

Classes

+ +
+

Classes

+
+
+class pyVHDLModel.Predefined.PredefinedLibrary(packages)[source]
+

A base-class for predefined VHDL libraries.

+

VHDL defines 2 predefined libraries:

+ +

Inheritance

+
+

Inheritance diagram of PredefinedLibrary

+
+
+
+
+__init__(packages)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+

parent – The parent model entity of this entity.

+
+
Return type:
+

None

+
+
+
+ +
+
+property Architectures: Dict[str, Dict[str, Architecture]]
+

Returns a list of all architectures declarations declared in this library.

+
+ +
+
+property Configurations: Dict[str, Configuration]
+

Returns a list of all configuration declarations declared in this library.

+
+ +
+
+property Contexts: Dict[str, Context]
+

Returns a list of all context declarations declared in this library.

+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this library by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Entities: Dict[str, Entity]
+

Returns a list of all entity declarations declared in this library.

+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+IndexArchitectures()
+

Index declared items in all architectures.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all architectures:

    + +
    2. +
+
+

See also

+
+
IndexPackages()

Index all declared items in a package.

+
+
IndexPackageBodies()

Index all declared items in a package body.

+
+
IndexEntities()

Index all declared items in an entity.

+
+
+
+
+ +
+
+IndexEntities()
+

Index declared items in all entities.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all entities:

    + +
    2. +
+
+

See also

+
+
IndexPackages()

Index all declared items in a package.

+
+
IndexPackageBodies()

Index all declared items in a package body.

+
+
IndexArchitectures()

Index all declared items in an architecture.

+
+
+
+
+ +
+
+IndexPackageBodies()
+

Index declared items in all package bodies.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all package bodies:

    + +
    2. +
+
+

See also

+
+
IndexPackages()

Index all declared items in a package.

+
+
IndexEntities()

Index all declared items in an entity.

+
+
IndexArchitectures()

Index all declared items in an architecture.

+
+
+
+
+ +
+
+IndexPackages()
+

Index declared items in all packages.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all packages:

    + +
    2. +
+
+

See also

+
+
IndexPackageBodies()

Index all declared items in a package body.

+
+
IndexEntities()

Index all declared items in an entity.

+
+
IndexArchitectures()

Index all declared items in an architecture.

+
+
+
+
+ +
+
+IterateDesignUnits(filter=<DesignUnitKind.All: 63>)
+

Iterate all design units in the library.

+

A union of DesignUnitKind values can be given to filter the returned result for suitable design units.

+

Algorithm

+
    +

  1. Iterate all contexts in that library.

    2. +

  2. Iterate all packages in that library.

    3. +

  3. Iterate all package bodies in that library.

    4. +

  4. Iterate all entites in that library.

    5. +

  5. Iterate all architectures in that library.

    6. +

  6. Iterate all configurations in that library.

    7. +
+
+
Parameters:
+

filter (DesignUnitKind) – An enumeration with possibly multiple flags to filter the returned design units.

+
+
Return type:
+

Generator[DesignUnit, None, None]

+
+
Returns:
+

A generator to iterate all matched design units in the library.

+
+
+
+

See also

+
+
pyVHDLModel.Design.IterateDesignUnits()

Iterate all design units in the design.

+
+
pyVHDLModel.Document.IterateDesignUnits()

Iterate all design units in the document.

+
+
+
+
+ +
+
+LinkArchitectures()
+

Link all architectures to corresponding entities.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all architecture groups (grouped per entity symbol’s name).

    +
      +

    • Check if entity symbol’s name exists as an entity in this library.

      • +
    +
      +

    1. For each architecture in the same architecture group:

      +
        +

      • Add architecture to entities architecture dictionary pyVHDLModel.DesignUnit.Entity._architectures.

        • +

      • Assign found entity to architecture’s entity symbol pyVHDLModel.DesignUnit.Architecture._entity

        • +

      • Set parent namespace of architecture’s namespace to the entitie’s namespace.

        • +

      • Add an edge in the dependency graph from the architecture’s corresponding dependency vertex to the entity’s corresponding dependency vertex.

        • +
      +
      2. +
    +
    2. +
+
+
Raises:
+
+
+
Return type:
+

None

+
+
+
+

See also

+
+
LinkPackageBodies()

Link all package bodies to corresponding packages.

+
+
+
+
+ +
+
+LinkPackageBodies()
+

Link all package bodies to corresponding packages.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all package bodies.

    +
      +

    • Check if package body symbol’s name exists as a package in this library.

      • +

    • Add package body to package pyVHDLModel.DesignUnit.Package._packageBody.

      • +

    • Assign found package to package body’s package symbol pyVHDLModel.DesignUnit.PackageBody._package

      • +

    • Set parent namespace of package body’s namespace to the package’s namespace.

      • +

    • Add an edge in the dependency graph from the package body’s corresponding dependency vertex to the package’s corresponding dependency vertex.

      • +
    +
    2. +
+
+
Raises:
+

VHDLModelException – If package name doesn’t exist.

+
+
Return type:
+

None

+
+
+
+

See also

+
+
LinkArchitectures()

Link all architectures to corresponding entities.

+
+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageBodies: Dict[str, PackageBody]
+

Returns a list of all package body declarations declared in this library.

+
+ +
+
+property Packages: Dict[str, Package]
+

Returns a list of all package declarations declared in this library.

+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__repr__()
+

Formats a representation of the library.

+

Format: Library: 'my_library'

+
+
Return type:
+

str

+
+
Returns:
+

String representation of the library.

+
+
+
+ +
+
+__str__()
+

Formats a representation of the library.

+

Format: Library: 'my_library'

+
+
Return type:
+

str

+
+
Returns:
+

String representation of the library.

+
+
+
+ +
+
+_architectures: Dict[str, Dict[str, Architecture]]
+

Dictionary of all architectures defined in a library.

+
+ +
+
+_configurations: Dict[str, Configuration]
+

Dictionary of all configurations defined in a library.

+
+ +
+
+_contexts: Dict[str, Context]
+

Dictionary of all contexts defined in a library.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, Union['Library', DesignUnit], None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the library.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_entities: Dict[str, Entity]
+

Dictionary of all entities defined in a library.

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageBodies: Dict[str, PackageBody]
+

Dictionary of all package bodies defined in a library.

+
+ +
+
+_packages: Dict[str, Package]
+

Dictionary of all packages defined in a library.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Predefined.PredefinedPackageMixin[source]
+

A mixin-class for predefined VHDL packages and package bodies.

+

Inheritance

+
+

Inheritance diagram of PredefinedPackageMixin

+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+ +
+
+class pyVHDLModel.Predefined.PredefinedPackage[source]
+

A base-class for predefined VHDL packages.

+

Inheritance

+
+

Inheritance diagram of PredefinedPackage

+
+
+
+
+__init__()[source]
+

Initializes a design unit.

+
+
Parameters:
+
    +

  • identifier – Identifier (name) of the design unit.

    • +

  • contextItems – A sequence of library, use or context clauses.

    • +

  • documentation – Associated documentation of the design unit.

    • +

  • parent – Reference to the logical parent in the model hierarchy.

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+IndexDeclaredItems()
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_contextItems: List['ContextUnion']
+

List of all context items (library, use and context clauses).

+
+ +
+
+_contextReferences: List['ContextReference']
+

List of context clauses.

+
+ +
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_libraryReferences: List['LibraryClause']
+

List of library clauses.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageReferences: List['UseClause']
+

List of use clauses.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+_referencedContexts: Dict[str, 'Context']
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_referencedLibraries: Dict[str, 'Library']
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, 'Package']]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+ +
+
+class pyVHDLModel.Predefined.PredefinedPackageBody[source]
+

A base-class for predefined VHDL package bodies.

+

Inheritance

+
+

Inheritance diagram of PredefinedPackageBody

+
+
+
+
+__init__()[source]
+

Initializes a design unit.

+
+
Parameters:
+
    +

  • identifier – Identifier (name) of the design unit.

    • +

  • contextItems – A sequence of library, use or context clauses.

    • +

  • documentation – Associated documentation of the design unit.

    • +

  • parent – Reference to the logical parent in the model hierarchy.

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+IndexDeclaredItems()
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_contextItems: List['ContextUnion']
+

List of all context items (library, use and context clauses).

+
+ +
+
+_contextReferences: List['ContextReference']
+

List of context clauses.

+
+ +
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_libraryReferences: List['LibraryClause']
+

List of library clauses.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageReferences: List['UseClause']
+

List of use clauses.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+_referencedContexts: Dict[str, 'Context']
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_referencedLibraries: Dict[str, 'Library']
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, 'Package']]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+ +
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/pyVHDLModel/pyVHDLModel.Regions.html b/pyVHDLModel/pyVHDLModel.Regions.html new file mode 100644 index 000000000..2de83d20f --- /dev/null +++ b/pyVHDLModel/pyVHDLModel.Regions.html @@ -0,0 +1,369 @@ + + + + + + + pyVHDLModel.Regions — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

pyVHDLModel.Regions

+

This module contains parts of an abstract document language model for VHDL.

+

tbd.

+

Classes

+ +
+

Classes

+
+
+class pyVHDLModel.Regions.ConcurrentDeclarationRegionMixin(declaredItems=None)[source]
+

Inheritance

+
+

Inheritance diagram of ConcurrentDeclarationRegionMixin

+
+
Parameters:
+

declaredItems (Iterable | None)

+
+
+
+
+__init__(declaredItems=None)[source]
+
+
Parameters:
+

declaredItems (Iterable | None)

+
+
Return type:
+

None

+
+
+
+ +
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+IndexDeclaredItems()[source]
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+ +
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/pyVHDLModel/pyVHDLModel.STD.html b/pyVHDLModel/pyVHDLModel.STD.html new file mode 100644 index 000000000..20269942c --- /dev/null +++ b/pyVHDLModel/pyVHDLModel.STD.html @@ -0,0 +1,3217 @@ + + + + + + + pyVHDLModel.STD — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

pyVHDLModel.STD

+

This module contains library and package declarations for VHDL library STD.

+

Classes

+
    +

  • Std: +Predefined VHDL library std.

    • +

  • Standard: +Predefined package std.standard.

    • +

  • Standard_Body: +Predefined package body of package std.standard.

    • +

  • TextIO: +Predefined package std.textio.

    • +

  • TextIO_Body: +Predefined package body of package std.textio.

    • +

  • Env: +Predefined package std.env.

    • +

  • Env_Body: +Predefined package body of package std.env.

    • +
+
+

Classes

+
+
+class pyVHDLModel.STD.Std[source]
+

Predefined VHDL library std.

+

The following predefined packages are in this library:

+ +
+

See also

+
+
Other predefined libraries:
+
+
+
+

Inheritance

+
+

Inheritance diagram of Std

+
+
+
+
+__init__()[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+

parent – The parent model entity of this entity.

+
+
Return type:
+

None

+
+
+
+ +
+
+property Architectures: Dict[str, Dict[str, Architecture]]
+

Returns a list of all architectures declarations declared in this library.

+
+ +
+
+property Configurations: Dict[str, Configuration]
+

Returns a list of all configuration declarations declared in this library.

+
+ +
+
+property Contexts: Dict[str, Context]
+

Returns a list of all context declarations declared in this library.

+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this library by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Entities: Dict[str, Entity]
+

Returns a list of all entity declarations declared in this library.

+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+IndexArchitectures()
+

Index declared items in all architectures.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all architectures:

    + +
    2. +
+
+

See also

+
+
IndexPackages()

Index all declared items in a package.

+
+
IndexPackageBodies()

Index all declared items in a package body.

+
+
IndexEntities()

Index all declared items in an entity.

+
+
+
+
+ +
+
+IndexEntities()
+

Index declared items in all entities.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all entities:

    + +
    2. +
+
+

See also

+
+
IndexPackages()

Index all declared items in a package.

+
+
IndexPackageBodies()

Index all declared items in a package body.

+
+
IndexArchitectures()

Index all declared items in an architecture.

+
+
+
+
+ +
+
+IndexPackageBodies()
+

Index declared items in all package bodies.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all package bodies:

    + +
    2. +
+
+

See also

+
+
IndexPackages()

Index all declared items in a package.

+
+
IndexEntities()

Index all declared items in an entity.

+
+
IndexArchitectures()

Index all declared items in an architecture.

+
+
+
+
+ +
+
+IndexPackages()
+

Index declared items in all packages.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all packages:

    + +
    2. +
+
+

See also

+
+
IndexPackageBodies()

Index all declared items in a package body.

+
+
IndexEntities()

Index all declared items in an entity.

+
+
IndexArchitectures()

Index all declared items in an architecture.

+
+
+
+
+ +
+
+IterateDesignUnits(filter=<DesignUnitKind.All: 63>)
+

Iterate all design units in the library.

+

A union of DesignUnitKind values can be given to filter the returned result for suitable design units.

+

Algorithm

+
    +

  1. Iterate all contexts in that library.

    2. +

  2. Iterate all packages in that library.

    3. +

  3. Iterate all package bodies in that library.

    4. +

  4. Iterate all entites in that library.

    5. +

  5. Iterate all architectures in that library.

    6. +

  6. Iterate all configurations in that library.

    7. +
+
+
Parameters:
+

filter (DesignUnitKind) – An enumeration with possibly multiple flags to filter the returned design units.

+
+
Return type:
+

Generator[DesignUnit, None, None]

+
+
Returns:
+

A generator to iterate all matched design units in the library.

+
+
+
+

See also

+
+
pyVHDLModel.Design.IterateDesignUnits()

Iterate all design units in the design.

+
+
pyVHDLModel.Document.IterateDesignUnits()

Iterate all design units in the document.

+
+
+
+
+ +
+
+LinkArchitectures()
+

Link all architectures to corresponding entities.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all architecture groups (grouped per entity symbol’s name).

    +
      +

    • Check if entity symbol’s name exists as an entity in this library.

      • +
    +
      +

    1. For each architecture in the same architecture group:

      +
        +

      • Add architecture to entities architecture dictionary pyVHDLModel.DesignUnit.Entity._architectures.

        • +

      • Assign found entity to architecture’s entity symbol pyVHDLModel.DesignUnit.Architecture._entity

        • +

      • Set parent namespace of architecture’s namespace to the entitie’s namespace.

        • +

      • Add an edge in the dependency graph from the architecture’s corresponding dependency vertex to the entity’s corresponding dependency vertex.

        • +
      +
      2. +
    +
    2. +
+
+
Raises:
+
+
+
Return type:
+

None

+
+
+
+

See also

+
+
LinkPackageBodies()

Link all package bodies to corresponding packages.

+
+
+
+
+ +
+
+LinkPackageBodies()
+

Link all package bodies to corresponding packages.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all package bodies.

    +
      +

    • Check if package body symbol’s name exists as a package in this library.

      • +

    • Add package body to package pyVHDLModel.DesignUnit.Package._packageBody.

      • +

    • Assign found package to package body’s package symbol pyVHDLModel.DesignUnit.PackageBody._package

      • +

    • Set parent namespace of package body’s namespace to the package’s namespace.

      • +

    • Add an edge in the dependency graph from the package body’s corresponding dependency vertex to the package’s corresponding dependency vertex.

      • +
    +
    2. +
+
+
Raises:
+

VHDLModelException – If package name doesn’t exist.

+
+
Return type:
+

None

+
+
+
+

See also

+
+
LinkArchitectures()

Link all architectures to corresponding entities.

+
+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageBodies: Dict[str, PackageBody]
+

Returns a list of all package body declarations declared in this library.

+
+ +
+
+property Packages: Dict[str, Package]
+

Returns a list of all package declarations declared in this library.

+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__repr__()
+

Formats a representation of the library.

+

Format: Library: 'my_library'

+
+
Return type:
+

str

+
+
Returns:
+

String representation of the library.

+
+
+
+ +
+
+__str__()
+

Formats a representation of the library.

+

Format: Library: 'my_library'

+
+
Return type:
+

str

+
+
Returns:
+

String representation of the library.

+
+
+
+ +
+
+_architectures: Dict[str, Dict[str, Architecture]]
+

Dictionary of all architectures defined in a library.

+
+ +
+
+_configurations: Dict[str, Configuration]
+

Dictionary of all configurations defined in a library.

+
+ +
+
+_contexts: Dict[str, Context]
+

Dictionary of all contexts defined in a library.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, Union['Library', DesignUnit], None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the library.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_entities: Dict[str, Entity]
+

Dictionary of all entities defined in a library.

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageBodies: Dict[str, PackageBody]
+

Dictionary of all package bodies defined in a library.

+
+ +
+
+_packages: Dict[str, Package]
+

Dictionary of all packages defined in a library.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.STD.Standard[source]
+

Predefined package std.standard.

+

Predefined types:

+
    +

  • boolean, boolean_vector

    • +

  • bit, bit_vector

    • +

  • character, string

    • +

  • integer, integer_vector

    • +

  • natural, positive

    • +

  • real, real_vector

    • +

  • time, time_vector

    • +

  • open_file_kind, open_file_status

    • +
+
+

See also

+

Matching Package Body declaration.

+
+

Inheritance

+
+

Inheritance diagram of Standard

+
+
+
+
+__init__()[source]
+

Initializes a design unit.

+
+
Parameters:
+
    +

  • identifier – Identifier (name) of the design unit.

    • +

  • contextItems – A sequence of library, use or context clauses.

    • +

  • documentation – Associated documentation of the design unit.

    • +

  • parent – Reference to the logical parent in the model hierarchy.

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+IndexDeclaredItems()
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_contextItems: List['ContextUnion']
+

List of all context items (library, use and context clauses).

+
+ +
+
+_contextReferences: List['ContextReference']
+

List of context clauses.

+
+ +
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_libraryReferences: List['LibraryClause']
+

List of library clauses.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageReferences: List['UseClause']
+

List of use clauses.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+_referencedContexts: Dict[str, 'Context']
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_referencedLibraries: Dict[str, 'Library']
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, 'Package']]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+ +
+
+class pyVHDLModel.STD.Standard_Body[source]
+

Predefined package body of package std.standard.

+
+

See also

+

Matching Package declaration.

+
+

Inheritance

+
+

Inheritance diagram of Standard_Body

+
+
+
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+IndexDeclaredItems()
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__()
+

Initializes a design unit.

+
+
Parameters:
+
    +

  • identifier – Identifier (name) of the design unit.

    • +

  • contextItems – A sequence of library, use or context clauses.

    • +

  • documentation – Associated documentation of the design unit.

    • +

  • parent – Reference to the logical parent in the model hierarchy.

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_contextItems: List['ContextUnion']
+

List of all context items (library, use and context clauses).

+
+ +
+
+_contextReferences: List['ContextReference']
+

List of context clauses.

+
+ +
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_libraryReferences: List['LibraryClause']
+

List of library clauses.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageReferences: List['UseClause']
+

List of use clauses.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+_referencedContexts: Dict[str, 'Context']
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_referencedLibraries: Dict[str, 'Library']
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, 'Package']]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+ +
+
+class pyVHDLModel.STD.TextIO[source]
+

Predefined package std.textio.

+
+

See also

+

Matching Package Body declaration.

+
+

Inheritance

+
+

Inheritance diagram of TextIO

+
+
+
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+IndexDeclaredItems()
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__()
+

Initializes a design unit.

+
+
Parameters:
+
    +

  • identifier – Identifier (name) of the design unit.

    • +

  • contextItems – A sequence of library, use or context clauses.

    • +

  • documentation – Associated documentation of the design unit.

    • +

  • parent – Reference to the logical parent in the model hierarchy.

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_contextItems: List['ContextUnion']
+

List of all context items (library, use and context clauses).

+
+ +
+
+_contextReferences: List['ContextReference']
+

List of context clauses.

+
+ +
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_libraryReferences: List['LibraryClause']
+

List of library clauses.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageReferences: List['UseClause']
+

List of use clauses.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+_referencedContexts: Dict[str, 'Context']
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_referencedLibraries: Dict[str, 'Library']
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, 'Package']]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+ +
+
+class pyVHDLModel.STD.TextIO_Body[source]
+

Predefined package body of package std.textio.

+
+

See also

+

Matching Package declaration.

+
+

Inheritance

+
+

Inheritance diagram of TextIO_Body

+
+
+
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+IndexDeclaredItems()
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__()
+

Initializes a design unit.

+
+
Parameters:
+
    +

  • identifier – Identifier (name) of the design unit.

    • +

  • contextItems – A sequence of library, use or context clauses.

    • +

  • documentation – Associated documentation of the design unit.

    • +

  • parent – Reference to the logical parent in the model hierarchy.

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_contextItems: List['ContextUnion']
+

List of all context items (library, use and context clauses).

+
+ +
+
+_contextReferences: List['ContextReference']
+

List of context clauses.

+
+ +
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_libraryReferences: List['LibraryClause']
+

List of library clauses.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageReferences: List['UseClause']
+

List of use clauses.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+_referencedContexts: Dict[str, 'Context']
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_referencedLibraries: Dict[str, 'Library']
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, 'Package']]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+ +
+
+class pyVHDLModel.STD.Env[source]
+

Predefined package std.env.

+
+

See also

+

Matching Package Body declaration.

+
+

Inheritance

+
+

Inheritance diagram of Env

+
+
+
+
+__init__()[source]
+

Initializes a design unit.

+
+
Parameters:
+
    +

  • identifier – Identifier (name) of the design unit.

    • +

  • contextItems – A sequence of library, use or context clauses.

    • +

  • documentation – Associated documentation of the design unit.

    • +

  • parent – Reference to the logical parent in the model hierarchy.

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+IndexDeclaredItems()
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_contextItems: List['ContextUnion']
+

List of all context items (library, use and context clauses).

+
+ +
+
+_contextReferences: List['ContextReference']
+

List of context clauses.

+
+ +
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_libraryReferences: List['LibraryClause']
+

List of library clauses.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageReferences: List['UseClause']
+

List of use clauses.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+_referencedContexts: Dict[str, 'Context']
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_referencedLibraries: Dict[str, 'Library']
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, 'Package']]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+ +
+
+class pyVHDLModel.STD.Env_Body[source]
+

Predefined package body of package std.env.

+
+

See also

+

Matching Package declaration.

+
+

Inheritance

+
+

Inheritance diagram of Env_Body

+
+
+
+
+property ContextItems: List[LibraryClause | UseClause | ContextReference]
+

Read-only property to access the sequence of all context items comprising library, use and context clauses +(_contextItems).

+
+
Returns:
+

Sequence of context items.

+
+
+
+ +
+
+property ContextReferences: List[ContextReference]
+

Read-only property to access the sequence of context clauses (_contextReferences).

+
+
Returns:
+

Sequence of context clauses.

+
+
+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property HierarchyVertex: Vertex
+

Read-only property to access the corresponding hierarchy vertex (_hierarchyVertex).

+

The hierarchy vertex references this design unit by its value field.

+
+
Returns:
+

The corresponding hierarchy vertex.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+IndexDeclaredItems()
+

Index declared items listed in the concurrent declaration region.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all declared items:

    +
      +

    • Every declared item is added to _namespace.

      • +

    • If the declared item is a FullType, then add an entry to _types.

      • +

    • If the declared item is a SubType, then add an entry to _subtypes.

      • +

    • If the declared item is a Function, then add an entry to _functions.

      • +

    • If the declared item is a Procedure, then add an entry to _procedures.

      • +

    • If the declared item is a Constant, then add an entry to _constants.

      • +

    • If the declared item is a Signal, then add an entry to _signals.

      • +

    • If the declared item is a Variable, TODO.

      • +

    • If the declared item is a SharedVariable, then add an entry to _sharedVariables.

      • +

    • If the declared item is a File, then add an entry to _files.

      • +

    • If the declared item is neither of these types, call _IndexOtherDeclaredItem().
      +Derived classes may override this virtual function.

      • +
    +
    2. +
+
+

See also

+
+
pyVHDLModel.Design.IndexPackages()

Iterate all packages in the design and index declared items.

+
+
pyVHDLModel.Library.IndexPackages()

Iterate all packages in the library and index declared items.

+
+
pyVHDLModel.Library._IndexOtherDeclaredItem()

Iterate all packages in the library and index declared items.

+
+
+
+
+ +
+
+property LibraryReferences: List[LibraryClause]
+

Read-only property to access the sequence of library clauses (_libraryReferences).

+
+
Returns:
+

Sequence of library clauses.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property PackageReferences: List[UseClause]
+

Read-only property to access the sequence of use clauses (_packageReferences).

+
+
Returns:
+

Sequence of use clauses.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__()
+

Initializes a design unit.

+
+
Parameters:
+
    +

  • identifier – Identifier (name) of the design unit.

    • +

  • contextItems – A sequence of library, use or context clauses.

    • +

  • documentation – Associated documentation of the design unit.

    • +

  • parent – Reference to the logical parent in the model hierarchy.

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_constants: Dict[str, Constant]
+

Dictionary of all constants declared in this concurrent declaration region.

+
+ +
+
+_contextItems: List['ContextUnion']
+

List of all context items (library, use and context clauses).

+
+ +
+
+_contextReferences: List['ContextReference']
+

List of context clauses.

+
+ +
+
+_declaredItems: List
+

List of all declared items in this concurrent declaration region.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the design unit.
This reference is set by CreateDependencyGraph().

+
+ +
+
+_document: Document
+

The VHDL library, the design unit was analyzed into.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_files: Dict[str, File]
+

Dictionary of all files declared in this concurrent declaration region.

+
+ +
+
+_functions: Dict[str, Dict[str, Function]]
+

Dictionary of all functions declared in this concurrent declaration region.

+
+ +
+
+_hierarchyVertex: Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The vertex in the hierarchy graph

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_libraryReferences: List['LibraryClause']
+

List of library clauses.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_packageReferences: List['UseClause']
+

List of use clauses.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_procedures: Dict[str, Dict[str, Procedure]]
+

Dictionary of all procedures declared in this concurrent declaration region.

+
+ +
+
+_referencedContexts: Dict[str, 'Context']
+

Referenced contexts based on explicit context references or implicit inheritance

+
+ +
+
+_referencedLibraries: Dict[str, 'Library']
+

Referenced libraries based on explicit library clauses or implicit inheritance

+
+ +
+
+_referencedPackages: Dict[str, Dict[str, 'Package']]
+

Referenced packages based on explicit use clauses or implicit inheritance

+
+ +
+
+_sharedVariables: Dict[str, SharedVariable]
+

Dictionary of all shared variables declared in this concurrent declaration region.

+
+ +
+
+_signals: Dict[str, Signal]
+

Dictionary of all signals declared in this concurrent declaration region.

+
+ +
+
+_subtypes: Dict[str, Subtype]
+

Dictionary of all subtypes declared in this concurrent declaration region.

+
+ +
+
+_types: Dict[str, FullType]
+

Dictionary of all types declared in this concurrent declaration region.

+
+ +
+ +
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/pyVHDLModel/pyVHDLModel.Sequential.html b/pyVHDLModel/pyVHDLModel.Sequential.html new file mode 100644 index 000000000..5ff324c51 --- /dev/null +++ b/pyVHDLModel/pyVHDLModel.Sequential.html @@ -0,0 +1,3945 @@ + + + + + + + pyVHDLModel.Sequential — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

pyVHDLModel.Sequential

+

This module contains parts of an abstract document language model for VHDL.

+

Declarations for sequential statements.

+

Classes

+ +
+

Classes

+
+
+class pyVHDLModel.Sequential.SequentialStatement(label=None, parent=None)[source]
+

A SequentialStatement is a base-class for all sequential statements.

+

Inheritance

+
+

Inheritance diagram of SequentialStatement

+
+
Parameters:
+

label (str | None)

+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Label: str | None
+

Returns a model entity’s label.

+
+
Returns:
+

Label of a model entity.

+
+
+
+ +
+
+property NormalizedLabel: str | None
+

Returns a model entity’s normalized (lower case) label.

+
+
Returns:
+

Normalized label of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(label=None, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
    +

  • parent – The parent model entity of this entity.

    • +

  • label (str | None)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+_label: Optional[str]
+

The label of a model entity.

+
+ +
+
+_normalizedLabel: Optional[str]
+

The normalized (lower case) label of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Sequential.SequentialStatementsMixin(statements=None)[source]
+

Inheritance

+
+

Inheritance diagram of SequentialStatementsMixin

+
+
Parameters:
+

statements (Iterable[SequentialStatement] | None)

+
+
+
+
+__init__(statements=None)[source]
+
+
Parameters:
+

statements (Iterable[SequentialStatement] | None)

+
+
Return type:
+

None

+
+
+
+ +
+
+property Statements: List[SequentialStatement]
+

Read-only property to access the list of sequential statements (_statements).

+
+
Returns:
+

A list of sequential statements.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+ +
+
+class pyVHDLModel.Sequential.SequentialProcedureCall(procedureName, parameterMappings=None, label=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of SequentialProcedureCall

+
+
Parameters:
+
+
+
+
+
+__init__(procedureName, parameterMappings=None, label=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Label: str | None
+

Returns a model entity’s label.

+
+
Returns:
+

Label of a model entity.

+
+
+
+ +
+
+property NormalizedLabel: str | None
+

Returns a model entity’s normalized (lower case) label.

+
+
Returns:
+

Normalized label of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_label: Optional[str]
+

The label of a model entity.

+
+ +
+
+_normalizedLabel: Optional[str]
+

The normalized (lower case) label of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Sequential.SequentialSignalAssignment(target, label=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of SequentialSignalAssignment

+
+
Parameters:
+
+
+
+
+
+__init__(target, label=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
    +

  • parent (ModelEntity) – The parent model entity of this entity.

    • +

  • target (Symbol)

    • +

  • label (str | None)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Label: str | None
+

Returns a model entity’s label.

+
+
Returns:
+

Label of a model entity.

+
+
+
+ +
+
+property NormalizedLabel: str | None
+

Returns a model entity’s normalized (lower case) label.

+
+
Returns:
+

Normalized label of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_label: Optional[str]
+

The label of a model entity.

+
+ +
+
+_normalizedLabel: Optional[str]
+

The normalized (lower case) label of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Sequential.SequentialSimpleSignalAssignment(target, waveform, label=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of SequentialSimpleSignalAssignment

+
+
Parameters:
+
+
+
+
+
+__init__(target, waveform, label=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+property Waveform: List[WaveformElement]
+

Read-only property to access the list waveform elements (_waveform).

+
+
Returns:
+

A list of waveform elements.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Label: str | None
+

Returns a model entity’s label.

+
+
Returns:
+

Label of a model entity.

+
+
+
+ +
+
+property NormalizedLabel: str | None
+

Returns a model entity’s normalized (lower case) label.

+
+
Returns:
+

Normalized label of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_label: Optional[str]
+

The label of a model entity.

+
+ +
+
+_normalizedLabel: Optional[str]
+

The normalized (lower case) label of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Sequential.SequentialVariableAssignment(target, expression, label=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of SequentialVariableAssignment

+
+
Parameters:
+
+
+
+
+
+__init__(target, expression, label=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Label: str | None
+

Returns a model entity’s label.

+
+
Returns:
+

Label of a model entity.

+
+
+
+ +
+
+property NormalizedLabel: str | None
+

Returns a model entity’s normalized (lower case) label.

+
+
Returns:
+

Normalized label of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_label: Nullable[str]
+

The label of a model entity.

+
+ +
+
+_normalizedLabel: Nullable[str]
+

The normalized (lower case) label of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Sequential.SequentialReportStatement(message, severity=None, label=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of SequentialReportStatement

+
+
Parameters:
+
+
+
+
+
+__init__(message, severity=None, label=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Label: str | None
+

Returns a model entity’s label.

+
+
Returns:
+

Label of a model entity.

+
+
+
+ +
+
+property NormalizedLabel: str | None
+

Returns a model entity’s normalized (lower case) label.

+
+
Returns:
+

Normalized label of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_label: Nullable[str]
+

The label of a model entity.

+
+ +
+
+_normalizedLabel: Nullable[str]
+

The normalized (lower case) label of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Sequential.SequentialAssertStatement(condition, message=None, severity=None, label=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of SequentialAssertStatement

+
+
Parameters:
+
+
+
+
+
+__init__(condition, message=None, severity=None, label=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+property Condition: BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal
+

Read-only property to access the condition of a statement (_condition).

+
+
Returns:
+

The expression representing the condition of a statement.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Label: str | None
+

Returns a model entity’s label.

+
+
Returns:
+

Label of a model entity.

+
+
+
+ +
+
+property NormalizedLabel: str | None
+

Returns a model entity’s normalized (lower case) label.

+
+
Returns:
+

Normalized label of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_label: Nullable[str]
+

The label of a model entity.

+
+ +
+
+_normalizedLabel: Nullable[str]
+

The normalized (lower case) label of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Sequential.CompoundStatement(label=None, parent=None)[source]
+

A CompoundStatement is a base-class for all compound statements.

+

Inheritance

+
+

Inheritance diagram of CompoundStatement

+
+
Parameters:
+

label (str | None)

+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Label: str | None
+

Returns a model entity’s label.

+
+
Returns:
+

Label of a model entity.

+
+
+
+ +
+
+property NormalizedLabel: str | None
+

Returns a model entity’s normalized (lower case) label.

+
+
Returns:
+

Normalized label of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(label=None, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
    +

  • parent – The parent model entity of this entity.

    • +

  • label (str | None)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+_label: Optional[str]
+

The label of a model entity.

+
+ +
+
+_normalizedLabel: Optional[str]
+

The normalized (lower case) label of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Sequential.Branch(statements=None, parent=None)[source]
+

A Branch is a base-class for all branches in a if statement.

+

Inheritance

+
+

Inheritance diagram of Branch

+
+
Parameters:
+
+
+
+
+
+__init__(statements=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+property Statements: List[SequentialStatement]
+

Read-only property to access the list of sequential statements (_statements).

+
+
Returns:
+

A list of sequential statements.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Sequential.IfBranch(condition, statements=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of IfBranch

+
+
Parameters:
+
+
+
+
+
+__init__(condition, statements=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+property Condition: BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal
+

Read-only property to access the condition of a statement (_condition).

+
+
Returns:
+

The expression representing the condition of a statement.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+property Statements: List[SequentialStatement]
+

Read-only property to access the list of sequential statements (_statements).

+
+
Returns:
+

A list of sequential statements.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Sequential.ElsifBranch(condition, statements=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of ElsifBranch

+
+
Parameters:
+
+
+
+
+
+__init__(condition, statements=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+property Condition: BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal
+

Read-only property to access the condition of a statement (_condition).

+
+
Returns:
+

The expression representing the condition of a statement.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+property Statements: List[SequentialStatement]
+

Read-only property to access the list of sequential statements (_statements).

+
+
Returns:
+

A list of sequential statements.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Sequential.ElseBranch(statements=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of ElseBranch

+
+
Parameters:
+
+
+
+
+
+__init__(statements=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+property Statements: List[SequentialStatement]
+

Read-only property to access the list of sequential statements (_statements).

+
+
Returns:
+

A list of sequential statements.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Sequential.IfStatement(ifBranch, elsifBranches=None, elseBranch=None, label=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of IfStatement

+
+
Parameters:
+
+
+
+
+
+__init__(ifBranch, elsifBranches=None, elseBranch=None, label=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+property IfBranch: IfBranch
+

Read-only property to access the if-branch of the if-statement (_ifBranch).

+
+
Returns:
+

The if-branch.

+
+
+
+ +
+
+property ElsIfBranches: List[ElsifBranch]
+

Read-only property to access the elsif-branch of the if-statement (_elsifBranch).

+
+
Returns:
+

The elsif-branch.

+
+
+
+ +
+
+property ElseBranch: ElseBranch | None
+

Read-only property to access the else-branch of the if-statement (_elseBranch).

+
+
Returns:
+

The else-branch.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Label: str | None
+

Returns a model entity’s label.

+
+
Returns:
+

Label of a model entity.

+
+
+
+ +
+
+property NormalizedLabel: str | None
+

Returns a model entity’s normalized (lower case) label.

+
+
Returns:
+

Normalized label of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_label: Optional[str]
+

The label of a model entity.

+
+ +
+
+_normalizedLabel: Optional[str]
+

The normalized (lower case) label of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Sequential.SequentialChoice(parent=None)[source]
+

A SequentialChoice is a base-class for all sequential choices (in case statements).

+

Inheritance

+
+

Inheritance diagram of SequentialChoice

+
+
Parameters:
+

parent (ModelEntity | None)

+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+

parent (Optional[ModelEntity]) – The parent model entity of this entity.

+
+
Return type:
+

None

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Sequential.IndexedChoice(expression, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of IndexedChoice

+
+
Parameters:
+
+
+
+
+
+__init__(expression, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Sequential.RangedChoice(rng, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of RangedChoice

+
+
Parameters:
+
+
+
+
+
+__init__(rng, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
    +

  • parent (ModelEntity) – The parent model entity of this entity.

    • +

  • rng (Range)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Sequential.SequentialCase(statements=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of SequentialCase

+
+
Parameters:
+
+
+
+
+
+__init__(statements=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+property Statements: List[SequentialStatement]
+

Read-only property to access the list of sequential statements (_statements).

+
+
Returns:
+

A list of sequential statements.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Sequential.Case(choices, statements=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of Case

+
+
Parameters:
+
+
+
+
+
+__init__(choices, statements=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+property Statements: List[SequentialStatement]
+

Read-only property to access the list of sequential statements (_statements).

+
+
Returns:
+

A list of sequential statements.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Sequential.OthersCase(statements=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of OthersCase

+
+
Parameters:
+
+
+
+
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+property Statements: List[SequentialStatement]
+

Read-only property to access the list of sequential statements (_statements).

+
+
Returns:
+

A list of sequential statements.

+
+
+
+ +
+
+__init__(statements=None, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Sequential.CaseStatement(expression, cases, label=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of CaseStatement

+
+
Parameters:
+
+
+
+
+
+__init__(expression, cases, label=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Label: str | None
+

Returns a model entity’s label.

+
+
Returns:
+

Label of a model entity.

+
+
+
+ +
+
+property NormalizedLabel: str | None
+

Returns a model entity’s normalized (lower case) label.

+
+
Returns:
+

Normalized label of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_label: Nullable[str]
+

The label of a model entity.

+
+ +
+
+_normalizedLabel: Nullable[str]
+

The normalized (lower case) label of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Sequential.LoopStatement(statements=None, label=None, parent=None)[source]
+

A LoopStatement is a base-class for all loop statements.

+

Inheritance

+
+

Inheritance diagram of LoopStatement

+
+
Parameters:
+
+
+
+
+
+__init__(statements=None, label=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Label: str | None
+

Returns a model entity’s label.

+
+
Returns:
+

Label of a model entity.

+
+
+
+ +
+
+property NormalizedLabel: str | None
+

Returns a model entity’s normalized (lower case) label.

+
+
Returns:
+

Normalized label of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+property Statements: List[SequentialStatement]
+

Read-only property to access the list of sequential statements (_statements).

+
+
Returns:
+

A list of sequential statements.

+
+
+
+ +
+
+_label: Optional[str]
+

The label of a model entity.

+
+ +
+
+_normalizedLabel: Optional[str]
+

The normalized (lower case) label of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Sequential.EndlessLoopStatement(statements=None, label=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of EndlessLoopStatement

+
+
Parameters:
+
+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Label: str | None
+

Returns a model entity’s label.

+
+
Returns:
+

Label of a model entity.

+
+
+
+ +
+
+property NormalizedLabel: str | None
+

Returns a model entity’s normalized (lower case) label.

+
+
Returns:
+

Normalized label of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+property Statements: List[SequentialStatement]
+

Read-only property to access the list of sequential statements (_statements).

+
+
Returns:
+

A list of sequential statements.

+
+
+
+ +
+
+__init__(statements=None, label=None, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+_label: Optional[str]
+

The label of a model entity.

+
+ +
+
+_normalizedLabel: Optional[str]
+

The normalized (lower case) label of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Sequential.ForLoopStatement(loopIndex, rng, statements=None, label=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of ForLoopStatement

+
+
Parameters:
+
+
+
+
+
+__init__(loopIndex, rng, statements=None, label=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Label: str | None
+

Returns a model entity’s label.

+
+
Returns:
+

Label of a model entity.

+
+
+
+ +
+
+property NormalizedLabel: str | None
+

Returns a model entity’s normalized (lower case) label.

+
+
Returns:
+

Normalized label of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+property Statements: List[SequentialStatement]
+

Read-only property to access the list of sequential statements (_statements).

+
+
Returns:
+

A list of sequential statements.

+
+
+
+ +
+
+_label: Optional[str]
+

The label of a model entity.

+
+ +
+
+_normalizedLabel: Optional[str]
+

The normalized (lower case) label of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Sequential.WhileLoopStatement(condition, statements=None, label=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of WhileLoopStatement

+
+
Parameters:
+
+
+
+
+
+__init__(condition, statements=None, label=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+property Condition: BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal
+

Read-only property to access the condition of a statement (_condition).

+
+
Returns:
+

The expression representing the condition of a statement.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Label: str | None
+

Returns a model entity’s label.

+
+
Returns:
+

Label of a model entity.

+
+
+
+ +
+
+property NormalizedLabel: str | None
+

Returns a model entity’s normalized (lower case) label.

+
+
Returns:
+

Normalized label of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+property Statements: List[SequentialStatement]
+

Read-only property to access the list of sequential statements (_statements).

+
+
Returns:
+

A list of sequential statements.

+
+
+
+ +
+
+_label: Nullable[str]
+

The label of a model entity.

+
+ +
+
+_normalizedLabel: Nullable[str]
+

The normalized (lower case) label of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Sequential.LoopControlStatement(condition=None, loopLabel=None, parent=None)[source]
+

A LoopControlStatement is a base-class for all loop controlling statements.

+

Inheritance

+
+

Inheritance diagram of LoopControlStatement

+
+
Parameters:
+
+
+
+
+
+__init__(condition=None, loopLabel=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+property Condition: BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal
+

Read-only property to access the condition of a statement (_condition).

+
+
Returns:
+

The expression representing the condition of a statement.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Label: str | None
+

Returns a model entity’s label.

+
+
Returns:
+

Label of a model entity.

+
+
+
+ +
+
+property NormalizedLabel: str | None
+

Returns a model entity’s normalized (lower case) label.

+
+
Returns:
+

Normalized label of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_label: Nullable[str]
+

The label of a model entity.

+
+ +
+
+_normalizedLabel: Nullable[str]
+

The normalized (lower case) label of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Sequential.NextStatement(condition=None, loopLabel=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of NextStatement

+
+
Parameters:
+
+
+
+
+
+property Condition: BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal
+

Read-only property to access the condition of a statement (_condition).

+
+
Returns:
+

The expression representing the condition of a statement.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Label: str | None
+

Returns a model entity’s label.

+
+
Returns:
+

Label of a model entity.

+
+
+
+ +
+
+property NormalizedLabel: str | None
+

Returns a model entity’s normalized (lower case) label.

+
+
Returns:
+

Normalized label of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(condition=None, loopLabel=None, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+_label: Nullable[str]
+

The label of a model entity.

+
+ +
+
+_normalizedLabel: Nullable[str]
+

The normalized (lower case) label of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Sequential.ExitStatement(condition=None, loopLabel=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of ExitStatement

+
+
Parameters:
+
+
+
+
+
+property Condition: BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal
+

Read-only property to access the condition of a statement (_condition).

+
+
Returns:
+

The expression representing the condition of a statement.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Label: str | None
+

Returns a model entity’s label.

+
+
Returns:
+

Label of a model entity.

+
+
+
+ +
+
+property NormalizedLabel: str | None
+

Returns a model entity’s normalized (lower case) label.

+
+
Returns:
+

Normalized label of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(condition=None, loopLabel=None, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+_label: Nullable[str]
+

The label of a model entity.

+
+ +
+
+_normalizedLabel: Nullable[str]
+

The normalized (lower case) label of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Sequential.NullStatement(label=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of NullStatement

+
+
Parameters:
+

label (str | None)

+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Label: str | None
+

Returns a model entity’s label.

+
+
Returns:
+

Label of a model entity.

+
+
+
+ +
+
+property NormalizedLabel: str | None
+

Returns a model entity’s normalized (lower case) label.

+
+
Returns:
+

Normalized label of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(label=None, parent=None)
+

Initializes a VHDL model entity.

+
+
Parameters:
+
    +

  • parent – The parent model entity of this entity.

    • +

  • label (str | None)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+_label: Optional[str]
+

The label of a model entity.

+
+ +
+
+_normalizedLabel: Optional[str]
+

The normalized (lower case) label of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Sequential.ReturnStatement(returnValue=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of ReturnStatement

+
+
Parameters:
+
+
+
+
+
+property Condition: BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal
+

Read-only property to access the condition of a statement (_condition).

+
+
Returns:
+

The expression representing the condition of a statement.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Label: str | None
+

Returns a model entity’s label.

+
+
Returns:
+

Label of a model entity.

+
+
+
+ +
+
+property NormalizedLabel: str | None
+

Returns a model entity’s normalized (lower case) label.

+
+
Returns:
+

Normalized label of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(returnValue=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+_label: Nullable[str]
+

The label of a model entity.

+
+ +
+
+_normalizedLabel: Nullable[str]
+

The normalized (lower case) label of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Sequential.WaitStatement(sensitivityList=None, condition=None, timeout=None, label=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of WaitStatement

+
+
Parameters:
+
+
+
+
+
+property Condition: BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal
+

Read-only property to access the condition of a statement (_condition).

+
+
Returns:
+

The expression representing the condition of a statement.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Label: str | None
+

Returns a model entity’s label.

+
+
Returns:
+

Label of a model entity.

+
+
+
+ +
+
+property NormalizedLabel: str | None
+

Returns a model entity’s normalized (lower case) label.

+
+
Returns:
+

Normalized label of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_label: Nullable[str]
+

The label of a model entity.

+
+ +
+
+_normalizedLabel: Nullable[str]
+

The normalized (lower case) label of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+__init__(sensitivityList=None, condition=None, timeout=None, label=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+ +
+
+class pyVHDLModel.Sequential.SequentialDeclarationsMixin(declaredItems)[source]
+

Inheritance

+
+

Inheritance diagram of SequentialDeclarationsMixin

+
+
Parameters:
+

declaredItems (Iterable)

+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+__init__(declaredItems)[source]
+
+
Parameters:
+

declaredItems (Iterable)

+
+
Return type:
+

None

+
+
+
+ +
+ +
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/pyVHDLModel/pyVHDLModel.Subprogram.html b/pyVHDLModel/pyVHDLModel.Subprogram.html new file mode 100644 index 000000000..464ea4638 --- /dev/null +++ b/pyVHDLModel/pyVHDLModel.Subprogram.html @@ -0,0 +1,980 @@ + + + + + + + pyVHDLModel.Subprogram — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

pyVHDLModel.Subprogram

+

This module contains parts of an abstract document language model for VHDL.

+

Subprograms are procedures, functions and methods.

+

Classes

+
    +

  • Subprogram: +ModelEntity is the base-class for all classes in the VHDL language model, except for mixin classes (see multiple

    • +

  • Procedure: +ModelEntity is the base-class for all classes in the VHDL language model, except for mixin classes (see multiple

    • +

  • Function: +ModelEntity is the base-class for all classes in the VHDL language model, except for mixin classes (see multiple

    • +

  • MethodMixin: +A Method is a mixin class for all subprograms in a protected type.

    • +

  • ProcedureMethod: +ModelEntity is the base-class for all classes in the VHDL language model, except for mixin classes (see multiple

    • +

  • FunctionMethod: +ModelEntity is the base-class for all classes in the VHDL language model, except for mixin classes (see multiple

    • +
+
+

Classes

+
+
+class pyVHDLModel.Subprogram.Subprogram(identifier, isPure, documentation=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of Subprogram

+
+
Parameters:
+
+
+
+
+
+__init__(identifier, isPure, documentation=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
    +

  • parent (ModelEntity) – The parent model entity of this entity.

    • +

  • identifier (str)

    • +

  • isPure (bool)

    • +

  • documentation (str | None)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Subprogram.Procedure(identifier, documentation=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of Procedure

+
+
Parameters:
+
+
+
+
+
+__init__(identifier, documentation=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
    +

  • parent (ModelEntity) – The parent model entity of this entity.

    • +

  • identifier (str)

    • +

  • documentation (str | None)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Subprogram.Function(identifier, isPure=True, documentation=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of Function

+
+
Parameters:
+
+
+
+
+
+__init__(identifier, isPure=True, documentation=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
    +

  • parent (ModelEntity) – The parent model entity of this entity.

    • +

  • identifier (str)

    • +

  • isPure (bool)

    • +

  • documentation (str | None)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Subprogram.MethodMixin(protectedType)[source]
+

A Method is a mixin class for all subprograms in a protected type.

+

Inheritance

+
+

Inheritance diagram of MethodMixin

+
+
Parameters:
+

protectedType (ProtectedType)

+
+
+
+
+__init__(protectedType)[source]
+
+
Parameters:
+

protectedType (ProtectedType)

+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+ +
+
+class pyVHDLModel.Subprogram.ProcedureMethod(identifier, documentation=None, protectedType=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of ProcedureMethod

+
+
Parameters:
+
+
+
+
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+__init__(identifier, documentation=None, protectedType=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
    +

  • parent (ModelEntity) – The parent model entity of this entity.

    • +

  • identifier (str)

    • +

  • documentation (str | None)

    • +

  • protectedType (ProtectedType | None)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+ +
+
+class pyVHDLModel.Subprogram.FunctionMethod(identifier, isPure=True, documentation=None, protectedType=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of FunctionMethod

+
+
Parameters:
+
+
+
+
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+__init__(identifier, isPure=True, documentation=None, protectedType=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+ +
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/pyVHDLModel/pyVHDLModel.Symbol.html b/pyVHDLModel/pyVHDLModel.Symbol.html new file mode 100644 index 000000000..76839330b --- /dev/null +++ b/pyVHDLModel/pyVHDLModel.Symbol.html @@ -0,0 +1,2799 @@ + + + + + + + pyVHDLModel.Symbol — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

pyVHDLModel.Symbol

+

This module contains parts of an abstract document language model for VHDL.

+

Symbols are entity specific wrappers for names that reference VHDL language entities.

+

Classes

+ +
+

Classes

+
+
+class pyVHDLModel.Symbol.PossibleReference(value, names=<not given>, *values, module=None, qualname=None, type=None, start=1, boundary=None)[source]
+

Is an enumeration, representing possible targets for a reference in a Symbol.

+

Inheritance

+
+

Inheritance diagram of PossibleReference

+
+
+Library = 1
+

Library

+
+ +
+
+Entity = 2
+

Entity

+
+ +
+
+Architecture = 4
+

Architecture

+
+ +
+
+Component = 8
+

Component

+
+ +
+
+Package = 16
+

Package

+
+ +
+
+Configuration = 32
+

Configuration

+
+ +
+
+Context = 64
+

Context

+
+ +
+
+Type = 128
+

Type

+
+ +
+
+Subtype = 256
+

Subtype

+
+ +
+
+ScalarType = 512
+

ScalarType

+
+ +
+
+ArrayType = 1024
+

ArrayType

+
+ +
+
+RecordType = 2048
+

RecordType

+
+ +
+
+RecordElement = 4096
+

RecordElement

+
+ +
+
+AccessType = 8192
+

AccessType

+
+ +
+
+ProtectedType = 16384
+

ProtectedType

+
+ +
+
+FileType = 32768
+

FileType

+
+ +
+
+Attribute = 65536
+

Attribute

+
+ +
+
+TypeAttribute = 131072
+

TypeAttribute

+
+ +
+
+ValueAttribute = 262144
+

ValueAttribute

+
+ +
+
+SignalAttribute = 524288
+

SignalAttribute

+
+ +
+
+RangeAttribute = 1048576
+

RangeAttribute

+
+ +
+
+ViewAttribute = 2097152
+

ViewAttribute

+
+ +
+
+Constant = 4194304
+

Constant

+
+ +
+
+Variable = 8388608
+

Variable

+
+ +
+
+Signal = 16777216
+

Signal

+
+ +
+
+File = 33554432
+

File

+
+ +
+
+EnumLiteral = 67108864
+

EnumLiteral

+
+ +
+
+Procedure = 134217728
+

Procedure

+
+ +
+
+Function = 268435456
+

Function

+
+ +
+
+Label = 536870912
+

Label

+
+ +
+
+View = 1073741824
+

View

+
+ +
+
+AnyType = 61184
+

Any possible type incl. subtypes.

+
+ +
+
+SubProgram = 402653184
+

Any subprogram

+
+ +
+
+PackageMember = 432074504
+

Any member of a package

+
+ +
+
+SimpleNameInExpression = 364904960
+

Any possible item in an expression.

+
+ +
+
+static _generate_next_value_(name, start, count, last_values)
+

Generate the next value when not given.

+

name: the name of the member +start: the initial start value or None +count: the number of existing members +last_values: the last value assigned or None

+
+ +
+
+_numeric_repr_()
+

Return the canonical string representation of the object.

+

For many object types, including most builtins, eval(repr(obj)) == obj.

+
+ +
+
+classmethod _iter_member_by_value_(value)
+

Extract all members from the value in definition (i.e. increasing value) order.

+
+ +
+
+classmethod _iter_member_(value)
+

Extract all members from the value in definition (i.e. increasing value) order.

+
+ +
+
+classmethod _iter_member_by_def_(value)
+

Extract all members from the value in definition order.

+
+ +
+
+classmethod _missing_(value)
+

Create a composite member containing all canonical members present in value.

+

If non-member values are present, result depends on _boundary_ setting.

+
+ +
+
+__contains__(other)
+

Returns True if self has at least the same flags set as other.

+
+ +
+
+__iter__()
+

Returns flags in definition order.

+
+ +
+
+__len__()
+

Return the number of members (no aliases)

+
+ +
+
+__repr__()
+

Return repr(self).

+
+ +
+
+__str__()
+

Return str(self).

+
+ +
+
+__bool__()
+

classes/types should always be True.

+
+ +
+
+__or__(other)
+

Return self|value.

+
+ +
+
+__ror__(other)
+

Return value|self.

+
+ +
+
+__new__(value)
+
+ +
+ +
+
+class pyVHDLModel.Symbol.Symbol(name, possibleReferences)[source]
+

Base-class for all symbol classes.

+

Inheritance

+
+

Inheritance diagram of Symbol

+
+
Parameters:
+
+
+
+
+
+__init__(name, possibleReferences)[source]
+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+_name: Name
+

The name to reference the langauge entity.

+
+ +
+
+_possibleReferences: PossibleReference
+

An enumeration to filter possible references.

+
+ +
+
+_reference: Optional[Any]
+

The resolved language entity, otherwise None.

+
+ +
+
+__repr__()[source]
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+ +
+
+class pyVHDLModel.Symbol.LibraryReferenceSymbol(name)[source]
+

Represents a reference (name) to a library.

+

The internal name will be a SimpleName.

+
+

Example

+
library ieee;
+--      ^^^^
+
+
+
+

Inheritance

+
+

Inheritance diagram of LibraryReferenceSymbol

+
+
Parameters:
+

name (Name)

+
+
+
+
+__init__(name)[source]
+
+
Parameters:
+

name (Name)

+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_name: Name
+

The name to reference the langauge entity.

+
+ +
+
+_possibleReferences: PossibleReference
+

An enumeration to filter possible references.

+
+ +
+
+_reference: Optional[Any]
+

The resolved language entity, otherwise None.

+
+ +
+ +
+
+class pyVHDLModel.Symbol.PackageReferenceSymbol(name)[source]
+

Represents a reference (name) to a package.

+

The internal name will be a SelectedName.

+
+

Example

+
use ieee.numeric_std;
+--  ^^^^^^^^^^^^^^^^
+
+
+
+

Inheritance

+
+

Inheritance diagram of PackageReferenceSymbol

+
+
Parameters:
+

name (Name)

+
+
+
+
+__init__(name)[source]
+
+
Parameters:
+

name (Name)

+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_name: Name
+

The name to reference the langauge entity.

+
+ +
+
+_possibleReferences: PossibleReference
+

An enumeration to filter possible references.

+
+ +
+
+_reference: Optional[Any]
+

The resolved language entity, otherwise None.

+
+ +
+ +
+
+class pyVHDLModel.Symbol.ContextReferenceSymbol(name)[source]
+

Represents a reference (name) to a context.

+

The internal name will be a SelectedName.

+
+

Example

+
context ieee.ieee_std_context;
+--      ^^^^^^^^^^^^^^^^^^^^^
+
+
+
+

Inheritance

+
+

Inheritance diagram of ContextReferenceSymbol

+
+
Parameters:
+

name (Name)

+
+
+
+
+__init__(name)[source]
+
+
Parameters:
+

name (Name)

+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_name: Name
+

The name to reference the langauge entity.

+
+ +
+
+_possibleReferences: PossibleReference
+

An enumeration to filter possible references.

+
+ +
+
+_reference: Optional[Any]
+

The resolved language entity, otherwise None.

+
+ +
+ +
+
+class pyVHDLModel.Symbol.PackageMemberReferenceSymbol(name)[source]
+

Represents a reference (name) to a package member.

+

The internal name will be a SelectedName.

+
+

Example

+
use ieee.numeric_std.unsigned;
+--  ^^^^^^^^^^^^^^^^^^^^^^^^^
+
+
+
+

Inheritance

+
+

Inheritance diagram of PackageMemberReferenceSymbol

+
+
Parameters:
+

name (Name)

+
+
+
+
+__init__(name)[source]
+
+
Parameters:
+

name (Name)

+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_name: Name
+

The name to reference the langauge entity.

+
+ +
+
+_possibleReferences: PossibleReference
+

An enumeration to filter possible references.

+
+ +
+
+_reference: Optional[Any]
+

The resolved language entity, otherwise None.

+
+ +
+ +
+
+class pyVHDLModel.Symbol.AllPackageMembersReferenceSymbol(name)[source]
+

Represents a reference (name) to all package members.

+

The internal name will be a AllName.

+
+

Example

+
use ieee.numeric_std.all;
+--  ^^^^^^^^^^^^^^^^^^^^
+
+
+
+

Inheritance

+
+

Inheritance diagram of AllPackageMembersReferenceSymbol

+
+
Parameters:
+

name (AllName)

+
+
+
+
+__init__(name)[source]
+
+
Parameters:
+

name (AllName)

+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_name: Name
+

The name to reference the langauge entity.

+
+ +
+
+_possibleReferences: PossibleReference
+

An enumeration to filter possible references.

+
+ +
+
+_reference: Optional[Any]
+

The resolved language entity, otherwise None.

+
+ +
+ +
+
+class pyVHDLModel.Symbol.EntityInstantiationSymbol(name)[source]
+

Represents a reference (name) to an entity in a direct entity instantiation.

+

The internal name will be a SimpleName or SelectedName.

+
+

Example

+
inst : entity work.Counter;
+--            ^^^^^^^^^^^^
+
+
+
+

Inheritance

+
+

Inheritance diagram of EntityInstantiationSymbol

+
+
Parameters:
+

name (Name)

+
+
+
+
+__init__(name)[source]
+
+
Parameters:
+

name (Name)

+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_name: Name
+

The name to reference the langauge entity.

+
+ +
+
+_possibleReferences: PossibleReference
+

An enumeration to filter possible references.

+
+ +
+
+_reference: Optional[Any]
+

The resolved language entity, otherwise None.

+
+ +
+ +
+
+class pyVHDLModel.Symbol.ComponentInstantiationSymbol(name)[source]
+

Represents a reference (name) to an entity in a component instantiation.

+

The internal name will be a SimpleName or SelectedName.

+
+

Example

+
inst : component Counter;
+--               ^^^^^^^
+
+
+
+

Inheritance

+
+

Inheritance diagram of ComponentInstantiationSymbol

+
+
Parameters:
+

name (Name)

+
+
+
+
+__init__(name)[source]
+
+
Parameters:
+

name (Name)

+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_name: Name
+

The name to reference the langauge entity.

+
+ +
+
+_possibleReferences: PossibleReference
+

An enumeration to filter possible references.

+
+ +
+
+_reference: Optional[Any]
+

The resolved language entity, otherwise None.

+
+ +
+ +
+
+class pyVHDLModel.Symbol.ConfigurationInstantiationSymbol(name)[source]
+

Represents a reference (name) to an entity in a configuration instantiation.

+

The internal name will be a SimpleName or SelectedName.

+
+

Example

+
inst : configuration Counter;
+--                   ^^^^^^^
+
+
+
+

Inheritance

+
+

Inheritance diagram of ConfigurationInstantiationSymbol

+
+
Parameters:
+

name (Name)

+
+
+
+
+__init__(name)[source]
+
+
Parameters:
+

name (Name)

+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_name: Name
+

The name to reference the langauge entity.

+
+ +
+
+_possibleReferences: PossibleReference
+

An enumeration to filter possible references.

+
+ +
+
+_reference: Optional[Any]
+

The resolved language entity, otherwise None.

+
+ +
+ +
+
+class pyVHDLModel.Symbol.EntitySymbol(name)[source]
+

Represents a reference (name) to an entity in an architecture declaration.

+

The internal name will be a SimpleName or SelectedName.

+
+

Example

+
architecture rtl of Counter is
+--                  ^^^^^^^
+begin
+end architecture;
+
+
+
+

Inheritance

+
+

Inheritance diagram of EntitySymbol

+
+
Parameters:
+

name (Name)

+
+
+
+
+__init__(name)[source]
+
+
Parameters:
+

name (Name)

+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_name: Name
+

The name to reference the langauge entity.

+
+ +
+
+_possibleReferences: PossibleReference
+

An enumeration to filter possible references.

+
+ +
+
+_reference: Optional[Any]
+

The resolved language entity, otherwise None.

+
+ +
+ +
+
+class pyVHDLModel.Symbol.ArchitectureSymbol(name)[source]
+

An entity reference in an entity instantiation with architecture name.

+

Inheritance

+
+

Inheritance diagram of ArchitectureSymbol

+
+
Parameters:
+

name (Name)

+
+
+
+
+__init__(name)[source]
+
+
Parameters:
+

name (Name)

+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_name: Name
+

The name to reference the langauge entity.

+
+ +
+
+_possibleReferences: PossibleReference
+

An enumeration to filter possible references.

+
+ +
+
+_reference: Optional[Any]
+

The resolved language entity, otherwise None.

+
+ +
+ +
+
+class pyVHDLModel.Symbol.PackageSymbol(name)[source]
+

Represents a reference (name) to a package in a package body declaration.

+

The internal name will be a SimpleName or SelectedName.

+
+

Example

+
package body Utilities is
+--           ^^^^^^^^^
+end package body;
+
+
+
+

Inheritance

+
+

Inheritance diagram of PackageSymbol

+
+
Parameters:
+

name (Name)

+
+
+
+
+__init__(name)[source]
+
+
Parameters:
+

name (Name)

+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_name: Name
+

The name to reference the langauge entity.

+
+ +
+
+_possibleReferences: PossibleReference
+

An enumeration to filter possible references.

+
+ +
+
+_reference: Optional[Any]
+

The resolved language entity, otherwise None.

+
+ +
+ +
+
+class pyVHDLModel.Symbol.RecordElementSymbol(name)[source]
+

Inheritance

+
+

Inheritance diagram of RecordElementSymbol

+
+
Parameters:
+

name (Name)

+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_name: Name
+

The name to reference the langauge entity.

+
+ +
+
+_possibleReferences: PossibleReference
+

An enumeration to filter possible references.

+
+ +
+
+_reference: Optional[Any]
+

The resolved language entity, otherwise None.

+
+ +
+
+__init__(name)[source]
+
+
Parameters:
+

name (Name)

+
+
Return type:
+

None

+
+
+
+ +
+ +
+
+class pyVHDLModel.Symbol.SubtypeSymbol(name)[source]
+

Inheritance

+
+

Inheritance diagram of SubtypeSymbol

+
+
Parameters:
+

name (Name)

+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_name: Name
+

The name to reference the langauge entity.

+
+ +
+
+_possibleReferences: PossibleReference
+

An enumeration to filter possible references.

+
+ +
+
+_reference: Optional[Any]
+

The resolved language entity, otherwise None.

+
+ +
+
+__init__(name)[source]
+
+
Parameters:
+

name (Name)

+
+
Return type:
+

None

+
+
+
+ +
+ +
+
+class pyVHDLModel.Symbol.SimpleSubtypeSymbol(name)[source]
+

Inheritance

+
+

Inheritance diagram of SimpleSubtypeSymbol

+
+
Parameters:
+

name (Name)

+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+__init__(name)
+
+
Parameters:
+

name (Name)

+
+
Return type:
+

None

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_name: Name
+

The name to reference the langauge entity.

+
+ +
+
+_possibleReferences: PossibleReference
+

An enumeration to filter possible references.

+
+ +
+
+_reference: Optional[Any]
+

The resolved language entity, otherwise None.

+
+ +
+ +
+
+class pyVHDLModel.Symbol.ConstrainedScalarSubtypeSymbol(name)[source]
+

Inheritance

+
+

Inheritance diagram of ConstrainedScalarSubtypeSymbol

+
+
Parameters:
+

name (Name)

+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+__init__(name)
+
+
Parameters:
+

name (Name)

+
+
Return type:
+

None

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_name: Name
+

The name to reference the langauge entity.

+
+ +
+
+_possibleReferences: PossibleReference
+

An enumeration to filter possible references.

+
+ +
+
+_reference: Optional[Any]
+

The resolved language entity, otherwise None.

+
+ +
+ +
+
+class pyVHDLModel.Symbol.ConstrainedCompositeSubtypeSymbol(name)[source]
+

Inheritance

+
+

Inheritance diagram of ConstrainedCompositeSubtypeSymbol

+
+
Parameters:
+

name (Name)

+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+__init__(name)
+
+
Parameters:
+

name (Name)

+
+
Return type:
+

None

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_name: Name
+

The name to reference the langauge entity.

+
+ +
+
+_possibleReferences: PossibleReference
+

An enumeration to filter possible references.

+
+ +
+
+_reference: Optional[Any]
+

The resolved language entity, otherwise None.

+
+ +
+ +
+
+class pyVHDLModel.Symbol.ConstrainedArraySubtypeSymbol(name)[source]
+

Inheritance

+
+

Inheritance diagram of ConstrainedArraySubtypeSymbol

+
+
Parameters:
+

name (Name)

+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+__init__(name)
+
+
Parameters:
+

name (Name)

+
+
Return type:
+

None

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_name: Name
+

The name to reference the langauge entity.

+
+ +
+
+_possibleReferences: PossibleReference
+

An enumeration to filter possible references.

+
+ +
+
+_reference: Optional[Any]
+

The resolved language entity, otherwise None.

+
+ +
+ +
+
+class pyVHDLModel.Symbol.ConstrainedRecordSubtypeSymbol(name)[source]
+

Inheritance

+
+

Inheritance diagram of ConstrainedRecordSubtypeSymbol

+
+
Parameters:
+

name (Name)

+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+__init__(name)
+
+
Parameters:
+

name (Name)

+
+
Return type:
+

None

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_name: Name
+

The name to reference the langauge entity.

+
+ +
+
+_possibleReferences: PossibleReference
+

An enumeration to filter possible references.

+
+ +
+
+_reference: Optional[Any]
+

The resolved language entity, otherwise None.

+
+ +
+ +
+
+class pyVHDLModel.Symbol.SimpleObjectOrFunctionCallSymbol(name)[source]
+

Inheritance

+
+

Inheritance diagram of SimpleObjectOrFunctionCallSymbol

+
+
Parameters:
+

name (Name)

+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_name: Name
+

The name to reference the langauge entity.

+
+ +
+
+_possibleReferences: PossibleReference
+

An enumeration to filter possible references.

+
+ +
+
+_reference: Optional[Any]
+

The resolved language entity, otherwise None.

+
+ +
+
+__init__(name)[source]
+
+
Parameters:
+

name (Name)

+
+
Return type:
+

None

+
+
+
+ +
+ +
+
+class pyVHDLModel.Symbol.IndexedObjectOrFunctionCallSymbol(name)[source]
+

Inheritance

+
+

Inheritance diagram of IndexedObjectOrFunctionCallSymbol

+
+
Parameters:
+

name (Name)

+
+
+
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+__str__()
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_name: Name
+

The name to reference the langauge entity.

+
+ +
+
+_possibleReferences: PossibleReference
+

An enumeration to filter possible references.

+
+ +
+
+_reference: Optional[Any]
+

The resolved language entity, otherwise None.

+
+ +
+
+__init__(name)[source]
+
+
Parameters:
+

name (Name)

+
+
Return type:
+

None

+
+
+
+ +
+ +
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/pyVHDLModel/pyVHDLModel.Type.html b/pyVHDLModel/pyVHDLModel.Type.html new file mode 100644 index 000000000..bd9c4cbb1 --- /dev/null +++ b/pyVHDLModel/pyVHDLModel.Type.html @@ -0,0 +1,3100 @@ + + + + + + + pyVHDLModel.Type — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

pyVHDLModel.Type

+

This module contains parts of an abstract document language model for VHDL.

+

Types.

+

Classes

+
    +

  • BaseType: +BaseType is the base-class of all type entities in this model.

    • +

  • Type: +BaseType is the base-class of all type entities in this model.

    • +

  • AnonymousType: +BaseType is the base-class of all type entities in this model.

    • +

  • FullType: +BaseType is the base-class of all type entities in this model.

    • +

  • Subtype: +BaseType is the base-class of all type entities in this model.

    • +

  • ScalarType: +A ScalarType is a base-class for all scalar types.

    • +

  • RangedScalarType: +A RangedScalarType is a base-class for all scalar types with a range.

    • +

  • NumericTypeMixin: +A NumericType is a mixin class for all numeric types.

    • +

  • DiscreteTypeMixin: +A DiscreteType is a mixin class for all discrete types.

    • +

  • EnumeratedType: +A ScalarType is a base-class for all scalar types.

    • +

  • IntegerType: +A RangedScalarType is a base-class for all scalar types with a range.

    • +

  • RealType: +A RangedScalarType is a base-class for all scalar types with a range.

    • +

  • PhysicalType: +A RangedScalarType is a base-class for all scalar types with a range.

    • +

  • CompositeType: +A CompositeType is a base-class for all composite types.

    • +

  • ArrayType: +A CompositeType is a base-class for all composite types.

    • +

  • RecordTypeElement: +ModelEntity is the base-class for all classes in the VHDL language model, except for mixin classes (see multiple

    • +

  • RecordType: +A CompositeType is a base-class for all composite types.

    • +

  • ProtectedType: +BaseType is the base-class of all type entities in this model.

    • +

  • ProtectedTypeBody: +BaseType is the base-class of all type entities in this model.

    • +

  • AccessType: +BaseType is the base-class of all type entities in this model.

    • +

  • FileType: +BaseType is the base-class of all type entities in this model.

    • +
+
+

Classes

+
+
+class pyVHDLModel.Type.BaseType(identifier, documentation=None, parent=None)[source]
+

BaseType is the base-class of all type entities in this model.

+

Inheritance

+
+

Inheritance diagram of BaseType

+
+
Parameters:
+
+
+
+
+
+__init__(identifier, documentation=None, parent=None)[source]
+

Initializes underlying BaseType.

+
+
Parameters:
+
    +

  • identifier (str) – Name of the type.

    • +

  • parent (ModelEntity) – Reference to the logical parent in the model hierarchy.

    • +

  • documentation (str | None)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_documentation: Optional[str]
+

The associated documentation of a model entity.

+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Type.Type(identifier, documentation=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of Type

+
+
Parameters:
+
+
+
+
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(identifier, documentation=None, parent=None)
+

Initializes underlying BaseType.

+
+
Parameters:
+
    +

  • identifier (str) – Name of the type.

    • +

  • parent (ModelEntity) – Reference to the logical parent in the model hierarchy.

    • +

  • documentation (str | None)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+_documentation: Optional[str]
+

The associated documentation of a model entity.

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Type.AnonymousType(identifier, documentation=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of AnonymousType

+
+
Parameters:
+
+
+
+
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(identifier, documentation=None, parent=None)
+

Initializes underlying BaseType.

+
+
Parameters:
+
    +

  • identifier (str) – Name of the type.

    • +

  • parent (ModelEntity) – Reference to the logical parent in the model hierarchy.

    • +

  • documentation (str | None)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+_documentation: Optional[str]
+

The associated documentation of a model entity.

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Type.FullType(identifier, documentation=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of FullType

+
+
Parameters:
+
+
+
+
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(identifier, documentation=None, parent=None)
+

Initializes underlying BaseType.

+
+
Parameters:
+
    +

  • identifier (str) – Name of the type.

    • +

  • parent (ModelEntity) – Reference to the logical parent in the model hierarchy.

    • +

  • documentation (str | None)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+_documentation: Optional[str]
+

The associated documentation of a model entity.

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Type.Subtype(identifier, symbol, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of Subtype

+
+
Parameters:
+
+
+
+
+
+__init__(identifier, symbol, parent=None)[source]
+

Initializes underlying BaseType.

+
+
Parameters:
+
    +

  • identifier (str) – Name of the type.

    • +

  • parent (ModelEntity) – Reference to the logical parent in the model hierarchy.

    • +

  • symbol (Symbol)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Type.ScalarType(identifier, documentation=None, parent=None)[source]
+

A ScalarType is a base-class for all scalar types.

+

Inheritance

+
+

Inheritance diagram of ScalarType

+
+
Parameters:
+
+
+
+
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(identifier, documentation=None, parent=None)
+

Initializes underlying BaseType.

+
+
Parameters:
+
    +

  • identifier (str) – Name of the type.

    • +

  • parent (ModelEntity) – Reference to the logical parent in the model hierarchy.

    • +

  • documentation (str | None)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+_documentation: Optional[str]
+

The associated documentation of a model entity.

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Type.RangedScalarType(identifier, rng, parent=None)[source]
+

A RangedScalarType is a base-class for all scalar types with a range.

+

Inheritance

+
+

Inheritance diagram of RangedScalarType

+
+
Parameters:
+
+
+
+
+
+__init__(identifier, rng, parent=None)[source]
+

Initializes underlying BaseType.

+
+
Parameters:
+
    +

  • identifier (str) – Name of the type.

    • +

  • parent (ModelEntity) – Reference to the logical parent in the model hierarchy.

    • +

  • rng (Range | Name)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Type.NumericTypeMixin[source]
+

A NumericType is a mixin class for all numeric types.

+

Inheritance

+
+

Inheritance diagram of NumericTypeMixin

+
+
+
+
+__init__()[source]
+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+ +
+
+class pyVHDLModel.Type.DiscreteTypeMixin[source]
+

A DiscreteType is a mixin class for all discrete types.

+

Inheritance

+
+

Inheritance diagram of DiscreteTypeMixin

+
+
+
+
+__init__()[source]
+
+
Return type:
+

None

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+ +
+
+class pyVHDLModel.Type.EnumeratedType(identifier, literals, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of EnumeratedType

+
+
Parameters:
+
+
+
+
+
+__init__(identifier, literals, parent=None)[source]
+

Initializes underlying BaseType.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_documentation: Optional[str]
+

The associated documentation of a model entity.

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Type.IntegerType(identifier, rng, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of IntegerType

+
+
Parameters:
+
+
+
+
+
+__init__(identifier, rng, parent=None)[source]
+

Initializes underlying BaseType.

+
+
Parameters:
+
    +

  • identifier (str) – Name of the type.

    • +

  • parent (ModelEntity) – Reference to the logical parent in the model hierarchy.

    • +

  • rng (Range | Name)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Type.RealType(identifier, rng, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of RealType

+
+
Parameters:
+
+
+
+
+
+__init__(identifier, rng, parent=None)[source]
+

Initializes underlying BaseType.

+
+
Parameters:
+
    +

  • identifier (str) – Name of the type.

    • +

  • parent (ModelEntity) – Reference to the logical parent in the model hierarchy.

    • +

  • rng (Range | Name)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Type.PhysicalType(identifier, rng, primaryUnit, units, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of PhysicalType

+
+
Parameters:
+
+
+
+
+
+__init__(identifier, rng, primaryUnit, units, parent=None)[source]
+

Initializes underlying BaseType.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Type.CompositeType(identifier, documentation=None, parent=None)[source]
+

A CompositeType is a base-class for all composite types.

+

Inheritance

+
+

Inheritance diagram of CompositeType

+
+
Parameters:
+
+
+
+
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+__init__(identifier, documentation=None, parent=None)
+

Initializes underlying BaseType.

+
+
Parameters:
+
    +

  • identifier (str) – Name of the type.

    • +

  • parent (ModelEntity) – Reference to the logical parent in the model hierarchy.

    • +

  • documentation (str | None)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+_documentation: Optional[str]
+

The associated documentation of a model entity.

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Type.ArrayType(identifier, indices, elementSubtype, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of ArrayType

+
+
Parameters:
+
+
+
+
+
+__init__(identifier, indices, elementSubtype, parent=None)[source]
+

Initializes underlying BaseType.

+
+
Parameters:
+
    +

  • identifier (str) – Name of the type.

    • +

  • parent (ModelEntity) – Reference to the logical parent in the model hierarchy.

    • +

  • indices (Iterable)

    • +

  • elementSubtype (Symbol)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_documentation: Optional[str]
+

The associated documentation of a model entity.

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Type.RecordTypeElement(identifiers, subtype, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of RecordTypeElement

+
+
Parameters:
+
+
+
+
+
+__init__(identifiers, subtype, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+_identifiers: Tuple[str]
+

A list of identifiers.

+
+ +
+
+_normalizedIdentifiers: Tuple[str]
+

A list of normalized (lower case) identifiers.

+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifiers: Tuple[str]
+

Returns a model entity’s tuple of identifiers (names).

+
+
Returns:
+

Tuple of identifiers.

+
+
+
+ +
+
+property NormalizedIdentifiers: Tuple[str]
+

Returns a model entity’s tuple of normalized identifiers (lower case names).

+
+
Returns:
+

Tuple of normalized identifiers.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Type.RecordType(identifier, elements=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of RecordType

+
+
Parameters:
+
+
+
+
+
+__init__(identifier, elements=None, parent=None)[source]
+

Initializes underlying BaseType.

+
+
Parameters:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_documentation: Optional[str]
+

The associated documentation of a model entity.

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Type.ProtectedType(identifier, methods=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of ProtectedType

+
+
Parameters:
+
+
+
+
+
+__init__(identifier, methods=None, parent=None)[source]
+

Initializes underlying BaseType.

+
+
Parameters:
+
    +

  • identifier (str) – Name of the type.

    • +

  • parent (ModelEntity) – Reference to the logical parent in the model hierarchy.

    • +

  • methods (List | Iterator)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Type.ProtectedTypeBody(identifier, declaredItems=None, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of ProtectedTypeBody

+
+
Parameters:
+
+
+
+
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_documentation: Nullable[str]
+

The associated documentation of a model entity.

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+__init__(identifier, declaredItems=None, parent=None)[source]
+

Initializes underlying BaseType.

+
+
Parameters:
+
    +

  • identifier (str) – Name of the type.

    • +

  • parent (ModelEntity) – Reference to the logical parent in the model hierarchy.

    • +

  • declaredItems (List | Iterator)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+ +
+
+class pyVHDLModel.Type.AccessType(identifier, designatedSubtype, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of AccessType

+
+
Parameters:
+
+
+
+
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_documentation: Optional[str]
+

The associated documentation of a model entity.

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+__init__(identifier, designatedSubtype, parent=None)[source]
+

Initializes underlying BaseType.

+
+
Parameters:
+
    +

  • identifier (str) – Name of the type.

    • +

  • parent (ModelEntity) – Reference to the logical parent in the model hierarchy.

    • +

  • designatedSubtype (Symbol)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+ +
+
+class pyVHDLModel.Type.FileType(identifier, designatedSubtype, parent=None)[source]
+

Inheritance

+
+

Inheritance diagram of FileType

+
+
Parameters:
+
+
+
+
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_documentation: Optional[str]
+

The associated documentation of a model entity.

+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+__init__(identifier, designatedSubtype, parent=None)[source]
+

Initializes underlying BaseType.

+
+
Parameters:
+
    +

  • identifier (str) – Name of the type.

    • +

  • parent (ModelEntity) – Reference to the logical parent in the model hierarchy.

    • +

  • designatedSubtype (Symbol)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+ +
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/pyVHDLModel/pyVHDLModel.html b/pyVHDLModel/pyVHDLModel.html new file mode 100644 index 000000000..f380f5f1e --- /dev/null +++ b/pyVHDLModel/pyVHDLModel.html @@ -0,0 +1,3480 @@ + + + + + + + pyVHDLModel — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

pyVHDLModel

+

An abstract VHDL language model.

+

This package provides a unified abstract language model for VHDL. Projects reading from source files can derive own +classes and implement additional logic to create a concrete language model for their tools.

+

Projects consuming pre-processed VHDL data (parsed, analyzed or elaborated) can build higher level features and services +on such a model, while supporting multiple frontends.

+
+

Copyright Information

+
+
copyright:
+

Copyright 2017-2024 Patrick Lehmann - Bötzingen, Germany

+
+
copyright:
+

Copyright 2016-2017 Patrick Lehmann - Dresden, Germany

+
+
license:
+

Apache License, Version 2.0

+
+
+
+

Submodules

+
+ +
+

Classes

+
    +

  • VHDLVersion: +An enumeration for all possible version numbers for VHDL and VHDL-AMS.

    • +

  • ObjectClass: +An ObjectClass is an enumeration and represents an object’s class (constant, signal, …).

    • +

  • DesignUnitKind: +A DesignUnitKind is an enumeration and represents the kind of design unit (Entity, Architecture, …).

    • +

  • DependencyGraphVertexKind: +A DependencyGraphVertexKind is an enumeration and represents the kind of vertex in the dependency graph.

    • +

  • DependencyGraphEdgeKind: +A DependencyGraphEdgeKind is an enumeration and represents the kind of edge in the dependency graph.

    • +

  • ObjectGraphVertexKind: +A ObjectGraphVertexKind is an enumeration and represents the kind of vertex in the object graph.

    • +

  • ObjectGraphEdgeKind: +A ObjectGraphEdgeKind is an enumeration and represents the kind of edge in the object graph.

    • +

  • Design: +A Design represents set of VHDL libraries as well as all loaded and analysed source files (see Document).

    • +

  • Library: +A Library represents a VHDL library. It contains all primary and secondary design units.

    • +

  • Document: +A Document represents a sourcefile. It contains primary and secondary design units.

    • +
+
+

Classes

+
+
+class pyVHDLModel.VHDLVersion(*_)[source]
+

An enumeration for all possible version numbers for VHDL and VHDL-AMS.

+

A version can be given as integer or string and is represented as a unified +enumeration value.

+

This enumeration supports compare operators.

+

Inheritance

+
+

Inheritance diagram of VHDLVersion

+
+
+Any = -1
+

Any

+
+ +
+
+VHDL87 = 87
+

VHDL-1987

+
+ +
+
+VHDL93 = 93
+

VHDL-1993

+
+ +
+
+AMS93 = 1993
+

VHDL-AMS-1993

+
+ +
+
+AMS99 = 1999
+

VHDL-AMS-1999

+
+ +
+
+VHDL2000 = 2000
+

VHDL-2000

+
+ +
+
+VHDL2002 = 2002
+

VHDL-2002

+
+ +
+
+VHDL2008 = 2008
+

VHDL-2008

+
+ +
+
+AMS2017 = 2017
+

VHDL-AMS-2017

+
+ +
+
+VHDL2019 = 2019
+

VHDL-2019

+
+ +
+
+Latest = 10000
+

Latest VHDL (2019)

+
+ +
+
+__VERSION_MAPPINGS__: Dict[Union[int, str], Enum] = {'00': 2000, '02': 2002, '08': 2008, '17': 2017, '19': 2019, '1987': 87, '1993': 1993, '1999': 1999, '2000': 2000, '2002': 2002, '2008': 2008, '2017': 2017, '2019': 2019, '87': 87, '93': 93, '99': 1999, 'Any': Any, 'Latest': Latest, -1: Any, 0: 2000, 10000: Latest, 17: 2017, 19: 2019, 1987: 87, 1993: 1993, 1999: 1999, 2: 2002, 2000: 2000, 2002: 2002, 2008: 2008, 2017: 2017, 2019: 2019, 8: 2008, 87: 87, 93: 93, 99: 1999}
+

Dictionary of VHDL and VHDL-AMS year codes variants as integer and strings for mapping to unique enum values.

+
+ +
+
+__init__(*_)[source]
+

Patch the embedded MAP dictionary

+
+
Return type:
+

None

+
+
+
+ +
+
+classmethod Parse(value)[source]
+

Parses a VHDL or VHDL-AMS year code as integer or string to an enum value.

+
+
Parameters:
+

value (Union[int, str]) – VHDL/VHDL-AMS year code.

+
+
Return type:
+

VHDLVersion

+
+
Returns:
+

Enumeration value.

+
+
Raises:
+

ValueError – If the year code is not recognized.

+
+
+
+ +
+
+__lt__(other)[source]
+

Compare two VHDL/VHDL-AMS versions if the version is less than the second operand.

+
+
Parameters:
+

other (-1) – Parameter to compare against.

+
+
Return type:
+

bool

+
+
Returns:
+

True if version is less than the second operand.

+
+
Raises:
+

TypeError – If parameter other is not of type VHDLVersion.

+
+
+
+ +
+
+__le__(other)[source]
+

Compare two VHDL/VHDL-AMS versions if the version is less or equal than the second operand.

+
+
Parameters:
+

other (-1) – Parameter to compare against.

+
+
Return type:
+

bool

+
+
Returns:
+

True if version is less or equal than the second operand.

+
+
Raises:
+

TypeError – If parameter other is not of type VHDLVersion.

+
+
+
+ +
+
+__gt__(other)[source]
+

Compare two VHDL/VHDL-AMS versions if the version is greater than the second operand.

+
+
Parameters:
+

other (-1) – Parameter to compare against.

+
+
Return type:
+

bool

+
+
Returns:
+

True if version is greater than the second operand.

+
+
Raises:
+

TypeError – If parameter other is not of type VHDLVersion.

+
+
+
+ +
+
+__ge__(other)[source]
+

Compare two VHDL/VHDL-AMS versions if the version is greater or equal than the second operand.

+
+
Parameters:
+

other (-1) – Parameter to compare against.

+
+
Return type:
+

bool

+
+
Returns:
+

True if version is greater or equal than the second operand.

+
+
Raises:
+

TypeError – If parameter other is not of type VHDLVersion.

+
+
+
+ +
+
+__ne__(other)[source]
+

Compare two VHDL/VHDL-AMS versions if the version is unequal to the second operand.

+
+
Parameters:
+

other (-1) – Parameter to compare against.

+
+
Return type:
+

bool

+
+
Returns:
+

True if version is unequal to the second operand.

+
+
Raises:
+

TypeError – If parameter other is not of type VHDLVersion.

+
+
+
+ +
+
+__eq__(other)[source]
+

Compare two VHDL/VHDL-AMS versions if the version is equal to the second operand.

+
+
Parameters:
+

other (-1) – Parameter to compare against.

+
+
Return type:
+

bool

+
+
Returns:
+

True if version is equal to the second operand.

+
+
Raises:
+

TypeError – If parameter other is not of type VHDLVersion.

+
+
+
+ +
+
+property IsVHDL: bool
+

Checks if the version is a VHDL (not VHDL-AMS) version.

+
+
Returns:
+

True if version is a VHDL version.

+
+
+
+ +
+
+property IsAMS: bool
+

Checks if the version is a VHDL-AMS (not VHDL) version.

+
+
Returns:
+

True if version is a VHDL-AMS version.

+
+
+
+ +
+
+__str__()[source]
+

Formats the VHDL version to pattern VHDL'xx or in case of VHDL-AMS to VHDL-AMS'xx.

+
+
Return type:
+

str

+
+
Returns:
+

Formatted VHDL/VHDL-AMS version.

+
+
+
+ +
+
+__repr__()[source]
+

Formats the VHDL/VHDL-AMS version to pattern xxxx.

+
+
Return type:
+

str

+
+
Returns:
+

Formatted VHDL/VHDL-AMS version.

+
+
+
+ +
+
+__hash__ = None
+
+ +
+ +
+
+class pyVHDLModel.ObjectClass(value, names=<not given>, *values, module=None, qualname=None, type=None, start=1, boundary=None)[source]
+

An ObjectClass is an enumeration and represents an object’s class (constant, signal, …).

+

In case no object class is defined, Default is used, so the object class is inferred from context.

+

Inheritance

+
+

Inheritance diagram of ObjectClass

+
+
+Default = 0
+

Object class not defined, thus it’s context dependent.

+
+ +
+
+Constant = 1
+

Constant

+
+ +
+
+Variable = 2
+

Variable

+
+ +
+
+Signal = 3
+

Signal

+
+ +
+
+File = 4
+

File

+
+ +
+
+Type = 5
+

Type

+
+ +
+
+Procedure = 6
+

Procedure

+
+ +
+
+Function = 7
+

Function

+
+ +
+
+__str__()[source]
+

Formats the object class.

+
+
Return type:
+

str

+
+
Returns:
+

Formatted object class.

+
+
+
+ +
+ +
+
+class pyVHDLModel.DesignUnitKind(value, names=<not given>, *values, module=None, qualname=None, type=None, start=1, boundary=None)[source]
+

A DesignUnitKind is an enumeration and represents the kind of design unit (Entity, Architecture, …).

+

Inheritance

+
+

Inheritance diagram of DesignUnitKind

+
+
+Context = 1
+

Context

+
+ +
+
+Package = 2
+

Package

+
+ +
+
+PackageBody = 4
+

Package Body

+
+ +
+
+Entity = 8
+

Entity

+
+ +
+
+Architecture = 16
+

Architecture

+
+ +
+
+Configuration = 32
+

Configuration

+
+ +
+
+Primary = 43
+

List of primary design units.

+
+ +
+
+Secondary = 20
+

List of secondary design units.

+
+ +
+
+WithContext = 62
+

List of design units with a context.

+
+ +
+
+WithDeclaredItems = 30
+

List of design units having a declaration region.

+
+ +
+
+All = 63
+

List of all design units.

+
+ +
+
+static _generate_next_value_(name, start, count, last_values)
+

Generate the next value when not given.

+

name: the name of the member +start: the initial start value or None +count: the number of existing members +last_values: the last value assigned or None

+
+ +
+
+_numeric_repr_()
+

Return the canonical string representation of the object.

+

For many object types, including most builtins, eval(repr(obj)) == obj.

+
+ +
+
+classmethod _iter_member_by_value_(value)
+

Extract all members from the value in definition (i.e. increasing value) order.

+
+ +
+
+classmethod _iter_member_(value)
+

Extract all members from the value in definition (i.e. increasing value) order.

+
+ +
+
+classmethod _iter_member_by_def_(value)
+

Extract all members from the value in definition order.

+
+ +
+
+classmethod _missing_(value)
+

Create a composite member containing all canonical members present in value.

+

If non-member values are present, result depends on _boundary_ setting.

+
+ +
+
+__contains__(other)
+

Returns True if self has at least the same flags set as other.

+
+ +
+
+__iter__()
+

Returns flags in definition order.

+
+ +
+
+__len__()
+

Return the number of members (no aliases)

+
+ +
+
+__repr__()
+

Return repr(self).

+
+ +
+
+__str__()
+

Return str(self).

+
+ +
+
+__bool__()
+

classes/types should always be True.

+
+ +
+
+__or__(other)
+

Return self|value.

+
+ +
+
+__ror__(other)
+

Return value|self.

+
+ +
+
+__new__(value)
+
+ +
+ +
+
+class pyVHDLModel.DependencyGraphVertexKind(value, names=<not given>, *values, module=None, qualname=None, type=None, start=1, boundary=None)[source]
+

A DependencyGraphVertexKind is an enumeration and represents the kind of vertex in the dependency graph.

+

Inheritance

+
+

Inheritance diagram of DependencyGraphVertexKind

+
+
+Document = 1
+

A document (VHDL source file).

+
+ +
+
+Library = 2
+

A VHDL library.

+
+ +
+
+Context = 4
+

A context design unit.

+
+ +
+
+Package = 8
+

A package design unit.

+
+ +
+
+PackageBody = 16
+

A package body design unit.

+
+ +
+
+Entity = 32
+

A entity design unit.

+
+ +
+
+Architecture = 64
+

A architecture design unit.

+
+ +
+
+Component = 128
+

A VHDL component.

+
+ +
+
+Configuration = 256
+

A configuration design unit.

+
+ +
+
+static _generate_next_value_(name, start, count, last_values)
+

Generate the next value when not given.

+

name: the name of the member +start: the initial start value or None +count: the number of existing members +last_values: the last value assigned or None

+
+ +
+
+_numeric_repr_()
+

Return the canonical string representation of the object.

+

For many object types, including most builtins, eval(repr(obj)) == obj.

+
+ +
+
+classmethod _iter_member_by_value_(value)
+

Extract all members from the value in definition (i.e. increasing value) order.

+
+ +
+
+classmethod _iter_member_(value)
+

Extract all members from the value in definition (i.e. increasing value) order.

+
+ +
+
+classmethod _iter_member_by_def_(value)
+

Extract all members from the value in definition order.

+
+ +
+
+classmethod _missing_(value)
+

Create a composite member containing all canonical members present in value.

+

If non-member values are present, result depends on _boundary_ setting.

+
+ +
+
+__contains__(other)
+

Returns True if self has at least the same flags set as other.

+
+ +
+
+__iter__()
+

Returns flags in definition order.

+
+ +
+
+__len__()
+

Return the number of members (no aliases)

+
+ +
+
+__repr__()
+

Return repr(self).

+
+ +
+
+__str__()
+

Return str(self).

+
+ +
+
+__bool__()
+

classes/types should always be True.

+
+ +
+
+__or__(other)
+

Return self|value.

+
+ +
+
+__ror__(other)
+

Return value|self.

+
+ +
+
+__new__(value)
+
+ +
+ +
+
+class pyVHDLModel.DependencyGraphEdgeKind(value, names=<not given>, *values, module=None, qualname=None, type=None, start=1, boundary=None)[source]
+

A DependencyGraphEdgeKind is an enumeration and represents the kind of edge in the dependency graph.

+

Inheritance

+
+

Inheritance diagram of DependencyGraphEdgeKind

+
+
+static _generate_next_value_(name, start, count, last_values)
+

Generate the next value when not given.

+

name: the name of the member +start: the initial start value or None +count: the number of existing members +last_values: the last value assigned or None

+
+ +
+
+_numeric_repr_()
+

Return the canonical string representation of the object.

+

For many object types, including most builtins, eval(repr(obj)) == obj.

+
+ +
+
+classmethod _iter_member_by_value_(value)
+

Extract all members from the value in definition (i.e. increasing value) order.

+
+ +
+
+classmethod _iter_member_(value)
+

Extract all members from the value in definition (i.e. increasing value) order.

+
+ +
+
+classmethod _iter_member_by_def_(value)
+

Extract all members from the value in definition order.

+
+ +
+
+classmethod _missing_(value)
+

Create a composite member containing all canonical members present in value.

+

If non-member values are present, result depends on _boundary_ setting.

+
+ +
+
+__contains__(other)
+

Returns True if self has at least the same flags set as other.

+
+ +
+
+__iter__()
+

Returns flags in definition order.

+
+ +
+
+__len__()
+

Return the number of members (no aliases)

+
+ +
+
+__repr__()
+

Return repr(self).

+
+ +
+
+__str__()
+

Return str(self).

+
+ +
+
+__bool__()
+

classes/types should always be True.

+
+ +
+
+__or__(other)
+

Return self|value.

+
+ +
+
+__ror__(other)
+

Return value|self.

+
+ +
+
+__new__(value)
+
+ +
+ +
+
+class pyVHDLModel.ObjectGraphVertexKind(value, names=<not given>, *values, module=None, qualname=None, type=None, start=1, boundary=None)[source]
+

A ObjectGraphVertexKind is an enumeration and represents the kind of vertex in the object graph.

+

Inheritance

+
+

Inheritance diagram of ObjectGraphVertexKind

+
+
+static _generate_next_value_(name, start, count, last_values)
+

Generate the next value when not given.

+

name: the name of the member +start: the initial start value or None +count: the number of existing members +last_values: the last value assigned or None

+
+ +
+
+_numeric_repr_()
+

Return the canonical string representation of the object.

+

For many object types, including most builtins, eval(repr(obj)) == obj.

+
+ +
+
+classmethod _iter_member_by_value_(value)
+

Extract all members from the value in definition (i.e. increasing value) order.

+
+ +
+
+classmethod _iter_member_(value)
+

Extract all members from the value in definition (i.e. increasing value) order.

+
+ +
+
+classmethod _iter_member_by_def_(value)
+

Extract all members from the value in definition order.

+
+ +
+
+classmethod _missing_(value)
+

Create a composite member containing all canonical members present in value.

+

If non-member values are present, result depends on _boundary_ setting.

+
+ +
+
+__contains__(other)
+

Returns True if self has at least the same flags set as other.

+
+ +
+
+__iter__()
+

Returns flags in definition order.

+
+ +
+
+__len__()
+

Return the number of members (no aliases)

+
+ +
+
+__repr__()
+

Return repr(self).

+
+ +
+
+__str__()
+

Return str(self).

+
+ +
+
+__bool__()
+

classes/types should always be True.

+
+ +
+
+__or__(other)
+

Return self|value.

+
+ +
+
+__ror__(other)
+

Return value|self.

+
+ +
+
+__new__(value)
+
+ +
+ +
+
+class pyVHDLModel.ObjectGraphEdgeKind(value, names=<not given>, *values, module=None, qualname=None, type=None, start=1, boundary=None)[source]
+

A ObjectGraphEdgeKind is an enumeration and represents the kind of edge in the object graph.

+

Inheritance

+
+

Inheritance diagram of ObjectGraphEdgeKind

+
+
+static _generate_next_value_(name, start, count, last_values)
+

Generate the next value when not given.

+

name: the name of the member +start: the initial start value or None +count: the number of existing members +last_values: the last value assigned or None

+
+ +
+
+_numeric_repr_()
+

Return the canonical string representation of the object.

+

For many object types, including most builtins, eval(repr(obj)) == obj.

+
+ +
+
+classmethod _iter_member_by_value_(value)
+

Extract all members from the value in definition (i.e. increasing value) order.

+
+ +
+
+classmethod _iter_member_(value)
+

Extract all members from the value in definition (i.e. increasing value) order.

+
+ +
+
+classmethod _iter_member_by_def_(value)
+

Extract all members from the value in definition order.

+
+ +
+
+classmethod _missing_(value)
+

Create a composite member containing all canonical members present in value.

+

If non-member values are present, result depends on _boundary_ setting.

+
+ +
+
+__contains__(other)
+

Returns True if self has at least the same flags set as other.

+
+ +
+
+__iter__()
+

Returns flags in definition order.

+
+ +
+
+__len__()
+

Return the number of members (no aliases)

+
+ +
+
+__repr__()
+

Return repr(self).

+
+ +
+
+__str__()
+

Return str(self).

+
+ +
+
+__bool__()
+

classes/types should always be True.

+
+ +
+
+__or__(other)
+

Return self|value.

+
+ +
+
+__ror__(other)
+

Return value|self.

+
+ +
+
+__new__(value)
+
+ +
+ +
+
+class pyVHDLModel.Design(name=None)[source]
+

A Design represents set of VHDL libraries as well as all loaded and analysed source files (see Document).

+

It’s the root of this code document-object-model (CodeDOM). It contains at least one VHDL library (see Library). When the design is +analysed (see Analyze()), multiple graph data structures will be created and populated with vertices and edges. As a first result, the design’s compile +order and hierarchy can be iterated. As a second result, the design’s top-level is identified and referenced from the design (see TopLevel).

+

The design contains references to the following graphs:

+ +

Inheritance

+
+

Inheritance diagram of Design

+
+
Parameters:
+

name (str | None)

+
+
+
+
+__init__(name=None)[source]
+

Initializes a VHDL design.

+
+
Parameters:
+

name (Optional[str]) – Name of the design.

+
+
Return type:
+

None

+
+
+
+ +
+
+_name: Optional[str]
+

Name of the design

+
+ +
+
+_libraries: Dict[str, Library]
+

List of all libraries defined for a design.

+
+ +
+
+_documents: List[Document]
+

List of all documents loaded for a design.

+
+ +
+
+_compileOrderGraph: Graph[None, None, None, None, None, None, None, None, None, Document, None, None, None, None, None, None, None, None, None, None, None, None, None]
+

A graph derived from dependency graph containing the order of documents for compilation.

+
+ +
+
+_dependencyGraph: Graph[None, None, None, None, None, None, None, None, str, DesignUnit, None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The graph of all dependencies in the designs.

+
+ +
+
+_hierarchyGraph: Graph[None, None, None, None, None, None, None, None, str, DesignUnit, None, None, None, None, None, None, None, None, None, None, None, None, None]
+

A graph derived from dependency graph containing the design hierarchy.

+
+ +
+
+_objectGraph: Graph[None, None, None, None, None, None, None, None, str, Obj, None, None, None, None, None, None, None, None, None, None, None, None, None]
+

The graph of all types and objects in the design.

+
+ +
+
+_toplevel: Union[Entity, Configuration]
+

When computed, the toplevel design unit is cached in this field.

+
+ +
+
+property Libraries: Dict[str, Library]
+

Read-only property to access the dictionary of library names and VHDL libraries (_libraries).

+
+
Returns:
+

A dictionary of library names and VHDL libraries.

+
+
+
+ +
+
+property Documents: List[Document]
+

Read-only property to access the list of all documents (VHDL source files) loaded for this design (_documents).

+
+
Returns:
+

A list of all documents.

+
+
+
+ +
+
+property CompileOrderGraph: Graph
+

Read-only property to access the compile-order graph (_compileOrderGraph).

+
+
Returns:
+

Reference to the compile-order graph.

+
+
+
+ +
+
+property DependencyGraph: Graph
+

Read-only property to access the dependency graph (_dependencyGraph).

+
+
Returns:
+

Reference to the dependency graph.

+
+
+
+ +
+
+property HierarchyGraph: Graph
+

Read-only property to access the hierarchy graph (_hierarchyGraph).

+
+
Returns:
+

Reference to the hierarchy graph.

+
+
+
+ +
+
+property ObjectGraph: Graph
+

Read-only property to access the object graph (_objectGraph).

+
+
Returns:
+

Reference to the object graph.

+
+
+
+ +
+
+property TopLevel: Entity | Configuration
+

Read-only property to access the design’s top-level (_toplevel).

+

When called the first time, the hierarchy graph is checked for its root elements. When there is only one root element in the graph, a new field toplevel +is added to _hierarchyGraph referencing that single element. In addition, the result is cached in _toplevel.

+
+
Returns:
+

Reference to the design’s top-level.

+
+
Raises:
+
+
+
+
+ +
+
+LoadStdLibrary()[source]
+

Load the predefined VHDL library std into the design.

+

This will create a virtual source code file std.vhdl and register VHDL design units of library std to that file.

+
+
Return type:
+

Library

+
+
Returns:
+

The library object of library std.

+
+
+
+ +
+
+LoadIEEELibrary()[source]
+

Load the predefined VHDL library ieee into the design.

+

This will create a virtual source code file ieee.vhdl and register VHDL design units of library ieee to that file.

+
+
Return type:
+

Library

+
+
Returns:
+

The library object of library ieee.

+
+
+
+ +
+
+AddLibrary(library)[source]
+

Add a VHDL library to the design.

+

Ensure the libraries name doesn’t collide with existing libraries in the design.
+If ok, set the libraries parent reference to the design.

+
+
Parameters:
+

library (Library) – Library object to loaded.

+
+
Raises:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+GetLibrary(libraryName)[source]
+

Return an (existing) VHDL library object of name libraryName.

+

If the requested VHDL library doesn’t exist, a new VHDL library with that name will be created.

+
+
Parameters:
+

libraryName (str) – Name of the requested VHDL library.

+
+
Return type:
+

Library

+
+
Returns:
+

The VHDL library object.

+
+
+
+ +
+
+AddDocument(document, library)[source]
+

Add a document (VHDL source file) to the design and register all embedded design units to the given VHDL library.

+

Algorithm

+
    +

  1. Iterate all entities in the document

    +
      +

    1. Check if entity name might exist in target library.

      2. +

    2. Add entity to library and update library membership.

      3. +
    +
    2. +

  2. Iterate all architectures in the document

    +
      +

    1. Check if architecture name might exist in target library.

      2. +

    2. Add architecture to library and update library membership.

      3. +
    +
    3. +

  3. Iterate all packages in the document

    +
      +

    1. Check if package name might exist in target library.

      2. +

    2. Add package to library and update library membership.

      3. +
    +
    4. +

  4. Iterate all package bodies in the document

    +
      +

    1. Check if package body name might exist in target library.

      2. +

    2. Add package body to library and update library membership.

      3. +
    +
    5. +

  5. Iterate all configurations in the document

    +
      +

    1. Check if configuration name might exist in target library.

      2. +

    2. Add configuration to library and update library membership.

      3. +
    +
    6. +

  6. Iterate all contexts in the document

    +
      +

    1. Check if context name might exist in target library.

      2. +

    2. Add context to library and update library membership.

      3. +
    +
    7. +
+
+
Parameters:
+
    +

  • document (Document) – The VHDL source code file.

    • +

  • library (Library) – The VHDL library used to register the embedded design units to.

    • +
+
+
Raises:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+IterateDesignUnits(filter=<DesignUnitKind.All: 63>)[source]
+

Iterate all design units in the design.

+

A union of DesignUnitKind values can be given to filter the returned result for suitable design units.

+

Algorithm

+
    +

  1. Iterate all VHDL libraries.

    +
      +

    1. Iterate all contexts in that library.

      2. +

    2. Iterate all packages in that library.

      3. +

    3. Iterate all package bodies in that library.

      4. +

    4. Iterate all entites in that library.

      5. +

    5. Iterate all architectures in that library.

      6. +

    6. Iterate all configurations in that library.

      7. +
    +
    2. +
+
+
Parameters:
+

filter (DesignUnitKind) – An enumeration with possibly multiple flags to filter the returned design units.

+
+
Return type:
+

Generator[DesignUnit, None, None]

+
+
Returns:
+

A generator to iterate all matched design units in the design.

+
+
+
+

See also

+
+
pyVHDLModel.Library.IterateDesignUnits()

Iterate all design units in the library.

+
+
pyVHDLModel.Document.IterateDesignUnits()

Iterate all design units in the document.

+
+
+
+
+ +
+
+Analyze()[source]
+

Analyze the whole design.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Analyze dependencies of design units.
    +This will also yield the design hierarchy and the compiler order.

    2. +

  2. Analyze dependencies of types and objects.

    3. +
+
+

See also

+
+
AnalyzeDependencies()

Analyze the dependencies of design units.

+
+
AnalyzeObjects()

Analyze the dependencies of types and objects.

+
+
+
+
+ +
+
+AnalyzeDependencies()[source]
+

Analyze the dependencies of design units.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Create all vertices of the dependency graph by iterating all design units in all libraries.
    +→ CreateDependencyGraph()

    2. +

  2. Create the compile order graph.
    +→ CreateCompileOrderGraph()

    3. +

  3. Index all packages.
    +→ IndexPackages()

    4. +

  4. Index all architectures.
    +→ IndexArchitectures()

    5. +

  5. Link all contexts
    +→ LinkContexts()

    6. +

  6. Link all architectures.
    +→ LinkArchitectures()

    7. +

  7. Link all package bodies.
    +→ LinkPackageBodies()

    8. +

  8. Link all library references.
    +→ LinkLibraryReferences()

    9. +

  9. Link all package references.
    +→ LinkPackageReferences()

    10. +

  10. Link all context references.
    +→ LinkContextReferences()

    11. +

  11. Link all components.
    +→ LinkComponents()

    12. +

  12. Link all instantiations.
    +→ LinkInstantiations()

    13. +

  13. Create the hierarchy graph.
    +→ CreateHierarchyGraph()

    14. +

  14. Compute the compile order.
    +→ ComputeCompileOrder()

    15. +
+
+ +
+
+AnalyzeObjects()[source]
+

Analyze the dependencies of types and objects.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Index all entities.
    +→ IndexEntities()

    2. +

  2. Index all package bodies.
    +→ IndexPackageBodies()

    3. +

  3. Import objects.
    +→ ImportObjects()

    4. +

  4. Create the type and object graph.
    +→ CreateTypeAndObjectGraph()

    5. +
+
+ +
+
+CreateDependencyGraph()[source]
+

Create all vertices of the dependency graph by iterating all design units in all libraries.

+

This method will purely create a sea of vertices without any linking between vertices. The edges will be created later by other methods.
+See AnalyzeDependencies() for these methods and their algorithmic order.

+

Each vertex has the following properties: +:rtype: None

+
    +

  • The vertex’ ID is the design unit’s identifier.

    • +

  • The vertex’ value references the design unit.

    • +

  • A key-value-pair called kind denotes the vertex’s kind as an enumeration value of type DependencyGraphVertexKind.

    • +

  • A key-value-pair called predefined denotes if the referenced design unit is a predefined language entity.

    • +
+

Algorithm

+
    +

  1. Iterate all libraries in the design.

    +
      +

    • Create a vertex for that library and reference the library by the vertex’ value field.
      +In return, set the library’s _dependencyVertex field to reference the created vertex.

      • +
    +
      +

    1. Iterate all contexts in that library.

      +
        +

      • Create a vertex for that context and reference the context by the vertex’ value field.
        +In return, set the context’s _dependencyVertex field to reference the created vertex.

        • +
      +
      2. +

    2. Iterate all packages in that library.

      +
        +

      • Create a vertex for that package and reference the package by the vertex’ value field.
        +In return, set the package’s _dependencyVertex field to reference the created vertex.

        • +
      +
      3. +

    3. Iterate all package bodies in that library.

      +
        +

      • Create a vertex for that package body and reference the package body by the vertex’ value field.
        +In return, set the package body’s _dependencyVertex field to reference the created vertex.

        • +
      +
      4. +

    4. Iterate all entities in that library.

      +
        +

      • Create a vertex for that entity and reference the entity by the vertex’ value field.
        +In return, set the entity’s _dependencyVertex field to reference the created vertex.

        • +
      +
      5. +

    5. Iterate all architectures in that library.

      +
        +

      • Create a vertex for that architecture and reference the architecture by the vertex’ value field.
        +In return, set the architecture’s _dependencyVertex field to reference the created vertex.

        • +
      +
      6. +

    6. Iterate all configurations in that library.

      +
        +

      • Create a vertex for that configuration and reference the configuration by the vertex’ value field.
        +In return, set the configuration’s _dependencyVertex field to reference the created vertex.

        • +
      +
      7. +
    +
    2. +
+
+
Return type:
+

None

+
+
+
+ +
+
+CreateCompileOrderGraph()[source]
+

Create a compile-order graph with bidirectional references to the dependency graph.

+

Add vertices representing a document (VHDL source file) to the dependency graph. Each “document” vertex in dependency graph is copied into the compile-order +graph and bidirectionally referenced.

+

In addition, each vertex of a corresponding design unit in a document is linked to the vertex representing that document to express the design unit in +document relationship.

+

Each added vertex has the following properties: +:rtype: None

+
    +

  • The vertex’ ID is the document’s filename.

    • +

  • The vertex’ value references the document.

    • +

  • A key-value-pair called kind denotes the vertex’s kind as an enumeration value of type DependencyGraphVertexKind.

    • +

  • A key-value-pair called predefined does not exist.

    • +
+

Algorithm

+
    +

  1. Iterate all documents in the design.

    +
      +

    • Create a vertex for that document and reference the document by the vertex’ value field.
      +In return, set the documents’s _dependencyVertex field to reference the created vertex.

      • +

    • Copy the vertex from dependency graph to compile-order graph and link both vertices bidirectionally.
      +In addition, set the documents’s _dependencyVertex field to reference the copied vertex.

      +
        +

      • Add a key-value-pair called compileOrderVertex to the dependency graph’s vertex.

        • +

      • Add a key-value-pair called dependencyVertex to the compiler-order graph’s vertex.

        • +
      +
      • +
    +
      +

    1. Iterate the documents design units and create an edge from the design unit’s corresponding dependency vertex to the documents corresponding +dependency vertex. This expresses a “design unit is located in document” relation.

      +
        +

      • Add a key-value-pair called kind` denoting the edge’s kind as an enumeration value of type DependencyGraphEdgeKind.

        • +
      +
      2. +
    +
    2. +
+
+
Return type:
+

None

+
+
+
+ +
+
+LinkContexts()[source]
+

Resolves and links all items (library clauses, use clauses and nested context references) in contexts.

+

It iterates all contexts in the design. Therefore, the library of the context is used as the working library. By +default, the working library is implicitly referenced in _referencedLibraries. In addition, a new empty +dictionary is created in _referencedPackages and _referencedContexts for that working library.

+

At first, all library clauses are resolved (a library clause my have multiple library reference symbols). For each +referenced library an entry in _referencedLibraries is generated and new empty dictionaries in +_referencedPackages and _referencedContexts for that working library. In addition, a vertex in the +dependency graph is added for that relationship.

+

At second, all use clauses are resolved (a use clause my have multiple package member reference symbols). For each +referenced package,

+
+
Return type:
+

None

+
+
+
+ +
+
+LinkArchitectures()[source]
+

Link all architectures to corresponding entities in all libraries.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all libraries:

    +
      +

    1. Iterate all architecture groups (grouped per entity symbol’s name). +→ pyVHDLModel.Library.LinkArchitectures()

      +
        +

      • Check if entity symbol’s name exists as an entity in this library.

        • +
      +
        +

      1. For each architecture in the same architecture group:

        +
          +

        • Add architecture to entities architecture dictionary pyVHDLModel.DesignUnit.Entity._architectures.

          • +

        • Assign found entity to architecture’s entity symbol pyVHDLModel.DesignUnit.Architecture._entity

          • +

        • Set parent namespace of architecture’s namespace to the entitie’s namespace.

          • +

        • Add an edge in the dependency graph from the architecture’s corresponding dependency vertex to the entity’s corresponding dependency vertex.

          • +
        +
        2. +
      +
      2. +
    +
    2. +
+
+

See also

+
+
LinkPackageBodies()

Link all package bodies to corresponding packages in all libraries.

+
+
+
+
+ +
+
+LinkPackageBodies()[source]
+

Link all package bodies to corresponding packages in all libraries.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all libraries:

    +
      +

    1. Iterate all package bodies. +→ pyVHDLModel.Library.LinkPackageBodies()

      +
        +

      • Check if package body symbol’s name exists as a package in this library.

        • +

      • Add package body to package pyVHDLModel.DesignUnit.Package._packageBody.

        • +

      • Assign found package to package body’s package symbol pyVHDLModel.DesignUnit.PackageBody._package

        • +

      • Set parent namespace of package body’s namespace to the package’s namespace.

        • +

      • Add an edge in the dependency graph from the package body’s corresponding dependency vertex to the package’s corresponding dependency vertex.

        • +
      +
      2. +
    +
    2. +
+
+

See also

+
+
LinkArchitectures()

Link all architectures to corresponding entities in all libraries.

+
+
+
+
+ +
+
+IndexPackages()[source]
+

Index all declared items in all packages in all libraries.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all libraries:

    +
      +

    1. Iterate all packages
      +→ pyVHDLModel.Library.IndexPackages()

      + +
      2. +
    +
    2. +
+
+

See also

+
+
IndexPackageBodies()

Index all declared items in all package bodies in all libraries.

+
+
IndexEntities()

Index all declared items in all entities in all libraries.

+
+
IndexArchitectures()

Index all declared items in all architectures in all libraries.

+
+
+
+
+ +
+
+IndexPackageBodies()[source]
+

Index all declared items in all packages in all libraries.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all libraries:

    +
      +

    1. Iterate all packages
      +→ pyVHDLModel.Library.IndexPackageBodies()

      + +
      2. +
    +
    2. +
+
+

See also

+
+
IndexPackages()

Index all declared items in all packages in all libraries.

+
+
IndexEntities()

Index all declared items in all entities in all libraries.

+
+
IndexArchitectures()

Index all declared items in all architectures in all libraries.

+
+
+
+
+ +
+
+IndexEntities()[source]
+

Index all declared items in all packages in all libraries.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all libraries:

    +
      +

    1. Iterate all packages
      +→ pyVHDLModel.Library.IndexEntities()

      + +
      2. +
    +
    2. +
+
+

See also

+
+
IndexPackages()

Index all declared items in all packages in all libraries.

+
+
IndexPackageBodies()

Index all declared items in all package bodies in all libraries.

+
+
IndexArchitectures()

Index all declared items in all architectures in all libraries.

+
+
+
+
+ +
+
+IndexArchitectures()[source]
+

Index all declared items in all packages in all libraries.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all libraries:

    +
      +

    1. Iterate all packages
      +→ pyVHDLModel.Library.IndexArchitectures()

      + +
      2. +
    +
    2. +
+
+

See also

+
+
IndexPackages()

Index all declared items in all packages in all libraries.

+
+
IndexPackageBodies()

Index all declared items in all package bodies in all libraries.

+
+
IndexEntities()

Index all declared items in all entities in all libraries.

+
+
+
+
+ +
+
+CreateHierarchyGraph()[source]
+

Create the hierarchy graph from dependency graph.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all vertices corresponding to entities and architectures in the dependency graph:

    +
      +

    • Copy these vertices to the hierarchy graph and create a bidirectional linking.
      +In addition, set the referenced design unit’s _hierarchyVertex field to reference the copied vertex.

      +
        +

      • Add a key-value-pair called hierarchyVertex to the dependency graph’s vertex.

        • +

      • Add a key-value-pair called dependencyVertex to the hierarchy graph’s vertex.

        • +
      +
      • +
    +
    2. +

  2. Iterate all architectures …

    +
    +

    Todo

    +

    Design::CreateHierarchyGraph describe algorithm

    +
    +
      +

    1. Iterate all outbound edges

      +
      +

      Todo

      +

      Design::CreateHierarchyGraph describe algorithm

      +
      +
      2. +
    +
    3. +
+
+ +
+
+IterateDocumentsInCompileOrder()[source]
+

Iterate all document in compile-order.

+

Algorithm

+
    +

  • Check if compile-order graph was populated with vertices and its vertices are linked by edges.

    • +
+
    +

  1. Iterate compile-order graph in topological order.
    +pyTooling.Graph.Graph.IterateTopologically()

    +
      +

    • yield the compiler-order vertex’ referenced document.

      • +
    +
    2. +
+
+
Return type:
+

Generator[Document, None, None]

+
+
Returns:
+

A generator to iterate all documents in compile-order in the design.

+
+
Raises:
+

VHDLModelException – If compile-order was not computed.

+
+
+
+

See also

+
+

Todo

+

missing text

+

pyVHDLModel.Design.ComputeCompileOrder()

+
+
+
+ +
+
+__repr__()[source]
+

Formats a representation of the design.

+

Format: Document: 'my_design'

+
+
Return type:
+

str

+
+
Returns:
+

String representation of the design.

+
+
+
+ +
+
+__str__()
+

Formats a representation of the design.

+

Format: Document: 'my_design'

+
+
Return type:
+

str

+
+
Returns:
+

String representation of the design.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Library(identifier, parent=None)[source]
+

A Library represents a VHDL library. It contains all primary and secondary design units.

+

Inheritance

+
+

Inheritance diagram of Library

+
+
Parameters:
+
+
+
+
+
+__init__(identifier, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
    +

  • parent (ModelEntity) – The parent model entity of this entity.

    • +

  • identifier (str)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+_contexts: Dict[str, Context]
+

Dictionary of all contexts defined in a library.

+
+ +
+
+_configurations: Dict[str, Configuration]
+

Dictionary of all configurations defined in a library.

+
+ +
+
+_entities: Dict[str, Entity]
+

Dictionary of all entities defined in a library.

+
+ +
+
+_architectures: Dict[str, Dict[str, Architecture]]
+

Dictionary of all architectures defined in a library.

+
+ +
+
+_packages: Dict[str, Package]
+

Dictionary of all packages defined in a library.

+
+ +
+
+_packageBodies: Dict[str, PackageBody]
+

Dictionary of all package bodies defined in a library.

+
+ +
+
+_dependencyVertex: Vertex[None, None, str, Union[Library, DesignUnit], None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the library.
This reference is set by CreateDependencyGraph().

+
+ +
+
+property Contexts: Dict[str, Context]
+

Returns a list of all context declarations declared in this library.

+
+ +
+
+property Configurations: Dict[str, Configuration]
+

Returns a list of all configuration declarations declared in this library.

+
+ +
+
+property Entities: Dict[str, Entity]
+

Returns a list of all entity declarations declared in this library.

+
+ +
+
+property Architectures: Dict[str, Dict[str, Architecture]]
+

Returns a list of all architectures declarations declared in this library.

+
+ +
+
+property Packages: Dict[str, Package]
+

Returns a list of all package declarations declared in this library.

+
+ +
+
+property PackageBodies: Dict[str, PackageBody]
+

Returns a list of all package body declarations declared in this library.

+
+ +
+
+property DependencyVertex: Vertex
+

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

+

The dependency vertex references this library by its value field.

+
+
Returns:
+

The corresponding dependency vertex.

+
+
+
+ +
+
+IterateDesignUnits(filter=<DesignUnitKind.All: 63>)[source]
+

Iterate all design units in the library.

+

A union of DesignUnitKind values can be given to filter the returned result for suitable design units.

+

Algorithm

+
    +

  1. Iterate all contexts in that library.

    2. +

  2. Iterate all packages in that library.

    3. +

  3. Iterate all package bodies in that library.

    4. +

  4. Iterate all entites in that library.

    5. +

  5. Iterate all architectures in that library.

    6. +

  6. Iterate all configurations in that library.

    7. +
+
+
Parameters:
+

filter (DesignUnitKind) – An enumeration with possibly multiple flags to filter the returned design units.

+
+
Return type:
+

Generator[DesignUnit, None, None]

+
+
Returns:
+

A generator to iterate all matched design units in the library.

+
+
+
+

See also

+
+
pyVHDLModel.Design.IterateDesignUnits()

Iterate all design units in the design.

+
+
pyVHDLModel.Document.IterateDesignUnits()

Iterate all design units in the document.

+
+
+
+
+ +
+
+LinkArchitectures()[source]
+

Link all architectures to corresponding entities.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all architecture groups (grouped per entity symbol’s name).

    +
      +

    • Check if entity symbol’s name exists as an entity in this library.

      • +
    +
      +

    1. For each architecture in the same architecture group:

      +
        +

      • Add architecture to entities architecture dictionary pyVHDLModel.DesignUnit.Entity._architectures.

        • +

      • Assign found entity to architecture’s entity symbol pyVHDLModel.DesignUnit.Architecture._entity

        • +

      • Set parent namespace of architecture’s namespace to the entitie’s namespace.

        • +

      • Add an edge in the dependency graph from the architecture’s corresponding dependency vertex to the entity’s corresponding dependency vertex.

        • +
      +
      2. +
    +
    2. +
+
+
Raises:
+
+
+
Return type:
+

None

+
+
+
+

See also

+
+
LinkPackageBodies()

Link all package bodies to corresponding packages.

+
+
+
+
+ +
+
+LinkPackageBodies()[source]
+

Link all package bodies to corresponding packages.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all package bodies.

    +
      +

    • Check if package body symbol’s name exists as a package in this library.

      • +

    • Add package body to package pyVHDLModel.DesignUnit.Package._packageBody.

      • +

    • Assign found package to package body’s package symbol pyVHDLModel.DesignUnit.PackageBody._package

      • +

    • Set parent namespace of package body’s namespace to the package’s namespace.

      • +

    • Add an edge in the dependency graph from the package body’s corresponding dependency vertex to the package’s corresponding dependency vertex.

      • +
    +
    2. +
+
+
Raises:
+

VHDLModelException – If package name doesn’t exist.

+
+
Return type:
+

None

+
+
+
+

See also

+
+
LinkArchitectures()

Link all architectures to corresponding entities.

+
+
+
+
+ +
+
+IndexPackages()[source]
+

Index declared items in all packages.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all packages:

    + +
    2. +
+
+

See also

+
+
IndexPackageBodies()

Index all declared items in a package body.

+
+
IndexEntities()

Index all declared items in an entity.

+
+
IndexArchitectures()

Index all declared items in an architecture.

+
+
+
+
+ +
+
+IndexPackageBodies()[source]
+

Index declared items in all package bodies.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all package bodies:

    + +
    2. +
+
+

See also

+
+
IndexPackages()

Index all declared items in a package.

+
+
IndexEntities()

Index all declared items in an entity.

+
+
IndexArchitectures()

Index all declared items in an architecture.

+
+
+
+
+ +
+
+IndexEntities()[source]
+

Index declared items in all entities.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all entities:

    + +
    2. +
+
+

See also

+
+
IndexPackages()

Index all declared items in a package.

+
+
IndexPackageBodies()

Index all declared items in a package body.

+
+
IndexArchitectures()

Index all declared items in an architecture.

+
+
+
+
+ +
+
+IndexArchitectures()[source]
+

Index declared items in all architectures.

+
+
Return type:
+

None

+
+
+

Algorithm

+
    +

  1. Iterate all architectures:

    + +
    2. +
+
+

See also

+
+
IndexPackages()

Index all declared items in a package.

+
+
IndexPackageBodies()

Index all declared items in a package body.

+
+
IndexEntities()

Index all declared items in an entity.

+
+
+
+
+ +
+
+__repr__()[source]
+

Formats a representation of the library.

+

Format: Library: 'my_library'

+
+
Return type:
+

str

+
+
Returns:
+

String representation of the library.

+
+
+
+ +
+
+__str__()
+

Formats a representation of the library.

+

Format: Library: 'my_library'

+
+
Return type:
+

str

+
+
Returns:
+

String representation of the library.

+
+
+
+ +
+
+_identifier: str
+

The identifier of a model entity.

+
+ +
+
+_normalizedIdentifier: str
+

The normalized (lower case) identifier of a model entity.

+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Identifier: str
+

Returns a model entity’s identifier (name).

+
+
Returns:
+

Name of a model entity.

+
+
+
+ +
+
+property NormalizedIdentifier: str
+

Returns a model entity’s normalized identifier (lower case name).

+
+
Returns:
+

Normalized name of a model entity.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+ +
+
+class pyVHDLModel.Document(path, documentation=None, parent=None)[source]
+

A Document represents a sourcefile. It contains primary and secondary design units.

+

Inheritance

+
+

Inheritance diagram of Document

+
+
Parameters:
+
+
+
+
+
+__init__(path, documentation=None, parent=None)[source]
+

Initializes a VHDL model entity.

+
+
Parameters:
+
    +

  • parent (ModelEntity) – The parent model entity of this entity.

    • +

  • path (Path)

    • +

  • documentation (str | None)

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+_path: Path
+

path to the document. None if virtual document.

+
+ +
+
+_designUnits: List[DesignUnit]
+

List of all design units defined in a document.

+
+ +
+
+_contexts: Dict[str, Context]
+

Dictionary of all contexts defined in a document.

+
+ +
+
+_configurations: Dict[str, Configuration]
+

Dictionary of all configurations defined in a document.

+
+ +
+
+_entities: Dict[str, Entity]
+

Dictionary of all entities defined in a document.

+
+ +
+
+_architectures: Dict[str, Dict[str, Architecture]]
+

Dictionary of all architectures defined in a document.

+
+ +
+
+_packages: Dict[str, Package]
+

Dictionary of all packages defined in a document.

+
+ +
+
+_packageBodies: Dict[str, PackageBody]
+

Dictionary of all package bodies defined in a document.

+
+ +
+
+_verificationUnits: Dict[str, VerificationUnit]
+

Dictionary of all PSL verification units defined in a document.

+
+ +
+
+_verificationProperties: Dict[str, VerificationProperty]
+

Dictionary of all PSL verification properties defined in a document.

+
+ +
+
+_verificationModes: Dict[str, VerificationMode]
+

Dictionary of all PSL verification modes defined in a document.

+
+ +
+
+_documentation: Optional[str]
+

The associated documentation of a model entity.

+
+ +
+
+property Documentation: str | None
+

Returns a model entity’s associated documentation.

+
+
Returns:
+

Associated documentation of a model entity.

+
+
+
+ +
+
+class property HasClassAttributes: bool
+

Read-only property to check if the class has Attributes (__pyattr__).

+
+
Returns:
+

True, if the class has Attributes.

+
+
+
+ +
+
+class property HasMethodAttributes: bool
+

Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).

+
+
Returns:
+

True, if the class has any method with Attributes.

+
+
+
+ +
+
+property Parent: ModelEntity
+

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

+
+
Returns:
+

Reference to the parent entity.

+
+
+
+ +
+
+_parent: ModelEntity
+

Reference to a parent entity in the logical model hierarchy.

+
+ +
+
+_dependencyVertex: Vertex[None, None, None, Document, None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the dependency graph representing the document.
This reference is set by CreateCompileOrderGraph().

+
+ +
+
+_compileOrderVertex: Vertex[None, None, None, Document, None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Reference to the vertex in the compile-order graph representing the document.
This reference is set by CreateCompileOrderGraph().

+
+ +
+
+_AddEntity(item)[source]
+

Add an entity to the document’s lists of design units.

+
+
Parameters:
+

item (Entity) – Entity object to be added to the document.

+
+
Raises:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+_AddArchitecture(item)[source]
+

Add an architecture to the document’s lists of design units.

+
+
Parameters:
+

item (Architecture) – Architecture object to be added to the document.

+
+
Raises:
+
    +

  • TypeError – If parameter ‘item’ is not of type Architecture.

    • +

  • VHDLModelException – If architecture name already exists for the referenced entity name in document.

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+_AddPackage(item)[source]
+

Add a package to the document’s lists of design units.

+
+
Parameters:
+

item (Package) – Package object to be added to the document.

+
+
Raises:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+_AddPackageBody(item)[source]
+

Add a package body to the document’s lists of design units.

+
+
Parameters:
+

item (PackageBody) – Package body object to be added to the document.

+
+
Raises:
+
    +

  • TypeError – If parameter ‘item’ is not of type PackageBody.

    • +

  • VHDLModelException – If package body name already exists in document.

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+_AddContext(item)[source]
+

Add a context to the document’s lists of design units.

+
+
Parameters:
+

item (Context) – Context object to be added to the document.

+
+
Raises:
+
+
+
Return type:
+

None

+
+
+
+ +
+
+_AddConfiguration(item)[source]
+

Add a configuration to the document’s lists of design units.

+
+
Parameters:
+

item (Configuration) – Configuration object to be added to the document.

+
+
Raises:
+
    +

  • TypeError – If parameter ‘item’ is not of type Configuration.

    • +

  • VHDLModelException – If configuration name already exists in document.

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+_AddDesignUnit(item)[source]
+

Add a design unit to the document’s lists of design units.

+
+
Parameters:
+

item (DesignUnit) – Configuration object to be added to the document.

+
+
Raises:
+
    +

  • TypeError – If parameter ‘item’ is not of type DesignUnit.

    • +

  • ValueError – If parameter ‘item’ is an unknown DesignUnit.

    • +

  • VHDLModelException – If configuration name already exists in document.

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+property Path: Path
+

Read-only property to access the document’s path (_path).

+
+
Returns:
+

The path of this document.

+
+
+
+ +
+
+property DesignUnits: List[DesignUnit]
+

Read-only property to access a list of all design units declarations found in this document (_designUnits).

+
+
Returns:
+

List of all design units.

+
+
+
+ +
+
+property Contexts: Dict[str, Context]
+

Read-only property to access a list of all context declarations found in this document (_contexts).

+
+
Returns:
+

List of all contexts.

+
+
+
+ +
+
+property Configurations: Dict[str, Configuration]
+

Read-only property to access a list of all configuration declarations found in this document (_configurations).

+
+
Returns:
+

List of all configurations.

+
+
+
+ +
+
+property Entities: Dict[str, Entity]
+

Read-only property to access a list of all entity declarations found in this document (_entities).

+
+
Returns:
+

List of all entities.

+
+
+
+ +
+
+property Architectures: Dict[str, Dict[str, Architecture]]
+

Read-only property to access a list of all architecture declarations found in this document (_architectures).

+
+
Returns:
+

List of all architectures.

+
+
+
+ +
+
+property Packages: Dict[str, Package]
+

Read-only property to access a list of all package declarations found in this document (_packages).

+
+
Returns:
+

List of all packages.

+
+
+
+ +
+
+property PackageBodies: Dict[str, PackageBody]
+

Read-only property to access a list of all package body declarations found in this document (_packageBodies).

+
+
Returns:
+

List of all package bodies.

+
+
+
+ +
+
+property VerificationUnits: Dict[str, VerificationUnit]
+

Read-only property to access a list of all verification unit declarations found in this document (_verificationUnits).

+
+
Returns:
+

List of all verification units.

+
+
+
+ +
+
+property VerificationProperties: Dict[str, VerificationProperty]
+

Read-only property to access a list of all verification properties declarations found in this document (_verificationProperties).

+
+
Returns:
+

List of all verification properties.

+
+
+
+ +
+
+property VerificationModes: Dict[str, VerificationMode]
+

Read-only property to access a list of all verification modes declarations found in this document (_verificationModes).

+
+
Returns:
+

List of all verification modes.

+
+
+
+ +
+
+property CompileOrderVertex: Vertex[None, None, None, Document, None, None, None, None, None, None, None, None, None, None, None, None, None]
+

Read-only property to access the corresponding compile-order vertex (_compileOrderVertex).

+

The compile-order vertex references this document by its value field.

+
+
Returns:
+

The corresponding compile-order vertex.

+
+
+
+ +
+
+IterateDesignUnits(filter=<DesignUnitKind.All: 63>)[source]
+

Iterate all design units in the document.

+

A union of DesignUnitKind values can be given to filter the returned result for suitable design units.

+

Algorithm

+
    +

  • If contexts are selected in the filter:

    +
      +

    1. Iterate all contexts in that library.

      2. +
    +
    • +

  • If packages are selected in the filter:

    +
      +

    1. Iterate all packages in that library.

      2. +
    +
    • +

  • If package bodies are selected in the filter:

    +
      +

    1. Iterate all package bodies in that library.

      2. +
    +
    • +

  • If entites are selected in the filter:

    +
      +

    1. Iterate all entites in that library.

      2. +
    +
    • +

  • If architectures are selected in the filter:

    +
      +

    1. Iterate all architectures in that library.

      2. +
    +
    • +

  • If configurations are selected in the filter:

    +
      +

    1. Iterate all configurations in that library.

      2. +
    +
    • +
+
+
Parameters:
+

filter (DesignUnitKind) – An enumeration with possibly multiple flags to filter the returned design units.

+
+
Return type:
+

Generator[DesignUnit, None, None]

+
+
Returns:
+

A generator to iterate all matched design units in the document.

+
+
+
+

See also

+
+
pyVHDLModel.Design.IterateDesignUnits()

Iterate all design units in the design.

+
+
pyVHDLModel.Library.IterateDesignUnits()

Iterate all design units in the library.

+
+
+
+
+ +
+
+__repr__()[source]
+

Formats a representation of the document.

+

Format: Document: 'path/to/file.vhdl'

+
+
Return type:
+

str

+
+
Returns:
+

String representation of the document.

+
+
+
+ +
+
+__str__()
+

Formats a representation of the document.

+

Format: Document: 'path/to/file.vhdl'

+
+
Return type:
+

str

+
+
Returns:
+

String representation of the document.

+
+
+
+ +
+ +
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/search.html b/search.html new file mode 100644 index 000000000..66e3009a4 --- /dev/null +++ b/search.html @@ -0,0 +1,168 @@ + + + + + + Search — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+
    +
    • +
  • Search
    • +
  • +
    • +
+
+
+
+
+ + + + +
+ +
+ +
+
+
+ +
+ +
+

© Copyright 2016-2024, Patrick Lehmann. + Last updated on 27.09.2024. +

+
+ + Built with Sphinx using a + theme + provided by Read the Docs. + + +
+
+
+
+
+ + + + + + + + + \ No newline at end of file diff --git a/searchindex.js b/searchindex.js new file mode 100644 index 000000000..c070ba883 --- /dev/null +++ b/searchindex.js @@ -0,0 +1 @@ +Search.setIndex({"alltitles": {"1. Create Dependency Graph": [[0, "create-dependency-graph"]], "1. Definitions.": [[24, "definitions"]], "10. Link Context References": [[0, "link-context-references"]], "11. Link Components": [[0, "link-components"]], "12. Link Instantiations": [[0, "link-instantiations"]], "13. Create Hierarchy Graph": [[0, "create-hierarchy-graph"]], "14. Compute Compile Order": [[0, "compute-compile-order"]], "2. Create Compile Order Graph": [[0, "create-compile-order-graph"]], "2. Grant of Copyright License.": [[24, "grant-of-copyright-license"]], "26.12.2020": [[1, "id1"]], "3. Grant of Patent License.": [[24, "grant-of-patent-license"]], "3. Index Packages": [[0, "index-packages"]], "4. Index Architectures": [[0, "index-architectures"]], "4. Redistribution.": [[24, "redistribution"]], "5. Link Contexts": [[0, "link-contexts"]], "5. Submission of Contributions.": [[24, "submission-of-contributions"]], "6. Link Architectures": [[0, "link-architectures"]], "6. Trademarks.": [[24, "trademarks"]], "7. Disclaimer of Warranty.": [[24, "disclaimer-of-warranty"]], "7. Link Package Bodies": [[0, "link-package-bodies"]], "8. Limitation of Liability.": [[24, "limitation-of-liability"]], "8. Link Library References": [[0, "link-library-references"]], "9. Accepting Warranty or Additional Liability.": [[24, "accepting-warranty-or-additional-liability"]], "9. Link Package References": [[0, "link-package-references"]], "Access": [[22, "access"]], "Adding Expressions": [[15, "adding-expressions"]], "Analyze": [[0, null]], "Apache License 2.0": [[24, null]], "Architeture": [[13, "architeture"]], "Array": [[22, "array"]], "Assert Statement": [[12, "assert-statement"], [19, "assert-statement"]], "Assignments": [[19, "assignments"]], "Bash": [[9, null], [9, null], [9, null], [9, null]], "Binary Expressions": [[15, "binary-expressions"]], "Branching": [[19, "branching"]], "Case Generate": [[12, "case-generate"]], "Case Statement": [[19, "case-statement"]], "ChangeLog": [[1, null]], "Code Coverage Report": [[26, null]], "Compile Order Graph": [[2, null], [5, "compile-order-graph"]], "Component Instantiation": [[12, "component-instantiation"]], "Composite Types": [[22, "composite-types"]], "Concepts not defined by VHDL": [[17, null]], "Concurrent Block Statement": [[12, "concurrent-block-statement"]], "Concurrent Statements": [[12, null]], "Configuration": [[13, "configuration"]], "Configuration Instantiation": [[12, "configuration-instantiation"]], "Constant": [[18, "constant"]], "Constant as Parameter": [[18, "constant-as-parameter"]], "Constants": [[18, "constants"]], "Context": [[13, "context"]], "Contributors": [[27, "contributors"]], "Copyright Information": [[28, null]], "Creative Commons Attribution 4.0 International": [[7, null]], "Data Structures": [[5, null]], "Dec. 2020 - Split from pyVHDLParser": [[27, "dec-2020-split-from-pyvhdlparser"]], "Dec. 2022 - Added Documentation Property": [[27, "dec-2022-added-documentation-property"]], "Deferred Constant": [[18, "deferred-constant"]], "Dependency": [[6, null]], "Dependency Analysis": [[0, "dependency-analysis"]], "Dependency Graph": [[3, null], [5, "dependency-graph"]], "Design": [[17, "design"]], "Design Units": [[13, null]], "Direction": [[14, "direction"]], "Document": [[17, "document"]], "Documentation Coverage": [[8, null]], "Endless Loop": [[19, "endless-loop"]], "Entity": [[13, "entity"]], "Entity Instantiation": [[12, "entity-instantiation"]], "Enumeration": [[22, "enumeration"]], "Enumeration Literal": [[15, "enumeration-literal"]], "Enumerations": [[14, null]], "Example": [[32, null], [32, null], [32, null], [32, null], [32, null], [32, null], [32, null], [32, null], [32, null], [32, null], [33, null], [33, null], [34, null], [34, null], [34, null], [34, null], [34, null], [34, null], [34, null], [34, null], [34, null], [34, null], [42, null], [42, null], [42, null], [42, null], [49, null], [49, null], [49, null], [49, null], [49, null], [49, null], [49, null], [49, null], [49, null], [49, null]], "Exit Statement": [[19, "exit-statement"]], "Expressions": [[15, "expressions"]], "File": [[18, "file"], [22, "file"]], "File as Parameter": [[18, "file-as-parameter"]], "Files": [[18, "files"]], "Floating Point Literal": [[15, "floating-point-literal"]], "For Generate": [[12, "for-generate"]], "For Loop": [[19, "for-loop"]], "Function": [[20, "function"]], "Function Instantiation": [[20, "function-instantiation"]], "Function as Method": [[20, "function-as-method"]], "Functions": [[20, "functions"]], "GHDL as Parser": [[9, "ghdl-as-parser"]], "Generate Statements": [[12, "generate-statements"]], "Generic Constant": [[18, "generic-constant"]], "Generic Function": [[20, "generic-function"]], "Generic Interface Items": [[16, "generic-interface-items"]], "Generic Procedure": [[20, "generic-procedure"]], "GenericConstantInterfaceItem": [[16, "genericconstantinterfaceitem"]], "GenericFunctionInterfaceItem": [[16, "genericfunctioninterfaceitem"]], "GenericPackageInterfaceItem": [[16, "genericpackageinterfaceitem"]], "GenericProcedureInterfaceItem": [[16, "genericprocedureinterfaceitem"]], "GenericTypeInterfaceItem": [[16, "generictypeinterfaceitem"]], "Getting Started": [[9, null]], "GettingStarted.py": [[9, null]], "Glossary": [[10, null]], "Graphs": [[5, "graphs"]], "Hierarchy Graph": [[4, null], [5, "hierarchy-graph"]], "If Generate": [[12, "if-generate"]], "If Statement": [[19, "if-statement"]], "Installation and Setup": [[9, "installation-and-setup"]], "Installation using setup.py": [[11, "installation-using-setup-py"]], "Installation/Updates": [[11, null]], "Installing a Wheel Package from PyPI using PIP": [[11, "installing-a-wheel-package-from-pypi-using-pip"]], "Instantiations": [[12, "instantiations"]], "Integer": [[22, "integer"]], "Integer Literal": [[15, "integer-literal"]], "Interface Items": [[16, null]], "Jan. 2021 - Documentation enhancements": [[27, "jan-2021-documentation-enhancements"]], "Jan. 2023 - Dependency, Hierarchy, Compile Order Analysis": [[27, "jan-2023-dependency-hierarchy-compile-order-analysis"]], "Jul. 2021 - First adoption and enhancements": [[27, "jul-2021-first-adoption-and-enhancements"]], "Jun. 2021 - Model and documentation enhancements": [[27, "jun-2021-model-and-documentation-enhancements"]], "Library": [[17, "library"]], "License": [[27, "license"]], "Literals": [[15, "literals"]], "Literals and Expressions": [[15, null]], "Local Packaging and Installation via PIP": [[11, "local-packaging-and-installation-via-pip"]], "Logical Expressions": [[15, "logical-expressions"]], "Loops": [[19, "loops"]], "Main Goals": [[27, "main-goals"]], "Mode": [[14, "mode"]], "Multiplying Expressions": [[15, "multiplying-expressions"]], "News": [[27, "news"]], "Next Statement": [[19, "next-statement"]], "Object Declarations": [[18, null]], "Object ObjectClass": [[14, "object-objectclass"]], "On Linux": [[9, "on-linux"]], "On Mac": [[9, "on-mac"]], "On Windows - MSYS2": [[9, "on-windows-msys2"]], "On Windows - Native": [[9, "on-windows-native"]], "On Windows from Sources": [[9, "on-windows-from-sources"]], "Package": [[13, "package"]], "Package Body": [[13, "package-body"]], "Packaging (Optional)": [[6, "packaging-optional"]], "Parameter Interface Item": [[16, "parameter-interface-item"]], "ParameterConstantInterfaceItem": [[16, "parameterconstantinterfaceitem"]], "ParameterFileInterfaceItem": [[16, "parameterfileinterfaceitem"]], "ParameterSignalInterfaceItem": [[16, "parametersignalinterfaceitem"]], "ParameterVariableInterfaceItem": [[16, "parametervariableinterfaceitem"]], "Physical": [[22, "physical"]], "Physical Literal": [[15, "physical-literal"]], "Port Interface Item": [[16, "port-interface-item"]], "PortSignalInterfaceItem": [[16, "portsignalinterfaceitem"]], "PowerShell": [[9, null], [9, null]], "Primary Units": [[13, "primary-units"]], "Procedure": [[20, "procedure"]], "Procedure Call": [[12, "procedure-call"], [19, "procedure-call"]], "Procedure Instantiation": [[20, "procedure-instantiation"]], "Procedure as Method": [[20, "procedure-as-method"]], "Procedures": [[20, "procedures"]], "Process": [[12, "process"]], "Protected": [[22, "protected"]], "Publishing (CI-Server only)": [[6, "publishing-ci-server-only"]], "Real": [[22, "real"]], "Record": [[22, "record"]], "Relational Expressions": [[15, "relational-expressions"]], "Report Statement": [[19, "report-statement"]], "Reporting": [[19, "reporting"]], "Return Statement": [[19, "return-statement"]], "Scalar Types": [[22, "scalar-types"]], "Secondary Units": [[13, "secondary-units"]], "Section 1 \u2013 Definitions.": [[7, "section-1-definitions"]], "Section 2 \u2013 Scope.": [[7, "section-2-scope"]], "Section 3 \u2013 License Conditions.": [[7, "section-3-license-conditions"]], "Section 4 \u2013 Sui Generis Database Rights.": [[7, "section-4-sui-generis-database-rights"]], "Section 5 \u2013 Disclaimer of Warranties and Limitation of Liability.": [[7, "section-5-disclaimer-of-warranties-and-limitation-of-liability"]], "Section 6 \u2013 Term and Termination.": [[7, "section-6-term-and-termination"]], "Section 7 \u2013 Other Terms and Conditions.": [[7, "section-7-other-terms-and-conditions"]], "Section 8 \u2013 Interpretation.": [[7, "section-8-interpretation"]], "Sequential Statements": [[19, null]], "Shared Variable": [[18, "shared-variable"]], "Shifting Expressions": [[15, "shifting-expressions"]], "Signal": [[18, "signal"]], "Signal Assignment": [[12, "signal-assignment"], [19, "signal-assignment"]], "Signal as Parameter": [[18, "signal-as-parameter"]], "Signal as Port": [[18, "signal-as-port"]], "Signals": [[18, "signals"]], "Sphinx Documentation (Optional)": [[6, "sphinx-documentation-optional"]], "Static Type Checking Report": [[51, null]], "Subprogram Declarations": [[20, null]], "Subtype Declarations": [[21, null]], "TODOs": [[25, null]], "Table of Content": [[12, "table-of-content"], [13, "table-of-content"], [14, "table-of-content"], [15, "table-of-content"], [16, "table-of-content"], [17, "table-of-content"], [18, "table-of-content"], [19, "table-of-content"], [20, "table-of-content"], [22, "table-of-content"]], "Ternary Expressions": [[15, "ternary-expressions"]], "The pyVHDLModel Documentation": [[27, null]], "Todo": [[9, "id1"], [9, "id2"], [12, "id1"], [12, "id2"], [12, "id3"], [12, "id4"], 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b/typing/html/pyVHDLModel/Association.py.html new file mode 100644 index 000000000..15419dee5 --- /dev/null +++ b/typing/html/pyVHDLModel/Association.py.html @@ -0,0 +1,239 @@ + + + + + + +

pyVHDLModel.Association

+ + + + + + +
pyVHDLModel/Association.py
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+
# ==================================================================================================================== #
+#             __     ___   _ ____  _     __  __           _      _                                                     #
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |                                                    #
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |                                                    #
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |                                                    #
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|                                                    #
+#  |_|    |___/                                                                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""
+This module contains parts of an abstract document language model for VHDL.
+
+Associations are used in generic maps, port maps and parameter maps.
+"""
+from typing               import Optional as Nullable, Union
+
+from pyTooling.Decorators import export, readonly
+
+from pyVHDLModel.Base       import ModelEntity
+from pyVHDLModel.Symbol     import Symbol
+from pyVHDLModel.Expression import BaseExpression, QualifiedExpression, FunctionCall, TypeConversion, Literal
+
+
+ExpressionUnion = Union[
+	BaseExpression,
+	QualifiedExpression,
+	FunctionCall,
+	TypeConversion,
+	# ConstantOrSymbol,     TODO: ObjectSymbol
+	Literal,
+]
+
+
+@export
+class AssociationItem(ModelEntity):
+	"""
+	A base-class for all association items.
+	"""
+
+	_formal: Nullable[Symbol]
+	_actual: ExpressionUnion
+
+	def __init__(self, actual: ExpressionUnion, formal: Nullable[Symbol] = None) -> None:
+		super().__init__()
+
+		self._formal = formal
+		if formal is not None:
+			formal._parent = self
+
+		self._actual = actual
+		# actual._parent = self  # FIXME: actual is provided as None
+
+	@readonly
+	def Formal(self) -> Nullable[Symbol]:  # TODO: can also be a conversion function !!
+		return self._formal
+
+	@readonly
+	def Actual(self) -> ExpressionUnion:
+		return self._actual
+
+	def __str__(self) -> str:
+		if self._formal is None:
+			return str(self._actual)
+		else:
+			return f"{self._formal!s} => {self._actual!s}"
+
+
+@export
+class GenericAssociationItem(AssociationItem):
+	"""
+	A base-class for all generic association items used in generic map aspects.
+	"""
+
+
+@export
+class PortAssociationItem(AssociationItem):
+	"""
+	A base-class for all port association items used in port map aspects.
+	"""
+
+
+@export
+class ParameterAssociationItem(AssociationItem):
+	"""
+	A base-class for all parameter association items used in parameter map aspects.
+	"""
+
+ + diff --git a/typing/html/pyVHDLModel/Base.py.html b/typing/html/pyVHDLModel/Base.py.html new file mode 100644 index 000000000..97162fcc5 --- /dev/null +++ b/typing/html/pyVHDLModel/Base.py.html @@ -0,0 +1,951 @@ + + + + + + +

pyVHDLModel.Base

+ + + + + + +
pyVHDLModel/Base.py
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+
# ==================================================================================================================== #
+#             __     ___   _ ____  _     __  __           _      _                                                     #
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |                                                    #
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |                                                    #
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |                                                    #
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|                                                    #
+#  |_|    |___/                                                                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""
+This module contains parts of an abstract document language model for VHDL.
+
+Base-classes for the VHDL language model.
+"""
+from enum                  import unique, Enum
+from typing                import Type, Tuple, Iterable, Optional as Nullable, Union, cast
+
+from pyTooling.Decorators  import export, readonly
+from pyTooling.MetaClasses import ExtendedType
+
+
+__all__ = ["ExpressionUnion"]
+
+
+ExpressionUnion = Union[
+	'BaseExpression',
+	'QualifiedExpression',
+	'FunctionCall',
+	'TypeConversion',
+	# ConstantOrSymbol,     TODO: ObjectSymbol
+	'Literal',
+]
+
+
+@export
+@unique
+class Direction(Enum):
+	"""An enumeration representing a direction in a range	(``to`` or ``downto``)."""
+
+	To =      0  #: Ascending direction
+	DownTo =  1  #: Descending direction
+
+	def __str__(self) -> str:
+		"""
+		Formats the direction to ``to`` or ``downto``.
+
+		:returns: Formatted direction.
+		"""
+		return ("to", "downto")[cast(int, self.value)]       # TODO: check performance
+
+
+@export
+@unique
+class Mode(Enum):
+	"""
+	A ``Mode`` is an enumeration. It represents the direction of data exchange (``in``, ``out``, ...) for objects in
+	generic, port or parameter lists.
+
+	In case no *mode* is defined, ``Default`` is used, so the *mode* is inferred from context.
+	"""
+
+	Default = 0  #: Mode not defined, thus it's context dependent.
+	In =      1  #: Input
+	Out =     2  #: Output
+	InOut =   3  #: Bi-directional
+	Buffer =  4  #: Buffered output
+	Linkage = 5  #: undocumented
+
+	def __str__(self) -> str:
+		"""
+		Formats the direction.
+
+		:returns: Formatted direction.
+		"""
+		return ("", "in", "out", "inout", "buffer", "linkage")[cast(int, self.value)]       # TODO: check performance
+
+
+@export
+class ModelEntity(metaclass=ExtendedType, slots=True):
+	"""
+	``ModelEntity`` is the base-class for all classes in the VHDL language model, except for mixin classes (see multiple
+	inheritance) and enumerations.
+
+	Each entity in this model has a reference to its parent entity. Therefore, a protected variable :attr:`_parent` is
+	available and a readonly property :attr:`Parent`.
+	"""
+
+	_parent: 'ModelEntity'      #: Reference to a parent entity in the logical model hierarchy.
+
+	def __init__(self, parent: Nullable["ModelEntity"] = None) -> None:
+		"""
+		Initializes a VHDL model entity.
+
+		:param parent: The parent model entity of this entity.
+		"""
+		self._parent = parent
+
+	@readonly
+	def Parent(self) -> 'ModelEntity':
+		"""
+		Read-only property to access the model entity's parent element reference in a logical hierarchy (:attr:`_parent`).
+
+		:returns: Reference to the parent entity.
+		"""
+		return self._parent
+
+	def GetAncestor(self, type: Type) -> 'ModelEntity':
+		parent = self._parent
+		while not isinstance(parent, type):
+			parent = parent._parent
+
+		return parent
+
+
+@export
+class NamedEntityMixin(metaclass=ExtendedType, mixin=True):
+	"""
+	A ``NamedEntityMixin`` is a mixin class for all VHDL entities that have identifiers.
+
+	Protected variables :attr:`_identifier` and :attr:`_normalizedIdentifier` are available to derived classes as well as
+	two readonly properties :attr:`Identifier` and :attr:`NormalizedIdentifier` for public access.
+	"""
+
+	_identifier: str            #: The identifier of a model entity.
+	_normalizedIdentifier: str  #: The normalized (lower case) identifier of a model entity.
+
+	def __init__(self, identifier: str) -> None:
+		"""
+		Initializes a named entity.
+
+		:param identifier: Identifier (name) of the model entity.
+		"""
+		self._identifier = identifier
+		self._normalizedIdentifier = identifier.lower()
+
+	@readonly
+	def Identifier(self) -> str:
+		"""
+		Returns a model entity's identifier (name).
+
+		:returns: Name of a model entity.
+		"""
+		return self._identifier
+
+	@readonly
+	def NormalizedIdentifier(self) -> str:
+		"""
+		Returns a model entity's normalized identifier (lower case name).
+
+		:returns: Normalized name of a model entity.
+		"""
+		return self._normalizedIdentifier
+
+
+@export
+class MultipleNamedEntityMixin(metaclass=ExtendedType, mixin=True):
+	"""
+	A ``MultipleNamedEntityMixin`` is a mixin class for all VHDL entities that declare multiple instances at once by
+	defining multiple identifiers.
+
+	Protected variables :attr:`_identifiers` and :attr:`_normalizedIdentifiers` are available to derived classes as well
+	as two readonly properties :attr:`Identifiers` and :attr:`NormalizedIdentifiers` for public access.
+	"""
+
+	_identifiers:           Tuple[str]  #: A list of identifiers.
+	_normalizedIdentifiers: Tuple[str]  #: A list of normalized (lower case) identifiers.
+
+	def __init__(self, identifiers: Iterable[str]) -> None:
+		"""
+		Initializes a multiple-named entity.
+
+		:param identifiers: Sequence of identifiers (names) of the model entity.
+		"""
+		self._identifiers = tuple(identifiers)
+		self._normalizedIdentifiers = tuple([identifier.lower() for identifier in identifiers])
+
+	@readonly
+	def Identifiers(self) -> Tuple[str]:
+		"""
+		Returns a model entity's tuple of identifiers (names).
+
+		:returns: Tuple of identifiers.
+		"""
+		return self._identifiers
+
+	@readonly
+	def NormalizedIdentifiers(self) -> Tuple[str]:
+		"""
+		Returns a model entity's tuple of normalized identifiers (lower case names).
+
+		:returns: Tuple of normalized identifiers.
+		"""
+		return self._normalizedIdentifiers
+
+
+@export
+class LabeledEntityMixin(metaclass=ExtendedType, mixin=True):
+	"""
+	A ``LabeledEntityMixin`` is a mixin class for all VHDL entities that can have labels.
+
+	protected variables :attr:`_label` and :attr:`_normalizedLabel` are available to derived classes as well as two
+	readonly properties :attr:`Label` and :attr:`NormalizedLabel` for public access.
+	"""
+	_label:           Nullable[str]  #: The label of a model entity.
+	_normalizedLabel: Nullable[str]  #: The normalized (lower case) label of a model entity.
+
+	def __init__(self, label: Nullable[str]) -> None:
+		"""
+		Initializes a labeled entity.
+
+		:param label: Label of the model entity.
+		"""
+		self._label = label
+		self._normalizedLabel = label.lower() if label is not None else None
+
+	@readonly
+	def Label(self) -> Nullable[str]:
+		"""
+		Returns a model entity's label.
+
+		:returns: Label of a model entity.
+		"""
+		return self._label
+
+	@readonly
+	def NormalizedLabel(self) -> Nullable[str]:
+		"""
+		Returns a model entity's normalized (lower case) label.
+
+		:returns: Normalized label of a model entity.
+		"""
+		return self._normalizedLabel
+
+
+@export
+class DocumentedEntityMixin(metaclass=ExtendedType, mixin=True):
+	"""
+	A ``DocumentedEntityMixin`` is a mixin class for all VHDL entities that can have an associated documentation.
+
+	A protected variable :attr:`_documentation` is available to derived classes as well as a readonly property
+	:attr:`Documentation` for public access.
+	"""
+
+	_documentation: Nullable[str]  #: The associated documentation of a model entity.
+
+	def __init__(self, documentation: Nullable[str]) -> None:
+		"""
+		Initializes a documented entity.
+
+		:param documentation: Documentation of a model entity.
+		"""
+		self._documentation = documentation
+
+	@readonly
+	def Documentation(self) -> Nullable[str]:
+		"""
+		Returns a model entity's associated documentation.
+
+		:returns: Associated documentation of a model entity.
+		"""
+		return self._documentation
+
+
+@export
+class ConditionalMixin(metaclass=ExtendedType, mixin=True):
+	"""A ``ConditionalMixin`` is a mixin-class for all statements with a condition."""
+
+	_condition: ExpressionUnion
+
+	def __init__(self, condition: Nullable[ExpressionUnion] = None) -> None:
+		"""
+		Initializes a statement with a condition.
+
+		When the condition is not None, the condition's parent reference is set to this statement.
+
+		:param condition: The expression representing the condition.
+		"""
+		self._condition = condition
+		if condition is not None:
+			condition._parent = self
+
+	@readonly
+	def Condition(self) -> ExpressionUnion:
+		"""
+		Read-only property to access the condition of a statement (:attr:`_condition`).
+
+		:returns: The expression representing the condition of a statement.
+		"""
+		return self._condition
+
+
+@export
+class BranchMixin(metaclass=ExtendedType, mixin=True):
+	"""A ``BranchMixin`` is a mixin-class for all statements with branches."""
+
+	def __init__(self) -> None:
+		pass
+
+
+@export
+class ConditionalBranchMixin(BranchMixin, ConditionalMixin, mixin=True):
+	"""A ``BaseBranch`` is a mixin-class for all branch statements with a condition."""
+	def __init__(self, condition: ExpressionUnion) -> None:
+		super().__init__()
+		ConditionalMixin.__init__(self, condition)
+
+
+@export
+class IfBranchMixin(ConditionalBranchMixin, mixin=True):
+	"""A ``BaseIfBranch`` is a mixin-class for all if-branches."""
+
+
+@export
+class ElsifBranchMixin(ConditionalBranchMixin, mixin=True):
+	"""A ``BaseElsifBranch`` is a mixin-class for all elsif-branches."""
+
+
+@export
+class ElseBranchMixin(BranchMixin, mixin=True):
+	"""A ``BaseElseBranch`` is a mixin-class for all else-branches."""
+
+
+@export
+class ReportStatementMixin(metaclass=ExtendedType, mixin=True):
+	"""A ``MixinReportStatement`` is a mixin-class for all report and assert statements."""
+
+	_message:  Nullable[ExpressionUnion]
+	_severity: Nullable[ExpressionUnion]
+
+	def __init__(self, message: Nullable[ExpressionUnion] = None, severity: Nullable[ExpressionUnion] = None) -> None:
+		self._message = message
+		if message is not None:
+			message._parent = self
+
+		self._severity = severity
+		if severity is not None:
+			severity._parent = self
+
+	@property
+	def Message(self) -> Nullable[ExpressionUnion]:
+		return self._message
+
+	@property
+	def Severity(self) -> Nullable[ExpressionUnion]:
+		return self._severity
+
+
+@export
+class AssertStatementMixin(ReportStatementMixin, ConditionalMixin, mixin=True):
+	"""A ``MixinAssertStatement`` is a mixin-class for all assert statements."""
+
+	def __init__(self, condition: ExpressionUnion, message: Nullable[ExpressionUnion] = None, severity: Nullable[ExpressionUnion] = None) -> None:
+		super().__init__(message, severity)
+		ConditionalMixin.__init__(self, condition)
+
+
+class BlockStatementMixin(metaclass=ExtendedType, mixin=True):
+	"""A ``BlockStatement`` is a mixin-class for all block statements."""
+
+	def __init__(self) -> None:
+		pass
+
+
+@export
+class BaseChoice(ModelEntity):
+	"""A ``Choice`` is a base-class for all choices."""
+
+
+@export
+class BaseCase(ModelEntity):
+	"""
+	A ``Case`` is a base-class for all cases.
+	"""
+
+
+@export
+class Range(ModelEntity):
+	_leftBound:  ExpressionUnion
+	_rightBound: ExpressionUnion
+	_direction:  Direction
+
+	def __init__(self, leftBound: ExpressionUnion, rightBound: ExpressionUnion, direction: Direction, parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+
+		self._leftBound = leftBound
+		leftBound._parent = self
+
+		self._rightBound = rightBound
+		rightBound._parent = self
+
+		self._direction = direction
+
+	@property
+	def LeftBound(self) -> ExpressionUnion:
+		return self._leftBound
+
+	@property
+	def RightBound(self) -> ExpressionUnion:
+		return self._rightBound
+
+	@property
+	def Direction(self) -> Direction:
+		return self._direction
+
+	def __str__(self) -> str:
+		return f"{self._leftBound!s} {self._direction!s} {self._rightBound!s}"
+
+
+@export
+class WaveformElement(ModelEntity):
+	_expression: ExpressionUnion
+	_after: ExpressionUnion
+
+	def __init__(self, expression: ExpressionUnion, after: Nullable[ExpressionUnion] = None, parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+
+		self._expression = expression
+		expression._parent = self
+
+		self._after = after
+		if after is not None:
+			after._parent = self
+
+	@property
+	def Expression(self) -> ExpressionUnion:
+		return self._expression
+
+	@property
+	def After(self) -> Expression:
+		return self._after
+
+ + diff --git a/typing/html/pyVHDLModel/Common.py.html b/typing/html/pyVHDLModel/Common.py.html new file mode 100644 index 000000000..5b7e43db4 --- /dev/null +++ b/typing/html/pyVHDLModel/Common.py.html @@ -0,0 +1,282 @@ + + + + + + +

pyVHDLModel.Common

+ + + + + + +
pyVHDLModel/Common.py
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+
# ==================================================================================================================== #
+#             __     ___   _ ____  _     __  __           _      _                                                     #
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |                                                    #
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |                                                    #
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |                                                    #
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|                                                    #
+#  |_|    |___/                                                                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""
+This module contains parts of an abstract document language model for VHDL.
+
+Common definitions and Mixins are used by many classes in the model as base-classes.
+"""
+from typing                  import List, Iterable, Union, Optional as Nullable
+
+from pyTooling.Decorators    import export, readonly
+from pyTooling.MetaClasses   import ExtendedType
+
+from pyVHDLModel.Base        import ModelEntity, LabeledEntityMixin
+from pyVHDLModel.Expression  import BaseExpression, QualifiedExpression, FunctionCall, TypeConversion, Literal
+from pyVHDLModel.Symbol      import Symbol
+from pyVHDLModel.Association import ParameterAssociationItem
+
+
+ExpressionUnion = Union[
+	BaseExpression,
+	QualifiedExpression,
+	FunctionCall,
+	TypeConversion,
+	# ConstantOrSymbol,     TODO: ObjectSymbol
+	Literal,
+]
+
+
+@export
+class Statement(ModelEntity, LabeledEntityMixin):
+	"""
+	A ``Statement`` is a base-class for all statements.
+	"""
+	def __init__(self, label: Nullable[str] = None, parent=None) -> None:
+		super().__init__(parent)
+		LabeledEntityMixin.__init__(self, label)
+
+
+@export
+class ProcedureCallMixin(metaclass=ExtendedType, mixin=True):
+	_procedure:         Symbol  # TODO: implement a ProcedureSymbol
+	_parameterMappings: List[ParameterAssociationItem]
+
+	def __init__(self, procedureName: Symbol, parameterMappings: Nullable[Iterable[ParameterAssociationItem]] = None) -> None:
+		self._procedure = procedureName
+		procedureName._parent = self
+
+		# TODO: extract to mixin
+		self._parameterMappings = []
+		if parameterMappings is not None:
+			for parameterMapping in parameterMappings:
+				self._parameterMappings.append(parameterMapping)
+				parameterMapping._parent = self
+
+	@readonly
+	def Procedure(self) -> Symbol:
+		return self._procedure
+
+	@property
+	def ParameterMappings(self) -> List[ParameterAssociationItem]:
+		return self._parameterMappings
+
+
+@export
+class AssignmentMixin(metaclass=ExtendedType, mixin=True):
+	"""A mixin-class for all assignment statements."""
+
+	_target: Symbol
+
+	def __init__(self, target: Symbol) -> None:
+		self._target = target
+		target._parent = self
+
+	@property
+	def Target(self) -> Symbol:
+		return self._target
+
+
+@export
+class SignalAssignmentMixin(AssignmentMixin, mixin=True):
+	"""A mixin-class for all signal assignment statements."""
+
+
+@export
+class VariableAssignmentMixin(AssignmentMixin, mixin=True):
+	"""A mixin-class for all variable assignment statements."""
+
+	# FIXME: move to sequential?
+	_expression: ExpressionUnion
+
+	def __init__(self, target: Symbol, expression: ExpressionUnion) -> None:
+		super().__init__(target)
+
+		self._expression = expression
+		expression._parent = self
+
+	@property
+	def Expression(self) -> ExpressionUnion:
+		return self._expression
+
+ + diff --git a/typing/html/pyVHDLModel/Concurrent.py.html b/typing/html/pyVHDLModel/Concurrent.py.html new file mode 100644 index 000000000..abcb6f2bd --- /dev/null +++ b/typing/html/pyVHDLModel/Concurrent.py.html @@ -0,0 +1,1832 @@ + + + + + + +

pyVHDLModel.Concurrent

+ + + + + + +
pyVHDLModel/Concurrent.py
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+
# ==================================================================================================================== #
+#             __     ___   _ ____  _     __  __           _      _                                                     #
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |                                                    #
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |                                                    #
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |                                                    #
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|                                                    #
+#  |_|    |___/                                                                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""
+This module contains parts of an abstract document language model for VHDL.
+
+Concurrent defines all concurrent statements used in entities, architectures, generates and block statements.
+"""
+from typing                  import List, Dict, Union, Iterable, Generator, Optional as Nullable
+
+from pyTooling.Decorators    import export, readonly
+from pyTooling.MetaClasses   import ExtendedType
+
+from pyVHDLModel.Base        import ModelEntity, LabeledEntityMixin, DocumentedEntityMixin, Range, BaseChoice, BaseCase, IfBranchMixin
+from pyVHDLModel.Base        import ElsifBranchMixin, ElseBranchMixin, AssertStatementMixin, BlockStatementMixin, WaveformElement
+from pyVHDLModel.Regions     import ConcurrentDeclarationRegionMixin
+from pyVHDLModel.Namespace   import Namespace
+from pyVHDLModel.Name        import Name
+from pyVHDLModel.Symbol      import ComponentInstantiationSymbol, EntityInstantiationSymbol, ArchitectureSymbol, ConfigurationInstantiationSymbol
+from pyVHDLModel.Expression  import BaseExpression, QualifiedExpression, FunctionCall, TypeConversion, Literal
+from pyVHDLModel.Association import AssociationItem, ParameterAssociationItem
+from pyVHDLModel.Interface   import PortInterfaceItemMixin
+from pyVHDLModel.Common      import Statement, ProcedureCallMixin, SignalAssignmentMixin
+from pyVHDLModel.Sequential  import SequentialStatement, SequentialStatementsMixin, SequentialDeclarationsMixin
+
+
+ExpressionUnion = Union[
+	BaseExpression,
+	QualifiedExpression,
+	FunctionCall,
+	TypeConversion,
+	# ConstantOrSymbol,     TODO: ObjectSymbol
+	Literal,
+]
+
+
+@export
+class ConcurrentStatement(Statement):
+	"""A base-class for all concurrent statements."""
+
+
+@export
+class ConcurrentStatementsMixin(metaclass=ExtendedType, mixin=True):
+	"""
+	A mixin-class for all language constructs supporting concurrent statements.
+
+	.. seealso::
+
+	   .. todo:: concurrent declaration region
+	"""
+
+	_statements:     List[ConcurrentStatement]
+
+	_instantiations: Dict[str, 'Instantiation']  # TODO: add another instantiation class level for entity/configuration/component inst.
+	_blocks:         Dict[str, 'ConcurrentBlockStatement']
+	_generates:      Dict[str, 'GenerateStatement']
+	_hierarchy:      Dict[str, Union['ConcurrentBlockStatement', 'GenerateStatement']]
+
+	def __init__(self, statements: Nullable[Iterable[ConcurrentStatement]] = None) -> None:
+		self._statements = []
+
+		self._instantiations = {}
+		self._blocks = {}
+		self._generates = {}
+		self._hierarchy = {}
+
+		if statements is not None:
+			for statement in statements:
+				self._statements.append(statement)
+				statement._parent = self
+
+	@readonly
+	def Statements(self) -> List[ConcurrentStatement]:
+		return self._statements
+
+	def IterateInstantiations(self) -> Generator['Instantiation', None, None]:
+		for instance in self._instantiations.values():
+			yield instance
+
+		for block in self._blocks.values():
+			yield from block.IterateInstantiations()
+
+		for generate in self._generates.values():
+			yield from generate.IterateInstantiations()
+
+	# TODO: move into _init__
+	def IndexStatements(self) -> None:
+		for statement in self._statements:
+			if isinstance(statement, (EntityInstantiation, ComponentInstantiation, ConfigurationInstantiation)):
+				self._instantiations[statement.NormalizedLabel] = statement
+			elif isinstance(statement, (ForGenerateStatement, IfGenerateStatement, CaseGenerateStatement)):
+				self._generates[statement.NormalizedLabel] = statement
+				statement.IndexStatement()
+			elif isinstance(statement, ConcurrentBlockStatement):
+				self._hierarchy[statement.NormalizedLabel] = statement
+				statement.IndexStatements()
+
+
+@export
+class Instantiation(ConcurrentStatement):
+	"""
+	A base-class for all (component) instantiations.
+	"""
+
+	_genericAssociations: List[AssociationItem]
+	_portAssociations: List[AssociationItem]
+
+	def __init__(
+		self,
+		label: str,
+		genericAssociations: Nullable[Iterable[AssociationItem]] = None,
+		portAssociations: Nullable[Iterable[AssociationItem]] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(label, parent)
+
+		# TODO: extract to mixin
+		self._genericAssociations = []
+		if genericAssociations is not None:
+			for association in genericAssociations:
+				self._genericAssociations.append(association)
+				association._parent = self
+
+		# TODO: extract to mixin
+		self._portAssociations = []
+		if portAssociations is not None:
+			for association in portAssociations:
+				self._portAssociations.append(association)
+				association._parent = self
+
+	@readonly
+	def GenericAssociations(self) -> List[AssociationItem]:
+		return self._genericAssociations
+
+	@property
+	def PortAssociations(self) -> List[AssociationItem]:
+		return self._portAssociations
+
+
+@export
+class ComponentInstantiation(Instantiation):
+	"""
+	Represents a component instantiation by referring to a component name.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      inst : component Counter;
+	"""
+
+	_component: ComponentInstantiationSymbol
+
+	def __init__(
+		self,
+		label: str,
+		componentSymbol: ComponentInstantiationSymbol,
+		genericAssociations: Nullable[Iterable[AssociationItem]] = None,
+		portAssociations: Nullable[Iterable[AssociationItem]] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(label, genericAssociations, portAssociations, parent)
+
+		self._component = componentSymbol
+		componentSymbol._parent = self
+
+	@property
+	def Component(self) -> ComponentInstantiationSymbol:
+		return self._component
+
+
+@export
+class EntityInstantiation(Instantiation):
+	"""
+	Represents an entity instantiation by referring to an entity name with optional architecture name.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      inst : entity work. Counter;
+	"""
+
+	_entity: EntityInstantiationSymbol
+	_architecture: ArchitectureSymbol
+
+	def __init__(
+		self,
+		label: str,
+		entitySymbol: EntityInstantiationSymbol,
+		architectureSymbol: Nullable[ArchitectureSymbol] = None,
+		genericAssociations: Nullable[Iterable[AssociationItem]] = None,
+		portAssociations: Nullable[Iterable[AssociationItem]] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(label, genericAssociations, portAssociations, parent)
+
+		self._entity = entitySymbol
+		entitySymbol._parent = self
+
+		self._architecture = architectureSymbol
+		if architectureSymbol is not None:
+			architectureSymbol._parent = self
+
+	@property
+	def Entity(self) -> EntityInstantiationSymbol:
+		return self._entity
+
+	@property
+	def Architecture(self) -> ArchitectureSymbol:
+		return self._architecture
+
+
+@export
+class ConfigurationInstantiation(Instantiation):
+	"""
+	Represents a configuration instantiation by referring to a configuration name.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      inst : configuration Counter;
+	"""
+
+	_configuration: ConfigurationInstantiationSymbol
+
+	def __init__(
+		self,
+		label: str,
+		configurationSymbol: ConfigurationInstantiationSymbol,
+		genericAssociations: Nullable[Iterable[AssociationItem]] = None,
+		portAssociations: Nullable[Iterable[AssociationItem]] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(label, genericAssociations, portAssociations, parent)
+
+		self._configuration = configurationSymbol
+		configurationSymbol._parent = self
+
+	@property
+	def Configuration(self) -> ConfigurationInstantiationSymbol:
+		return self._configuration
+
+
+@export
+class ProcessStatement(ConcurrentStatement, SequentialDeclarationsMixin, SequentialStatementsMixin, DocumentedEntityMixin):
+	"""
+	Represents a process statement with sensitivity list, sequential declaration region and sequential statements.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      proc: process(Clock)
+	        -- sequential declarations
+	      begin
+	        -- sequential statements
+	      end process;
+	"""
+
+	_sensitivityList: List[Name]  # TODO: implement a SignalSymbol
+
+	def __init__(
+		self,
+		label: Nullable[str] = None,
+		declaredItems: Nullable[Iterable] = None,
+		statements: Nullable[Iterable[SequentialStatement]] = None,
+		sensitivityList: Nullable[Iterable[Name]] = None,
+		documentation: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(label, parent)
+		SequentialDeclarationsMixin.__init__(self, declaredItems)
+		SequentialStatementsMixin.__init__(self, statements)
+		DocumentedEntityMixin.__init__(self, documentation)
+
+		if sensitivityList is None:
+			self._sensitivityList = None
+		else:
+			self._sensitivityList = []  # TODO: convert to dict
+			for signalSymbol in sensitivityList:
+				self._sensitivityList.append(signalSymbol)
+				# signalSymbol._parent = self  # FIXME: currently str are provided
+
+	@property
+	def SensitivityList(self) -> List[Name]:
+		return self._sensitivityList
+
+
+@export
+class ConcurrentProcedureCall(ConcurrentStatement, ProcedureCallMixin):
+	def __init__(
+		self,
+		label: str,
+		procedureName: Name,
+		parameterMappings: Nullable[Iterable[ParameterAssociationItem]] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(label, parent)
+		ProcedureCallMixin.__init__(self, procedureName, parameterMappings)
+
+
+@export
+class ConcurrentBlockStatement(ConcurrentStatement, BlockStatementMixin, LabeledEntityMixin, ConcurrentDeclarationRegionMixin, ConcurrentStatementsMixin, DocumentedEntityMixin):
+	_portItems:     List[PortInterfaceItemMixin]
+
+	def __init__(
+		self,
+		label: str,
+		portItems: Nullable[Iterable[PortInterfaceItemMixin]] = None,
+		declaredItems: Nullable[Iterable] = None,
+		statements: Iterable['ConcurrentStatement'] = None,
+		documentation: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(label, parent)
+		BlockStatementMixin.__init__(self)
+		LabeledEntityMixin.__init__(self, label)
+		ConcurrentDeclarationRegionMixin.__init__(self, declaredItems)
+		ConcurrentStatementsMixin.__init__(self, statements)
+		DocumentedEntityMixin.__init__(self, documentation)
+
+		# TODO: extract to mixin
+		self._portItems = []
+		if portItems is not None:
+			for item in portItems:
+				self._portItems.append(item)
+				item._parent = self
+
+	@property
+	def PortItems(self) -> List[PortInterfaceItemMixin]:
+		return self._portItems
+
+
+@export
+class GenerateBranch(ModelEntity, ConcurrentDeclarationRegionMixin, ConcurrentStatementsMixin):
+	"""
+	A base-class for all branches in a generate statements.
+
+	.. seealso::
+
+	   * :class:`If-generate branch <pyVHDLModel.Concurrent.IfGenerateBranch>`
+	   * :class:`Elsif-generate branch <pyVHDLModel.Concurrent.ElsifGenerateBranch>`
+	   * :class:`Else-generate branch <pyVHDLModel.Concurrent.ElseGenerateBranch>`
+	"""
+
+	_alternativeLabel:           Nullable[str]
+	_normalizedAlternativeLabel: Nullable[str]
+
+	_namespace:                  Namespace
+
+	def __init__(
+		self,
+		declaredItems: Nullable[Iterable] = None,
+		statements: Nullable[Iterable[ConcurrentStatement]] = None,
+		alternativeLabel: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(parent)
+		ConcurrentDeclarationRegionMixin.__init__(self, declaredItems)
+		ConcurrentStatementsMixin.__init__(self, statements)
+
+		self._alternativeLabel = alternativeLabel
+		self._normalizedAlternativeLabel = alternativeLabel.lower() if alternativeLabel is not None else None
+
+		self._namespace = Namespace(self._normalizedAlternativeLabel)
+
+	@property
+	def AlternativeLabel(self) -> Nullable[str]:
+		return self._alternativeLabel
+
+	@property
+	def NormalizedAlternativeLabel(self) -> Nullable[str]:
+		return self._normalizedAlternativeLabel
+
+
+@export
+class IfGenerateBranch(GenerateBranch, IfBranchMixin):
+	"""
+	Represents if-generate branch in a generate statement with a concurrent declaration region and concurrent statements.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      gen: if condition generate
+	        -- concurrent declarations
+	      begin
+	        -- concurrent statements
+	      elsif condition generate
+	        -- ...
+	      else generate
+	        -- ...
+	      end generate;
+	"""
+
+	def __init__(
+		self,
+		condition: ExpressionUnion,
+		declaredItems: Nullable[Iterable] = None,
+		statements: Nullable[Iterable[ConcurrentStatement]] = None,
+		alternativeLabel: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(declaredItems, statements, alternativeLabel, parent)
+		IfBranchMixin.__init__(self, condition)
+
+
+@export
+class ElsifGenerateBranch(GenerateBranch, ElsifBranchMixin):
+	"""
+	Represents elsif-generate branch in a generate statement with a concurrent declaration region and concurrent statements.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      gen: if condition generate
+	        -- ...
+	      elsif condition generate
+	        -- concurrent declarations
+	      begin
+	        -- concurrent statements
+	      else generate
+	        -- ...
+	      end generate;
+	"""
+
+	def __init__(
+		self,
+		condition: ExpressionUnion,
+		declaredItems: Nullable[Iterable] = None,
+		statements: Nullable[Iterable[ConcurrentStatement]] = None,
+		alternativeLabel: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(declaredItems, statements, alternativeLabel, parent)
+		ElsifBranchMixin.__init__(self, condition)
+
+
+@export
+class ElseGenerateBranch(GenerateBranch, ElseBranchMixin):
+	"""
+	Represents else-generate branch in a generate statement with a concurrent declaration region and concurrent statements.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      gen: if condition generate
+	        -- ...
+	      elsif condition generate
+	        -- ...
+	      else generate
+	        -- concurrent declarations
+	      begin
+	        -- concurrent statements
+	      end generate;
+	"""
+
+	def __init__(
+		self,
+		declaredItems: Nullable[Iterable] = None,
+		statements: Nullable[Iterable[ConcurrentStatement]] = None,
+		alternativeLabel: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(declaredItems, statements, alternativeLabel, parent)
+		ElseBranchMixin.__init__(self)
+
+
+@export
+class GenerateStatement(ConcurrentStatement):
+	"""
+	A base-class for all generate statements.
+
+	.. seealso::
+
+	   * :class:`If...generate statement <pyVHDLModel.Concurrent.IfGenerateStatement>`
+	   * :class:`Case...generate statement <pyVHDLModel.Concurrent.CaseGenerateStatement>`
+	   * :class:`For...generate statement <pyVHDLModel.Concurrent.ForGenerateStatement>`
+	"""
+
+	_namespace: Namespace
+
+	def __init__(
+		self,
+		label: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(label, parent)
+
+		self._namespace = Namespace(self._normalizedLabel)
+
+	# @mustoverride
+	def IterateInstantiations(self) -> Generator[Instantiation, None, None]:
+		raise NotImplementedError()
+
+	# @mustoverride
+	def IndexStatement(self) -> None:
+		raise NotImplementedError()
+
+
+@export
+class IfGenerateStatement(GenerateStatement):
+	"""
+	Represents an if...generate statement.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      gen: if condition generate
+	        -- ...
+	      elsif condition generate
+	        -- ...
+	      else generate
+	        -- ...
+	      end generate;
+
+	.. seealso::
+
+	   * :class:`Generate branch <pyVHDLModel.Concurrent.GenerateBranch>` base-class
+	   * :class:`If-generate branch <pyVHDLModel.Concurrent.IfGenerateBranch>`
+	   * :class:`Elsif-generate branch <pyVHDLModel.Concurrent.ElsifGenerateBranch>`
+	   * :class:`Else-generate branch <pyVHDLModel.Concurrent.ElseGenerateBranch>`
+	"""
+
+	_ifBranch:      IfGenerateBranch
+	_elsifBranches: List[ElsifGenerateBranch]
+	_elseBranch:    Nullable[ElseGenerateBranch]
+
+	def __init__(
+		self,
+		label: str,
+		ifBranch: IfGenerateBranch,
+		elsifBranches: Nullable[Iterable[ElsifGenerateBranch]] = None,
+		elseBranch: Nullable[ElseGenerateBranch] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(label, parent)
+
+		self._ifBranch = ifBranch
+		ifBranch._parent = self
+
+		self._elsifBranches = []
+		if elsifBranches is not None:
+			for branch in elsifBranches:
+				self._elsifBranches.append(branch)
+				branch._parent = self
+
+		if elseBranch is not None:
+			self._elseBranch = elseBranch
+			elseBranch._parent = self
+		else:
+			self._elseBranch = None
+
+	@property
+	def IfBranch(self) -> IfGenerateBranch:
+		return self._ifBranch
+
+	@property
+	def ElsifBranches(self) -> List[ElsifGenerateBranch]:
+		return self._elsifBranches
+
+	@property
+	def ElseBranch(self) -> Nullable[ElseGenerateBranch]:
+		return self._elseBranch
+
+	def IterateInstantiations(self) -> Generator[Instantiation, None, None]:
+		yield from self._ifBranch.IterateInstantiations()
+		for branch in self._elsifBranches:
+			yield from branch.IterateInstantiations()
+		if self._elseBranch is not None:
+			yield from self._ifBranch.IterateInstantiations()
+
+	def IndexStatement(self) -> None:
+		self._ifBranch.IndexStatements()
+		for branch in self._elsifBranches:
+			branch.IndexStatements()
+		if self._elseBranch is not None:
+			self._elseBranch.IndexStatements()
+
+
+@export
+class ConcurrentChoice(BaseChoice):
+	"""A base-class for all concurrent choices (in case...generate statements)."""
+
+
+@export
+class IndexedGenerateChoice(ConcurrentChoice):
+	_expression: ExpressionUnion
+
+	def __init__(self, expression: ExpressionUnion, parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+
+		self._expression = expression
+		expression._parent = self
+
+	@property
+	def Expression(self) -> ExpressionUnion:
+		return self._expression
+
+	def __str__(self) -> str:
+		return str(self._expression)
+
+
+@export
+class RangedGenerateChoice(ConcurrentChoice):
+	_range: 'Range'
+
+	def __init__(self, rng: 'Range', parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+
+		self._range = rng
+		rng._parent = self
+
+	@property
+	def Range(self) -> 'Range':
+		return self._range
+
+	def __str__(self) -> str:
+		return str(self._range)
+
+
+@export
+class ConcurrentCase(BaseCase, LabeledEntityMixin, ConcurrentDeclarationRegionMixin, ConcurrentStatementsMixin):
+	def __init__(
+		self,
+		declaredItems: Nullable[Iterable] = None,
+		statements: Nullable[Iterable[ConcurrentStatement]] = None,
+		alternativeLabel: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(parent)
+		LabeledEntityMixin.__init__(self, alternativeLabel)
+		ConcurrentDeclarationRegionMixin.__init__(self, declaredItems)
+		ConcurrentStatementsMixin.__init__(self, statements)
+
+
+@export
+class GenerateCase(ConcurrentCase):
+	_choices: List[ConcurrentChoice]
+
+	def __init__(
+		self,
+		choices: Iterable[ConcurrentChoice],
+		declaredItems: Nullable[Iterable] = None,
+		statements: Nullable[Iterable[ConcurrentStatement]] = None,
+		alternativeLabel: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(declaredItems, statements, alternativeLabel, parent)
+
+		# TODO: move to parent or grandparent
+		self._choices = []
+		if choices is not None:
+			for choice in choices:
+				self._choices.append(choice)
+				choice._parent = self
+
+	# TODO: move to parent or grandparent
+	@property
+	def Choices(self) -> List[ConcurrentChoice]:
+		return self._choices
+
+	def __str__(self) -> str:
+		return "when {choices} =>".format(choices=" | ".join(str(c) for c in self._choices))
+
+
+@export
+class OthersGenerateCase(ConcurrentCase):
+	def __str__(self) -> str:
+		return "when others =>"
+
+
+@export
+class CaseGenerateStatement(GenerateStatement):
+	"""
+	Represents a case...generate statement.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      gen: case selector generate
+	        case choice1 =>
+	          -- ...
+	        case choice2 =>
+	          -- ...
+	        case others =>
+	          -- ...
+	      end generate;
+	"""
+
+	_expression: ExpressionUnion
+	_cases:      List[GenerateCase]
+
+	def __init__(
+		self,
+		label: str,
+		expression: ExpressionUnion,
+		cases: Iterable[ConcurrentCase],
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(label, parent)
+
+		self._expression = expression
+		expression._parent = self
+
+		# TODO: create a mixin for things with cases
+		self._cases = []
+		if cases is not None:
+			for case in cases:
+				self._cases.append(case)
+				case._parent = self
+
+	@property
+	def SelectExpression(self) -> ExpressionUnion:
+		return self._expression
+
+	@property
+	def Cases(self) -> List[GenerateCase]:
+		return self._cases
+
+	def IterateInstantiations(self) -> Generator[Instantiation, None, None]:
+		for case in self._cases:
+			yield from case.IterateInstantiations()
+
+	def IndexStatement(self) -> None:
+		for case in self._cases:
+			case.IndexStatements()
+
+
+@export
+class ForGenerateStatement(GenerateStatement, ConcurrentDeclarationRegionMixin, ConcurrentStatementsMixin):
+	"""
+	Represents a for...generate statement.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      gen: for i in 0 to 3 generate
+	        -- ...
+	      end generate;
+	"""
+
+	_loopIndex: str
+	_range:     Range
+
+	def __init__(
+		self,
+		label: str,
+		loopIndex: str,
+		rng: Range,
+		declaredItems: Nullable[Iterable] = None,
+		statements: Nullable[Iterable[ConcurrentStatement]] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(label, parent)
+		ConcurrentDeclarationRegionMixin.__init__(self, declaredItems)
+		ConcurrentStatementsMixin.__init__(self, statements)
+
+		self._loopIndex = loopIndex
+
+		self._range = rng
+		rng._parent = self
+
+	@property
+	def LoopIndex(self) -> str:
+		return self._loopIndex
+
+	@property
+	def Range(self) -> Range:
+		return self._range
+
+	# IndexDeclaredItems = ConcurrentStatements.IndexDeclaredItems
+
+	def IndexStatement(self) -> None:
+		self.IndexStatements()
+
+	def IndexStatements(self) -> None:
+		super().IndexStatements()
+
+	def IterateInstantiations(self) -> Generator[Instantiation, None, None]:
+		return ConcurrentStatementsMixin.IterateInstantiations(self)
+
+
+@export
+class ConcurrentSignalAssignment(ConcurrentStatement, SignalAssignmentMixin):
+	"""
+	A base-class for concurrent signal assignments.
+
+	.. seealso::
+
+	   * :class:`~pyVHDLModel.Concurrent.ConcurrentSimpleSignalAssignment`
+	   * :class:`~pyVHDLModel.Concurrent.ConcurrentSelectedSignalAssignment`
+	   * :class:`~pyVHDLModel.Concurrent.ConcurrentConditionalSignalAssignment`
+	"""
+	def __init__(self, label: str, target: Name, parent: ModelEntity = None) -> None:
+		super().__init__(label, parent)
+		SignalAssignmentMixin.__init__(self, target)
+
+
+@export
+class ConcurrentSimpleSignalAssignment(ConcurrentSignalAssignment):
+	_waveform: List[WaveformElement]
+
+	def __init__(self, label: str, target: Name, waveform: Iterable[WaveformElement], parent: ModelEntity = None) -> None:
+		super().__init__(label, target, parent)
+
+		# TODO: extract to mixin
+		self._waveform = []
+		if waveform is not None:
+			for waveformElement in waveform:
+				self._waveform.append(waveformElement)
+				waveformElement._parent = self
+
+	@property
+	def Waveform(self) -> List[WaveformElement]:
+		return self._waveform
+
+
+@export
+class ConcurrentSelectedSignalAssignment(ConcurrentSignalAssignment):
+	def __init__(self, label: str, target: Name, expression: ExpressionUnion, parent: ModelEntity = None) -> None:
+		super().__init__(label, target, parent)
+
+
+@export
+class ConcurrentConditionalSignalAssignment(ConcurrentSignalAssignment):
+	def __init__(self, label: str, target: Name, expression: ExpressionUnion, parent: ModelEntity = None) -> None:
+		super().__init__(label, target, parent)
+
+
+@export
+class ConcurrentAssertStatement(ConcurrentStatement, AssertStatementMixin):
+	def __init__(
+		self,
+		condition: ExpressionUnion,
+		message: ExpressionUnion,
+		severity: Nullable[ExpressionUnion] = None,
+		label: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(label, parent)
+		AssertStatementMixin.__init__(self, condition, message, severity)
+
+ + diff --git a/typing/html/pyVHDLModel/Declaration.py.html b/typing/html/pyVHDLModel/Declaration.py.html new file mode 100644 index 000000000..0d404c3a2 --- /dev/null +++ b/typing/html/pyVHDLModel/Declaration.py.html @@ -0,0 +1,407 @@ + + + + + + +

pyVHDLModel.Declaration

+ + + + + + +
pyVHDLModel/Declaration.py
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+
# ==================================================================================================================== #
+#             __     ___   _ ____  _     __  __           _      _                                                     #
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |                                                    #
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |                                                    #
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |                                                    #
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|                                                    #
+#  |_|    |___/                                                                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""
+This module contains parts of an abstract document language model for VHDL.
+
+
+"""
+from enum                   import unique, Enum
+from typing                 import List, Iterable, Union, Optional as Nullable
+
+from pyTooling.Decorators   import export, readonly
+
+from pyVHDLModel.Base       import ModelEntity, NamedEntityMixin, DocumentedEntityMixin
+from pyVHDLModel.Expression import BaseExpression, QualifiedExpression, FunctionCall, TypeConversion, Literal
+from pyVHDLModel.Name       import Name
+from pyVHDLModel.Symbol     import Symbol
+
+
+
+ExpressionUnion = Union[
+	BaseExpression,
+	QualifiedExpression,
+	FunctionCall,
+	TypeConversion,
+	# ConstantOrSymbol,     TODO: ObjectSymbol
+	Literal,
+]
+
+
+@export
+@unique
+class EntityClass(Enum):
+	"""An ``EntityClass`` is an enumeration. It represents a VHDL language entity class (``entity``, ``label``, ...)."""
+
+	Entity =        0   #: Entity
+	Architecture =  1   #: Architecture
+	Configuration = 2   #: Configuration
+	Procedure =     3   #: Procedure
+	Function =      4   #: Function
+	Package =       5   #: Package
+	Type =          6   #: Type
+	Subtype =       7   #: Subtype
+	Constant =      8   #: Constant
+	Signal =        9   #: Signal
+	Variable =      10  #: Variable
+	Component =     11  #: Component
+	Label =         12  #: Label
+	Literal =       13  #: Literal
+	Units =         14  #: Units
+	Group =         15  #: Group
+	File =          16  #: File
+	Property =      17  #: Property
+	Sequence =      18  #: Sequence
+	View =          19  #: View
+	Others =        20  #: Others
+
+
+@export
+class Attribute(ModelEntity, NamedEntityMixin, DocumentedEntityMixin):
+	"""
+	Represents an attribute declaration.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      attribute TotalBits : natural;
+	"""
+
+	_subtype: Symbol
+
+	def __init__(
+		self,
+		identifier: str,
+		subtype: Symbol,
+		documentation: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(parent)
+		NamedEntityMixin.__init__(self, identifier)
+		DocumentedEntityMixin.__init__(self, documentation)
+
+		self._subtype = subtype
+		subtype._parent = self
+
+	@readonly
+	def Subtype(self) -> None:
+		return self._subtype
+
+
+@export
+class AttributeSpecification(ModelEntity, DocumentedEntityMixin):
+	"""
+	Represents an attribute specification.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      attribute TotalBits of BusType : subtype is 32;
+	"""
+
+	_identifiers: List[Name]
+	_attribute: Name
+	_entityClass: EntityClass
+	_expression: ExpressionUnion
+
+	def __init__(
+		self,
+		identifiers: Iterable[Name],
+		attribute: Name,
+		entityClass: EntityClass,
+		expression: ExpressionUnion,
+		documentation: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(parent)
+		DocumentedEntityMixin.__init__(self, documentation)
+
+		self._identifiers = []  # TODO: convert to dict
+		for identifier in identifiers:
+			self._identifiers.append(identifier)
+			identifier._parent = self
+
+		self._attribute = attribute
+		attribute._parent = self
+
+		self._entityClass = entityClass
+
+		self._expression = expression
+		expression._parent = self
+
+	@readonly
+	def Identifiers(self) -> List[Name]:
+		return self._identifiers
+
+	@readonly
+	def Attribute(self) -> Name:
+		return self._attribute
+
+	@readonly
+	def EntityClass(self) -> EntityClass:
+		return self._entityClass
+
+	@readonly
+	def Expression(self) -> ExpressionUnion:
+		return self._expression
+
+
+# TODO: move somewhere else
+@export
+class Alias(ModelEntity, NamedEntityMixin, DocumentedEntityMixin):
+	def __init__(self, identifier: str, documentation: Nullable[str] = None, parent: ModelEntity = None) -> None:
+		"""
+		Initializes underlying ``BaseType``.
+
+		:param identifier: Name of the type.
+		"""
+		super().__init__(parent)
+		NamedEntityMixin.__init__(self, identifier)
+		DocumentedEntityMixin.__init__(self, documentation)
+
+ + diff --git a/typing/html/pyVHDLModel/DesignUnit.py.html b/typing/html/pyVHDLModel/DesignUnit.py.html new file mode 100644 index 000000000..f68566813 --- /dev/null +++ b/typing/html/pyVHDLModel/DesignUnit.py.html @@ -0,0 +1,1647 @@ + + + + + + +

pyVHDLModel.DesignUnit

+ + + + + + +
pyVHDLModel/DesignUnit.py
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+
# ==================================================================================================================== #
+#             __     ___   _ ____  _     __  __           _      _                                                     #
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |                                                    #
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |                                                    #
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |                                                    #
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|                                                    #
+#  |_|    |___/                                                                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""
+This module contains parts of an abstract document language model for VHDL.
+
+Design units are contexts, entities, architectures, packages and their bodies as well as configurations.
+"""
+from typing import List, Dict, Union, Iterable, Optional as Nullable
+
+from pyTooling.Decorators   import export, readonly
+from pyTooling.MetaClasses  import ExtendedType
+from pyTooling.Graph        import Vertex
+
+from pyVHDLModel.Exception  import VHDLModelException
+from pyVHDLModel.Base       import ModelEntity, NamedEntityMixin, DocumentedEntityMixin
+from pyVHDLModel.Namespace  import Namespace
+from pyVHDLModel.Regions    import ConcurrentDeclarationRegionMixin
+from pyVHDLModel.Symbol     import Symbol, PackageSymbol, EntitySymbol, LibraryReferenceSymbol
+from pyVHDLModel.Interface  import GenericInterfaceItemMixin, PortInterfaceItemMixin
+from pyVHDLModel.Object     import DeferredConstant
+from pyVHDLModel.Concurrent import ConcurrentStatement, ConcurrentStatementsMixin
+
+
+@export
+class Reference(ModelEntity):
+	"""
+	A base-class for all references.
+
+	.. seealso::
+
+	   * :class:`~pyVHDLModel.DesignUnit.LibraryClause`
+	   * :class:`~pyVHDLModel.DesignUnit.UseClause`
+	   * :class:`~pyVHDLModel.DesignUnit.ContextReference`
+	"""
+
+	_symbols:       List[Symbol]
+
+	def __init__(self, symbols: Iterable[Symbol], parent: ModelEntity = None) -> None:
+		"""
+		Initializes a reference by taking a list of symbols and a parent reference.
+
+		:param symbols: A list of symbols this reference references to.
+		:param parent:  Reference to the logical parent in the model hierarchy.
+		"""
+		super().__init__(parent)
+
+		self._symbols = [s for s in symbols]
+
+	@readonly
+	def Symbols(self) -> List[Symbol]:
+		"""
+		Read-only property to access the symbols this reference references to (:attr:`_symbols`).
+
+		:returns: A list of symbols.
+		"""
+		return self._symbols
+
+
+@export
+class LibraryClause(Reference):
+	"""
+	Represents a library clause.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      library std, ieee;
+	"""
+
+	@readonly
+	def Symbols(self) -> List[LibraryReferenceSymbol]:
+		"""
+		Read-only property to access the symbols this library clause references to (:attr:`_symbols`).
+
+		:returns: A list of library reference symbols.
+		"""
+		return self._symbols
+
+
+@export
+class UseClause(Reference):
+	"""
+	Represents a use clause.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      use std.text_io.all, ieee.numeric_std.all;
+	"""
+
+
+@export
+class ContextReference(Reference):
+	"""
+	Represents a context reference.
+
+	.. hint:: It's called *context reference* not *context clause* by the LRM.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      context ieee.ieee_std_context;
+	"""
+
+
+ContextUnion = Union[
+	LibraryClause,
+	UseClause,
+	ContextReference
+]
+
+
+@export
+class DesignUnitWithContextMixin(metaclass=ExtendedType, mixin=True):
+	"""
+	A mixin-class for all design units with a context.
+	"""
+
+
+@export
+class DesignUnit(ModelEntity, NamedEntityMixin, DocumentedEntityMixin):
+	"""
+	A base-class for all design units.
+
+	.. seealso::
+
+	   * :class:`Primary design units <pyVHDLModel.DesignUnit.PrimaryUnit>`
+
+	     * :class:`~pyVHDLModel.DesignUnit.Context`
+	     * :class:`~pyVHDLModel.DesignUnit.Entity`
+	     * :class:`~pyVHDLModel.DesignUnit.Package`
+	     * :class:`~pyVHDLModel.DesignUnit.Configuration`
+
+	   * :class:`Secondary design units <pyVHDLModel.DesignUnit.SecondaryUnit>`
+
+	     * :class:`~pyVHDLModel.DesignUnit.Architecture`
+	     * :class:`~pyVHDLModel.DesignUnit.PackageBody`
+	"""
+
+	_document: 'Document'                                  #: The VHDL library, the design unit was analyzed into.
+
+	# Either written as statements before (e.g. entity, architecture, package, ...), or as statements inside (context)
+	_contextItems:        List['ContextUnion']             #: List of all context items (library, use and context clauses).
+	_libraryReferences:   List['LibraryClause']            #: List of library clauses.
+	_packageReferences:   List['UseClause']                #: List of use clauses.
+	_contextReferences:   List['ContextReference']         #: List of context clauses.
+
+	_referencedLibraries: Dict[str, 'Library']             #: Referenced libraries based on explicit library clauses or implicit inheritance
+	_referencedPackages:  Dict[str, Dict[str, 'Package']]  #: Referenced packages based on explicit use clauses or implicit inheritance
+	_referencedContexts:  Dict[str, 'Context']             #: Referenced contexts based on explicit context references or implicit inheritance
+
+	_dependencyVertex:    Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]  #: Reference to the vertex in the dependency graph representing the design unit. |br| This reference is set by :meth:`~pyVHDLModel.Design.CreateDependencyGraph`.
+	_hierarchyVertex:     Vertex[None, None, str, 'DesignUnit', None, None, None, None, None, None, None, None, None, None, None, None, None]  #: The vertex in the hierarchy graph
+
+	_namespace:           'Namespace'
+
+	def __init__(self, identifier: str, contextItems: Nullable[Iterable[ContextUnion]] = None, documentation: Nullable[str] = None, parent: ModelEntity = None) -> None:
+		"""
+		Initializes a design unit.
+
+		:param identifier:    Identifier (name) of the design unit.
+		:param contextItems:  A sequence of library, use or context clauses.
+		:param documentation: Associated documentation of the design unit.
+		:param parent:        Reference to the logical parent in the model hierarchy.
+		"""
+		super().__init__(parent)
+		NamedEntityMixin.__init__(self, identifier)
+		DocumentedEntityMixin.__init__(self, documentation)
+
+		self._document = None
+
+		self._contextItems = []
+		self._libraryReferences = []
+		self._packageReferences = []
+		self._contextReferences = []
+
+		if contextItems is not None:
+			for item in contextItems:
+				self._contextItems.append(item)
+				if isinstance(item, UseClause):
+					self._packageReferences.append(item)
+				elif isinstance(item, LibraryClause):
+					self._libraryReferences.append(item)
+				elif isinstance(item, ContextReference):
+					self._contextReferences.append(item)
+
+		self._referencedLibraries = {}
+		self._referencedPackages = {}
+		self._referencedContexts = {}
+
+		self._dependencyVertex = None
+		self._hierarchyVertex = None
+
+		self._namespace = Namespace(self._normalizedIdentifier)
+
+	@readonly
+	def Document(self) -> 'Document':
+		return self._document
+
+	@Document.setter
+	def Document(self, document: 'Document') -> None:
+		self._document = document
+
+	@property
+	def Library(self) -> 'Library':
+		return self._parent
+
+	@Library.setter
+	def Library(self, library: 'Library') -> None:
+		self._parent = library
+
+	@property
+	def ContextItems(self) -> List['ContextUnion']:
+		"""
+		Read-only property to access the sequence of all context items comprising library, use and context clauses
+		(:attr:`_contextItems`).
+
+		:returns: Sequence of context items.
+		"""
+		return self._contextItems
+
+	@property
+	def ContextReferences(self) -> List['ContextReference']:
+		"""
+		Read-only property to access the sequence of context clauses (:attr:`_contextReferences`).
+
+		:returns: Sequence of context clauses.
+		"""
+		return self._contextReferences
+
+	@property
+	def LibraryReferences(self) -> List['LibraryClause']:
+		"""
+		Read-only property to access the sequence of library clauses (:attr:`_libraryReferences`).
+
+		:returns: Sequence of library clauses.
+		"""
+		return self._libraryReferences
+
+	@property
+	def PackageReferences(self) -> List['UseClause']:
+		"""
+		Read-only property to access the sequence of use clauses (:attr:`_packageReferences`).
+
+		:returns: Sequence of use clauses.
+		"""
+		return self._packageReferences
+
+	@property
+	def ReferencedLibraries(self) -> Dict[str, 'Library']:
+		return self._referencedLibraries
+
+	@property
+	def ReferencedPackages(self) -> Dict[str, 'Package']:
+		return self._referencedPackages
+
+	@property
+	def ReferencedContexts(self) -> Dict[str, 'Context']:
+		return self._referencedContexts
+
+	@property
+	def DependencyVertex(self) -> Vertex:
+		"""
+		Read-only property to access the corresponding dependency vertex (:attr:`_dependencyVertex`).
+
+		The dependency vertex references this design unit by its value field.
+
+		:returns: The corresponding dependency vertex.
+		"""
+		return self._dependencyVertex
+
+	@property
+	def HierarchyVertex(self) -> Vertex:
+		"""
+		Read-only property to access the corresponding hierarchy vertex (:attr:`_hierarchyVertex`).
+
+		The hierarchy vertex references this design unit by its value field.
+
+		:returns: The corresponding hierarchy vertex.
+		"""
+		return self._hierarchyVertex
+
+
+@export
+class PrimaryUnit(DesignUnit):
+	"""
+	A base-class for all primary design units.
+
+	.. seealso::
+
+	   * :class:`~pyVHDLModel.DesignUnit.Context`
+	   * :class:`~pyVHDLModel.DesignUnit.Entity`
+	   * :class:`~pyVHDLModel.DesignUnit.Package`
+	   * :class:`~pyVHDLModel.DesignUnit.Configuration`
+	"""
+
+
+@export
+class SecondaryUnit(DesignUnit):
+	"""
+	A base-class for all secondary design units.
+
+	.. seealso::
+
+	   * :class:`~pyVHDLModel.DesignUnit.Architecture`
+	   * :class:`~pyVHDLModel.DesignUnit.PackageBody`
+	"""
+
+
+@export
+class Context(PrimaryUnit):
+	"""
+	Represents a context declaration.
+
+	A context contains a generic list of all its items (library clauses, use clauses and context references) in
+	:data:`_references`.
+
+	Furthermore, when a context gets initialized, the item kinds get separated into individual lists:
+
+	* :class:`~pyVHDLModel.DesignUnit.LibraryClause` |rarr| :data:`_libraryReferences`
+	* :class:`~pyVHDLModel.DesignUnit.UseClause` |rarr| :data:`_packageReferences`
+	* :class:`~pyVHDLModel.DesignUnit.ContextReference` |rarr| :data:`_contextReferences`
+
+	When :meth:`pyVHDLModel.Design.LinkContexts` got called, these lists were processed and the fields:
+
+	* :data:`_referencedLibraries` (:pycode:`Dict[libName, Library]`)
+	* :data:`_referencedPackages` (:pycode:`Dict[libName, [pkgName, Package]]`)
+	* :data:`_referencedContexts` (:pycode:`Dict[libName, [ctxName, Context]]`)
+
+	are populated.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      context ctx is
+	        -- ...
+	      end context;
+	"""
+
+	_references:        List[ContextUnion]
+
+	def __init__(self, identifier: str, references: Nullable[Iterable[ContextUnion]] = None, documentation: Nullable[str] = None, parent: ModelEntity = None) -> None:
+		super().__init__(identifier, None, documentation, parent)
+
+		self._references = []
+		self._libraryReferences = []
+		self._packageReferences = []
+		self._contextReferences = []
+
+		if references is not None:
+			for reference in references:
+				self._references.append(reference)
+				reference._parent = self
+
+				if isinstance(reference, LibraryClause):
+					self._libraryReferences.append(reference)
+				elif isinstance(reference, UseClause):
+					self._packageReferences.append(reference)
+				elif isinstance(reference, ContextReference):
+					self._contextReferences.append(reference)
+				else:
+					raise VHDLModelException()  # FIXME: needs exception message
+
+	@property
+	def LibraryReferences(self) -> List[LibraryClause]:
+		return self._libraryReferences
+
+	@property
+	def PackageReferences(self) -> List[UseClause]:
+		return self._packageReferences
+
+	@property
+	def ContextReferences(self) -> List[ContextReference]:
+		return self._contextReferences
+
+	def __str__(self) -> str:
+		lib = self._parent._identifier + "?" if self._parent is not None else ""
+
+		return f"Context: {lib}.{self._identifier}"
+
+
+@export
+class Package(PrimaryUnit, DesignUnitWithContextMixin, ConcurrentDeclarationRegionMixin):
+	"""
+	Represents a package declaration.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      package pkg is
+	        -- ...
+	      end package;
+	"""
+
+	_packageBody:       Nullable["PackageBody"]
+
+	_genericItems:      List[GenericInterfaceItemMixin]
+
+	_deferredConstants: Dict[str, DeferredConstant]
+	_components:        Dict[str, 'Component']
+
+	def __init__(
+		self,
+		identifier: str,
+		contextItems: Nullable[Iterable[ContextUnion]] = None,
+		genericItems: Nullable[Iterable[GenericInterfaceItemMixin]] = None,
+		declaredItems: Nullable[Iterable] = None,
+		documentation: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(identifier, contextItems, documentation, parent)
+		DesignUnitWithContextMixin.__init__(self)
+		ConcurrentDeclarationRegionMixin.__init__(self, declaredItems)
+
+		self._packageBody = None
+
+		# TODO: extract to mixin
+		self._genericItems = []  # TODO: convert to dict
+		if genericItems is not None:
+			for generic in genericItems:
+				self._genericItems.append(generic)
+				generic._parent = self
+
+		self._deferredConstants = {}
+		self._components = {}
+
+	@property
+	def PackageBody(self) -> Nullable["PackageBody"]:
+		return self._packageBody
+
+	@property
+	def GenericItems(self) -> List[GenericInterfaceItemMixin]:
+		return self._genericItems
+
+	@property
+	def DeclaredItems(self) -> List:
+		return self._declaredItems
+
+	@property
+	def DeferredConstants(self):
+		return self._deferredConstants
+
+	@property
+	def Components(self):
+		return self._components
+
+	def _IndexOtherDeclaredItem(self, item):
+		if isinstance(item, DeferredConstant):
+			for normalizedIdentifier in item.NormalizedIdentifiers:
+				self._deferredConstants[normalizedIdentifier] = item
+		elif isinstance(item, Component):
+			self._components[item.NormalizedIdentifier] = item
+		else:
+			super()._IndexOtherDeclaredItem(item)
+
+	def __str__(self) -> str:
+		lib = self._parent._identifier if self._parent is not None else "%"
+
+		return f"Package: '{lib}.{self._identifier}'"
+
+	def __repr__(self) -> str:
+		lib = self._parent._identifier if self._parent is not None else "%"
+
+		return f"{lib}.{self._identifier}"
+
+
+@export
+class PackageBody(SecondaryUnit, DesignUnitWithContextMixin, ConcurrentDeclarationRegionMixin):
+	"""
+	Represents a package body declaration.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      package body pkg is
+	        -- ...
+	      end package body;
+	"""
+
+	_package:       PackageSymbol
+
+	def __init__(
+		self,
+		packageSymbol: PackageSymbol,
+		contextItems: Nullable[Iterable[ContextUnion]] = None,
+		declaredItems: Nullable[Iterable] = None,
+		documentation: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(packageSymbol.Name.Identifier, contextItems, documentation, parent)
+		DesignUnitWithContextMixin.__init__(self)
+		ConcurrentDeclarationRegionMixin.__init__(self, declaredItems)
+
+		self._package = packageSymbol
+		packageSymbol._parent = self
+
+	@property
+	def Package(self) -> PackageSymbol:
+		return self._package
+
+	@property
+	def DeclaredItems(self) -> List:
+		return self._declaredItems
+
+	def LinkDeclaredItemsToPackage(self) -> None:
+		pass
+
+	def __str__(self) -> str:
+		lib = self._parent._identifier + "?" if self._parent is not None else ""
+
+		return f"Package Body: {lib}.{self._identifier}(body)"
+
+	def __repr__(self) -> str:
+		lib = self._parent._identifier + "?" if self._parent is not None else ""
+
+		return f"{lib}.{self._identifier}(body)"
+
+
+@export
+class Entity(PrimaryUnit, DesignUnitWithContextMixin, ConcurrentDeclarationRegionMixin, ConcurrentStatementsMixin):
+	"""
+	Represents an entity declaration.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      entity ent is
+	        -- ...
+	      end entity;
+	"""
+
+	_genericItems:  List[GenericInterfaceItemMixin]
+	_portItems:     List[PortInterfaceItemMixin]
+
+	_architectures: Dict[str, 'Architecture']
+
+	def __init__(
+		self,
+		identifier: str,
+		contextItems: Nullable[Iterable[ContextUnion]] = None,
+		genericItems: Nullable[Iterable[GenericInterfaceItemMixin]] = None,
+		portItems: Nullable[Iterable[PortInterfaceItemMixin]] = None,
+		declaredItems: Nullable[Iterable] = None,
+		statements: Nullable[Iterable[ConcurrentStatement]] = None,
+		documentation: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(identifier, contextItems, documentation, parent)
+		DesignUnitWithContextMixin.__init__(self)
+		ConcurrentDeclarationRegionMixin.__init__(self, declaredItems)
+		ConcurrentStatementsMixin.__init__(self, statements)
+
+		# TODO: extract to mixin
+		self._genericItems = []
+		if genericItems is not None:
+			for item in genericItems:
+				self._genericItems.append(item)
+				item._parent = self
+
+		# TODO: extract to mixin
+		self._portItems = []
+		if portItems is not None:
+			for item in portItems:
+				self._portItems.append(item)
+				item._parent = self
+
+		self._architectures = {}
+
+	# TODO: extract to mixin for generics
+	@property
+	def GenericItems(self) -> List[GenericInterfaceItemMixin]:
+		return self._genericItems
+
+	# TODO: extract to mixin for ports
+	@property
+	def PortItems(self) -> List[PortInterfaceItemMixin]:
+		return self._portItems
+
+	@property
+	def Architectures(self) -> Dict[str, 'Architecture']:
+		return self._architectures
+
+	def __str__(self) -> str:
+		lib = self._parent._identifier if self._parent is not None else "%"
+		archs = ', '.join(self._architectures.keys()) if self._architectures else "%"
+
+		return f"Entity: '{lib}.{self._identifier}({archs})'"
+
+	def __repr__(self) -> str:
+		lib = self._parent._identifier if self._parent is not None else "%"
+		archs = ', '.join(self._architectures.keys()) if self._architectures else "%"
+
+		return f"{lib}.{self._identifier}({archs})"
+
+
+@export
+class Architecture(SecondaryUnit, DesignUnitWithContextMixin, ConcurrentDeclarationRegionMixin, ConcurrentStatementsMixin):
+	"""
+	Represents an architecture declaration.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      architecture rtl of ent is
+	        -- ...
+	      begin
+	        -- ...
+	      end architecture;
+	"""
+
+	_entity: EntitySymbol
+
+	def __init__(
+		self,
+		identifier: str,
+		entity: EntitySymbol,
+		contextItems: Nullable[Iterable[Context]] = None,
+		declaredItems: Nullable[Iterable] = None,
+		statements: Iterable['ConcurrentStatement'] = None,
+		documentation: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(identifier, contextItems, documentation, parent)
+		DesignUnitWithContextMixin.__init__(self)
+		ConcurrentDeclarationRegionMixin.__init__(self, declaredItems)
+		ConcurrentStatementsMixin.__init__(self, statements)
+
+		self._entity = entity
+		entity._parent = self
+
+	@property
+	def Entity(self) -> EntitySymbol:
+		return self._entity
+
+	def __str__(self) -> str:
+		lib = self._parent._identifier if self._parent is not None else "%"
+		ent = self._entity._name._identifier if self._entity is not None else "%"
+
+		return f"Architecture: {lib}.{ent}({self._identifier})"
+
+	def __repr__(self) -> str:
+		lib = self._parent._identifier if self._parent is not None else "%"
+		ent = self._entity._name._identifier if self._entity is not None else "%"
+
+		return f"{lib}.{ent}({self._identifier})"
+
+
+@export
+class Component(ModelEntity, NamedEntityMixin, DocumentedEntityMixin):
+	"""
+	Represents a configuration declaration.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      component ent is
+	        -- ...
+	      end component;
+	"""
+
+	_genericItems:      List[GenericInterfaceItemMixin]
+	_portItems:         List[PortInterfaceItemMixin]
+
+	_entity:            Nullable[Entity]
+
+	def __init__(
+		self,
+		identifier: str,
+		genericItems: Nullable[Iterable[GenericInterfaceItemMixin]] = None,
+		portItems: Nullable[Iterable[PortInterfaceItemMixin]] = None,
+		documentation: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(parent)
+		NamedEntityMixin.__init__(self, identifier)
+		DocumentedEntityMixin.__init__(self, documentation)
+
+		# TODO: extract to mixin
+		self._genericItems = []
+		if genericItems is not None:
+			for item in genericItems:
+				self._genericItems.append(item)
+				item._parent = self
+
+		# TODO: extract to mixin
+		self._portItems = []
+		if portItems is not None:
+			for item in portItems:
+				self._portItems.append(item)
+				item._parent = self
+
+	@property
+	def GenericItems(self) -> List[GenericInterfaceItemMixin]:
+		return self._genericItems
+
+	@property
+	def PortItems(self) -> List[PortInterfaceItemMixin]:
+		return self._portItems
+
+	@property
+	def Entity(self) -> Nullable[Entity]:
+		return self._entity
+
+	@Entity.setter
+	def Entity(self, value: Entity) -> None:
+		self._entity = value
+
+
+@export
+class Configuration(PrimaryUnit, DesignUnitWithContextMixin):
+	"""
+	Represents a configuration declaration.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      configuration cfg of ent is
+	        for rtl
+	          -- ...
+	        end for;
+	      end configuration;
+	"""
+
+	def __init__(
+		self,
+		identifier: str,
+		contextItems: Nullable[Iterable[Context]] = None,
+		documentation: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(identifier, contextItems, documentation, parent)
+		DesignUnitWithContextMixin.__init__(self)
+
+	def __str__(self) -> str:
+		lib = self._parent._identifier if self._parent is not None else "%"
+
+		return f"Configuration: {lib}.{self._identifier}"
+
+	def __repr__(self) -> str:
+		lib = self._parent._identifier if self._parent is not None else "%"
+
+		return f"{lib}.{self._identifier}"
+
+ + diff --git a/typing/html/pyVHDLModel/Exception.py.html b/typing/html/pyVHDLModel/Exception.py.html new file mode 100644 index 000000000..419f332f3 --- /dev/null +++ b/typing/html/pyVHDLModel/Exception.py.html @@ -0,0 +1,757 @@ + + + + + + +

pyVHDLModel.Exception

+ + + + + + +
pyVHDLModel/Exception.py
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+
# ==================================================================================================================== #
+#             __     ___   _ ____  _     __  __           _      _                                                     #
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |                                                    #
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |                                                    #
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |                                                    #
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|                                                    #
+#  |_|    |___/                                                                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""
+This module contains parts of an abstract document language model for VHDL.
+
+The module ``Exceptions`` contains all structured errors that are raised by pyVHDLModel. Besides a default error
+message in english, each exception object contains one or multiple references to the exception's context.
+"""
+from sys    import version_info
+from typing import List
+
+from pyTooling.Decorators import export, readonly
+
+from pyVHDLModel.Symbol import Symbol
+
+
+@export
+class VHDLModelException(Exception):
+	"""Base-class for all exceptions (errors) raised by pyVHDLModel."""
+
+	# WORKAROUND: for Python <3.11
+	# Implementing a dummy method for Python versions before
+	__notes__: List[str]
+	if version_info < (3, 11):  # pragma: no cover
+		def add_note(self, message: str) -> None:
+			try:
+				self.__notes__.append(message)
+			except AttributeError:
+				self.__notes__ = [message]
+
+
+@export
+class LibraryExistsInDesignError(VHDLModelException):
+	"""
+	This exception is raised, when the library is already existing in the design.
+
+	Message: :pycode:`f"Library '{library._identifier}' already exists in design."`
+	"""
+
+	_library: 'Library'
+
+	def __init__(self, library: 'Library') -> None:
+		"""
+		Initializes the exception message based on given library object.
+
+		:param library: The library that already exists in the design.
+		"""
+		super().__init__(f"Library '{library._identifier}' already exists in design.")
+		self._library = library
+
+	@readonly
+	def Library(self) -> 'Library':
+		"""
+		Read-only property to access the duplicate library (:attr:`_library`).
+
+		:returns: Duplicate library (by name).
+		"""
+		return self._library
+
+
+@export
+class LibraryRegisteredToForeignDesignError(VHDLModelException):
+	"""
+	This exception is raised, when the library is already registered to a foreign design.
+
+	Message: :pycode:`f"Library '{library._identifier}' already registered in design '{library.Parent}'."`
+	"""
+
+	_library: 'Library'
+
+	def __init__(self, library: 'Library') -> None:
+		"""
+		Initializes the exception message based on given library object.
+
+		:param library: The library that is already registered to another design.
+		"""
+		super().__init__(f"Library '{library._identifier}' already registered in design '{library.Parent}'.")
+		self._library = library
+
+	@readonly
+	def Library(self) -> 'Library':
+		return self._library
+
+
+@export
+class LibraryNotRegisteredError(VHDLModelException):
+	"""
+	This exception is raised, when the library is not registered in the design.
+
+	Message: :pycode:`f"Library '{library._identifier}' is not registered in the design."`
+	"""
+
+	_library: 'Library'
+
+	def __init__(self, library: 'Library') -> None:
+		"""
+		Initializes the exception message based on given library object.
+
+		:param library: The library that isn't registered in the design.
+		"""
+		super().__init__(f"Library '{library._identifier}' is not registered in the design.")
+		self._library = library
+
+	@readonly
+	def Library(self) -> 'Library':
+		return self._library
+
+
+@export
+class EntityExistsInLibraryError(VHDLModelException):
+	"""
+	This exception is raised, when the entity already existing in the library.
+
+	Message: :pycode:`f"Entity '{entity._identifier}' already exists in library '{library._identifier}'."`
+	"""
+
+	_library: 'Library'
+	_entity: 'Entity'
+
+	def __init__(self, entity: 'Entity', library: 'Library') -> None:
+		"""
+		Initializes the exception message based on given entity and library objects.
+
+		:param entity:  The entity that already exists in the library.
+		:param library: The library that already contains the entity.
+		"""
+		super().__init__(f"Entity '{entity._identifier}' already exists in library '{library._identifier}'.")
+		self._library = library
+		self._entity = entity
+
+	@readonly
+	def Library(self) -> 'Library':
+		return self._library
+
+	@readonly
+	def Entity(self) -> 'Entity':
+		return self._entity
+
+
+@export
+class ArchitectureExistsInLibraryError(VHDLModelException):
+	"""
+	This exception is raised, when the architecture already existing in the library.
+
+	Message: :pycode:`f"Architecture '{architecture._identifier}' for entity '{entity._identifier}' already exists in library '{library._identifier}'."`
+	"""
+
+	_library: 'Library'
+	_entity: 'Entity'
+	_architecture: 'Architecture'
+
+	def __init__(self, architecture: 'Architecture', entity: 'Entity', library: 'Library') -> None:
+		"""
+		Initializes the exception message based on given architecture, entity and library objects.
+
+		:param architecture: The architecture that already exists in the library.
+		:param entity:       The entity the architecture refers to, which already exists in the library.
+		:param library:      The library that already contains the architecture.
+		"""
+		super().__init__(f"Architecture '{architecture._identifier}' for entity '{entity._identifier}' already exists in library '{library._identifier}'.")
+		self._library = library
+		self._entity = entity
+		self._architecture = architecture
+
+	@readonly
+	def Library(self) -> 'Library':
+		return self._library
+
+	@readonly
+	def Entity(self) -> 'Entity':
+		return self._entity
+
+	@readonly
+	def Architecture(self) -> 'Architecture':
+		return self._architecture
+
+
+@export
+class PackageExistsInLibraryError(VHDLModelException):
+	"""
+	This exception is raised, when the package already existing in the library.
+
+	Message: :pycode:`f"Package '{package._identifier}' already exists in library '{library._identifier}'."`
+	"""
+
+	_library: 'Library'
+	_package: 'Package'
+
+	def __init__(self, package: 'Package', library: 'Library') -> None:
+		"""
+		Initializes the exception message based on given package and library objects.
+
+		:param package: The package that already exists in the library.
+		:param library: The library that already contains the package.
+		"""
+		super().__init__(f"Package '{package._identifier}' already exists in library '{library._identifier}'.")
+		self._library = library
+		self._package = package
+
+	@readonly
+	def Library(self) -> 'Library':
+		return self._library
+
+	@readonly
+	def Package(self) -> 'Package':
+		return self._package
+
+
+@export
+class PackageBodyExistsError(VHDLModelException):
+	"""
+	This exception is raised, when the package body already existing in the library.
+
+	Message: :pycode:`f"Package body '{packageBody._identifier}' already exists in library '{library._identifier}'."`
+	"""
+
+	_library: 'Library'
+	_packageBody: 'PackageBody'
+
+	def __init__(self, packageBody: 'PackageBody', library: 'Library') -> None:
+		"""
+		Initializes the exception message based on given package body and library objects.
+
+		:param packageBody: The package body that already exists in the library.
+		:param library:     The library that already contains the package body.
+		"""
+		super().__init__(f"Package body '{packageBody._identifier}' already exists in library '{library._identifier}'.")
+		self._library = library
+		self._packageBody = packageBody
+
+	@readonly
+	def Library(self) -> 'Library':
+		return self._library
+
+	@property
+	def PackageBody(self) -> 'PackageBody':
+		return self._packageBody
+
+
+@export
+class ConfigurationExistsInLibraryError(VHDLModelException):
+	"""
+	This exception is raised, when the configuration already existing in the library.
+
+	Message: :pycode:`f"Configuration '{configuration._identifier}' already exists in library '{library._identifier}'."`
+	"""
+
+	_library: 'Library'
+	_configuration: 'Configuration'
+
+	def __init__(self, configuration: 'Configuration', library: 'Library') -> None:
+		"""
+		Initializes the exception message based on given configuration and library objects.
+
+		:param configuration: The configuration that already exists in the library.
+		:param library:       The library that already contains the configuration.
+		"""
+		super().__init__(f"Configuration '{configuration._identifier}' already exists in library '{library._identifier}'.")
+		self._library = library
+		self._configuration = configuration
+
+	@property
+	def Library(self) -> 'Library':
+		return self._library
+
+	@property
+	def Configuration(self) -> 'Configuration':
+		return self._configuration
+
+
+@export
+class ContextExistsInLibraryError(VHDLModelException):
+	"""
+	This exception is raised, when the context already existing in the library.
+
+	Message: :pycode:`f"Context '{context._identifier}' already exists in library '{library._identifier}'."`
+	"""
+
+	_library: 'Library'
+	_context: 'Context'
+
+	def __init__(self, context: 'Context', library: 'Library') -> None:
+		"""
+		Initializes the exception message based on given context and library objects.
+
+		:param context: The context that already exists in the library.
+		:param library: The library that already contains the context.
+		"""
+		super().__init__(f"Context '{context._identifier}' already exists in library '{library._identifier}'.")
+		self._library = library
+		self._context = context
+
+	@property
+	def Library(self) -> 'Library':
+		return self._library
+
+	@property
+	def Context(self) -> 'Context':
+		return self._context
+
+
+@export
+class ReferencedLibraryNotExistingError(VHDLModelException):
+	"""
+	This exception is raised, when a library is referenced by a `library clause`, but doesn't exist in the design.
+
+	Message: :pycode:`f"Library '{librarySymbol.Name._identifier}' referenced by library clause of context '{context._identifier}' doesn't exist in design."`
+	"""
+
+	_librarySymbol: Symbol
+	_context: 'Context'
+
+	def __init__(self, context: 'Context', librarySymbol: Symbol) -> None:
+		"""
+		Initializes the exception message based on given context and library objects.
+
+		:param context:       The context that already exists in the library.
+		:param librarySymbol: The library that already contains the context.
+		"""
+		super().__init__(f"Library '{librarySymbol.Name._identifier}' referenced by library clause of context '{context._identifier}' doesn't exist in design.")
+		self._librarySymbol = librarySymbol
+		self._context = context
+
+	@property
+	def LibrarySymbol(self) -> Symbol:
+		return self._librarySymbol
+
+	@property
+	def Context(self) -> 'Context':
+		return self._context
+
+ + diff --git a/typing/html/pyVHDLModel/Expression.py.html b/typing/html/pyVHDLModel/Expression.py.html new file mode 100644 index 000000000..7eee22308 --- /dev/null +++ b/typing/html/pyVHDLModel/Expression.py.html @@ -0,0 +1,1694 @@ + + + + + + +

pyVHDLModel.Expression

+ + + + + + +
pyVHDLModel/Expression.py
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+
# ==================================================================================================================== #
+#             __     ___   _ ____  _     __  __           _      _                                                     #
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |                                                    #
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |                                                    #
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |                                                    #
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|                                                    #
+#  |_|    |___/                                                                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""
+This module contains parts of an abstract document language model for VHDL.
+
+All declarations for literals, aggregates, operators forming an expressions.
+"""
+from typing               import Tuple, List, Iterable, Union
+
+from pyTooling.Decorators import export, readonly
+
+from pyVHDLModel.Base     import ModelEntity, Direction, Range
+from pyVHDLModel.Symbol   import Symbol
+
+
+ExpressionUnion = Union[
+	'BaseExpression',
+	'QualifiedExpression',
+	'FunctionCall',
+	'TypeConversion',
+	# ConstantOrSymbol,     TODO: ObjectSymbol
+	'Literal',
+]
+
+
+@export
+class BaseExpression(ModelEntity):
+	"""A ``BaseExpression`` is a base-class for all expressions."""
+
+
+@export
+class Literal(BaseExpression):
+	"""A ``Literal`` is a base-class for all literals."""
+
+
+@export
+class NullLiteral(Literal):
+	def __str__(self) -> str:
+		return "null"
+
+
+@export
+class EnumerationLiteral(Literal):
+	_value: str
+
+	def __init__(self, value: str, parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+
+		self._value = value
+
+	@readonly
+	def Value(self) -> str:
+		return self._value
+
+	def __str__(self) -> str:
+		return self._value
+
+
+@export
+class NumericLiteral(Literal):
+	"""A ``NumericLiteral`` is a base-class for all numeric literals."""
+
+
+@export
+class IntegerLiteral(NumericLiteral):
+	_value: int
+
+	def __init__(self, value: int) -> None:
+		super().__init__()
+		self._value = value
+
+	@readonly
+	def Value(self) -> int:
+		return self._value
+
+	def __str__(self) -> str:
+		return str(self._value)
+
+
+@export
+class FloatingPointLiteral(NumericLiteral):
+	_value: float
+
+	def __init__(self, value: float) -> None:
+		super().__init__()
+		self._value = value
+
+	@readonly
+	def Value(self) -> float:
+		return self._value
+
+	def __str__(self) -> str:
+		return str(self._value)
+
+
+@export
+class PhysicalLiteral(NumericLiteral):
+	_unitName: str
+
+	def __init__(self, unitName: str) -> None:
+		super().__init__()
+		self._unitName = unitName
+
+	@readonly
+	def UnitName(self) -> str:
+		return self._unitName
+
+	def __str__(self) -> str:
+		return f"{self._value} {self._unitName}"
+
+
+@export
+class PhysicalIntegerLiteral(PhysicalLiteral):
+	_value: int
+
+	def __init__(self, value: int, unitName: str) -> None:
+		super().__init__(unitName)
+		self._value = value
+
+	@readonly
+	def Value(self) -> int:
+		return self._value
+
+
+@export
+class PhysicalFloatingLiteral(PhysicalLiteral):
+	_value: float
+
+	def __init__(self, value: float, unitName: str) -> None:
+		super().__init__(unitName)
+		self._value = value
+
+	@readonly
+	def Value(self) -> float:
+		return self._value
+
+
+@export
+class CharacterLiteral(Literal):
+	_value: str
+
+	def __init__(self, value: str) -> None:
+		super().__init__()
+		self._value = value
+
+	@readonly
+	def Value(self) -> str:
+		return self._value
+
+	def __str__(self) -> str:
+		return str(self._value)
+
+
+@export
+class StringLiteral(Literal):
+	_value: str
+
+	def __init__(self, value: str) -> None:
+		super().__init__()
+		self._value = value
+
+	@readonly
+	def Value(self) -> str:
+		return self._value
+
+	def __str__(self) -> str:
+		return "\"" + self._value + "\""
+
+
+@export
+class BitStringLiteral(Literal):
+	_value: str
+
+	def __init__(self, value: str) -> None:
+		super().__init__()
+		self._value = value
+
+	@readonly
+	def Value(self) -> str:
+		return self._value
+
+	def __str__(self) -> str:
+		return "\"" + self._value + "\""
+
+
+@export
+class ParenthesisExpression: #(Protocol):
+	__slots__ = ()  # FIXME: use ExtendedType?
+
+	@readonly
+	def Operand(self) -> ExpressionUnion:
+		return None
+
+
+@export
+class UnaryExpression(BaseExpression):
+	"""A ``UnaryExpression`` is a base-class for all unary expressions."""
+
+	_FORMAT:  Tuple[str, str]
+	_operand: ExpressionUnion
+
+	def __init__(self, operand: ExpressionUnion, parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+
+		self._operand = operand
+		# operand._parent = self  # FIXME: operand is provided as None
+
+	@readonly
+	def Operand(self):
+		return self._operand
+
+	def __str__(self) -> str:
+		return f"{self._FORMAT[0]}{self._operand!s}{self._FORMAT[1]}"
+
+
+@export
+class NegationExpression(UnaryExpression):
+	_FORMAT = ("-", "")
+
+
+@export
+class IdentityExpression(UnaryExpression):
+	_FORMAT = ("+", "")
+
+
+@export
+class InverseExpression(UnaryExpression):
+	_FORMAT = ("not ", "")
+
+
+@export
+class UnaryAndExpression(UnaryExpression):
+	_FORMAT = ("and ", "")
+
+
+@export
+class UnaryNandExpression(UnaryExpression):
+	_FORMAT = ("nand ", "")
+
+
+@export
+class UnaryOrExpression(UnaryExpression):
+	_FORMAT = ("or ", "")
+
+
+@export
+class UnaryNorExpression(UnaryExpression):
+	_FORMAT = ("nor ", "")
+
+
+@export
+class UnaryXorExpression(UnaryExpression):
+	_FORMAT = ("xor ", "")
+
+
+@export
+class UnaryXnorExpression(UnaryExpression):
+	_FORMAT = ("xnor ", "")
+
+
+@export
+class AbsoluteExpression(UnaryExpression):
+	_FORMAT = ("abs ", "")
+
+
+@export
+class TypeConversion(UnaryExpression):
+	pass
+
+
+@export
+class SubExpression(UnaryExpression, ParenthesisExpression):
+	_FORMAT = ("(", ")")
+
+
+@export
+class BinaryExpression(BaseExpression):
+	"""A ``BinaryExpression`` is a base-class for all binary expressions."""
+
+	_FORMAT: Tuple[str, str, str]
+	_leftOperand:  ExpressionUnion
+	_rightOperand: ExpressionUnion
+
+	def __init__(self, leftOperand: ExpressionUnion, rightOperand: ExpressionUnion, parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+
+		self._leftOperand = leftOperand
+		leftOperand._parent = self
+
+		self._rightOperand = rightOperand
+		rightOperand._parent = self
+
+	@property
+	def LeftOperand(self):
+		return self._leftOperand
+
+	@property
+	def RightOperand(self):
+		return self._rightOperand
+
+	def __str__(self) -> str:
+		return "{leftOperator}{leftOperand!s}{middleOperator}{rightOperand!s}{rightOperator}".format(
+			leftOperator=self._FORMAT[0],
+			leftOperand=self._leftOperand,
+			middleOperator=self._FORMAT[1],
+			rightOperand=self._rightOperand,
+			rightOperator=self._FORMAT[2],
+		)
+
+
+@export
+class RangeExpression(BinaryExpression):
+	_direction: Direction
+
+	@property
+	def Direction(self) -> Direction:
+		return self._direction
+
+
+@export
+class AscendingRangeExpression(RangeExpression):
+	_direction = Direction.To
+	_FORMAT = ("", " to ", "")
+
+
+@export
+class DescendingRangeExpression(RangeExpression):
+	_direction = Direction.DownTo
+	_FORMAT = ("", " downto ", "")
+
+
+@export
+class AddingExpression(BinaryExpression):
+	"""A ``AddingExpression`` is a base-class for all adding expressions."""
+
+
+@export
+class AdditionExpression(AddingExpression):
+	_FORMAT = ("", " + ", "")
+
+
+@export
+class SubtractionExpression(AddingExpression):
+	_FORMAT = ("", " - ", "")
+
+
+@export
+class ConcatenationExpression(AddingExpression):
+	_FORMAT = ("", " & ", "")
+
+
+@export
+class MultiplyingExpression(BinaryExpression):
+	"""A ``MultiplyingExpression`` is a base-class for all multiplying expressions."""
+
+
+@export
+class MultiplyExpression(MultiplyingExpression):
+	_FORMAT = ("", " * ", "")
+
+
+@export
+class DivisionExpression(MultiplyingExpression):
+	_FORMAT = ("", " / ", "")
+
+
+@export
+class RemainderExpression(MultiplyingExpression):
+	_FORMAT = ("", " rem ", "")
+
+
+@export
+class ModuloExpression(MultiplyingExpression):
+	_FORMAT = ("", " mod ", "")
+
+
+@export
+class ExponentiationExpression(MultiplyingExpression):
+	_FORMAT = ("", "**", "")
+
+
+@export
+class LogicalExpression(BinaryExpression):
+	"""A ``LogicalExpression`` is a base-class for all logical expressions."""
+
+
+@export
+class AndExpression(LogicalExpression):
+	_FORMAT = ("", " and ", "")
+
+
+@export
+class NandExpression(LogicalExpression):
+	_FORMAT = ("", " nand ", "")
+
+
+@export
+class OrExpression(LogicalExpression):
+	_FORMAT = ("", " or ", "")
+
+
+@export
+class NorExpression(LogicalExpression):
+	_FORMAT = ("", " nor ", "")
+
+
+@export
+class XorExpression(LogicalExpression):
+	_FORMAT = ("", " xor ", "")
+
+
+@export
+class XnorExpression(LogicalExpression):
+	_FORMAT = ("", " xnor ", "")
+
+
+@export
+class RelationalExpression(BinaryExpression):
+	"""A ``RelationalExpression`` is a base-class for all shifting expressions."""
+
+
+@export
+class EqualExpression(RelationalExpression):
+	_FORMAT = ("", " = ", "")
+
+
+@export
+class UnequalExpression(RelationalExpression):
+	_FORMAT = ("", " /= ", "")
+
+
+@export
+class GreaterThanExpression(RelationalExpression):
+	_FORMAT = ("", " > ", "")
+
+
+@export
+class GreaterEqualExpression(RelationalExpression):
+	_FORMAT = ("", " >= ", "")
+
+
+@export
+class LessThanExpression(RelationalExpression):
+	_FORMAT = ("", " < ", "")
+
+
+@export
+class LessEqualExpression(RelationalExpression):
+	_FORMAT = ("", " <= ", "")
+
+
+@export
+class MatchingRelationalExpression(RelationalExpression):
+	pass
+
+
+@export
+class MatchingEqualExpression(MatchingRelationalExpression):
+	_FORMAT = ("", " ?= ", "")
+
+
+@export
+class MatchingUnequalExpression(MatchingRelationalExpression):
+	_FORMAT = ("", " ?/= ", "")
+
+
+@export
+class MatchingGreaterThanExpression(MatchingRelationalExpression):
+	_FORMAT = ("", " ?> ", "")
+
+
+@export
+class MatchingGreaterEqualExpression(MatchingRelationalExpression):
+	_FORMAT = ("", " ?>= ", "")
+
+
+@export
+class MatchingLessThanExpression(MatchingRelationalExpression):
+	_FORMAT = ("", " ?< ", "")
+
+
+@export
+class MatchingLessEqualExpression(MatchingRelationalExpression):
+	_FORMAT = ("", " ?<= ", "")
+
+
+@export
+class ShiftExpression(BinaryExpression):
+	"""A ``ShiftExpression`` is a base-class for all shifting expressions."""
+
+
+@export
+class ShiftLogicExpression(ShiftExpression):
+	pass
+
+
+@export
+class ShiftArithmeticExpression(ShiftExpression):
+	pass
+
+
+@export
+class RotateExpression(ShiftExpression):
+	pass
+
+
+@export
+class ShiftRightLogicExpression(ShiftLogicExpression):
+	_FORMAT = ("", " srl ", "")
+
+
+@export
+class ShiftLeftLogicExpression(ShiftLogicExpression):
+	_FORMAT = ("", " sll ", "")
+
+
+@export
+class ShiftRightArithmeticExpression(ShiftArithmeticExpression):
+	_FORMAT = ("", " sra ", "")
+
+
+@export
+class ShiftLeftArithmeticExpression(ShiftArithmeticExpression):
+	_FORMAT = ("", " sla ", "")
+
+
+@export
+class RotateRightExpression(RotateExpression):
+	_FORMAT = ("", " ror ", "")
+
+
+@export
+class RotateLeftExpression(RotateExpression):
+	_FORMAT = ("", " rol ", "")
+
+
+@export
+class QualifiedExpression(BaseExpression, ParenthesisExpression):
+	_operand:  ExpressionUnion
+	_subtype:  Symbol
+
+	def __init__(self, subtype: Symbol, operand: ExpressionUnion, parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+
+		self._operand = operand
+		operand._parent = self
+
+		self._subtype = subtype
+		subtype._parent = self
+
+	@property
+	def Operand(self):
+		return self._operand
+
+	@property
+	def Subtyped(self):
+		return self._subtype
+
+	def __str__(self) -> str:
+		return f"{self._subtype}'({self._operand!s})"
+
+
+@export
+class TernaryExpression(BaseExpression):
+	"""A ``TernaryExpression`` is a base-class for all ternary expressions."""
+
+	_FORMAT: Tuple[str, str, str, str]
+	_firstOperand:  ExpressionUnion
+	_secondOperand: ExpressionUnion
+	_thirdOperand:  ExpressionUnion
+
+	def __init__(self, parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+
+		# FIXME: parameters and initializers are missing !!
+
+	@property
+	def FirstOperand(self):
+		return self._firstOperand
+
+	@property
+	def SecondOperand(self):
+		return self._secondOperand
+
+	@property
+	def ThirdOperand(self):
+		return self._thirdOperand
+
+	def __str__(self) -> str:
+		return "{beforeFirstOperator}{firstOperand!s}{beforeSecondOperator}{secondOperand!s}{beforeThirdOperator}{thirdOperand!s}{lastOperator}".format(
+			beforeFirstOperator=self._FORMAT[0],
+			firstOperand=self._firstOperand,
+			beforeSecondOperator=self._FORMAT[1],
+			secondOperand=self._secondOperand,
+			beforeThirdOperator=self._FORMAT[2],
+			thirdOperand=self._thirdOperand,
+			lastOperator=self._FORMAT[4],
+		)
+
+
+@export
+class WhenElseExpression(TernaryExpression):
+	_FORMAT = ("", " when ", " else ", "")
+
+
+@export
+class FunctionCall(BaseExpression):
+	pass
+
+
+@export
+class Allocation(BaseExpression):
+	pass
+
+
+@export
+class SubtypeAllocation(Allocation):
+	_subtype: Symbol
+
+	def __init__(self, subtype: Symbol, parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+
+		self._subtype = subtype
+		subtype._parent = self
+
+	@property
+	def Subtype(self) -> Symbol:
+		return self._subtype
+
+	def __str__(self) -> str:
+		return f"new {self._subtype!s}"
+
+
+@export
+class QualifiedExpressionAllocation(Allocation):
+	_qualifiedExpression: QualifiedExpression
+
+	def __init__(self, qualifiedExpression: QualifiedExpression, parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+
+		self._qualifiedExpression = qualifiedExpression
+		qualifiedExpression._parent = self
+
+	@property
+	def QualifiedExpression(self) -> QualifiedExpression:
+		return self._qualifiedExpression
+
+	def __str__(self) -> str:
+		return f"new {self._qualifiedExpression!s}"
+
+
+@export
+class AggregateElement(ModelEntity):
+	"""A ``AggregateElement`` is a base-class for all aggregate elements."""
+
+	_expression: ExpressionUnion
+
+	def __init__(self, expression: ExpressionUnion, parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+
+		self._expression = expression
+		expression._parent = self
+
+	@property
+	def Expression(self):
+		return self._expression
+
+
+@export
+class SimpleAggregateElement(AggregateElement):
+	def __str__(self) -> str:
+		return str(self._expression)
+
+
+@export
+class IndexedAggregateElement(AggregateElement):
+	_index: int
+
+	def __init__(self, index: ExpressionUnion, expression: ExpressionUnion, parent: ModelEntity = None) -> None:
+		super().__init__(expression, parent)
+
+		self._index = index
+
+	@property
+	def Index(self) -> int:
+		return self._index
+
+	def __str__(self) -> str:
+		return f"{self._index!s} => {self._expression!s}"
+
+
+@export
+class RangedAggregateElement(AggregateElement):
+	_range: Range
+
+	def __init__(self, rng: Range, expression: ExpressionUnion, parent: ModelEntity = None) -> None:
+		super().__init__(expression, parent)
+
+		self._range = rng
+		rng._parent = self
+
+	@property
+	def Range(self) -> Range:
+		return self._range
+
+	def __str__(self) -> str:
+		return f"{self._range!s} => {self._expression!s}"
+
+
+@export
+class NamedAggregateElement(AggregateElement):
+	_name: Symbol
+
+	def __init__(self, name: Symbol, expression: ExpressionUnion, parent: ModelEntity = None) -> None:
+		super().__init__(expression, parent)
+
+		self._name = name
+		name._parent = self
+
+	@property
+	def Name(self) -> Symbol:
+		return self._name
+
+	def __str__(self) -> str:
+		return "{name!s} => {value!s}".format(
+			name=self._name,
+			value=self._expression,
+		)
+
+
+@export
+class OthersAggregateElement(AggregateElement):
+	def __str__(self) -> str:
+		return "others => {value!s}".format(
+			value=self._expression,
+		)
+
+
+@export
+class Aggregate(BaseExpression):
+	_elements: List[AggregateElement]
+
+	def __init__(self, elements: Iterable[AggregateElement], parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+
+		self._elements = []
+		for element in elements:
+			self._elements.append(element)
+			element._parent = self
+
+	@property
+	def Elements(self) -> List[AggregateElement]:
+		return self._elements
+
+	def __str__(self) -> str:
+		choices = [str(element) for element in self._elements]
+		return "({choices})".format(
+			choices=", ".join(choices)
+		)
+
+ + diff --git a/typing/html/pyVHDLModel/IEEE.py.html b/typing/html/pyVHDLModel/IEEE.py.html new file mode 100644 index 000000000..7a599a411 --- /dev/null +++ b/typing/html/pyVHDLModel/IEEE.py.html @@ -0,0 +1,929 @@ + + + + + + +

pyVHDLModel.IEEE

+ + + + + + +
pyVHDLModel/IEEE.py
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+
# ==================================================================================================================== #
+#             __     ___   _ ____  _     __  __           _      _                                                     #
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |                                                    #
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |                                                    #
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |                                                    #
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|                                                    #
+#  |_|    |___/                                                                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""This module contains library and package declarations for VHDL library ``IEEE``."""
+from pyTooling.Decorators   import export
+
+from pyVHDLModel.Expression import EnumerationLiteral
+from pyVHDLModel.Name       import SimpleName
+from pyVHDLModel.Predefined import PredefinedLibrary, PredefinedPackage, PredefinedPackageBody
+from pyVHDLModel.Symbol     import SimpleSubtypeSymbol
+from pyVHDLModel.Type       import EnumeratedType, ArrayType, Subtype
+
+
+@export
+class Ieee(PredefinedLibrary):
+	"""
+	Predefined VHDL library ``ieee``.
+
+	The following predefined packages are in this library:
+
+	* Math
+
+	  * :class:`~pyVHDLModel.IEEE.Math_Real`
+	  * :class:`~pyVHDLModel.IEEE.Math_Complex`
+
+	* Std_logic
+
+	  * :class:`~pyVHDLModel.IEEE.Std_Logic_1164`
+	  * :class:`~pyVHDLModel.IEEE.Std_Logic_TextIO`
+	  * :class:`~pyVHDLModel.IEEE.Std_Logic_Misc`
+
+	* Numeric
+
+	  * :class:`~pyVHDLModel.IEEE.Numeric_Bit`
+	  * :class:`~pyVHDLModel.IEEE.Numeric_Bit_Unsigned`
+	  * :class:`~pyVHDLModel.IEEE.Numeric_Std`
+	  * :class:`~pyVHDLModel.IEEE.Numeric_Std_Unsigned`
+
+	* Fixed/floating point
+
+	  * :class:`~pyVHDLModel.IEEE.Fixed_Float_Types`
+	  * :class:`~pyVHDLModel.IEEE.Fixed_Generic_Pkg`
+	  * :class:`~pyVHDLModel.IEEE.Fixed_Pkg`
+	  * :class:`~pyVHDLModel.IEEE.Float_Generic_Pkg`
+	  * :class:`~pyVHDLModel.IEEE.Float_Pkg`
+
+	.. seealso::
+
+	   Other predefined libraries:
+	     * Library :class:`~pyVHDLModel.STD.Std`
+	"""
+
+	def __init__(self) -> None:
+		super().__init__(PACKAGES)
+
+	def LoadSynopsysPackages(self) -> None:
+		self.AddPackages(PACKAGES_SYNOPSYS)
+
+
+
+@export
+class Math_Real(PredefinedPackage):
+	"""
+	Predefined package ``ieee.math_real``.
+	"""
+
+
+@export
+class Math_Real_Body(PredefinedPackageBody):
+	"""
+	Predefined package body of package ``ieee.math_real``.
+	"""
+
+
+@export
+class Math_Complex(PredefinedPackage):
+	"""
+	Predefined package ``ieee.math_complex``.
+	"""
+
+	def __init__(self) -> None:
+		super().__init__()
+
+		self._AddPackageClause(("work.math_real.all",))
+
+
+@export
+class Math_Complex_Body(PredefinedPackageBody):
+	"""
+	Predefined package body of package ``ieee.math_complex``.
+	"""
+
+	def __init__(self) -> None:
+		super().__init__()
+
+		self._AddPackageClause(("work.math_real.all",))
+
+
+@export
+class Std_logic_1164(PredefinedPackage):
+	"""
+	Predefined package ``ieee.std_logic_1164``.
+
+	Predefined types:
+
+	* ``std_ulogic``, ``std_ulogic_vector``
+	* ``std_logic``, ``std_logic_vector``
+	"""
+
+	def __init__(self) -> None:
+		super().__init__()
+
+		self._AddPackageClause(("STD.TEXTIO.all", ))
+
+		stdULogic = EnumeratedType("std_ulogic", (
+			EnumerationLiteral("U"),
+			EnumerationLiteral("X"),
+			EnumerationLiteral("0"),
+			EnumerationLiteral("1"),
+			EnumerationLiteral("Z"),
+			EnumerationLiteral("W"),
+			EnumerationLiteral("L"),
+			EnumerationLiteral("H"),
+			EnumerationLiteral("-"),
+		), None)
+		self._types[stdULogic._normalizedIdentifier] = stdULogic
+		self._declaredItems.append(stdULogic)
+
+		stdULogicVector = ArrayType("std_ulogic_vector", (SimpleSubtypeSymbol(SimpleName("natural")),), SimpleSubtypeSymbol(SimpleName("std_ulogic")), None)
+		self._types[stdULogicVector._normalizedIdentifier] = stdULogicVector
+		self._declaredItems.append(stdULogicVector)
+
+		stdLogic = Subtype("std_logic", SimpleSubtypeSymbol(SimpleName("std_ulogic")), None)
+		stdLogic._baseType = stdULogic
+		self._subtypes[stdLogic._normalizedIdentifier] = stdLogic
+		self._declaredItems.append(stdLogic)
+
+		stdLogicVector = Subtype("std_logic_vector", SimpleSubtypeSymbol(SimpleName("std_ulogic_vector")), None)
+		stdLogicVector._baseType = stdULogicVector
+		self._subtypes[stdLogicVector._normalizedIdentifier] = stdLogicVector
+		self._declaredItems.append(stdLogicVector)
+
+
+@export
+class Std_logic_1164_Body(PredefinedPackageBody):
+	"""
+	Predefined package body of package ``ieee.std_logic_1164``.
+	"""
+
+
+@export
+class std_logic_textio(PredefinedPackage):
+	"""
+	Predefined package ``ieee.std_logic_textio``.
+	"""
+
+	def __init__(self) -> None:
+		super().__init__()
+
+		self._AddPackageClause(("STD.TEXTIO.all", ))
+		self._AddLibraryClause(("IEEE", ))
+		self._AddPackageClause(("IEEE.std_logic_1164.all", ))
+
+
+@export
+class Std_logic_misc(PredefinedPackage):
+	"""
+	Predefined package ``ieee.std_logic_misc``.
+	"""
+
+	def __init__(self) -> None:
+		super().__init__()
+
+		self._AddLibraryClause(("IEEE", ))
+		self._AddPackageClause(("IEEE.std_logic_1164.all", ))
+
+
+@export
+class Std_logic_misc_Body(PredefinedPackageBody):
+	"""
+	Predefined package body of package ``ieee.std_logic_misc``.
+	"""
+
+
+@export
+class Numeric_Bit(PredefinedPackage):
+	"""
+	Predefined package ``ieee.numeric_bit``.
+	"""
+
+	def __init__(self) -> None:
+		super().__init__()
+
+		self._AddPackageClause(("STD.TEXTIO.all", ))
+
+
+@export
+class Numeric_Bit_Body(PredefinedPackageBody):
+	"""
+	Predefined package body of package ``ieee.numeric_bit``.
+	"""
+
+
+@export
+class Numeric_Bit_Unsigned(PredefinedPackage):
+	"""
+	Predefined package ``ieee.numeric_bit_unsigned``.
+	"""
+
+
+@export
+class Numeric_Bit_Unsigned_Body(PredefinedPackageBody):
+	"""
+	Predefined package body of package ``ieee.numeric_bit_unsigned``.
+	"""
+
+	def __init__(self) -> None:
+		super().__init__()
+
+		self._AddLibraryClause(("IEEE", ))
+		self._AddPackageClause(("IEEE.numeric_bit.all", ))
+
+
+@export
+class Numeric_Std(PredefinedPackage):
+	"""
+	Predefined package ``ieee.numeric_std``.
+
+	Predefined types:
+
+	* ``unresolved_unsigned``, ``unsigned``
+	* ``unresolved_signed``, ``signed``
+	"""
+
+	def __init__(self) -> None:
+		super().__init__()
+
+		self._AddPackageClause(("STD.TEXTIO.all", ))
+		self._AddLibraryClause(("IEEE", ))
+		self._AddPackageClause(("IEEE.std_logic_1164.all", ))
+
+		unresolvedUnsigned = ArrayType("unresolved_unsigned", (SimpleSubtypeSymbol(SimpleName("natural")),), SimpleSubtypeSymbol(SimpleName("std_ulogic")), None)
+		self._types[unresolvedUnsigned._normalizedIdentifier] = unresolvedUnsigned
+		self._declaredItems.append(unresolvedUnsigned)
+
+		unsigned = Subtype("unsigned", SimpleSubtypeSymbol(SimpleName("unresolved_unsigned")), None)
+		unsigned._baseType = unresolvedUnsigned
+		self._subtypes[unsigned._normalizedIdentifier] = unsigned
+		self._declaredItems.append(unsigned)
+
+		unresolvedSigned = ArrayType("unresolved_signed", (SimpleSubtypeSymbol(SimpleName("natural")),), SimpleSubtypeSymbol(SimpleName("std_ulogic")), None)
+		self._types[unresolvedSigned._normalizedIdentifier] = unresolvedSigned
+		self._declaredItems.append(unresolvedSigned)
+
+		signed = Subtype("signed", SimpleSubtypeSymbol(SimpleName("unresolved_signed")), None)
+		signed._baseType = unresolvedSigned
+		self._subtypes[signed._normalizedIdentifier] = signed
+		self._declaredItems.append(signed)
+
+
+@export
+class Numeric_Std_Body(PredefinedPackageBody):
+	"""
+	Predefined package body of package ``ieee.numeric_std``.
+	"""
+
+
+@export
+class Numeric_Std_Unsigned(PredefinedPackage):
+	"""
+	Predefined package ``ieee.numeric_std_unsigned``.
+	"""
+
+	def __init__(self) -> None:
+		super().__init__()
+
+		self._AddLibraryClause(("IEEE", ))
+		self._AddPackageClause(("IEEE.std_logic_1164.all", ))
+
+
+@export
+class Numeric_Std_Unsigned_Body(PredefinedPackageBody):
+	"""
+	Predefined package body of package ``ieee.numeric_std_unsigned``.
+	"""
+
+	def __init__(self) -> None:
+		super().__init__()
+
+		self._AddLibraryClause(("IEEE", ))
+		self._AddPackageClause(("IEEE.numeric_std.all", ))
+
+
+@export
+class Fixed_Float_Types(PredefinedPackage):
+	"""
+	Predefined package ``ieee.fixed_float_types``.
+	"""
+
+
+@export
+class Fixed_Generic_Pkg(PredefinedPackage):
+	"""
+	Predefined package ``ieee.fixed_generic_pkg``.
+	"""
+
+	def __init__(self) -> None:
+		super().__init__()
+
+		self._AddPackageClause(("STD.TEXTIO.all", ))
+		self._AddLibraryClause(("IEEE", ))
+		self._AddPackageClause(("IEEE.STD_LOGIC_1164.all", ))
+		self._AddPackageClause(("IEEE.NUMERIC_STD.all", ))
+		self._AddPackageClause(("IEEE.fixed_float_types.all", ))
+
+
+@export
+class Fixed_Generic_Pkg_Body(PredefinedPackageBody):
+	"""
+	Predefined package body of package ``ieee.fixed_generic_pkg``.
+	"""
+
+	def __init__(self) -> None:
+		super().__init__()
+
+		self._AddLibraryClause(("IEEE", ))
+		self._AddPackageClause(("IEEE.MATH_REAL.all", ))
+
+
+@export
+class Fixed_Pkg(PredefinedPackage):
+	"""
+	Predefined package ``ieee.fixed_pkg``.
+	"""
+	def __init__(self) -> None:
+		super().__init__()
+
+		self._AddLibraryClause(("IEEE", ))
+
+
+@export
+class Float_Generic_Pkg(PredefinedPackage):
+	"""
+	Predefined package ``ieee.float_generic_pkg``.
+	"""
+
+	def __init__(self) -> None:
+		super().__init__()
+
+		self._AddPackageClause(("STD.TEXTIO.all", ))
+		self._AddLibraryClause(("IEEE", ))
+		self._AddPackageClause(("IEEE.STD_LOGIC_1164.all", ))
+		self._AddPackageClause(("IEEE.NUMERIC_STD.all", ))
+		self._AddPackageClause(("IEEE.fixed_float_types.all", ))
+
+
+@export
+class Float_Generic_Pkg_Body(PredefinedPackageBody):
+	"""
+	Predefined package body of package ``ieee.float_generic_pkg``.
+	"""
+
+
+@export
+class Float_Pkg(PredefinedPackage):
+	"""
+	Predefined package ``ieee.float_pkg``.
+	"""
+
+	def __init__(self) -> None:
+		super().__init__()
+
+		self._AddLibraryClause(("IEEE", ))
+
+
+PACKAGES = (
+	(Math_Real,            Math_Real_Body),
+	(Math_Complex,         Math_Complex_Body),
+	(Std_logic_1164,       Std_logic_1164_Body),
+	(std_logic_textio,     None),
+	(Numeric_Bit,          Numeric_Bit_Body),
+	(Numeric_Bit_Unsigned, Numeric_Bit_Unsigned_Body),
+	(Numeric_Std,          Numeric_Std_Body),
+	(Numeric_Std_Unsigned, Numeric_Std_Unsigned_Body),
+	(Fixed_Float_Types,    None),
+	(Fixed_Generic_Pkg,    Fixed_Generic_Pkg_Body),
+	(Fixed_Pkg,            None),
+	(Float_Generic_Pkg,    Float_Generic_Pkg_Body),
+	(Float_Pkg,            None),
+)
+
+PACKAGES_SYNOPSYS = (
+	(Std_logic_misc,       Std_logic_misc_Body),
+)
+
+ + diff --git a/typing/html/pyVHDLModel/Instantiation.py.html b/typing/html/pyVHDLModel/Instantiation.py.html new file mode 100644 index 000000000..a2865a019 --- /dev/null +++ b/typing/html/pyVHDLModel/Instantiation.py.html @@ -0,0 +1,226 @@ + + + + + + +

pyVHDLModel.Instantiation

+ + + + + + +
pyVHDLModel/Instantiation.py
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# ==================================================================================================================== #
+#             __     ___   _ ____  _     __  __           _      _                                                     #
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |                                                    #
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |                                                    #
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |                                                    #
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|                                                    #
+#  |_|    |___/                                                                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""
+This module contains parts of an abstract document language model for VHDL.
+
+Instantiations of packages, procedures, functions and protected types.
+"""
+from typing import List, Optional as Nullable
+
+from pyTooling.Decorators    import export, readonly
+from pyTooling.MetaClasses   import ExtendedType
+
+from pyVHDLModel.Base        import ModelEntity
+from pyVHDLModel.DesignUnit  import PrimaryUnit
+from pyVHDLModel.Association import GenericAssociationItem
+from pyVHDLModel.Subprogram  import Procedure, Function, Subprogram
+from pyVHDLModel.Symbol      import PackageReferenceSymbol
+
+
+@export
+class GenericInstantiationMixin(metaclass=ExtendedType, mixin=True):
+	def __init__(self) -> None:
+		pass
+
+
+@export
+class GenericEntityInstantiationMixin(GenericInstantiationMixin, mixin=True):
+	def __init__(self) -> None:
+		pass
+
+
+@export
+class SubprogramInstantiationMixin(GenericInstantiationMixin, mixin=True):
+	_subprogramReference: Subprogram  # FIXME: is this a subprogram symbol?
+
+	def __init__(self) -> None:
+		super().__init__()
+		self._subprogramReference = None
+
+
+@export
+class ProcedureInstantiation(Procedure, SubprogramInstantiationMixin):
+	pass
+
+
+@export
+class FunctionInstantiation(Function, SubprogramInstantiationMixin):
+	pass
+
+
+@export
+class PackageInstantiation(PrimaryUnit, GenericInstantiationMixin):
+	_packageReference: PackageReferenceSymbol
+	_genericAssociations: List[GenericAssociationItem]
+
+	def __init__(self, identifier: str, uninstantiatedPackage: PackageReferenceSymbol, documentation: Nullable[str] = None, parent: ModelEntity = None) -> None:
+		super().__init__(identifier, documentation, parent)
+		GenericEntityInstantiationMixin.__init__(self)
+
+		self._packageReference = uninstantiatedPackage
+		# uninstantiatedPackage._parent = self    # FIXME: uninstantiatedPackage is provided as int
+
+		# TODO: extract to mixin
+		self._genericAssociations = []
+
+	@readonly
+	def PackageReference(self) -> PackageReferenceSymbol:
+		return self._packageReference
+
+	@readonly
+	def GenericAssociations(self) -> List[GenericAssociationItem]:
+		return self._genericAssociations
+
+ + diff --git a/typing/html/pyVHDLModel/Interface.py.html b/typing/html/pyVHDLModel/Interface.py.html new file mode 100644 index 000000000..7232a6aad --- /dev/null +++ b/typing/html/pyVHDLModel/Interface.py.html @@ -0,0 +1,457 @@ + + + + + + +

pyVHDLModel.Interface

+ + + + + + +
pyVHDLModel/Interface.py
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+
# ==================================================================================================================== #
+#             __     ___   _ ____  _     __  __           _      _                                                     #
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |                                                    #
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |                                                    #
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |                                                    #
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|                                                    #
+#  |_|    |___/                                                                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""
+This module contains parts of an abstract document language model for VHDL.
+
+Interface items are used in generic, port and parameter declarations.
+"""
+from typing                 import Iterable, Optional as Nullable
+
+from pyTooling.Decorators   import export, readonly
+from pyTooling.MetaClasses  import ExtendedType
+
+from pyVHDLModel.Symbol     import Symbol
+from pyVHDLModel.Base       import ModelEntity, DocumentedEntityMixin, ExpressionUnion, Mode
+from pyVHDLModel.Object     import Constant, Signal, Variable, File
+from pyVHDLModel.Subprogram import Procedure, Function
+from pyVHDLModel.Type       import Type
+
+
+@export
+class InterfaceItemMixin(DocumentedEntityMixin, mixin=True):
+	"""An ``InterfaceItem`` is a base-class for all mixin-classes for all interface items."""
+
+	def __init__(self, documentation: Nullable[str] = None) -> None:
+		super().__init__(documentation)
+
+
+@export
+class InterfaceItemWithModeMixin(metaclass=ExtendedType, mixin=True):
+	"""An ``InterfaceItemWithMode`` is a mixin-class to provide a ``Mode`` to interface items."""
+
+	_mode: Mode
+
+	def __init__(self, mode: Mode) -> None:
+		self._mode = mode
+
+	@readonly
+	def Mode(self) -> Mode:
+		return self._mode
+
+
+@export
+class GenericInterfaceItemMixin(InterfaceItemMixin, mixin=True):
+	"""A ``GenericInterfaceItem`` is a mixin class for all generic interface items."""
+
+
+@export
+class PortInterfaceItemMixin(InterfaceItemMixin, InterfaceItemWithModeMixin, mixin=True):
+	"""A ``PortInterfaceItem`` is a mixin class for all port interface items."""
+
+	def __init__(self, mode: Mode) -> None:
+		super().__init__()
+		InterfaceItemWithModeMixin.__init__(self, mode)
+
+
+@export
+class ParameterInterfaceItemMixin(InterfaceItemMixin, mixin=True):
+	"""A ``ParameterInterfaceItem`` is a mixin class for all parameter interface items."""
+
+
+@export
+class GenericConstantInterfaceItem(Constant, GenericInterfaceItemMixin, InterfaceItemWithModeMixin):
+	def __init__(
+		self,
+		identifiers: Iterable[str],
+		mode: Mode,
+		subtype: Symbol,
+		defaultExpression: Nullable[ExpressionUnion] = None,
+		documentation: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(identifiers, subtype, defaultExpression, documentation, parent)
+		GenericInterfaceItemMixin.__init__(self)
+		InterfaceItemWithModeMixin.__init__(self, mode)
+
+
+@export
+class GenericTypeInterfaceItem(Type, GenericInterfaceItemMixin):
+	def __init__(self, identifier: str, documentation: Nullable[str] = None, parent: ModelEntity = None) -> None:
+		super().__init__(identifier, documentation, parent)
+		GenericInterfaceItemMixin.__init__(self)
+
+
+@export
+class GenericSubprogramInterfaceItem(GenericInterfaceItemMixin):
+	pass
+
+
+@export
+class GenericProcedureInterfaceItem(Procedure, GenericInterfaceItemMixin):
+	def __init__(self, identifier: str, documentation: Nullable[str] = None, parent: ModelEntity = None) -> None:
+		super().__init__(identifier, documentation, parent)
+		GenericInterfaceItemMixin.__init__(self)
+
+
+@export
+class GenericFunctionInterfaceItem(Function, GenericInterfaceItemMixin):
+	def __init__(self, identifier: str, documentation: Nullable[str] = None, parent: ModelEntity = None) -> None:
+		super().__init__(identifier, documentation, parent)
+		GenericInterfaceItemMixin.__init__(self)
+
+
+@export
+class GenericPackageInterfaceItem(GenericInterfaceItemMixin):
+	def __init__(self, identifier: str, documentation: Nullable[str] = None, parent: ModelEntity = None) -> None:
+		super().__init__(identifier, documentation, parent)
+		GenericInterfaceItemMixin.__init__(self)
+
+
+@export
+class PortSignalInterfaceItem(Signal, PortInterfaceItemMixin):
+	def __init__(
+		self,
+		identifiers: Iterable[str],
+		mode: Mode,
+		subtype: Symbol,
+		defaultExpression: Nullable[ExpressionUnion] = None,
+		documentation: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(identifiers, subtype, defaultExpression, documentation, parent)
+		PortInterfaceItemMixin.__init__(self, mode)
+
+
+@export
+class ParameterConstantInterfaceItem(Constant, ParameterInterfaceItemMixin, InterfaceItemWithModeMixin):
+	def __init__(
+		self,
+		identifiers: Iterable[str],
+		mode: Mode,
+		subtype: Symbol,
+		defaultExpression: Nullable[ExpressionUnion] = None,
+		documentation: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(identifiers, subtype, defaultExpression, documentation, parent)
+		ParameterInterfaceItemMixin.__init__(self)
+		InterfaceItemWithModeMixin.__init__(self, mode)
+
+
+@export
+class ParameterVariableInterfaceItem(Variable, ParameterInterfaceItemMixin, InterfaceItemWithModeMixin):
+	def __init__(
+		self,
+		identifiers: Iterable[str],
+		mode: Mode,
+		subtype: Symbol,
+		defaultExpression: Nullable[ExpressionUnion] = None,
+		documentation: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(identifiers, subtype, defaultExpression, documentation, parent)
+		ParameterInterfaceItemMixin.__init__(self)
+		InterfaceItemWithModeMixin.__init__(self, mode)
+
+
+@export
+class ParameterSignalInterfaceItem(Signal, ParameterInterfaceItemMixin, InterfaceItemWithModeMixin):
+	def __init__(
+		self,
+		identifiers: Iterable[str],
+		mode: Mode,
+		subtype: Symbol,
+		defaultExpression: Nullable[ExpressionUnion] = None,
+		documentation: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(identifiers, subtype, defaultExpression, documentation, parent)
+		ParameterInterfaceItemMixin.__init__(self)
+		InterfaceItemWithModeMixin.__init__(self, mode)
+
+
+@export
+class ParameterFileInterfaceItem(File, ParameterInterfaceItemMixin):
+	def __init__(
+		self,
+		identifiers: Iterable[str],
+		subtype: Symbol,
+		documentation: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(identifiers, subtype, documentation, parent)
+		ParameterInterfaceItemMixin.__init__(self)
+
+ + diff --git a/typing/html/pyVHDLModel/Name.py.html b/typing/html/pyVHDLModel/Name.py.html new file mode 100644 index 000000000..2430ed6b1 --- /dev/null +++ b/typing/html/pyVHDLModel/Name.py.html @@ -0,0 +1,497 @@ + + + + + + +

pyVHDLModel.Name

+ + + + + + +
pyVHDLModel/Name.py
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+
# ==================================================================================================================== #
+#             __     ___   _ ____  _     __  __           _      _                                                     #
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |                                                    #
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |                                                    #
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |                                                    #
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|                                                    #
+#  |_|    |___/                                                                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""
+This module contains parts of an abstract document language model for VHDL.
+
+VHDL uses *names* to express cross-references from *usage locations* to *declarations*. Here, *names* are single or
+combined identifiers. :mod:`Symbols <pyVHDLModel.Symbol>` are structures representing a *name* and a reference
+(pointer) to the referenced vhdl language entity.
+"""
+from typing import List, Iterable, Optional as Nullable
+
+from pyTooling.Decorators import export, readonly
+
+from pyVHDLModel.Base import ModelEntity, ExpressionUnion
+
+
+@export
+class Name(ModelEntity):
+	"""``Name`` is the base-class for all *names* in the VHDL language model."""
+
+	_identifier: str
+	_normalizedIdentifier: str
+	_root: Nullable['Name']     # TODO: seams to be unused. There is no reverse linking, or?
+	_prefix: Nullable['Name']
+
+	def __init__(self, identifier: str, prefix: Nullable["Name"] = None, parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+
+		self._identifier = identifier
+		self._normalizedIdentifier = identifier.lower()
+
+		if prefix is None:
+			self._prefix = None
+			self._root = self
+		else:
+			self._prefix = prefix
+			self._root = prefix._root
+
+	@readonly
+	def Identifier(self) -> str:
+		"""
+		The identifier the name is referencing.
+
+		:returns: The referenced identifier.
+		"""
+		return self._identifier
+
+	@readonly
+	def NormalizedIdentifier(self) -> str:
+		"""
+		The normalized identifier the name is referencing.
+
+		:returns: The referenced identifier (normalized).
+		"""
+		return self._normalizedIdentifier
+
+	@readonly
+	def Root(self) -> 'Name':
+		"""
+		The root (left-most) element in a chain of names.
+
+		In case the name is a :class:`simple name <SimpleName>`, the root points to the name itself.
+
+		:returns: The name's root element.
+		"""
+		return self._root
+
+	@readonly
+	def Prefix(self) -> Nullable['Name']:
+		"""
+		The name's prefix in a chain of names.
+
+		:returns: The name left from current name, if not a simple name, otherwise ``None``.
+		"""
+		return self._prefix
+
+	@readonly
+	def HasPrefix(self) -> bool:
+		"""
+		Returns true, if the name has a prefix.
+
+		This is true for all names except :class:`simple names <SimpleName>`.
+
+		:returns: ``True``, if the name as a prefix.
+		"""
+		return self._prefix is not None
+
+	def __repr__(self) -> str:
+		return f"Name: '{self.__str__()}'"
+
+	def __str__(self) -> str:
+		return self._identifier
+
+
+@export
+class SimpleName(Name):
+	"""
+	A *simple name* is a name made from a single word.
+
+	For example, the entity name in an architecture declaration is a simple name, while the name of the architecture
+	itself is an identifier. The simple name references is again an identifier in the entity declaration, thus names
+	reference other (already) declared language entities.
+	"""
+
+
+@export
+class ParenthesisName(Name):
+	_associations: List
+
+	def __init__(self, prefix: Name, associations: Iterable, parent: ModelEntity = None) -> None:
+		super().__init__("", prefix, parent)
+
+		self._associations = []
+		for association in associations:
+			self._associations.append(association)
+			association._parent = self
+
+	@readonly
+	def Associations(self) -> List:
+		return self._associations
+
+	def __str__(self) -> str:
+		return f"{self._prefix!s}({', '.join(str(a) for a in self._associations)})"
+
+
+@export
+class IndexedName(Name):
+	_indices: List[ExpressionUnion]
+
+	def __init__(self, prefix: Name, indices: Iterable[ExpressionUnion], parent: ModelEntity = None) -> None:
+		super().__init__("", prefix, parent)
+
+		self._indices = []
+		for index in indices:
+			self._indices.append(index)
+			index._parent = self
+
+	@readonly
+	def Indices(self) -> List[ExpressionUnion]:
+		return self._indices
+
+	def __str__(self) -> str:
+		return f"{self._prefix!s}({', '.join(str(i) for i in self._indices)})"
+
+
+@export
+class SlicedName(Name):
+	pass
+
+
+@export
+class SelectedName(Name):
+	"""
+	A *selected name* is a name made from multiple words separated by a dot (``.``).
+
+	For example, the library and entity name in a direct entity instantiation is a selected name. Here the entity
+	identifier is a selected name. The library identifier is a :class:`simple name <SimpleName>`, which is
+	referenced by the selected name via the :attr:`~pyVHDLModel.Name.Prefix` property.
+	"""
+
+	def __init__(self, identifier: str, prefix: Name, parent: ModelEntity = None) -> None:
+		super().__init__(identifier, prefix, parent)
+
+	def __str__(self) -> str:
+		return f"{self._prefix!s}.{self._identifier}"
+
+
+@export
+class AttributeName(Name):
+	def __init__(self, identifier: str, prefix: Name, parent: ModelEntity = None) -> None:
+		super().__init__(identifier, prefix, parent)
+
+	def __str__(self) -> str:
+		return f"{self._prefix!s}'{self._identifier}"
+
+
+@export
+class AllName(SelectedName):
+	"""
+	The *all name* represents the reserved word ``all`` used in names.
+
+	Most likely this name is used in use-statements.
+	"""
+	def __init__(self, prefix: Name, parent: ModelEntity = None) -> None:
+		super().__init__("all", prefix, parent)  # TODO: the case of 'ALL' is not preserved
+
+
+@export
+class OpenName(Name):
+	"""
+	The *open name* represents the reserved word ``open``.
+
+	Most likely this name is used in port associations.
+	"""
+	def __init__(self, parent: ModelEntity = None) -> None:
+		super().__init__("open", parent)  # TODO: the case of 'OPEN' is not preserved
+
+	def __str__(self) -> str:
+		return "open"
+
+ + diff --git a/typing/html/pyVHDLModel/Namespace.py.html b/typing/html/pyVHDLModel/Namespace.py.html new file mode 100644 index 000000000..4ef056c60 --- /dev/null +++ b/typing/html/pyVHDLModel/Namespace.py.html @@ -0,0 +1,356 @@ + + + + + + +

pyVHDLModel.Namespace

+ + + + + + +
pyVHDLModel/Namespace.py
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+
# ==================================================================================================================== #
+#             __     ___   _ ____  _     __  __           _      _                                                     #
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |                                                    #
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |                                                    #
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |                                                    #
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|                                                    #
+#  |_|    |___/                                                                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""
+This module contains parts of an abstract document language model for VHDL.
+
+A helper class to implement namespaces and scopes.
+"""
+from typing               import TypeVar, Generic, Dict, Optional as Nullable
+
+from pyTooling.Decorators import readonly
+
+from pyVHDLModel.Object   import Obj, Signal, Constant, Variable
+from pyVHDLModel.Symbol   import ComponentInstantiationSymbol, Symbol, PossibleReference
+from pyVHDLModel.Type     import Subtype, FullType, BaseType
+
+K = TypeVar("K")
+O = TypeVar("O")
+
+
+class Namespace(Generic[K, O]):
+	_name:            str
+	_parentNamespace: 'Namespace'
+	_subNamespaces:   Dict[str, 'Namespace']
+	_elements:        Dict[K, O]
+
+	def __init__(self, name: str, parentNamespace: Nullable["Namespace"] = None) -> None:
+		self._name = name
+		self._parentNamespace = parentNamespace
+		self._subNamespaces = {}
+		self._elements = {}
+
+	@readonly
+	def Name(self) -> str:
+		return self._name
+
+	@readonly
+	def ParentNamespace(self) -> 'Namespace':
+		return self._parentNamespace
+
+	@ParentNamespace.setter
+	def ParentNamespace(self, value: 'Namespace'):
+		self._parentNamespace = value
+		value._subNamespaces[self._name] = self
+
+	@readonly
+	def SubNamespaces(self) -> Dict[str, 'Namespace']:
+		return self._subNamespaces
+
+	def Elements(self) -> Dict[K, O]:
+		return self._elements
+
+	def FindComponent(self, componentSymbol: ComponentInstantiationSymbol) -> 'Component':
+		from pyVHDLModel.DesignUnit import Component
+
+		try:
+			element = self._elements[componentSymbol._name._normalizedIdentifier]
+			if isinstance(element, Component):
+				return element
+			else:
+				raise TypeError(f"Found element '{componentSymbol._name._identifier}', but it is not a component.")
+		except KeyError:
+			parentNamespace = self._parentNamespace
+			if parentNamespace is None:
+				raise KeyError(f"Component '{componentSymbol._name._identifier}' not found in '{self._name}'.")
+
+			return parentNamespace.FindComponent(componentSymbol)
+
+	def FindSubtype(self, subtypeSymbol: Symbol) -> BaseType:
+		try:
+			element = self._elements[subtypeSymbol._name._normalizedIdentifier]
+			if isinstance(element, Subtype):
+				if PossibleReference.Subtype in subtypeSymbol._possibleReferences:
+					return element
+				else:
+					raise TypeError(f"Found subtype '{subtypeSymbol._name._identifier}', but it was not expected.")
+			elif isinstance(element, FullType):
+				if PossibleReference.Type in subtypeSymbol._possibleReferences:
+					return element
+				else:
+					raise TypeError(f"Found type '{subtypeSymbol._name._identifier}', but it was not expected.")
+			else:
+				raise TypeError(f"Found element '{subtypeSymbol._name._identifier}', but it is not a type or subtype.")
+		except KeyError:
+			parentNamespace = self._parentNamespace
+			if parentNamespace is None:
+				raise KeyError(f"Subtype '{subtypeSymbol._name._identifier}' not found in '{self._name}'.")
+
+			return parentNamespace.FindSubtype(subtypeSymbol)
+
+	def FindObject(self, objectSymbol: Symbol) -> Obj:
+		try:
+			element = self._elements[objectSymbol._name._normalizedIdentifier]
+			if isinstance(element, Signal):
+				if PossibleReference.Signal in objectSymbol._possibleReferences:
+					return element
+				elif PossibleReference.SignalAttribute in objectSymbol._possibleReferences:
+					return element
+				else:
+					raise TypeError(f"Found signal '{objectSymbol._name._identifier}', but it was not expected.")
+			elif isinstance(element, Constant):
+				if PossibleReference.Constant in objectSymbol._possibleReferences:
+					return element
+				else:
+					raise TypeError(f"Found constant '{objectSymbol._name._identifier}', but it was not expected.")
+			elif isinstance(element, Variable):
+				if PossibleReference.Variable in objectSymbol._possibleReferences:
+					return element
+				else:
+					raise TypeError(f"Found variable '{objectSymbol._name._identifier}', but it was not expected.")
+			else:
+				raise TypeError(f"Found element '{objectSymbol._name._identifier}', but it is not a type or subtype.")
+		except KeyError:
+			parentNamespace = self._parentNamespace
+			if parentNamespace is None:
+				raise KeyError(f"Subtype '{objectSymbol._name._identifier}' not found in '{self._name}'.")
+
+			return parentNamespace.FindObject(objectSymbol)
+
+ + diff --git a/typing/html/pyVHDLModel/Object.py.html b/typing/html/pyVHDLModel/Object.py.html new file mode 100644 index 000000000..281ea7ddd --- /dev/null +++ b/typing/html/pyVHDLModel/Object.py.html @@ -0,0 +1,526 @@ + + + + + + +

pyVHDLModel.Object

+ + + + + + +
pyVHDLModel/Object.py
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+
# ==================================================================================================================== #
+#             __     ___   _ ____  _     __  __           _      _                                                     #
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |                                                    #
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |                                                    #
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |                                                    #
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|                                                    #
+#  |_|    |___/                                                                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""
+This module contains parts of an abstract document language model for VHDL.
+
+Objects are constants, variables, signals and files.
+"""
+from typing                import Iterable, Optional as Nullable
+
+from pyTooling.Decorators  import export, readonly
+from pyTooling.MetaClasses import ExtendedType
+from pyTooling.Graph       import Vertex
+
+from pyVHDLModel.Base      import ModelEntity, MultipleNamedEntityMixin, DocumentedEntityMixin, ExpressionUnion
+from pyVHDLModel.Symbol    import Symbol
+
+
+@export
+class Obj(ModelEntity, MultipleNamedEntityMixin, DocumentedEntityMixin):
+	"""
+	Base-class for all objects (constants, signals, variables and files) in VHDL.
+
+	An object (syntax element) can define multiple objects (semantic elements) in a single declaration, thus
+	:class:`~pyVHDLModel.Base.MultipleNamedEntityMixin` is inherited. All objects can be documented, thus
+	:class:`~pyVHDLModel.Base.DocumentedEntityMixin` is inherited too.
+
+	Each object references a subtype via :data:`_subtype`.
+
+	Objects are elements in the type and object graph, thus a reference to a vertex in that graph is stored in
+	:data:`__objectVertex`.
+	"""
+
+	_subtype:      Symbol
+	_objectVertex: Nullable[Vertex]
+
+	def __init__(self, identifiers: Iterable[str], subtype: Symbol, documentation: Nullable[str] = None, parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+		MultipleNamedEntityMixin.__init__(self, identifiers)
+		DocumentedEntityMixin.__init__(self, documentation)
+
+		self._subtype = subtype
+		subtype._parent = self
+
+		self._objectVertex = None
+
+	@readonly
+	def Subtype(self) -> Symbol:
+		return self._subtype
+
+	@readonly
+	def ObjectVertex(self) -> Nullable[Vertex]:
+		"""
+		Read-only property to access the corresponding object vertex (:attr:`_objectVertex`).
+
+		The object vertex references this Object by its value field.
+
+		:returns: The corresponding object vertex.
+		"""
+		return self._objectVertex
+
+
+@export
+class WithDefaultExpressionMixin(metaclass=ExtendedType, mixin=True):
+	"""
+	A ``WithDefaultExpression`` is a mixin-class for all objects declarations accepting default expressions.
+
+	The default expression is referenced by :data:`__defaultExpression`. If no default expression is present, this field
+	is ``None``.
+	"""
+
+	_defaultExpression: Nullable[ExpressionUnion]
+
+	def __init__(self, defaultExpression: Nullable[ExpressionUnion] = None) -> None:
+		self._defaultExpression = defaultExpression
+		if defaultExpression is not None:
+			defaultExpression._parent = self
+
+	@readonly
+	def DefaultExpression(self) -> Nullable[ExpressionUnion]:
+		return self._defaultExpression
+
+
+@export
+class BaseConstant(Obj):
+	"""
+	Base-class for all constants (normal and deferred constants) in VHDL.
+	"""
+
+
+@export
+class Constant(BaseConstant, WithDefaultExpressionMixin):
+	"""
+	Represents a constant.
+
+	As constants (always) have a default expression, the class :class:`~pyVHDLModel.Object.WithDefaultExpressionMixin` is inherited.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      constant BITS : positive := 8;
+	"""
+
+	def __init__(
+		self,
+		identifiers: Iterable[str],
+		subtype: Symbol,
+		defaultExpression: Nullable[ExpressionUnion] = None,
+		documentation: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(identifiers, subtype, documentation, parent)
+		WithDefaultExpressionMixin.__init__(self, defaultExpression)
+
+
+@export
+class DeferredConstant(BaseConstant):
+	"""
+	Represents a deferred constant.
+
+	Deferred constants are forward declarations for a (complete) constant declaration, thus it contains a
+	field :data:`__constantReference` to the complete constant declaration.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      constant BITS : positive;
+	"""
+	_constantReference: Nullable[Constant]
+
+	def __init__(
+		self,
+		identifiers: Iterable[str],
+		subtype: Symbol,
+		documentation: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(identifiers, subtype, documentation, parent)
+
+	@readonly
+	def ConstantReference(self) -> Nullable[Constant]:
+		return self._constantReference
+
+	def __str__(self) -> str:
+		return f"constant {', '.join(self._identifiers)} : {self._subtype}"
+
+
+@export
+class Variable(Obj, WithDefaultExpressionMixin):
+	"""
+	Represents a variable.
+
+	As variables might have a default expression, the class :class:`~pyVHDLModel.Object.WithDefaultExpressionMixin` is inherited.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      variable result : natural := 0;
+	"""
+
+	def __init__(
+		self,
+		identifiers: Iterable[str],
+		subtype: Symbol,
+		defaultExpression: Nullable[ExpressionUnion] = None,
+		documentation: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(identifiers, subtype, documentation, parent)
+		WithDefaultExpressionMixin.__init__(self, defaultExpression)
+
+
+@export
+class SharedVariable(Obj):
+	"""
+	Represents a shared variable.
+
+	.. todo:: Shared variable object not implemented.
+	"""
+
+
+
+@export
+class Signal(Obj, WithDefaultExpressionMixin):
+	"""
+	Represents a signal.
+
+	As signals might have a default expression, the class :class:`~pyVHDLModel.Object.WithDefaultExpressionMixin` is inherited.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      signal counter : unsigned(7 downto 0) := '0';
+	"""
+
+	def __init__(
+		self,
+		identifiers: Iterable[str],
+		subtype: Symbol,
+		defaultExpression: Nullable[ExpressionUnion] = None,
+		documentation: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(identifiers, subtype, documentation, parent)
+		WithDefaultExpressionMixin.__init__(self, defaultExpression)
+
+
+@export
+class File(Obj):
+	"""
+	Represents a file.
+
+	.. todo:: File object not implemented.
+	"""
+
+ + diff --git a/typing/html/pyVHDLModel/PSLModel.py.html b/typing/html/pyVHDLModel/PSLModel.py.html new file mode 100644 index 000000000..54f45f89e --- /dev/null +++ b/typing/html/pyVHDLModel/PSLModel.py.html @@ -0,0 +1,168 @@ + + + + + + +

pyVHDLModel.PSLModel

+ + + + + + +
pyVHDLModel/PSLModel.py
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+
# ==================================================================================================================== #
+#             __     ___   _ ____  _     __  __           _      _                                                     #
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |                                                    #
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |                                                    #
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |                                                    #
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|                                                    #
+#  |_|    |___/                                                                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""
+This module contains an abstract document language model for PSL in VHDL.
+"""
+from pyTooling.Decorators import export
+
+from pyVHDLModel.Base       import ModelEntity, NamedEntityMixin
+from pyVHDLModel.DesignUnit import PrimaryUnit
+
+
+@export
+class PSLEntity(ModelEntity):
+	pass
+
+
+@export
+class PSLPrimaryUnit(PrimaryUnit):
+	pass
+
+
+@export
+class VerificationUnit(PSLPrimaryUnit):
+	def __init__(self, identifier: str) -> None:
+		super().__init__(identifier, parent=None)
+
+
+@export
+class VerificationProperty(PSLPrimaryUnit):
+	def __init__(self, identifier: str) -> None:
+		super().__init__(identifier, parent=None)
+
+
+@export
+class VerificationMode(PSLPrimaryUnit):
+	def __init__(self, identifier: str) -> None:
+		super().__init__(identifier, parent=None)
+
+
+@export
+class DefaultClock(PSLEntity, NamedEntityMixin):
+	def __init__(self, identifier: str) -> None:
+		super().__init__()
+		NamedEntityMixin.__init__(self, identifier)
+
+ + diff --git a/typing/html/pyVHDLModel/Predefined.py.html b/typing/html/pyVHDLModel/Predefined.py.html new file mode 100644 index 000000000..be924f7c8 --- /dev/null +++ b/typing/html/pyVHDLModel/Predefined.py.html @@ -0,0 +1,273 @@ + + + + + + +

pyVHDLModel.Predefined

+ + + + + + +
pyVHDLModel/Predefined.py
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# ==================================================================================================================== #
+#             __     ___   _ ____  _     __  __           _      _                                                     #
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |                                                    #
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |                                                    #
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |                                                    #
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|                                                    #
+#  |_|    |___/                                                                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""This module contains base-classes for predefined library and package declarations."""
+from typing                 import Iterable
+
+from pyTooling.Decorators   import export
+from pyTooling.MetaClasses  import ExtendedType
+
+from pyVHDLModel            import Library, Package, PackageBody, AllPackageMembersReferenceSymbol, PackageMemberReferenceSymbol
+from pyVHDLModel.Name       import SimpleName, SelectedName, AllName
+from pyVHDLModel.Symbol     import LibraryReferenceSymbol, PackageSymbol
+from pyVHDLModel.DesignUnit import LibraryClause, UseClause
+
+
+@export
+class PredefinedLibrary(Library):
+	"""
+	A base-class for predefined VHDL libraries.
+
+	VHDL defines 2 predefined libraries:
+
+	* :class:`~pyVHDLModel.STD.Std`
+	* :class:`~pyVHDLModel.IEEE.Ieee`
+	"""
+
+	def __init__(self, packages) -> None:
+		super().__init__(self.__class__.__name__, None)
+
+		self.AddPackages(packages)
+
+	def AddPackages(self, packages) -> None:
+		for packageType, packageBodyType in packages:
+			package: Package = packageType()
+			package.Library = self
+			self._packages[package.NormalizedIdentifier] = package
+
+			if packageBodyType is not None:
+				packageBody: PackageBody = packageBodyType()
+				packageBody.Library = self
+				self._packageBodies[packageBody.NormalizedIdentifier] = packageBody
+
+
+@export
+class PredefinedPackageMixin(metaclass=ExtendedType, mixin=True):
+	"""
+	A mixin-class for predefined VHDL packages and package bodies.
+	"""
+
+	def _AddLibraryClause(self, libraries: Iterable[str]):
+		symbols = [LibraryReferenceSymbol(SimpleName(libName)) for libName in libraries]
+		libraryClause = LibraryClause(symbols)
+
+		self._contextItems.append(libraryClause)
+		self._libraryReferences.append(libraryClause)
+
+	def _AddPackageClause(self, packages: Iterable[str]):
+		symbols = []
+		for qualifiedPackageName in packages:
+			libName, packName, members = qualifiedPackageName.split(".")
+
+			packageName = SelectedName(packName, SimpleName(libName))
+			if members.lower() == "all":
+				symbols.append(AllPackageMembersReferenceSymbol(AllName(packageName)))
+			else:
+				symbols.append(PackageMemberReferenceSymbol(SelectedName(members, packageName)))
+
+		useClause = UseClause(symbols)
+		self._contextItems.append(useClause)
+		self._packageReferences.append(useClause)
+
+
+@export
+class PredefinedPackage(Package, PredefinedPackageMixin):
+	"""
+	A base-class for predefined VHDL packages.
+	"""
+
+	def __init__(self) -> None:
+		super().__init__(self.__class__.__name__, parent=None)
+
+
+@export
+class PredefinedPackageBody(PackageBody, PredefinedPackageMixin):
+	"""
+	A base-class for predefined VHDL package bodies.
+	"""
+
+	def __init__(self) -> None:
+		packageSymbol = PackageSymbol(SimpleName(self.__class__.__name__[:-5]))
+		super().__init__(packageSymbol, parent=None)
+
+ + diff --git a/typing/html/pyVHDLModel/Regions.py.html b/typing/html/pyVHDLModel/Regions.py.html new file mode 100644 index 000000000..d7a8690c5 --- /dev/null +++ b/typing/html/pyVHDLModel/Regions.py.html @@ -0,0 +1,446 @@ + + + + + + +

pyVHDLModel.Regions

+ + + + + + +
pyVHDLModel/Regions.py
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+
# ==================================================================================================================== #
+#             __     ___   _ ____  _     __  __           _      _                                                     #
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |                                                    #
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |                                                    #
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |                                                    #
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|                                                    #
+#  |_|    |___/                                                                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""
+This module contains parts of an abstract document language model for VHDL.
+
+tbd.
+"""
+from typing                 import List, Dict, Iterable, Optional as Nullable
+
+from pyTooling.Decorators   import export, readonly
+from pyTooling.MetaClasses  import ExtendedType
+
+from pyVHDLModel.Object     import Constant, SharedVariable, File, Variable, Signal
+from pyVHDLModel.Subprogram import Subprogram, Function, Procedure
+from pyVHDLModel.Type       import Subtype, FullType
+
+
+@export
+class ConcurrentDeclarationRegionMixin(metaclass=ExtendedType, mixin=True):
+	# FIXME: define list prefix type e.g. via Union
+	_declaredItems:   List                              #: List of all declared items in this concurrent declaration region.
+
+	# _attributes:     Dict[str, Attribute]
+	# _aliases:        Dict[str, Alias]
+	_types:           Dict[str, FullType]               #: Dictionary of all types declared in this concurrent declaration region.
+	_subtypes:        Dict[str, Subtype]                #: Dictionary of all subtypes declared in this concurrent declaration region.
+	# _objects:        Dict[str, Union[Constant, Variable, Signal]]
+	_constants:       Dict[str, Constant]               #: Dictionary of all constants declared in this concurrent declaration region.
+	_signals:         Dict[str, Signal]                 #: Dictionary of all signals declared in this concurrent declaration region.
+	_sharedVariables: Dict[str, SharedVariable]         #: Dictionary of all shared variables declared in this concurrent declaration region.
+	_files:           Dict[str, File]                   #: Dictionary of all files declared in this concurrent declaration region.
+	# _subprograms:     Dict[str, Dict[str, Subprogram]]  #: Dictionary of all subprograms declared in this concurrent declaration region.
+	_functions:       Dict[str, Dict[str, Function]]    #: Dictionary of all functions declared in this concurrent declaration region.
+	_procedures:      Dict[str, Dict[str, Procedure]]   #: Dictionary of all procedures declared in this concurrent declaration region.
+
+	def __init__(self, declaredItems: Nullable[Iterable] = None) -> None:
+		# TODO: extract to mixin
+		self._declaredItems = []  # TODO: convert to dict
+		if declaredItems is not None:
+			for item in declaredItems:
+				self._declaredItems.append(item)
+				item._parent = self
+
+		self._types =       {}
+		self._subtypes =    {}
+		# self._objects =     {}
+		self._constants =   {}
+		self._signals =     {}
+		self._sharedVariables = {}
+		self._files =       {}
+		# self._subprograms = {}
+		self._functions =   {}
+		self._procedures =  {}
+
+	@readonly
+	def DeclaredItems(self) -> List:
+		return self._declaredItems
+
+	@readonly
+	def Types(self) -> Dict[str, FullType]:
+		return self._types
+
+	@readonly
+	def Subtypes(self) -> Dict[str, Subtype]:
+		return self._subtypes
+
+	# @readonly
+	# def Objects(self) -> Dict[str, Union[Constant, SharedVariable, Signal, File]]:
+	# 	return self._objects
+
+	@readonly
+	def Constants(self) -> Dict[str, Constant]:
+		return self._constants
+
+	@readonly
+	def Signals(self) -> Dict[str, Signal]:
+		return self._signals
+
+	@readonly
+	def SharedVariables(self) -> Dict[str, SharedVariable]:
+		return self._sharedVariables
+
+	@readonly
+	def Files(self) -> Dict[str, File]:
+		return self._files
+
+	# @readonly
+	# def Subprograms(self) -> Dict[str, Subprogram]:
+	# 	return self._subprograms
+
+	@readonly
+	def Functions(self) -> Dict[str, Dict[str, Function]]:
+		return self._functions
+
+	@readonly
+	def Procedures(self) -> Dict[str, Dict[str, Procedure]]:
+		return self._procedures
+
+	def IndexDeclaredItems(self) -> None:
+		"""
+		Index declared items listed in the concurrent declaration region.
+
+		.. rubric:: Algorithm
+
+		1. Iterate all declared items:
+
+		   * Every declared item is added to :attr:`_namespace`.
+		   * If the declared item is a :class:`~pyVHDLModel.Type.FullType`, then add an entry to :attr:`_types`.
+		   * If the declared item is a :class:`~pyVHDLModel.Type.SubType`, then add an entry to :attr:`_subtypes`.
+		   * If the declared item is a :class:`~pyVHDLModel.Subprogram.Function`, then add an entry to :attr:`_functions`.
+		   * If the declared item is a :class:`~pyVHDLModel.Subprogram.Procedure`, then add an entry to :attr:`_procedures`.
+		   * If the declared item is a :class:`~pyVHDLModel.Object.Constant`, then add an entry to :attr:`_constants`.
+		   * If the declared item is a :class:`~pyVHDLModel.Object.Signal`, then add an entry to :attr:`_signals`.
+		   * If the declared item is a :class:`~pyVHDLModel.Object.Variable`, TODO.
+		   * If the declared item is a :class:`~pyVHDLModel.Object.SharedVariable`, then add an entry to :attr:`_sharedVariables`.
+		   * If the declared item is a :class:`~pyVHDLModel.Object.File`, then add an entry to :attr:`_files`.
+		   * If the declared item is neither of these types, call :meth:`_IndexOtherDeclaredItem`. |br|
+		     Derived classes may override this virtual function.
+
+		.. seealso::
+
+		   :meth:`pyVHDLModel.Design.IndexPackages`
+		     Iterate all packages in the design and index declared items.
+		   :meth:`pyVHDLModel.Library.IndexPackages`
+		     Iterate all packages in the library and index declared items.
+		   :meth:`pyVHDLModel.Library._IndexOtherDeclaredItem`
+		     Iterate all packages in the library and index declared items.
+		"""
+		for item in self._declaredItems:
+			if isinstance(item, FullType):
+				self._types[item._normalizedIdentifier] = item
+				self._namespace._elements[item._normalizedIdentifier] = item
+			elif isinstance(item, Subtype):
+				self._subtypes[item._normalizedIdentifier] = item
+				self._namespace._elements[item._normalizedIdentifier] = item
+			elif isinstance(item, Function):
+				self._functions[item._normalizedIdentifier] = item
+				self._namespace._elements[item._normalizedIdentifier] = item
+			elif isinstance(item, Procedure):
+				self._procedures[item._normalizedIdentifier] = item
+				self._namespace._elements[item._normalizedIdentifier] = item
+			elif isinstance(item, Constant):
+				for normalizedIdentifier in item._normalizedIdentifiers:
+					self._constants[normalizedIdentifier] = item
+					self._namespace._elements[normalizedIdentifier] = item
+					# self._objects[normalizedIdentifier] = item
+			elif isinstance(item, Signal):
+				for normalizedIdentifier in item._normalizedIdentifiers:
+					self._signals[normalizedIdentifier] = item
+					self._namespace._elements[normalizedIdentifier] = item
+			elif isinstance(item, Variable):
+				print(f"IndexDeclaredItems - {item._identifiers}")
+			elif isinstance(item, SharedVariable):
+				for normalizedIdentifier in item._normalizedIdentifiers:
+					self._sharedVariables[normalizedIdentifier] = item
+					self._namespace._elements[normalizedIdentifier] = item
+			elif isinstance(item, File):
+				for normalizedIdentifier in item._normalizedIdentifiers:
+					self._files[normalizedIdentifier] = item
+					self._namespace._elements[normalizedIdentifier] = item
+			else:
+				self._IndexOtherDeclaredItem(item)
+
+	def _IndexOtherDeclaredItem(self, item) -> None:
+		print(f"_IndexOtherDeclaredItem - {item}\n  ({' -> '.join(t.__name__ for t in type(item).mro())})")
+
+ + diff --git a/typing/html/pyVHDLModel/STD.py.html b/typing/html/pyVHDLModel/STD.py.html new file mode 100644 index 000000000..06381bcf8 --- /dev/null +++ b/typing/html/pyVHDLModel/STD.py.html @@ -0,0 +1,550 @@ + + + + + + +

pyVHDLModel.STD

+ + + + + + +
pyVHDLModel/STD.py
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# ==================================================================================================================== #
+#             __     ___   _ ____  _     __  __           _      _                                                     #
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |                                                    #
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |                                                    #
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |                                                    #
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|                                                    #
+#  |_|    |___/                                                                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""This module contains library and package declarations for VHDL library ``STD``."""
+
+from pyTooling.Decorators    import export
+
+from pyVHDLModel.Base        import Range, Direction
+from pyVHDLModel.Name        import SimpleName
+from pyVHDLModel.Symbol      import SimpleSubtypeSymbol
+from pyVHDLModel.Expression  import EnumerationLiteral, IntegerLiteral, PhysicalIntegerLiteral
+from pyVHDLModel.Type        import EnumeratedType, IntegerType, Subtype, PhysicalType, ArrayType
+from pyVHDLModel.Predefined  import PredefinedLibrary, PredefinedPackage, PredefinedPackageBody
+
+
+@export
+class Std(PredefinedLibrary):
+	"""
+	Predefined VHDL library ``std``.
+
+	The following predefined packages are in this library:
+
+	* :class:`~pyVHDLModel.STD.Standard`
+	* :class:`~pyVHDLModel.STD.Env`
+	* :class:`~pyVHDLModel.STD.TextIO`
+
+	.. seealso::
+
+	   Other predefined libraries:
+	     * Library :class:`~pyVHDLModel.IEEE.Ieee`
+	"""
+
+	def __init__(self) -> None:
+		super().__init__(PACKAGES)
+
+
+@export
+class Standard(PredefinedPackage):
+	"""
+	Predefined package ``std.standard``.
+
+	Predefined types:
+
+	* ``boolean``, ``boolean_vector``
+	* ``bit``, ``bit_vector``
+	* ``character``, ``string``
+	* ``integer``, ``integer_vector``
+	* ``natural``, ``positive``
+	* ``real``, ``real_vector``
+	* ``time``, ``time_vector``
+	* ``open_file_kind``, ``open_file_status``
+
+	.. seealso::
+
+	   Matching :class:`Package Body <pyVHDLModel.STD.Standard_Body>` declaration.
+	"""
+
+	def __init__(self) -> None:
+		super().__init__()
+
+		boolean = EnumeratedType("boolean", (EnumerationLiteral("false"), EnumerationLiteral("true")), None)
+		self._types[boolean._normalizedIdentifier] = boolean
+		self._declaredItems.append(boolean)
+
+		bit = EnumeratedType("bit", (EnumerationLiteral("'0'"), EnumerationLiteral("'1'")), None)
+		self._types[bit._normalizedIdentifier] = bit
+		self._declaredItems.append(bit)
+
+		chars = \
+			"nul", "soh", "stx", "etx", "eot", "enq", "ack", "bel", "bs", "ht", "lf", "vt", "ff", "cr", "so", "si", "dle", "dc1", "dc2", "dc3",\
+			"dc4", "nak", "syn", "etb", "can", "em", "sub", "esc", "fsp", "gsp", "rsp", "usp", "' '", "'!'", "'\"'", "'#'", "'$'", "'%'", "'&'", "'''",\
+			"'('", "')'", "'*'", "'+'", "','", "'-'", "'.'", "'/'", "'0'", "'1'", "'2'", "'3'", "'4'", "'5'", "'6'", "'7'", "'8'", "'9'", "':'", "';'",\
+			"'<'", "'='", "'>'", "'?'", "'@'", "'A'", "'B'", "'C'", "'D'", "'E'", "'F'", "'G'", "'H'", "'I'", "'J'", "'K'", "'L'", "'M'", "'N'", "'O'",\
+			"'P'", "'Q'", "'R'", "'S'", "'T'", "'U'", "'V'", "'W'", "'X'", "'Y'", "'Z'", "'['", "'\'", "']'", "'^'", "'_'", "'`'", "'a'", "'b'", "'c'",\
+			"'d'", "'e'", "'f'", "'g'", "'h'", "'i'", "'j'", "'k'", "'l'", "'m'", "'n'", "'o'", "'p'", "'q'", "'r'", "'s'", "'t'", "'u'", "'v'", "'w'",\
+			"'x'", "'y'", "'z'", "'{'", "'|'", "'}'", "'~'", "del", "c128", "c129", "c130", "c131", "c132", "c133", "c134", "c135", "c136", "c137", "c138", "c139",\
+			"c140", "c141", "c142", "c143", "c144", "c145", "c146", "c147", "c148", "c149", "c150", "c151", "c152", "c153", "c154", "c155", "c156", "c157", "c158", "c159",\
+			"' '", "'¡'", "'¢'", "'£'", "'¤'", "'¥'", "'¦'", "'§'", "'¨'", "'©'", "'ª'", "'«'", "'¬'", "'­'", "'®'", "'¯'", "'°'", "'±'", "'²'", "'³'",\
+			"'´'", "'µ'", "'¶'", "'·'", "'¸'", "'¹'", "'º'", "'»'", "'¼'", "'½'", "'¾'", "'¿'", "'À'", "'Á'", "'Â'", "'Ã'", "'Ä'", "'Å'", "'Æ'", "'Ç'",\
+			"'È'", "'É'", "'Ê'", "'Ë'", "'Ì'", "'Í'", "'Î'", "'Ï'", "'Ð'", "'Ñ'", "'Ò'", "'Ó'", "'Ô'", "'Õ'", "'Ö'", "'×'", "'Ø'", "'Ù'", "'Ú'", "'Û'",\
+			"'Ü'", "'Ý'", "'Þ'", "'ß'", "'à'", "'á'", "'â'", "'ã'", "'ä'", "'å'", "'æ'", "'ç'", "'è'", "'é'", "'ê'", "'ë'", "'ì'", "'í'", "'î'", "'ï'",\
+			"'ð'", "'ñ'", "'ò'", "'ó'", "'ô'", "'õ'", "'ö'", "'÷'", "'ø'", "'ù'", "'ú'", "'û'", "'ü'", "'ý'", "'þ'", "'ÿ'"
+		character = EnumeratedType("character", [EnumerationLiteral(char) for char in chars], None)
+		self._types[character._normalizedIdentifier] = character
+		self._declaredItems.append(character)
+
+		levels = "note", "warning", "error", "failure"
+		severityLevel = EnumeratedType("severityLevel", [EnumerationLiteral(level) for level in levels], None)
+		self._types[severityLevel._normalizedIdentifier] = severityLevel
+		self._declaredItems.append(severityLevel)
+
+		integer = IntegerType("integer", Range(IntegerLiteral(-2**31), IntegerLiteral(2**31 - 1), Direction.To), None)
+		self._types[integer._normalizedIdentifier] = integer
+		self._declaredItems.append(integer)
+
+		# real
+
+		time = PhysicalType("time", Range(IntegerLiteral(-2**63), IntegerLiteral(2**63 - 1), Direction.To), primaryUnit="fs", units=(
+			("ps", PhysicalIntegerLiteral(1000, "fs")),
+			("ns", PhysicalIntegerLiteral(1000, "ps")),
+			("us", PhysicalIntegerLiteral(1000, "ns")),
+			("ms", PhysicalIntegerLiteral(1000, "us")),
+			("sec", PhysicalIntegerLiteral(1000, "ms")),
+			("min", PhysicalIntegerLiteral(60, "sec")),
+			("hr", PhysicalIntegerLiteral(60, "min")),
+		), parent=None)
+		self._types[time._normalizedIdentifier] = time
+		self._declaredItems.append(time)
+
+		# delay_length
+
+		# now
+
+		natural = Subtype("natural", SimpleSubtypeSymbol(SimpleName("integer")), None)
+		natural._baseType = integer
+		natural._range = Range(IntegerLiteral(0), IntegerLiteral(2**31 - 1), Direction.To)
+		self._subtypes[natural._normalizedIdentifier] = natural
+		self._declaredItems.append(natural)
+
+		positive = Subtype("positive", SimpleSubtypeSymbol(SimpleName("integer")), None)
+		positive._baseType = integer
+		positive._range = Range(IntegerLiteral(1), IntegerLiteral(2**31 - 1), Direction.To)
+		self._subtypes[positive._normalizedIdentifier] = positive
+		self._declaredItems.append(positive)
+
+		string = ArrayType("string", (SimpleSubtypeSymbol(SimpleName("positive")),), SimpleSubtypeSymbol(SimpleName("character")), None)
+		self._types[string._normalizedIdentifier] = string
+		self._declaredItems.append(string)
+
+		booleanVector = ArrayType("boolean_vector", (SimpleSubtypeSymbol(SimpleName("natural")),), SimpleSubtypeSymbol(SimpleName("boolean")), None)
+		self._types[booleanVector._normalizedIdentifier] = booleanVector
+		self._declaredItems.append(booleanVector)
+
+		bitVector = ArrayType("bit_vector", (SimpleSubtypeSymbol(SimpleName("natural")),), SimpleSubtypeSymbol(SimpleName("bit")), None)
+		self._types[bitVector._normalizedIdentifier] = bitVector
+		self._declaredItems.append(bitVector)
+
+		integerVector = ArrayType("integer_vector", (SimpleSubtypeSymbol(SimpleName("natural")),), SimpleSubtypeSymbol(SimpleName("integer")), None)
+		self._types[integerVector._normalizedIdentifier] = integerVector
+		self._declaredItems.append(integerVector)
+
+		# real_vector
+
+		timeVector = ArrayType("time_vector", (SimpleSubtypeSymbol(SimpleName("natural")),), SimpleSubtypeSymbol(SimpleName("time")), None)
+		self._types[timeVector._normalizedIdentifier] = timeVector
+		self._declaredItems.append(timeVector)
+
+		fileOpenKinds = "read_mode", "write_mode", "append_mode"
+		openFileKind = EnumeratedType("open_file_kind", [EnumerationLiteral(kind) for kind in fileOpenKinds], None)
+		self._types[openFileKind._normalizedIdentifier] = openFileKind
+		self._declaredItems.append(openFileKind)
+
+		fileOpenStati = "open_ok", "status_error", "name_error", "mode_error"
+		fileOpenStatus = EnumeratedType("open_file_status", [EnumerationLiteral(status) for status in fileOpenStati], None)
+		self._types[fileOpenStatus._normalizedIdentifier] = fileOpenStatus
+		self._declaredItems.append(fileOpenStatus)
+
+		# attribute foreign
+
+
+@export
+class Standard_Body(PredefinedPackageBody):
+	"""
+	Predefined package body of package ``std.standard``.
+
+	.. seealso::
+
+	   Matching :class:`Package <pyVHDLModel.STD.Standard>` declaration.
+	"""
+
+
+@export
+class TextIO(PredefinedPackage):
+	"""
+	Predefined package ``std.textio``.
+
+	.. seealso::
+
+	   Matching :class:`Package Body <pyVHDLModel.STD.TextIO_Body>` declaration.
+	"""
+
+
+@export
+class TextIO_Body(PredefinedPackageBody):
+	"""
+	Predefined package body of package ``std.textio``.
+
+	.. seealso::
+
+	   Matching :class:`Package <pyVHDLModel.STD.TextIO>` declaration.
+	"""
+
+
+@export
+class Env(PredefinedPackage):
+	"""
+	Predefined package ``std.env``.
+
+	.. seealso::
+
+	   Matching :class:`Package Body <pyVHDLModel.STD.Env_Body>` declaration.
+	"""
+
+	def __init__(self) -> None:
+		super().__init__()
+
+		self._AddPackageClause(("work.textio.all",))
+
+
+@export
+class Env_Body(PredefinedPackageBody):
+	"""
+	Predefined package body of package ``std.env``.
+
+	.. seealso::
+
+	   Matching :class:`Package <pyVHDLModel.STD.Env>` declaration.
+	"""
+
+
+PACKAGES = (
+	(Standard, Standard_Body),
+	(TextIO, TextIO_Body),
+	(Env, Env_Body),
+)
+
+ + diff --git a/typing/html/pyVHDLModel/Sequential.py.html b/typing/html/pyVHDLModel/Sequential.py.html new file mode 100644 index 000000000..fbee07366 --- /dev/null +++ b/typing/html/pyVHDLModel/Sequential.py.html @@ -0,0 +1,1063 @@ + + + + + + +

pyVHDLModel.Sequential

+ + + + + + +
pyVHDLModel/Sequential.py
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+
# ==================================================================================================================== #
+#             __     ___   _ ____  _     __  __           _      _                                                     #
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |                                                    #
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |                                                    #
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |                                                    #
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|                                                    #
+#  |_|    |___/                                                                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""
+This module contains parts of an abstract document language model for VHDL.
+
+Declarations for sequential statements.
+"""
+from typing                  import List, Iterable, Optional as Nullable
+
+from pyTooling.Decorators    import export, readonly
+from pyTooling.MetaClasses   import ExtendedType
+
+from pyVHDLModel.Base        import ModelEntity, ExpressionUnion, Range, BaseChoice, BaseCase, ConditionalMixin, IfBranchMixin, ElsifBranchMixin
+from pyVHDLModel.Base        import ElseBranchMixin, ReportStatementMixin, AssertStatementMixin, WaveformElement
+from pyVHDLModel.Symbol      import Symbol
+from pyVHDLModel.Common      import Statement, ProcedureCallMixin
+from pyVHDLModel.Common      import SignalAssignmentMixin, VariableAssignmentMixin
+from pyVHDLModel.Association import ParameterAssociationItem
+
+
+@export
+class SequentialStatement(Statement):
+	"""A ``SequentialStatement`` is a base-class for all sequential statements."""
+
+
+@export
+class SequentialStatementsMixin(metaclass=ExtendedType, mixin=True):
+	_statements: List[SequentialStatement]
+
+	def __init__(self, statements: Nullable[Iterable[SequentialStatement]] = None) -> None:
+		# TODO: extract to mixin
+		self._statements = []
+		if statements is not None:
+			for item in statements:
+				self._statements.append(item)
+				item._parent = self
+
+	@readonly
+	def Statements(self) -> List[SequentialStatement]:
+		"""
+		Read-only property to access the list of sequential statements (:attr:`_statements`).
+
+		:returns: A list of sequential statements.
+		"""
+		return self._statements
+
+
+@export
+class SequentialProcedureCall(SequentialStatement, ProcedureCallMixin):
+	def __init__(
+		self,
+		procedureName: Symbol,
+		parameterMappings: Nullable[Iterable[ParameterAssociationItem]] = None,
+		label: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(label, parent)
+		ProcedureCallMixin.__init__(self, procedureName, parameterMappings)
+
+
+@export
+class SequentialSignalAssignment(SequentialStatement, SignalAssignmentMixin):
+	def __init__(self, target: Symbol, label: Nullable[str] = None, parent: ModelEntity = None) -> None:
+		super().__init__(label, parent)
+		SignalAssignmentMixin.__init__(self, target)
+
+
+@export
+class SequentialSimpleSignalAssignment(SequentialSignalAssignment):
+	_waveform: List[WaveformElement]
+
+	def __init__(self, target: Symbol, waveform: Iterable[WaveformElement], label: Nullable[str] = None, parent: ModelEntity = None) -> None:
+		super().__init__(target, label, parent)
+
+		# TODO: extract to mixin
+		self._waveform = []
+		if waveform is not None:
+			for waveformElement in waveform:
+				self._waveform.append(waveformElement)
+				waveformElement._parent = self
+
+	@readonly
+	def Waveform(self) -> List[WaveformElement]:
+		"""
+		Read-only property to access the list waveform elements (:attr:`_waveform`).
+
+		:returns: A list of waveform elements.
+		"""
+		return self._waveform
+
+
+@export
+class SequentialVariableAssignment(SequentialStatement, VariableAssignmentMixin):
+	def __init__(self, target: Symbol, expression: ExpressionUnion, label: Nullable[str] = None, parent: ModelEntity = None) -> None:
+		super().__init__(label, parent)
+		VariableAssignmentMixin.__init__(self, target, expression)
+
+
+@export
+class SequentialReportStatement(SequentialStatement, ReportStatementMixin):
+	def __init__(self, message: ExpressionUnion, severity: Nullable[ExpressionUnion] = None, label: Nullable[str] = None, parent: ModelEntity = None) -> None:
+		super().__init__(label, parent)
+		ReportStatementMixin.__init__(self, message, severity)
+
+
+@export
+class SequentialAssertStatement(SequentialStatement, AssertStatementMixin):
+	def __init__(
+		self,
+		condition: ExpressionUnion,
+		message: Nullable[ExpressionUnion] = None,
+		severity: Nullable[ExpressionUnion] = None,
+		label: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(label, parent)
+		AssertStatementMixin.__init__(self, condition, message, severity)
+
+
+@export
+class CompoundStatement(SequentialStatement):
+	"""A ``CompoundStatement`` is a base-class for all compound statements."""
+
+
+@export
+class Branch(ModelEntity, SequentialStatementsMixin):
+	"""A ``Branch`` is a base-class for all branches in a if statement."""
+
+	def __init__(self, statements: Nullable[Iterable[SequentialStatement]] = None, parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+		SequentialStatementsMixin.__init__(self, statements)
+
+
+@export
+class IfBranch(Branch, IfBranchMixin):
+	def __init__(self, condition: ExpressionUnion, statements: Nullable[Iterable[SequentialStatement]] = None, parent: ModelEntity = None) -> None:
+		super().__init__(statements, parent)
+		IfBranchMixin.__init__(self, condition)
+
+
+@export
+class ElsifBranch(Branch, ElsifBranchMixin):
+	def __init__(self, condition: ExpressionUnion, statements: Nullable[Iterable[SequentialStatement]] = None, parent: ModelEntity = None) -> None:
+		super().__init__(statements, parent)
+		ElsifBranchMixin.__init__(self, condition)
+
+
+@export
+class ElseBranch(Branch, ElseBranchMixin):
+	def __init__(self, statements: Nullable[Iterable[SequentialStatement]] = None, parent: ModelEntity = None) -> None:
+		super().__init__(statements, parent)
+		ElseBranchMixin.__init__(self)
+
+
+@export
+class IfStatement(CompoundStatement):
+	_ifBranch: IfBranch
+	_elsifBranches: List['ElsifBranch']
+	_elseBranch: Nullable[ElseBranch]
+
+	def __init__(
+		self,
+		ifBranch: IfBranch,
+		elsifBranches: Nullable[Iterable[ElsifBranch]] = None,
+		elseBranch: Nullable[ElseBranch] = None,
+		label: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(label, parent)
+
+		self._ifBranch = ifBranch
+		ifBranch._parent = self
+
+		self._elsifBranches = []
+		if elsifBranches is not None:
+			for branch in elsifBranches:
+				self._elsifBranches.append(branch)
+				branch._parent = self
+
+		if elseBranch is not None:
+			self._elseBranch = elseBranch
+			elseBranch._parent = self
+		else:
+			self._elseBranch = None
+
+	@readonly
+	def IfBranch(self) -> IfBranch:
+		"""
+		Read-only property to access the if-branch of the if-statement (:attr:`_ifBranch`).
+
+		:returns: The if-branch.
+		"""
+		return self._ifBranch
+
+	@property
+	def ElsIfBranches(self) -> List['ElsifBranch']:
+		"""
+		Read-only property to access the elsif-branch of the if-statement (:attr:`_elsifBranch`).
+
+		:returns: The elsif-branch.
+		"""
+		return self._elsifBranches
+
+	@property
+	def ElseBranch(self) -> Nullable[ElseBranch]:
+		"""
+		Read-only property to access the else-branch of the if-statement (:attr:`_elseBranch`).
+
+		:returns: The else-branch.
+		"""
+		return self._elseBranch
+
+
+@export
+class SequentialChoice(BaseChoice):
+	"""A ``SequentialChoice`` is a base-class for all sequential choices (in case statements)."""
+
+
+@export
+class IndexedChoice(SequentialChoice):
+	_expression: ExpressionUnion
+
+	def __init__(self, expression: ExpressionUnion, parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+
+		self._expression = expression
+		# expression._parent = self    # FIXME: received None
+
+	@property
+	def Expression(self) -> ExpressionUnion:
+		return self._expression
+
+	def __str__(self) -> str:
+		return str(self._expression)
+
+
+@export
+class RangedChoice(SequentialChoice):
+	_range: 'Range'
+
+	def __init__(self, rng: 'Range', parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+
+		self._range = rng
+		rng._parent = self
+
+	@property
+	def Range(self) -> 'Range':
+		return self._range
+
+	def __str__(self) -> str:
+		return str(self._range)
+
+
+@export
+class SequentialCase(BaseCase, SequentialStatementsMixin):
+	_choices: List
+
+	def __init__(self, statements: Nullable[Iterable[SequentialStatement]] = None, parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+		SequentialStatementsMixin.__init__(self, statements)
+
+		# TODO: what about choices?
+
+	@property
+	def Choices(self) -> List[BaseChoice]:
+		return self._choices
+
+
+@export
+class Case(SequentialCase):
+	def __init__(self, choices: Iterable[SequentialChoice], statements: Nullable[Iterable[SequentialStatement]] = None, parent: ModelEntity = None) -> None:
+		super().__init__(statements, parent)
+
+		self._choices = []
+		if choices is not None:
+			for choice in choices:
+				self._choices.append(choice)
+				choice._parent = self
+
+	@property
+	def Choices(self) -> List[SequentialChoice]:
+		return self._choices
+
+	def __str__(self) -> str:
+		return "when {choices} =>".format(choices=" | ".join(str(c) for c in self._choices))
+
+
+@export
+class OthersCase(SequentialCase):
+	def __str__(self) -> str:
+		return "when others =>"
+
+
+@export
+class CaseStatement(CompoundStatement):
+	_expression: ExpressionUnion
+	_cases:      List[SequentialCase]
+
+	def __init__(self, expression: ExpressionUnion, cases: Iterable[SequentialCase], label: Nullable[str] = None, parent: ModelEntity = None) -> None:
+		super().__init__(label, parent)
+
+		self._expression = expression
+		expression._parent = self
+
+		self._cases = []
+		if cases is not None:
+			for case in cases:
+				self._cases.append(case)
+				case._parent = self
+
+	@property
+	def SelectExpression(self) -> ExpressionUnion:
+		return self._expression
+
+	@property
+	def Cases(self) -> List[SequentialCase]:
+		return self._cases
+
+
+@export
+class LoopStatement(CompoundStatement, SequentialStatementsMixin):
+	"""A ``LoopStatement`` is a base-class for all loop statements."""
+
+	def __init__(self, statements: Nullable[Iterable[SequentialStatement]] = None, label: Nullable[str] = None, parent: ModelEntity = None) -> None:
+		super().__init__(label, parent)
+		SequentialStatementsMixin.__init__(self, statements)
+
+
+@export
+class EndlessLoopStatement(LoopStatement):
+	pass
+
+
+@export
+class ForLoopStatement(LoopStatement):
+	_loopIndex: str
+	_range:     Range
+
+	def __init__(self, loopIndex: str, rng: Range, statements: Nullable[Iterable[SequentialStatement]] = None, label: Nullable[str] = None, parent: ModelEntity = None) -> None:
+		super().__init__(statements, label, parent)
+
+		self._loopIndex = loopIndex
+
+		self._range = rng
+		rng._parent = self
+
+	@property
+	def LoopIndex(self) -> str:
+		return self._loopIndex
+
+	@property
+	def Range(self) -> Range:
+		return self._range
+
+
+@export
+class WhileLoopStatement(LoopStatement, ConditionalMixin):
+	def __init__(
+		self,
+		condition: ExpressionUnion,
+		statements: Nullable[Iterable[SequentialStatement]] = None,
+		label: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(statements, label, parent)
+		ConditionalMixin.__init__(self, condition)
+
+
+@export
+class LoopControlStatement(SequentialStatement, ConditionalMixin):
+	"""A ``LoopControlStatement`` is a base-class for all loop controlling statements."""
+
+	_loopReference: LoopStatement
+
+	def __init__(self, condition: Nullable[ExpressionUnion] = None, loopLabel: Nullable[str] = None, parent: ModelEntity = None) -> None:  # TODO: is this label (currently str) a Name or a Label class?
+		super().__init__(parent)
+		ConditionalMixin.__init__(self, condition)
+
+		# TODO: loopLabel
+		# TODO: loop reference -> is it a symbol?
+
+	@property
+	def LoopReference(self) -> LoopStatement:
+		return self._loopReference
+
+
+@export
+class NextStatement(LoopControlStatement):
+	pass
+
+
+@export
+class ExitStatement(LoopControlStatement):
+	pass
+
+
+@export
+class NullStatement(SequentialStatement):
+	pass
+
+
+@export
+class ReturnStatement(SequentialStatement, ConditionalMixin):
+	_returnValue: ExpressionUnion
+
+	def __init__(self, returnValue: Nullable[ExpressionUnion] = None, parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+		ConditionalMixin.__init__(self, returnValue)
+
+		# TODO: return value?
+
+	@property
+	def ReturnValue(self) -> ExpressionUnion:
+		return self._returnValue
+
+
+@export
+class WaitStatement(SequentialStatement, ConditionalMixin):
+	_sensitivityList: Nullable[List[Symbol]]
+	_timeout:         ExpressionUnion
+
+	def __init__(
+		self,
+		sensitivityList: Nullable[Iterable[Symbol]] = None,
+		condition: Nullable[ExpressionUnion] = None,
+		timeout: Nullable[ExpressionUnion] = None,
+		label: Nullable[str] = None,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(label, parent)
+		ConditionalMixin.__init__(self, condition)
+
+		if sensitivityList is None:
+			self._sensitivityList = None
+		else:
+			self._sensitivityList = []  # TODO: convert to dict
+			for signalSymbol in sensitivityList:
+				self._sensitivityList.append(signalSymbol)
+				signalSymbol._parent = self
+
+		self._timeout = timeout
+		if timeout is not None:
+			timeout._parent = self
+
+	@property
+	def SensitivityList(self) -> List[Symbol]:
+		return self._sensitivityList
+
+	@property
+	def Timeout(self) -> ExpressionUnion:
+		return self._timeout
+
+
+@export
+class SequentialDeclarationsMixin(metaclass=ExtendedType, mixin=True):
+	_declaredItems: List
+
+	def __init__(self, declaredItems: Iterable) -> None:
+		# TODO: extract to mixin
+		self._declaredItems = []  # TODO: convert to dict
+		if declaredItems is not None:
+			for item in declaredItems:
+				self._declaredItems.append(item)
+				item._parent = self
+
+	@property
+	def DeclaredItems(self) -> List:
+		return self._declaredItems
+
+ + diff --git a/typing/html/pyVHDLModel/Subprogram.py.html b/typing/html/pyVHDLModel/Subprogram.py.html new file mode 100644 index 000000000..feb65b257 --- /dev/null +++ b/typing/html/pyVHDLModel/Subprogram.py.html @@ -0,0 +1,299 @@ + + + + + + +

pyVHDLModel.Subprogram

+ + + + + + +
pyVHDLModel/Subprogram.py
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+
# ==================================================================================================================== #
+#             __     ___   _ ____  _     __  __           _      _                                                     #
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |                                                    #
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |                                                    #
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |                                                    #
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|                                                    #
+#  |_|    |___/                                                                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""
+This module contains parts of an abstract document language model for VHDL.
+
+Subprograms are procedures, functions and methods.
+"""
+from typing                 import List, Optional as Nullable
+
+from pyTooling.Decorators   import export, readonly
+from pyTooling.MetaClasses  import ExtendedType
+
+from pyVHDLModel.Base       import ModelEntity, NamedEntityMixin, DocumentedEntityMixin
+from pyVHDLModel.Type       import Subtype, ProtectedType
+from pyVHDLModel.Sequential import SequentialStatement
+
+
+@export
+class Subprogram(ModelEntity, NamedEntityMixin, DocumentedEntityMixin):
+	_genericItems:   List['GenericInterfaceItem']
+	_parameterItems: List['ParameterInterfaceItem']
+	_declaredItems:  List
+	_statements:     List['SequentialStatement']
+	_isPure:         bool
+
+	def __init__(self, identifier: str, isPure: bool, documentation: Nullable[str] = None, parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+		NamedEntityMixin.__init__(self, identifier)
+		DocumentedEntityMixin.__init__(self, documentation)
+
+		self._genericItems =    []  # TODO: convert to dict
+		self._parameterItems =  []  # TODO: convert to dict
+		self._declaredItems =   []  # TODO: use mixin class
+		self._statements =      []  # TODO: use mixin class
+		self._isPure =          isPure
+
+	@readonly
+	def GenericItems(self) -> List['GenericInterfaceItem']:
+		return self._genericItems
+
+	@readonly
+	def ParameterItems(self) -> List['ParameterInterfaceItem']:
+		return self._parameterItems
+
+	@readonly
+	def DeclaredItems(self) -> List:
+		return self._declaredItems
+
+	@readonly
+	def Statements(self) -> List['SequentialStatement']:
+		return self._statements
+
+	@readonly
+	def IsPure(self) -> bool:
+		return self._isPure
+
+
+@export
+class Procedure(Subprogram):
+	def __init__(self, identifier: str, documentation: Nullable[str] = None, parent: ModelEntity = None) -> None:
+		super().__init__(identifier, False, documentation, parent)
+
+
+@export
+class Function(Subprogram):
+	_returnType: Subtype
+
+	def __init__(self, identifier: str, isPure: bool = True, documentation: Nullable[str] = None, parent: ModelEntity = None) -> None:
+		super().__init__(identifier, isPure, documentation, parent)
+
+		# FIXME: return type is missing
+
+	@readonly
+	def ReturnType(self) -> Subtype:
+		return self._returnType
+
+
+@export
+class MethodMixin(metaclass=ExtendedType, mixin=True):
+	"""A ``Method`` is a mixin class for all subprograms in a protected type."""
+
+	_protectedType: ProtectedType
+
+	def __init__(self, protectedType: ProtectedType) -> None:
+		self._protectedType = protectedType
+		protectedType._parent = self
+
+	@readonly
+	def ProtectedType(self) -> ProtectedType:
+		return self._protectedType
+
+
+@export
+class ProcedureMethod(Procedure, MethodMixin):
+	def __init__(self, identifier: str, documentation: Nullable[str] = None, protectedType: Nullable[ProtectedType] = None, parent: ModelEntity = None) -> None:
+		super().__init__(identifier, documentation, parent)
+		MethodMixin.__init__(self, protectedType)
+
+
+@export
+class FunctionMethod(Function, MethodMixin):
+	def __init__(self, identifier: str, isPure: bool = True, documentation: Nullable[str] = None, protectedType: Nullable[ProtectedType] = None, parent: ModelEntity = None) -> None:
+		super().__init__(identifier, isPure, documentation, parent)
+		MethodMixin.__init__(self, protectedType)
+
+ + diff --git a/typing/html/pyVHDLModel/Symbol.py.html b/typing/html/pyVHDLModel/Symbol.py.html new file mode 100644 index 000000000..e11ae2db6 --- /dev/null +++ b/typing/html/pyVHDLModel/Symbol.py.html @@ -0,0 +1,1035 @@ + + + + + + +

pyVHDLModel.Symbol

+ + + + + + +
pyVHDLModel/Symbol.py
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+
# ==================================================================================================================== #
+#             __     ___   _ ____  _     __  __           _      _                                                     #
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |                                                    #
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |                                                    #
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |                                                    #
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|                                                    #
+#  |_|    |___/                                                                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""
+This module contains parts of an abstract document language model for VHDL.
+
+Symbols are entity specific wrappers for names that reference VHDL language entities.
+"""
+from enum                  import Flag, auto
+from typing                import Any, Optional as Nullable, Iterable, List, Dict, Mapping
+
+from pyTooling.Decorators  import export, readonly
+from pyTooling.MetaClasses import ExtendedType
+
+from pyVHDLModel.Base      import Range
+from pyVHDLModel.Name      import Name, AllName
+
+
+@export
+class PossibleReference(Flag):
+	"""
+	Is an enumeration, representing possible targets for a reference in a :class:`~pyVHDLModel.Symbol`.
+	"""
+
+	Unknown =         0
+	Library =         auto()  #: Library
+	Entity =          auto()  #: Entity
+	Architecture =    auto()  #: Architecture
+	Component =       auto()  #: Component
+	Package =         auto()  #: Package
+	Configuration =   auto()  #: Configuration
+	Context =         auto()  #: Context
+	Type =            auto()  #: Type
+	Subtype =         auto()  #: Subtype
+	ScalarType =      auto()  #: ScalarType
+	ArrayType =       auto()  #: ArrayType
+	RecordType =      auto()  #: RecordType
+	RecordElement =   auto()  #: RecordElement
+	AccessType =      auto()  #: AccessType
+	ProtectedType =   auto()  #: ProtectedType
+	FileType =        auto()  #: FileType
+#	Alias =           auto()   # TODO: Is this needed?
+	Attribute =       auto()  #: Attribute
+	TypeAttribute =   auto()  #: TypeAttribute
+	ValueAttribute =  auto()  #: ValueAttribute
+	SignalAttribute = auto()  #: SignalAttribute
+	RangeAttribute =  auto()  #: RangeAttribute
+	ViewAttribute =   auto()  #: ViewAttribute
+	Constant =        auto()  #: Constant
+	Variable =        auto()  #: Variable
+	Signal =          auto()  #: Signal
+	File =            auto()  #: File
+#	Object =          auto()   # TODO: Is this needed?
+	EnumLiteral =     auto()  #: EnumLiteral
+	Procedure =       auto()  #: Procedure
+	Function =        auto()  #: Function
+	Label =           auto()  #: Label
+	View =            auto()  #: View
+
+	AnyType = ScalarType | ArrayType | RecordType | ProtectedType | AccessType | FileType | Subtype  #: Any possible type incl. subtypes.
+	Object = Constant | Variable | Signal  # | File                                                     #: Any object
+	SubProgram = Procedure | Function                                                                #: Any subprogram
+	PackageMember = AnyType | Object | SubProgram | Component                                        #: Any member of a package
+	SimpleNameInExpression = Constant | Variable | Signal | ScalarType | EnumLiteral | Function      #: Any possible item in an expression.
+
+
+@export
+class Symbol(metaclass=ExtendedType):
+	"""
+	Base-class for all symbol classes.
+	"""
+
+	_name:               Name               #: The name to reference the langauge entity.
+	_possibleReferences: PossibleReference  #: An enumeration to filter possible references.
+	_reference:          Nullable[Any]      #: The resolved language entity, otherwise ``None``.
+
+	def __init__(self, name: Name, possibleReferences: PossibleReference) -> None:
+		self._name = name
+		self._possibleReferences = possibleReferences
+		self._reference = None
+
+	@readonly
+	def Name(self) -> Name:
+		return self._name
+
+	@readonly
+	def Reference(self) -> Nullable[Any]:
+		return self._reference
+
+	@readonly
+	def IsResolved(self) -> bool:
+		return self._reference is not None
+
+	def __bool__(self) -> bool:
+		return self._reference is not None
+
+	def __repr__(self) -> str:
+		if self._reference is not None:
+			return f"{self.__class__.__name__}: '{self._name!s}' -> {self._reference!s}"
+
+		return f"{self.__class__.__name__}: '{self._name!s}' -> unresolved"
+
+	def __str__(self) -> str:
+		if self._reference is not None:
+			return str(self._reference)
+
+		return f"{self._name!s}?"
+
+
+@export
+class LibraryReferenceSymbol(Symbol):
+	"""
+	Represents a reference (name) to a library.
+
+	The internal name will be a :class:`~pyVHDLModel.Name.SimpleName`.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      library ieee;
+	      --      ^^^^
+	"""
+
+	def __init__(self, name: Name) -> None:
+		super().__init__(name, PossibleReference.Library)
+
+	@readonly
+	def Library(self) -> Nullable['Library']:
+		return self._reference
+
+	@Library.setter
+	def Library(self, value: 'Library') -> None:
+		self._reference = value
+
+
+@export
+class PackageReferenceSymbol(Symbol):
+	"""
+	Represents a reference (name) to a package.
+
+	The internal name will be a :class:`~pyVHDLModel.Name.SelectedName`.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      use ieee.numeric_std;
+	      --  ^^^^^^^^^^^^^^^^
+	"""
+
+	def __init__(self, name: Name) -> None:
+		super().__init__(name, PossibleReference.Package)
+
+	@property
+	def Package(self) -> Nullable['Package']:
+		return self._reference
+
+	@Package.setter
+	def Package(self, value: 'Package') -> None:
+		self._reference = value
+
+
+@export
+class ContextReferenceSymbol(Symbol):
+	"""
+	Represents a reference (name) to a context.
+
+	The internal name will be a :class:`~pyVHDLModel.Name.SelectedName`.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      context ieee.ieee_std_context;
+	      --      ^^^^^^^^^^^^^^^^^^^^^
+	"""
+
+	def __init__(self, name: Name) -> None:
+		super().__init__(name, PossibleReference.Context)
+
+	@property
+	def Context(self) -> 'Context':
+		return self._reference
+
+	@Context.setter
+	def Context(self, value: 'Context') -> None:
+		self._reference = value
+
+
+@export
+class PackageMemberReferenceSymbol(Symbol):
+	"""
+	Represents a reference (name) to a package member.
+
+	The internal name will be a :class:`~pyVHDLModel.Name.SelectedName`.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      use ieee.numeric_std.unsigned;
+	      --  ^^^^^^^^^^^^^^^^^^^^^^^^^
+	"""
+
+	def __init__(self, name: Name) -> None:
+		super().__init__(name, PossibleReference.PackageMember)
+
+	@property
+	def Member(self) -> Nullable['Package']:  # TODO: typehint
+		return self._reference
+
+	@Member.setter
+	def Member(self, value: 'Package') -> None:  # TODO: typehint
+		self._reference = value
+
+
+@export
+class AllPackageMembersReferenceSymbol(Symbol):
+	"""
+	Represents a reference (name) to all package members.
+
+	The internal name will be a :class:`~pyVHDLModel.Name.AllName`.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      use ieee.numeric_std.all;
+	      --  ^^^^^^^^^^^^^^^^^^^^
+	"""
+
+	def __init__(self, name: AllName) -> None:
+		super().__init__(name, PossibleReference.PackageMember)
+
+	@property
+	def Members(self) -> 'Package':  # TODO: typehint
+		return self._reference
+
+	@Members.setter
+	def Members(self, value: 'Package') -> None:  # TODO: typehint
+		self._reference = value
+
+
+@export
+class EntityInstantiationSymbol(Symbol):
+	"""
+	Represents a reference (name) to an entity in a direct entity instantiation.
+
+	The internal name will be a :class:`~pyVHDLModel.Name.SimpleName` or :class:`~pyVHDLModel.Name.SelectedName`.
+
+	.. admonition:: Example
+
+	    .. code-block:: VHDL
+
+	       inst : entity work.Counter;
+	       --            ^^^^^^^^^^^^
+	"""
+
+	def __init__(self, name: Name) -> None:
+		super().__init__(name, PossibleReference.Entity)
+
+	@property
+	def Entity(self) -> 'Entity':
+		return self._reference
+
+	@Entity.setter
+	def Entity(self, value: 'Entity') -> None:
+		self._reference = value
+
+
+@export
+class ComponentInstantiationSymbol(Symbol):
+	"""
+	Represents a reference (name) to an entity in a component instantiation.
+
+	The internal name will be a :class:`~pyVHDLModel.Name.SimpleName` or :class:`~pyVHDLModel.Name.SelectedName`.
+
+	.. admonition:: Example
+
+	    .. code-block:: VHDL
+
+	       inst : component Counter;
+	       --               ^^^^^^^
+	"""
+
+	def __init__(self, name: Name) -> None:
+		super().__init__(name, PossibleReference.Component)
+
+	@property
+	def Component(self) -> 'Component':
+		return self._reference
+
+	@Component.setter
+	def Component(self, value: 'Component') -> None:
+		self._reference = value
+
+
+@export
+class ConfigurationInstantiationSymbol(Symbol):
+	"""
+	Represents a reference (name) to an entity in a configuration instantiation.
+
+	The internal name will be a :class:`~pyVHDLModel.Name.SimpleName` or :class:`~pyVHDLModel.Name.SelectedName`.
+
+	.. admonition:: Example
+
+	    .. code-block:: VHDL
+
+	       inst : configuration Counter;
+	       --                   ^^^^^^^
+	"""
+
+	def __init__(self, name: Name) -> None:
+		super().__init__(name, PossibleReference.Configuration)
+
+	@property
+	def Configuration(self) -> 'Configuration':
+		return self._reference
+
+	@Configuration.setter
+	def Configuration(self, value: 'Configuration') -> None:
+		self._reference = value
+
+
+@export
+class EntitySymbol(Symbol):
+	"""
+	Represents a reference (name) to an entity in an architecture declaration.
+
+	The internal name will be a :class:`~pyVHDLModel.Name.SimpleName` or :class:`~pyVHDLModel.Name.SelectedName`.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      architecture rtl of Counter is
+	      --                  ^^^^^^^
+	      begin
+	      end architecture;
+	"""
+
+	def __init__(self, name: Name) -> None:
+		super().__init__(name, PossibleReference.Entity)
+
+	@property
+	def Entity(self) -> 'Entity':
+		return self._reference
+
+	@Entity.setter
+	def Entity(self, value: 'Entity') -> None:
+		self._reference = value
+
+
+@export
+class ArchitectureSymbol(Symbol):
+	"""An entity reference in an entity instantiation with architecture name."""
+
+	def __init__(self, name: Name) -> None:
+		super().__init__(name, PossibleReference.Architecture)
+
+	@property
+	def Architecture(self) -> 'Architecture':
+		return self._reference
+
+	@Architecture.setter
+	def Architecture(self, value: 'Architecture') -> None:
+		self._reference = value
+
+
+@export
+class PackageSymbol(Symbol):
+	"""
+	Represents a reference (name) to a package in a package body declaration.
+
+	The internal name will be a :class:`~pyVHDLModel.Name.SimpleName` or :class:`~pyVHDLModel.Name.SelectedName`.
+
+	.. admonition:: Example
+
+	   .. code-block:: VHDL
+
+	      package body Utilities is
+	      --           ^^^^^^^^^
+	      end package body;
+	"""
+
+	def __init__(self, name: Name) -> None:
+		super().__init__(name, PossibleReference.Package)
+
+	@property
+	def Package(self) -> 'Package':
+		return self._reference
+
+	@Package.setter
+	def Package(self, value: 'Package') -> None:
+		self._reference = value
+
+
+@export
+class RecordElementSymbol(Symbol):
+	def __init__(self, name: Name) -> None:
+		super().__init__(name, PossibleReference.RecordElement)
+
+
+@export
+class SubtypeSymbol(Symbol):
+	def __init__(self, name: Name) -> None:
+		super().__init__(name, PossibleReference.Type | PossibleReference.Subtype)
+
+	@property
+	def Subtype(self) -> 'Subtype':
+		return self._reference
+
+	@Subtype.setter
+	def Subtype(self, value: 'Subtype') -> None:
+		self._reference = value
+
+
+@export
+class SimpleSubtypeSymbol(SubtypeSymbol):
+	pass
+
+
+@export
+class ConstrainedScalarSubtypeSymbol(SubtypeSymbol):
+	pass
+
+
+@export
+class ConstrainedCompositeSubtypeSymbol(SubtypeSymbol):
+	pass
+
+
+@export
+class ConstrainedArraySubtypeSymbol(ConstrainedCompositeSubtypeSymbol):
+	pass
+
+
+@export
+class ConstrainedRecordSubtypeSymbol(ConstrainedCompositeSubtypeSymbol):
+	pass
+
+
+@export
+class SimpleObjectOrFunctionCallSymbol(Symbol):
+	def __init__(self, name: Name) -> None:
+		super().__init__(name, PossibleReference.SimpleNameInExpression)
+
+
+@export
+class IndexedObjectOrFunctionCallSymbol(Symbol):
+	def __init__(self, name: Name) -> None:
+		super().__init__(name, PossibleReference.Object | PossibleReference.Function)
+
+ + diff --git a/typing/html/pyVHDLModel/Type.py.html b/typing/html/pyVHDLModel/Type.py.html new file mode 100644 index 000000000..76f0ac573 --- /dev/null +++ b/typing/html/pyVHDLModel/Type.py.html @@ -0,0 +1,819 @@ + + + + + + +

pyVHDLModel.Type

+ + + + + + +
pyVHDLModel/Type.py
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+
# ==================================================================================================================== #
+#             __     ___   _ ____  _     __  __           _      _                                                     #
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |                                                    #
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |                                                    #
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |                                                    #
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|                                                    #
+#  |_|    |___/                                                                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""
+This module contains parts of an abstract document language model for VHDL.
+
+Types.
+"""
+from typing                 import Union, List, Iterator, Iterable, Tuple, Optional as Nullable, Dict, Mapping
+
+from pyTooling.Decorators   import export, readonly
+from pyTooling.MetaClasses  import ExtendedType
+from pyTooling.Graph        import Vertex
+
+from pyVHDLModel.Base       import ModelEntity, NamedEntityMixin, MultipleNamedEntityMixin, DocumentedEntityMixin, ExpressionUnion, Range
+from pyVHDLModel.Symbol     import Symbol
+from pyVHDLModel.Name       import Name
+from pyVHDLModel.Expression import EnumerationLiteral, PhysicalIntegerLiteral
+
+
+@export
+class BaseType(ModelEntity, NamedEntityMixin, DocumentedEntityMixin):
+	"""``BaseType`` is the base-class of all type entities in this model."""
+
+	_objectVertex: Vertex
+
+	def __init__(self, identifier: str, documentation: Nullable[str] = None, parent: ModelEntity = None) -> None:
+		"""
+		Initializes underlying ``BaseType``.
+
+		:param identifier: Name of the type.
+		:param parent:     Reference to the logical parent in the model hierarchy.
+		"""
+		super().__init__(parent)
+		NamedEntityMixin.__init__(self, identifier)
+		DocumentedEntityMixin.__init__(self, documentation)
+
+		_objectVertex = None
+
+
+@export
+class Type(BaseType):
+	pass
+
+
+@export
+class AnonymousType(Type):
+	pass
+
+
+@export
+class FullType(BaseType):
+	pass
+
+
+@export
+class Subtype(BaseType):
+	_type:               Symbol
+	_baseType:           BaseType
+	_range:              Range
+	_resolutionFunction: 'Function'
+
+	def __init__(self, identifier: str, symbol: Symbol, parent: ModelEntity = None) -> None:
+		super().__init__(identifier, parent)
+
+		self._type = symbol
+		self._baseType = None
+		self._range = None
+		self._resolutionFunction = None
+
+	@readonly
+	def Type(self) -> Symbol:
+		return self._type
+
+	@readonly
+	def BaseType(self) -> BaseType:
+		return self._baseType
+
+	@readonly
+	def Range(self) -> Range:
+		return self._range
+
+	@readonly
+	def ResolutionFunction(self) -> 'Function':
+		return self._resolutionFunction
+
+	def __str__(self) -> str:
+		return f"subtype {self._identifier} is {self._baseType}"
+
+
+@export
+class ScalarType(FullType):
+	"""A ``ScalarType`` is a base-class for all scalar types."""
+
+
+@export
+class RangedScalarType(ScalarType):
+	"""A ``RangedScalarType`` is a base-class for all scalar types with a range."""
+
+	_range:      Union[Range, Name]
+	_leftBound:  ExpressionUnion
+	_rightBound: ExpressionUnion
+
+	def __init__(self, identifier: str, rng: Union[Range, Name], parent: ModelEntity = None) -> None:
+		super().__init__(identifier, parent)
+		self._range = rng
+
+	@readonly
+	def Range(self) -> Union[Range, Name]:
+		return self._range
+
+
+@export
+class NumericTypeMixin(metaclass=ExtendedType, mixin=True):
+	"""A ``NumericType`` is a mixin class for all numeric types."""
+
+	def __init__(self) -> None:
+		pass
+
+
+@export
+class DiscreteTypeMixin(metaclass=ExtendedType, mixin=True):
+	"""A ``DiscreteType`` is a mixin class for all discrete types."""
+
+	def __init__(self) -> None:
+		pass
+
+
+@export
+class EnumeratedType(ScalarType, DiscreteTypeMixin):
+	_literals: List[EnumerationLiteral]
+
+	def __init__(self, identifier: str, literals: Iterable[EnumerationLiteral], parent: ModelEntity = None) -> None:
+		super().__init__(identifier, parent)
+
+		self._literals = []
+		if literals is not None:
+			for literal in literals:
+				self._literals.append(literal)
+				literal._parent = self
+
+	@readonly
+	def Literals(self) -> List[EnumerationLiteral]:
+		return self._literals
+
+	def __str__(self) -> str:
+		return f"{self._identifier} is ({', '.join(str(l) for l in self._literals)})"
+
+
+@export
+class IntegerType(RangedScalarType, NumericTypeMixin, DiscreteTypeMixin):
+	def __init__(self, identifier: str, rng: Union[Range, Name], parent: ModelEntity = None) -> None:
+		super().__init__(identifier, rng, parent)
+
+	def __str__(self) -> str:
+		return f"{self._identifier} is range {self._range}"
+
+
+@export
+class RealType(RangedScalarType, NumericTypeMixin):
+	def __init__(self, identifier: str, rng: Union[Range, Name], parent: ModelEntity = None) -> None:
+		super().__init__(identifier, rng, parent)
+
+	def __str__(self) -> str:
+		return f"{self._identifier} is range {self._range}"
+
+
+@export
+class PhysicalType(RangedScalarType, NumericTypeMixin):
+	_primaryUnit:    str
+	_secondaryUnits: List[Tuple[str, PhysicalIntegerLiteral]]
+
+	def __init__(
+		self,
+		identifier: str,
+		rng: Union[Range, Name],
+		primaryUnit: str,
+		units: Iterable[Tuple[str, PhysicalIntegerLiteral]],
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(identifier, rng, parent)
+
+		self._primaryUnit = primaryUnit
+
+		self._secondaryUnits = []  # TODO: convert to dict
+		for unit in units:
+			self._secondaryUnits.append(unit)
+			unit[1]._parent = self
+
+	@readonly
+	def PrimaryUnit(self) -> str:
+		return self._primaryUnit
+
+	@property
+	def SecondaryUnits(self) -> List[Tuple[str, PhysicalIntegerLiteral]]:
+		return self._secondaryUnits
+
+	def __str__(self) -> str:
+		return f"{self._identifier} is range {self._range} units {self._primaryUnit}; {'; '.join(su + ' = ' + str(pu) for su, pu in self._secondaryUnits)};"
+
+
+@export
+class CompositeType(FullType):
+	"""A ``CompositeType`` is a base-class for all composite types."""
+
+
+@export
+class ArrayType(CompositeType):
+	_dimensions:  List[Range]
+	_elementType: Symbol
+
+	def __init__(
+		self,
+		identifier: str,
+		indices: Iterable,
+		elementSubtype: Symbol,
+		parent: ModelEntity = None
+	) -> None:
+		super().__init__(identifier, parent)
+
+		self._dimensions = []
+		for index in indices:
+			self._dimensions.append(index)
+			# index._parent = self  # FIXME: indices are provided as empty list
+
+		self._elementType = elementSubtype
+		# elementSubtype._parent = self   # FIXME: subtype is provided as None
+
+	@property
+	def Dimensions(self) -> List[Range]:
+		return self._dimensions
+
+	@property
+	def ElementType(self) -> Symbol:
+		return self._elementType
+
+	def __str__(self) -> str:
+		return f"{self._identifier} is array({'; '.join(str(r) for r in self._dimensions)}) of {self._elementType}"
+
+
+@export
+class RecordTypeElement(ModelEntity, MultipleNamedEntityMixin):
+	_subtype: Symbol
+
+	def __init__(self, identifiers: Iterable[str], subtype: Symbol, parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+		MultipleNamedEntityMixin.__init__(self, identifiers)
+
+		self._subtype = subtype
+		subtype._parent = self
+
+	@property
+	def Subtype(self) -> Symbol:
+		return self._subtype
+
+	def __str__(self) -> str:
+		return f"{', '.join(self._identifiers)} : {self._subtype}"
+
+
+@export
+class RecordType(CompositeType):
+	_elements: List[RecordTypeElement]
+
+	def __init__(self, identifier: str, elements: Nullable[Iterable[RecordTypeElement]] = None, parent: ModelEntity = None) -> None:
+		super().__init__(identifier, parent)
+
+		self._elements = []  # TODO: convert to dict
+		if elements is not None:
+			for element in elements:
+				self._elements.append(element)
+				element._parent = self
+
+	@property
+	def Elements(self) -> List[RecordTypeElement]:
+		return self._elements
+
+	def __str__(self) -> str:
+		return f"{self._identifier} is record {'; '.join(str(re) for re in self._elements)};"
+
+
+@export
+class ProtectedType(FullType):
+	_methods: List[Union['Procedure', 'Function']]
+
+	def __init__(self, identifier: str, methods: Union[List, Iterator] = None, parent: ModelEntity = None) -> None:
+		super().__init__(identifier, parent)
+
+		self._methods = []
+		if methods is not None:
+			for method in methods:
+				self._methods.append(method)
+				method._parent = self
+
+	@property
+	def Methods(self) -> List[Union['Procedure', 'Function']]:
+		return self._methods
+
+
+@export
+class ProtectedTypeBody(FullType):
+	_methods: List[Union['Procedure', 'Function']]
+
+	def __init__(self, identifier: str, declaredItems: Union[List, Iterator] = None, parent: ModelEntity = None) -> None:
+		super().__init__(identifier, parent)
+
+		self._methods = []
+		if declaredItems is not None:
+			for method in declaredItems:
+				self._methods.append(method)
+				method._parent = self
+
+	# FIXME: needs to be declared items or so
+	@property
+	def Methods(self) -> List[Union['Procedure', 'Function']]:
+		return self._methods
+
+
+@export
+class AccessType(FullType):
+	_designatedSubtype: Symbol
+
+	def __init__(self, identifier: str, designatedSubtype: Symbol, parent: ModelEntity = None) -> None:
+		super().__init__(identifier, parent)
+
+		self._designatedSubtype = designatedSubtype
+		designatedSubtype._parent = self
+
+	@property
+	def DesignatedSubtype(self):
+		return self._designatedSubtype
+
+	def __str__(self) -> str:
+		return f"{self._identifier} is access {self._designatedSubtype}"
+
+
+@export
+class FileType(FullType):
+	_designatedSubtype: Symbol
+
+	def __init__(self, identifier: str, designatedSubtype: Symbol, parent: ModelEntity = None) -> None:
+		super().__init__(identifier, parent)
+
+		self._designatedSubtype = designatedSubtype
+		designatedSubtype._parent = self
+
+	@property
+	def DesignatedSubtype(self):
+		return self._designatedSubtype
+
+	def __str__(self) -> str:
+		return f"{self._identifier} is access {self._designatedSubtype}"
+
+ + diff --git a/typing/html/pyVHDLModel/__init__.py.html b/typing/html/pyVHDLModel/__init__.py.html new file mode 100644 index 000000000..8c1731e55 --- /dev/null +++ b/typing/html/pyVHDLModel/__init__.py.html @@ -0,0 +1,5577 @@ + + + + + + +

pyVHDLModel

+ + + + + + +
pyVHDLModel/__init__.py
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+
# ==================================================================================================================== #
+#             __     ___   _ ____  _     __  __           _      _                                                     #
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |                                                    #
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |                                                    #
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |                                                    #
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|                                                    #
+#  |_|    |___/                                                                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany                                                               #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""
+**An abstract VHDL language model.**
+
+This package provides a unified abstract language model for VHDL. Projects reading from source files can derive own
+classes and implement additional logic to create a concrete language model for their tools.
+
+Projects consuming pre-processed VHDL data (parsed, analyzed or elaborated) can build higher level features and services
+on such a model, while supporting multiple frontends.
+
+.. admonition:: Copyright Information
+
+   :copyright: Copyright 2017-2024 Patrick Lehmann - Bötzingen, Germany
+   :copyright: Copyright 2016-2017 Patrick Lehmann - Dresden, Germany
+   :license: Apache License, Version 2.0
+"""
+__author__ =    "Patrick Lehmann"
+__email__ =     "Paebbels@gmail.com"
+__copyright__ = "2016-2024, Patrick Lehmann"
+__license__ =   "Apache License, Version 2.0"
+__version__ =   "0.29.0"
+
+
+from enum                      import unique, Enum, Flag, auto
+from pathlib                   import Path
+from sys                       import version_info
+
+from typing                    import Union, Dict, cast, List, Generator, Optional as Nullable
+
+from pyTooling.Common          import getFullyQualifiedName
+from pyTooling.Decorators      import export, readonly
+from pyTooling.Graph           import Graph, Vertex, Edge
+
+from pyVHDLModel.Exception     import VHDLModelException
+from pyVHDLModel.Exception     import LibraryExistsInDesignError, LibraryRegisteredToForeignDesignError, LibraryNotRegisteredError, EntityExistsInLibraryError
+from pyVHDLModel.Exception     import ArchitectureExistsInLibraryError, PackageExistsInLibraryError, PackageBodyExistsError, ConfigurationExistsInLibraryError
+from pyVHDLModel.Exception     import ContextExistsInLibraryError, ReferencedLibraryNotExistingError
+from pyVHDLModel.Base          import ModelEntity, NamedEntityMixin, MultipleNamedEntityMixin, DocumentedEntityMixin
+from pyVHDLModel.Expression    import UnaryExpression, BinaryExpression, TernaryExpression
+from pyVHDLModel.Namespace     import Namespace
+from pyVHDLModel.Object        import Obj, Signal, Constant, DeferredConstant
+from pyVHDLModel.Symbol        import PackageReferenceSymbol, AllPackageMembersReferenceSymbol, PackageMemberReferenceSymbol, SimpleObjectOrFunctionCallSymbol
+from pyVHDLModel.Concurrent    import EntityInstantiation, ComponentInstantiation, ConfigurationInstantiation
+from pyVHDLModel.DesignUnit    import DesignUnit, PrimaryUnit, Architecture, PackageBody, Context, Entity, Configuration, Package
+from pyVHDLModel.PSLModel      import VerificationUnit, VerificationProperty, VerificationMode
+from pyVHDLModel.Instantiation import PackageInstantiation
+from pyVHDLModel.Type          import IntegerType, PhysicalType, ArrayType, RecordType
+
+
+@export
+@unique
+class VHDLVersion(Enum):
+	"""
+	An enumeration for all possible version numbers for VHDL and VHDL-AMS.
+
+	A version can be given as integer or string and is represented as a unified
+	enumeration value.
+
+	This enumeration supports compare operators.
+	"""
+
+	Any =                -1  #: Any
+	VHDL87 =             87  #: VHDL-1987
+	VHDL93 =             93  #: VHDL-1993
+	AMS93 =            1993  #: VHDL-AMS-1993
+	AMS99 =            1999  #: VHDL-AMS-1999
+	VHDL2000 =         2000  #: VHDL-2000
+	VHDL2002 =         2002  #: VHDL-2002
+	VHDL2008 =         2008  #: VHDL-2008
+	AMS2017 =          2017  #: VHDL-AMS-2017
+	VHDL2019 =         2019  #: VHDL-2019
+	Latest =          10000  #: Latest VHDL (2019)
+
+	__VERSION_MAPPINGS__: Dict[Union[int, str], Enum] = {
+		-1:       Any,
+		87:       VHDL87,
+		93:       VHDL93,
+		# 93:       AMS93,
+		99:       AMS99,
+		0:        VHDL2000,
+		2:        VHDL2002,
+		8:        VHDL2008,
+		17:       AMS2017,
+		19:       VHDL2019,
+		1987:     VHDL87,
+		# 1993:     VHDL93,
+		1993:     AMS93,
+		1999:     AMS99,
+		2000:     VHDL2000,
+		2002:     VHDL2002,
+		2008:     VHDL2008,
+		2017:     AMS2017,
+		2019:     VHDL2019,
+		10000:    Latest,
+		"Any":    Any,
+		"87":     VHDL87,
+		"93":     VHDL93,
+		# "93":     AMS93,
+		"99":     AMS99,
+		"00":     VHDL2000,
+		"02":     VHDL2002,
+		"08":     VHDL2008,
+		"17":     AMS2017,
+		"19":     VHDL2019,
+		"1987":   VHDL87,
+		# "1993":   VHDL93,
+		"1993":   AMS93,
+		"1999":   AMS99,
+		"2000":   VHDL2000,
+		"2002":   VHDL2002,
+		"2008":   VHDL2008,
+		"2017":   AMS2017,
+		"2019":   VHDL2019,
+		"Latest": Latest,
+	}  #: Dictionary of VHDL and VHDL-AMS year codes variants as integer and strings for mapping to unique enum values.
+
+	def __init__(self, *_) -> None:
+		"""Patch the embedded MAP dictionary"""
+		for k, v in self.__class__.__VERSION_MAPPINGS__.items():
+			if (not isinstance(v, self.__class__)) and (v == self.value):
+				self.__class__.__VERSION_MAPPINGS__[k] = self
+
+	@classmethod
+	def Parse(cls, value: Union[int, str]) -> "VHDLVersion":
+		"""
+		Parses a VHDL or VHDL-AMS year code as integer or string to an enum value.
+
+		:param value:       VHDL/VHDL-AMS year code.
+		:returns:           Enumeration value.
+		:raises ValueError: If the year code is not recognized.
+		"""
+		try:
+			return cls.__VERSION_MAPPINGS__[value]
+		except KeyError:
+			raise ValueError(f"Value '{value!s}' cannot be parsed to member of {cls.__name__}.")
+
+	def __lt__(self, other: Any) -> bool:
+		"""
+		Compare two VHDL/VHDL-AMS versions if the version is less than the second operand.
+
+		:param other:      Parameter to compare against.
+		:returns:          True if version is less than the second operand.
+		:raises TypeError: If parameter ``other`` is not of type :class:`VHDLVersion`.
+		"""
+		if isinstance(other, VHDLVersion):
+			return self.value < other.value
+		else:
+			raise TypeError("Second operand is not of type 'VHDLVersion'.")
+
+	def __le__(self, other: Any) -> bool:
+		"""
+		Compare two VHDL/VHDL-AMS versions if the version is less or equal than the second operand.
+
+		:param other:      Parameter to compare against.
+		:returns:          True if version is less or equal than the second operand.
+		:raises TypeError: If parameter ``other`` is not of type :class:`VHDLVersion`.
+		"""
+		if isinstance(other, VHDLVersion):
+			return self.value <= other.value
+		else:
+			raise TypeError("Second operand is not of type 'VHDLVersion'.")
+
+	def __gt__(self, other: Any) -> bool:
+		"""
+		Compare two VHDL/VHDL-AMS versions if the version is greater than the second operand.
+
+		:param other:      Parameter to compare against.
+		:returns:          True if version is greater than the second operand.
+		:raises TypeError: If parameter ``other`` is not of type :class:`VHDLVersion`.
+		"""
+		if isinstance(other, VHDLVersion):
+			return self.value > other.value
+		else:
+			raise TypeError("Second operand is not of type 'VHDLVersion'.")
+
+	def __ge__(self, other: Any) -> bool:
+		"""
+		Compare two VHDL/VHDL-AMS versions if the version is greater or equal than the second operand.
+
+		:param other:      Parameter to compare against.
+		:returns:          True if version is greater or equal than the second operand.
+		:raises TypeError: If parameter ``other`` is not of type :class:`VHDLVersion`.
+		"""
+		if isinstance(other, VHDLVersion):
+			return self.value >= other.value
+		else:
+			raise TypeError("Second operand is not of type 'VHDLVersion'.")
+
+	def __ne__(self, other: Any) -> bool:
+		"""
+		Compare two VHDL/VHDL-AMS versions if the version is unequal to the second operand.
+
+		:param other:      Parameter to compare against.
+		:returns:          True if version is unequal to the second operand.
+		:raises TypeError: If parameter ``other`` is not of type :class:`VHDLVersion`.
+		"""
+		if isinstance(other, VHDLVersion):
+			return self.value != other.value
+		else:
+			raise TypeError("Second operand is not of type 'VHDLVersion'.")
+
+	def __eq__(self, other: Any) -> bool:
+		"""
+		Compare two VHDL/VHDL-AMS versions if the version is equal to the second operand.
+
+		:param other:      Parameter to compare against.
+		:returns:          True if version is equal to the second operand.
+		:raises TypeError: If parameter ``other`` is not of type :class:`VHDLVersion`.
+		"""
+		if isinstance(other, VHDLVersion):
+			if (self is self.__class__.Any) or (other is self.__class__.Any):
+				return True
+			else:
+				return self.value == other.value
+		else:
+			raise TypeError("Second operand is not of type 'VHDLVersion'.")
+
+	@readonly
+	def IsVHDL(self) -> bool:
+		"""
+		Checks if the version is a VHDL (not VHDL-AMS) version.
+
+		:returns:          True if version is a VHDL version.
+		"""
+		return self in (self.VHDL87, self.VHDL93, self.VHDL2002, self.VHDL2008, self.VHDL2019)
+
+	@readonly
+	def IsAMS(self) -> bool:
+		"""
+		Checks if the version is a VHDL-AMS (not VHDL) version.
+
+		:returns:          True if version is a VHDL-AMS version.
+		"""
+		return self in (self.AMS93, self.AMS99, self.AMS2017)
+
+	def __str__(self) -> str:
+		"""
+		Formats the VHDL version to pattern ``VHDL'xx`` or in case of VHDL-AMS to ``VHDL-AMS'xx``.
+
+		:return: Formatted VHDL/VHDL-AMS version.
+		"""
+		if self.value == self.Any.value:
+			return "VHDL'Any"
+		elif self.value == self.Latest.value:
+			return "VHDL'Latest"
+
+		year = str(self.value)[-2:]
+		if self.IsVHDL:
+			return f"VHDL'{year}"
+		else:
+			return f"VHDL-AMS'{year}"
+
+	def __repr__(self) -> str:
+		"""
+		Formats the VHDL/VHDL-AMS version to pattern ``xxxx``.
+
+		:return: Formatted VHDL/VHDL-AMS version.
+		"""
+		if self.value == self.Any.value:
+			return "Any"
+		elif self.value == self.Latest.value:
+			return "Latest"
+		else:
+			return str(self.value)
+
+
+@export
+@unique
+class ObjectClass(Enum):
+	"""
+	An ``ObjectClass`` is an enumeration and represents an object's class (``constant``, ``signal``, ...).
+
+	In case no *object class* is defined, ``Default`` is used, so the *object class* is inferred from context.
+	"""
+
+	Default =    0  #: Object class not defined, thus it's context dependent.
+	Constant =   1  #: Constant
+	Variable =   2  #: Variable
+	Signal =     3  #: Signal
+	File =       4  #: File
+	Type =       5  #: Type
+	# FIXME: Package?
+	Procedure =  6  #: Procedure
+	Function =   7  #: Function
+
+	def __str__(self) -> str:
+		"""
+		Formats the object class.
+
+		:return: Formatted object class.
+		"""
+		return ("", "constant", "variable", "signal", "file", "type", "procedure", "function")[cast(int, self.value)]       # TODO: check performance
+
+
+@export
+@unique
+class DesignUnitKind(Flag):
+	"""
+	A ``DesignUnitKind`` is an enumeration and represents the kind of design unit (``Entity``, ``Architecture``, ...).
+
+	"""
+	Context = auto()                                                             #: Context
+	Package = auto()                                                             #: Package
+	PackageBody = auto()                                                         #: Package Body
+	Entity = auto()                                                              #: Entity
+	Architecture = auto()                                                        #: Architecture
+	Configuration = auto()                                                       #: Configuration
+
+	Primary = Context | Configuration | Entity | Package                         #: List of primary design units.
+	Secondary = PackageBody | Architecture                                       #: List of secondary design units.
+	WithContext = Configuration | Package | Entity | PackageBody | Architecture  #: List of design units with a context.
+	WithDeclaredItems = Package | Entity | PackageBody | Architecture            #: List of design units having a declaration region.
+
+	All = Primary | Secondary                                                    #: List of all design units.
+
+
+@export
+@unique
+class DependencyGraphVertexKind(Flag):
+	"""
+	A ``DependencyGraphVertexKind`` is an enumeration and represents the kind of vertex in the dependency graph.
+	"""
+	Document = auto()       #: A document (VHDL source file).
+	Library = auto()        #: A VHDL library.
+
+	Context = auto()        #: A context design unit.
+	Package = auto()        #: A package design unit.
+	PackageBody = auto()    #: A package body design unit.
+	Entity = auto()         #: A entity design unit.
+	Architecture = auto()   #: A architecture design unit.
+	Component = auto()      #: A VHDL component.
+	Configuration = auto()  #: A configuration design unit.
+
+
+@export
+@unique
+class DependencyGraphEdgeKind(Flag):
+	"""
+	A ``DependencyGraphEdgeKind`` is an enumeration and represents the kind of edge in the dependency graph.
+	"""
+	Document =       auto()
+	Library =        auto()
+	Context =        auto()
+	Package =        auto()
+	Entity =         auto()
+	# Architecture = auto()
+	Configuration =  auto()
+	Component =      auto()
+
+	DeclaredIn =     auto()
+	Order =          auto()
+	Reference =      auto()
+	Implementation = auto()
+	Instantiation =  auto()
+
+	SourceFile =                 Document | DeclaredIn
+	CompileOrder =               Document | Order
+
+	LibraryClause =              Library | Reference
+	UseClause =                  Package | Reference
+	ContextReference =           Context | Reference
+
+	EntityImplementation =       Entity | Implementation
+	PackageImplementation =      Package | Implementation
+
+	EntityInstantiation =        Entity | Instantiation
+	ComponentInstantiation =     Component | Instantiation
+	ConfigurationInstantiation = Configuration | Instantiation
+
+
+@export
+@unique
+class ObjectGraphVertexKind(Flag):
+	"""
+	A ``ObjectGraphVertexKind`` is an enumeration and represents the kind of vertex in the object graph.
+	"""
+	Type = auto()
+	Subtype = auto()
+
+	Constant = auto()
+	DeferredConstant = auto()
+	Variable = auto()
+	Signal = auto()
+	File = auto()
+
+	Alias = auto()
+
+
+@export
+@unique
+class ObjectGraphEdgeKind(Flag):
+	"""
+	A ``ObjectGraphEdgeKind`` is an enumeration and represents the kind of edge in the object graph.
+	"""
+	BaseType = auto()
+	Subtype = auto()
+
+	ReferenceInExpression = auto()
+
+
+@export
+class Design(ModelEntity):
+	"""
+	A ``Design`` represents set of VHDL libraries as well as all loaded and analysed source files (see :class:`~pyVHDLModel.Document`).
+
+	It's the root of this code document-object-model (CodeDOM). It contains at least one VHDL library (see :class:`~pyVHDLModel.Library`). When the design is
+	analysed (see :meth:`Analyze`), multiple graph data structures will be created and populated with vertices and edges. As a first result, the design's compile
+	order and hierarchy can be iterated. As a second result, the design's *top-level* is identified and referenced from the design (see :attr:`TopLevel`).
+
+	The *design* contains references to the following graphs:
+
+	* :attr:`DependencyGraph`
+	* :attr:`CompileOrderGraph`
+	* :attr:`HierarchyGraph`
+	* :attr:`ObjectGraph`
+	"""
+	_name:              Nullable[str]         #: Name of the design
+	_libraries:         Dict[str, 'Library']  #: List of all libraries defined for a design.
+	_documents:         List['Document']      #: List of all documents loaded for a design.
+	_dependencyGraph:   Graph[None, None, None, None, None, None, None, None, str, DesignUnit, None, None, None, None, None, None, None, None, None, None, None, None, None]   #: The graph of all dependencies in the designs.
+	_compileOrderGraph: Graph[None, None, None, None, None, None, None, None, None, 'Document', None, None, None, None, None, None, None, None, None, None, None, None, None]  #: A graph derived from dependency graph containing the order of documents for compilation.
+	_hierarchyGraph:    Graph[None, None, None, None, None, None, None, None, str, DesignUnit, None, None, None, None, None, None, None, None, None, None, None, None, None]   #: A graph derived from dependency graph containing the design hierarchy.
+	_objectGraph:       Graph[None, None, None, None, None, None, None, None, str, Obj, None, None, None, None, None, None, None, None, None, None, None, None, None]          #: The graph of all types and objects in the design.
+	_toplevel:          Union[Entity, Configuration]  #: When computed, the toplevel design unit is cached in this field.
+
+	def __init__(self, name: Nullable[str] = None) -> None:
+		"""
+		Initializes a VHDL design.
+
+		:param name: Name of the design.
+		"""
+		super().__init__()
+
+		self._name =      name
+		self._libraries = {}
+		self._documents = []
+
+		self._compileOrderGraph = Graph()
+		self._dependencyGraph = Graph()
+		self._hierarchyGraph = Graph()
+		self._objectGraph = Graph()
+		self._toplevel = None
+
+	@readonly
+	def Libraries(self) -> Dict[str, 'Library']:
+		"""
+		Read-only property to access the dictionary of library names and VHDL libraries (:attr:`_libraries`).
+
+		:returns: A dictionary of library names and VHDL libraries.
+		"""
+		return self._libraries
+
+	@readonly
+	def Documents(self) -> List['Document']:
+		"""
+		Read-only property to access the list of all documents (VHDL source files) loaded for this design (:attr:`_documents`).
+
+		:returns: A list of all documents.
+		"""
+		return self._documents
+
+	@readonly
+	def CompileOrderGraph(self) -> Graph:
+		"""
+		Read-only property to access the compile-order graph (:attr:`_compileOrderGraph`).
+
+		:returns: Reference to the compile-order graph.
+		"""
+		return self._compileOrderGraph
+
+	@readonly
+	def DependencyGraph(self) -> Graph:
+		"""
+		Read-only property to access the dependency graph (:attr:`_dependencyGraph`).
+
+		:returns: Reference to the dependency graph.
+		"""
+		return self._dependencyGraph
+
+	@readonly
+	def HierarchyGraph(self) -> Graph:
+		"""
+		Read-only property to access the hierarchy graph (:attr:`_hierarchyGraph`).
+
+		:returns: Reference to the hierarchy graph.
+		"""
+		return self._hierarchyGraph
+
+	@readonly
+	def ObjectGraph(self) -> Graph:
+		"""
+		Read-only property to access the object graph (:attr:`_objectGraph`).
+
+		:returns: Reference to the object graph.
+		"""
+		return self._objectGraph
+
+	@readonly
+	def TopLevel(self) -> Union[Entity, Configuration]:
+		"""
+		Read-only property to access the design's *top-level* (:attr:`_toplevel`).
+
+		When called the first time, the hierarchy graph is checked for its root elements. When there is only one root element in the graph, a new field ``toplevel``
+		is added to :attr:`_hierarchyGraph` referencing that single element. In addition, the result is cached in :attr:`_toplevel`.
+
+		:returns:                   Reference to the design's *top-level*.
+		:raises VHDLModelException: If the hierarchy graph is not yet computed from dependency graph.
+		:raises VHDLModelException: If there is more than one *top-level*.
+		"""
+		# Check for cached result
+		if self._toplevel is not None:
+			return self._toplevel
+
+		if self._hierarchyGraph.EdgeCount == 0:
+			raise VHDLModelException(f"Hierarchy is not yet computed from dependency graph.")
+
+		roots = tuple(self._hierarchyGraph.IterateRoots())
+		if len(roots) == 1:
+			toplevel = roots[0]
+			self._hierarchyGraph["toplevel"] = toplevel
+			self._toplevel = toplevel.Value
+
+			return toplevel.Value
+		else:
+			raise VHDLModelException(f"Found more than one toplevel: {', '.join(roots)}")
+
+	def LoadStdLibrary(self) -> 'Library':
+		"""
+		Load the predefined VHDL library ``std`` into the design.
+
+		This will create a virtual source code file ``std.vhdl`` and register VHDL design units of library ``std`` to that file.
+
+		:returns: The library object of library ``std``.
+		"""
+		from pyVHDLModel.STD import Std
+
+		doc = Document(Path("std.vhdl"), parent=self)
+
+		library = Std()
+		for designUnit in library.IterateDesignUnits():
+			doc._AddDesignUnit(designUnit)
+
+		self.AddLibrary(library)
+
+		return library
+
+	def LoadIEEELibrary(self) -> 'Library':
+		"""
+		Load the predefined VHDL library ``ieee`` into the design.
+
+		This will create a virtual source code file ``ieee.vhdl`` and register VHDL design units of library ``ieee`` to that file.
+
+		:returns: The library object of library ``ieee``.
+		"""
+		from pyVHDLModel.IEEE import Ieee
+
+		doc = Document(Path("ieee.vhdl"), parent=self)
+
+		library = Ieee()
+		for designUnit in library.IterateDesignUnits():
+			doc._AddDesignUnit(designUnit)
+
+		self.AddLibrary(library)
+
+		return library
+
+	def AddLibrary(self, library: 'Library') -> None:
+		"""
+		Add a VHDL library to the design.
+
+		Ensure the libraries name doesn't collide with existing libraries in the design. |br|
+		If ok, set the libraries parent reference to the design.
+
+		:param library:                                Library object to loaded.
+		:raises LibraryExistsInDesignError:            If the library already exists in the design.
+		:raises LibraryRegisteredToForeignDesignError: If library is already used by a different design.
+		"""
+		libraryIdentifier = library.NormalizedIdentifier
+		if libraryIdentifier in self._libraries:
+			raise LibraryExistsInDesignError(library)
+
+		if library._parent is not None:
+			raise LibraryRegisteredToForeignDesignError(library)
+
+		self._libraries[libraryIdentifier] = library
+		library._parent = self
+
+	def GetLibrary(self, libraryName: str) -> 'Library':
+		"""
+		Return an (existing) VHDL library object of name ``libraryName``.
+
+		If the requested VHDL library doesn't exist, a new VHDL library with that name will be created.
+
+		:param libraryName: Name of the requested VHDL library.
+		:returns:           The VHDL library object.
+		"""
+		libraryIdentifier = libraryName.lower()
+		try:
+			return self._libraries[libraryIdentifier]
+		except KeyError:
+			lib = Library(libraryName, parent=self)
+			self._libraries[libraryIdentifier] = lib
+			lib._parent = self
+			return lib
+
+	# TODO: allow overloaded parameter library to be str?
+	def AddDocument(self, document: 'Document', library: 'Library') -> None:
+		"""
+		Add a document (VHDL source file) to the design and register all embedded design units to the given VHDL library.
+
+		.. rubric:: Algorithm
+
+		1. Iterate all entities in the document
+
+		   1. Check if entity name might exist in target library.
+		   2. Add entity to library and update library membership.
+
+		2. Iterate all architectures in the document
+
+		   1. Check if architecture name might exist in target library.
+		   2. Add architecture to library and update library membership.
+
+		3. Iterate all packages in the document
+
+		   1. Check if package name might exist in target library.
+		   2. Add package to library and update library membership.
+
+		4. Iterate all package bodies in the document
+
+		   1. Check if package body name might exist in target library.
+		   2. Add package body to library and update library membership.
+
+		5. Iterate all configurations in the document
+
+		   1. Check if configuration name might exist in target library.
+		   2. Add configuration to library and update library membership.
+
+		6. Iterate all contexts in the document
+
+		   1. Check if context name might exist in target library.
+		   2. Add context to library and update library membership.
+
+		:param document:                           The VHDL source code file.
+		:param library:                            The VHDL library used to register the embedded design units to.
+		:raises LibraryNotRegisteredError:         If the given VHDL library is not a library in the design.
+		:raises EntityExistsInLibraryError:        If the processed entity's name is already existing in the VHDL library.
+		:raises ArchitectureExistsInLibraryError:  If the processed architecture's name is already existing in the VHDL library.
+		:raises PackageExistsInLibraryError:       If the processed package's name is already existing in the VHDL library.
+		:raises PackageBodyExistsError:            If the processed package body's name is already existing in the VHDL library.
+		:raises ConfigurationExistsInLibraryError: If the processed configuration's name is already existing in the VHDL library.
+		:raises ContextExistsInLibraryError:       If the processed context's name is already existing in the VHDL library.
+		"""
+		# FIXME: this checks for the library name, but not the object
+		# should the libraries parent be checked too?
+		if library._normalizedIdentifier not in self._libraries:
+			raise LibraryNotRegisteredError(library)
+
+		self._documents.append(document)
+		document._parent = self
+
+		for entityIdentifier, entity in document._entities.items():
+			if entityIdentifier in library._entities:
+				raise EntityExistsInLibraryError(entity, library)
+
+			library._entities[entityIdentifier] = entity
+			entity.Library = library
+
+		for entityIdentifier, architectures in document._architectures.items():
+			try:
+				architecturesPerEntity = library._architectures[entityIdentifier]
+				for architectureIdentifier, architecture in architectures.items():
+					if architectureIdentifier in architecturesPerEntity:
+						raise ArchitectureExistsInLibraryError(architecture, library._entities[entityIdentifier], library)
+
+					architecturesPerEntity[architectureIdentifier] = architecture
+					architecture.Library = library
+			except KeyError:
+				architecturesPerEntity = document._architectures[entityIdentifier].copy()
+				library._architectures[entityIdentifier] = architecturesPerEntity
+
+				for architecture in architecturesPerEntity.values():
+					architecture.Library = library
+
+		for packageIdentifier, package in document._packages.items():
+			if packageIdentifier in library._packages:
+				raise PackageExistsInLibraryError(package, library)
+
+			library._packages[packageIdentifier] = package
+			package.Library = library
+
+		for packageBodyIdentifier, packageBody in document._packageBodies.items():
+			if packageBodyIdentifier in library._packageBodies:
+				raise PackageBodyExistsError(packageBody, library)
+
+			library._packageBodies[packageBodyIdentifier] = packageBody
+			packageBody.Library = library
+
+		for configurationIdentifier, configuration in document._configurations.items():
+			if configurationIdentifier in library._configurations:
+				raise ConfigurationExistsInLibraryError(configuration, library)
+
+			library._configurations[configurationIdentifier] = configuration
+			configuration.Library = library
+
+		for contextIdentifier, context in document._contexts.items():
+			if contextIdentifier in library._contexts:
+				raise ContextExistsInLibraryError(context, library)
+
+			library._contexts[contextIdentifier] = context
+			context.Library = library
+
+	def IterateDesignUnits(self, filter: DesignUnitKind = DesignUnitKind.All) -> Generator[DesignUnit, None, None]:
+		"""
+		Iterate all design units in the design.
+
+		A union of :class:`DesignUnitKind` values can be given to filter the returned result for suitable design units.
+
+		.. rubric:: Algorithm
+
+		1. Iterate all VHDL libraries.
+
+		   1. Iterate all contexts in that library.
+		   2. Iterate all packages in that library.
+		   3. Iterate all package bodies in that library.
+		   4. Iterate all entites in that library.
+		   5. Iterate all architectures in that library.
+		   6. Iterate all configurations in that library.
+
+		:param filter: An enumeration with possibly multiple flags to filter the returned design units.
+		:returns:      A generator to iterate all matched design units in the design.
+
+		.. seealso::
+
+		   :meth:`pyVHDLModel.Library.IterateDesignUnits`
+		     Iterate all design units in the library.
+		   :meth:`pyVHDLModel.Document.IterateDesignUnits`
+		     Iterate all design units in the document.
+		"""
+		for library in self._libraries.values():
+			yield from library.IterateDesignUnits(filter)
+
+	def Analyze(self) -> None:
+		"""
+		Analyze the whole design.
+
+		.. rubric:: Algorithm
+
+		1. Analyze dependencies of design units. |br|
+		   This will also yield the design hierarchy and the compiler order.
+		2. Analyze dependencies of types and objects.
+
+		.. seealso::
+
+		   :meth:`AnalyzeDependencies`
+		     Analyze the dependencies of design units.
+
+		   :meth:`AnalyzeObjects`
+		     Analyze the dependencies of types and objects.
+		"""
+		self.AnalyzeDependencies()
+		self.AnalyzeObjects()
+
+	def AnalyzeDependencies(self) -> None:
+		"""
+		Analyze the dependencies of design units.
+
+		.. rubric:: Algorithm
+
+		1. Create all vertices of the dependency graph by iterating all design units in all libraries. |br|
+		   |rarr| :meth:`CreateDependencyGraph`
+		2. Create the compile order graph. |br|
+		   |rarr| :meth:`CreateCompileOrderGraph`
+		3. Index all packages. |br|
+		   |rarr| :meth:`IndexPackages`
+		4. Index all architectures. |br|
+		   |rarr| :meth:`IndexArchitectures`
+		5. Link all contexts |br|
+		   |rarr| :meth:`LinkContexts`
+		6. Link all architectures. |br|
+		   |rarr| :meth:`LinkArchitectures`
+		7. Link all package bodies. |br|
+		   |rarr| :meth:`LinkPackageBodies`
+		8. Link all library references. |br|
+		   |rarr| :meth:`LinkLibraryReferences`
+		9. Link all package references. |br|
+		   |rarr| :meth:`LinkPackageReferences`
+		10. Link all context references. |br|
+		    |rarr| :meth:`LinkContextReferences`
+		11. Link all components. |br|
+		    |rarr| :meth:`LinkComponents`
+		12. Link all instantiations. |br|
+		    |rarr| :meth:`LinkInstantiations`
+		13. Create the hierarchy graph. |br|
+		    |rarr| :meth:`CreateHierarchyGraph`
+		14. Compute the compile order. |br|
+		    |rarr| :meth:`ComputeCompileOrder`
+		"""
+		self.CreateDependencyGraph()
+		self.CreateCompileOrderGraph()
+
+		self.IndexPackages()
+		self.IndexArchitectures()
+
+		self.LinkContexts()
+		self.LinkArchitectures()
+		self.LinkPackageBodies()
+		self.LinkLibraryReferences()
+		self.LinkPackageReferences()
+		self.LinkContextReferences()
+
+		self.LinkComponents()
+		self.LinkInstantiations()
+		self.CreateHierarchyGraph()
+		self.ComputeCompileOrder()
+
+	def AnalyzeObjects(self) -> None:
+		"""
+		Analyze the dependencies of types and objects.
+
+		.. rubric:: Algorithm
+
+		1. Index all entities. |br|
+		   |rarr| :meth:`IndexEntities`
+		2. Index all package bodies. |br|
+		   |rarr| :meth:`IndexPackageBodies`
+		3. Import objects. |br|
+		   |rarr| :meth:`ImportObjects`
+		4. Create the type and object graph. |br|
+		   |rarr| :meth:`CreateTypeAndObjectGraph`
+		"""
+		self.IndexEntities()
+		self.IndexPackageBodies()
+
+		self.ImportObjects()
+		self.CreateTypeAndObjectGraph()
+
+	def CreateDependencyGraph(self) -> None:
+		"""
+		Create all vertices of the dependency graph by iterating all design units in all libraries.
+
+		This method will purely create a sea of vertices without any linking between vertices. The edges will be created later by other methods. |br|
+		See :meth:`AnalyzeDependencies` for these methods and their algorithmic order.
+
+		Each vertex has the following properties:
+
+		* The vertex' ID is the design unit's identifier.
+		* The vertex' value references the design unit.
+		* A key-value-pair called ``kind`` denotes the vertex's kind as an enumeration value of type :class:`DependencyGraphVertexKind`.
+		* A key-value-pair called ``predefined`` denotes if the referenced design unit is a predefined language entity.
+
+		.. rubric:: Algorithm
+
+		1. Iterate all libraries in the design.
+
+		   * Create a vertex for that library and reference the library by the vertex' value field. |br|
+		     In return, set the library's :attr:`~pyVHDLModel.Library._dependencyVertex` field to reference the created vertex.
+
+		   1. Iterate all contexts in that library.
+
+		      * Create a vertex for that context and reference the context by the vertex' value field. |br|
+		        In return, set the context's :attr:`~pyVHDLModel.DesignUnit.Context._dependencyVertex` field to reference the created vertex.
+
+		   2. Iterate all packages in that library.
+
+		      * Create a vertex for that package and reference the package by the vertex' value field. |br|
+		        In return, set the package's :attr:`~pyVHDLModel.DesignUnit.Package._dependencyVertex` field to reference the created vertex.
+
+		   3. Iterate all package bodies in that library.
+
+		      * Create a vertex for that package body and reference the package body by the vertex' value field. |br|
+		        In return, set the package body's :attr:`~pyVHDLModel.DesignUnit.PackageBody._dependencyVertex` field to reference the created vertex.
+
+		   4. Iterate all entities in that library.
+
+		      * Create a vertex for that entity and reference the entity by the vertex' value field. |br|
+		        In return, set the entity's :attr:`~pyVHDLModel.DesignUnit.Entity._dependencyVertex` field to reference the created vertex.
+
+		   5. Iterate all architectures in that library.
+
+		      * Create a vertex for that architecture and reference the architecture by the vertex' value field. |br|
+		        In return, set the architecture's :attr:`~pyVHDLModel.DesignUnit.Architecture._dependencyVertex` field to reference the created vertex.
+
+		   6. Iterate all configurations in that library.
+
+		      * Create a vertex for that configuration and reference the configuration by the vertex' value field. |br|
+		        In return, set the configuration's :attr:`~pyVHDLModel.DesignUnit.Configuration._dependencyVertex` field to reference the created vertex.
+		"""
+		predefinedLibraries = ("std", "ieee")
+
+		for libraryIdentifier, library in self._libraries.items():
+			dependencyVertex = Vertex(vertexID=f"{libraryIdentifier}", value=library, graph=self._dependencyGraph)
+			dependencyVertex["kind"] = DependencyGraphVertexKind.Library
+			dependencyVertex["predefined"] = libraryIdentifier in predefinedLibraries
+			library._dependencyVertex = dependencyVertex
+
+			for contextIdentifier, context in library._contexts.items():
+				dependencyVertex = Vertex(vertexID=f"{libraryIdentifier}.{contextIdentifier}", value=context, graph=self._dependencyGraph)
+				dependencyVertex["kind"] = DependencyGraphVertexKind.Context
+				dependencyVertex["predefined"] = context._parent._normalizedIdentifier in predefinedLibraries
+				context._dependencyVertex = dependencyVertex
+
+			for packageIdentifier, package in library._packages.items():
+				dependencyVertex = Vertex(vertexID=f"{libraryIdentifier}.{packageIdentifier}", value=package, graph=self._dependencyGraph)
+				dependencyVertex["kind"] = DependencyGraphVertexKind.Package
+				dependencyVertex["predefined"] = package._parent._normalizedIdentifier in predefinedLibraries
+				package._dependencyVertex = dependencyVertex
+
+			for packageBodyIdentifier, packageBody in library._packageBodies.items():
+				dependencyVertex = Vertex(vertexID=f"{libraryIdentifier}.{packageBodyIdentifier}(body)", value=packageBody, graph=self._dependencyGraph)
+				dependencyVertex["kind"] = DependencyGraphVertexKind.PackageBody
+				dependencyVertex["predefined"] = packageBody._parent._normalizedIdentifier in predefinedLibraries
+				packageBody._dependencyVertex = dependencyVertex
+
+			for entityIdentifier, entity in library._entities.items():
+				dependencyVertex = Vertex(vertexID=f"{libraryIdentifier}.{entityIdentifier}", value=entity, graph=self._dependencyGraph)
+				dependencyVertex["kind"] = DependencyGraphVertexKind.Entity
+				dependencyVertex["predefined"] = entity._parent._normalizedIdentifier in predefinedLibraries
+				entity._dependencyVertex = dependencyVertex
+
+			for entityIdentifier, architectures in library._architectures.items():
+				for architectureIdentifier, architecture in architectures.items():
+					dependencyVertex = Vertex(vertexID=f"{libraryIdentifier}.{entityIdentifier}({architectureIdentifier})", value=architecture, graph=self._dependencyGraph)
+					dependencyVertex["kind"] = DependencyGraphVertexKind.Architecture
+					dependencyVertex["predefined"] = architecture._parent._normalizedIdentifier in predefinedLibraries
+					architecture._dependencyVertex = dependencyVertex
+
+			for configurationIdentifier, configuration in library._configurations.items():
+				dependencyVertex = Vertex(vertexID=f"{libraryIdentifier}.{configurationIdentifier}", value=configuration, graph=self._dependencyGraph)
+				dependencyVertex["kind"] = DependencyGraphVertexKind.Configuration
+				dependencyVertex["predefined"] = configuration._parent._normalizedIdentifier in predefinedLibraries
+				configuration._dependencyVertex = dependencyVertex
+
+	def CreateCompileOrderGraph(self) -> None:
+		"""
+		Create a compile-order graph with bidirectional references to the dependency graph.
+
+		Add vertices representing a document (VHDL source file) to the dependency graph. Each "document" vertex in dependency graph is copied into the compile-order
+		graph and bidirectionally referenced.
+
+		In addition, each vertex of a corresponding design unit in a document is linked to the vertex representing that document to express the design unit in
+		document relationship.
+
+		Each added vertex has the following properties:
+
+		* The vertex' ID is the document's filename.
+		* The vertex' value references the document.
+		* A key-value-pair called ``kind`` denotes the vertex's kind as an enumeration value of type :class:`DependencyGraphVertexKind`.
+		* A key-value-pair called ``predefined`` does not exist.
+
+		.. rubric:: Algorithm
+
+		1. Iterate all documents in the design.
+
+		   * Create a vertex for that document and reference the document by the vertex' value field. |br|
+		     In return, set the documents's :attr:`~pyVHDLModel.Document._dependencyVertex` field to reference the created vertex.
+		   * Copy the vertex from dependency graph to compile-order graph and link both vertices bidirectionally. |br|
+		     In addition, set the documents's :attr:`~pyVHDLModel.Document._dependencyVertex` field to reference the copied vertex.
+
+		     * Add a key-value-pair called ``compileOrderVertex`` to the dependency graph's vertex.
+		     * Add a key-value-pair called ``dependencyVertex`` to the compiler-order graph's vertex.
+
+		   1. Iterate the documents design units and create an edge from the design unit's corresponding dependency vertex to the documents corresponding
+		      dependency vertex. This expresses a "design unit is located in document" relation.
+
+		      * Add a key-value-pair called `kind`` denoting the edge's kind as an enumeration value of type :class:`DependencyGraphEdgeKind`.
+		"""
+		for document in self._documents:
+			dependencyVertex = Vertex(vertexID=document.Path.name, value=document, graph=self._dependencyGraph)
+			dependencyVertex["kind"] = DependencyGraphVertexKind.Document
+			document._dependencyVertex = dependencyVertex
+
+			compilerOrderVertex = dependencyVertex.Copy(
+				self._compileOrderGraph,
+				copyDict=True,
+				linkingKeyToOriginalVertex="dependencyVertex",
+				linkingKeyFromOriginalVertex="compileOrderVertex"
+			)
+			document._compileOrderVertex = compilerOrderVertex
+
+			for designUnit in document._designUnits:
+				edge = dependencyVertex.EdgeFromVertex(designUnit._dependencyVertex)
+				edge["kind"] = DependencyGraphEdgeKind.SourceFile
+
+	def ImportObjects(self) -> None:
+		def _ImportObjects(package: Package) -> None:
+			for referencedLibrary in package._referencedPackages.values():
+				for referencedPackage in referencedLibrary.values():
+					for declaredItem in referencedPackage._declaredItems:
+						if isinstance(declaredItem, MultipleNamedEntityMixin):
+							for normalizedIdentifier in declaredItem._normalizedIdentifiers:
+								package._namespace._elements[normalizedIdentifier] = declaredItem
+						elif isinstance(declaredItem, NamedEntityMixin):
+							package._namespace._elements[declaredItem._normalizedIdentifier] = declaredItem
+						else:
+							raise VHDLModelException(f"Unexpected declared item.")
+
+		for libraryName in ("std", "ieee"):
+			for package in self.GetLibrary(libraryName).IterateDesignUnits(filter=DesignUnitKind.Package):  # type: Package
+				_ImportObjects(package)
+
+		for document in self.IterateDocumentsInCompileOrder():
+			for package in document.IterateDesignUnits(filter=DesignUnitKind.Package):  # type: Package
+				_ImportObjects(package)
+
+	def CreateTypeAndObjectGraph(self) -> None:
+		def _HandlePackage(package) -> None:
+			packagePrefix = f"{package.Library.NormalizedIdentifier}.{package.NormalizedIdentifier}"
+
+			for deferredConstant in package._deferredConstants.values():
+				print(f"Deferred Constant: {deferredConstant}")
+				deferredConstantVertex = Vertex(
+					vertexID=f"{packagePrefix}.{deferredConstant.NormalizedIdentifiers[0]}",
+					value=deferredConstant,
+					graph=self._objectGraph
+				)
+				deferredConstantVertex["kind"] = ObjectGraphVertexKind.DeferredConstant
+				deferredConstant._objectVertex = deferredConstantVertex
+
+			for constant in package._constants.values():
+				print(f"Constant: {constant}")
+				constantVertex = Vertex(
+					vertexID=f"{packagePrefix}.{constant.NormalizedIdentifiers[0]}",
+					value=constant,
+					graph=self._objectGraph
+				)
+				constantVertex["kind"] = ObjectGraphVertexKind.Constant
+				constant._objectVertex = constantVertex
+
+			for type in package._types.values():
+				print(f"Type: {type}")
+				typeVertex = Vertex(
+					vertexID=f"{packagePrefix}.{type.NormalizedIdentifier}",
+					value=type,
+					graph=self._objectGraph
+				)
+				typeVertex["kind"] = ObjectGraphVertexKind.Type
+				type._objectVertex = typeVertex
+
+			for subtype in package._subtypes.values():
+				print(f"Subtype: {subtype}")
+				subtypeVertex = Vertex(
+					vertexID=f"{packagePrefix}.{subtype.NormalizedIdentifier}",
+					value=subtype,
+					graph=self._objectGraph
+				)
+				subtypeVertex["kind"] = ObjectGraphVertexKind.Subtype
+				subtype._objectVertex = subtypeVertex
+
+			for function in package._functions.values():
+				print(f"Function: {function}")
+				functionVertex = Vertex(
+					vertexID=f"{packagePrefix}.{function.NormalizedIdentifier}",
+					value=function,
+					graph=self._objectGraph
+				)
+				functionVertex["kind"] = ObjectGraphVertexKind.Function
+				function._objectVertex = functionVertex
+
+			for procedure in package._procedures.values():
+				print(f"Procedure: {procedure}")
+				procedureVertex = Vertex(
+					vertexID=f"{packagePrefix}.{procedure.NormalizedIdentifier}",
+					value=procedure,
+					graph=self._objectGraph
+				)
+				procedureVertex["kind"] = ObjectGraphVertexKind.Function
+				procedure._objectVertex = procedureVertex
+
+			for signal in package._signals.values():
+				print(f"Signal: {signal}")
+				signalVertex = Vertex(
+					vertexID=f"{packagePrefix}.{signal.NormalizedIdentifiers[0]}",
+					value=signal,
+					graph=self._objectGraph
+				)
+				signalVertex["kind"] = ObjectGraphVertexKind.Signal
+				signal._objectVertex = signalVertex
+
+		def _LinkSymbolsInExpression(expression, namespace: Namespace, typeVertex: Vertex):
+			if isinstance(expression, UnaryExpression):
+				_LinkSymbolsInExpression(expression.Operand, namespace, typeVertex)
+			elif isinstance(expression, BinaryExpression):
+				_LinkSymbolsInExpression(expression.LeftOperand, namespace, typeVertex)
+				_LinkSymbolsInExpression(expression.RightOperand, namespace, typeVertex)
+			elif isinstance(expression, TernaryExpression):
+				pass
+			elif isinstance(expression, SimpleObjectOrFunctionCallSymbol):
+				obj = namespace.FindObject(expression)
+				expression._reference = obj
+
+				edge = obj._objectVertex.EdgeToVertex(typeVertex)
+				edge["kind"] = ObjectGraphEdgeKind.ReferenceInExpression
+			else:
+				pass
+
+		def _LinkItems(package: Package):
+			for item in package._declaredItems:
+				if isinstance(item, Constant):
+					print(f"constant: {item}")
+				elif isinstance(item, DeferredConstant):
+					print(f"deferred constant: {item}")
+				elif isinstance(item, Signal):
+					print(f"signal: {item}")
+				elif isinstance(item, IntegerType):
+					typeNode = item._objectVertex
+
+					_LinkSymbolsInExpression(item.Range.LeftBound, package._namespace, typeNode)
+					_LinkSymbolsInExpression(item.Range.RightBound, package._namespace, typeNode)
+				# elif isinstance(item, FloatingType):
+				# 	print(f"signal: {item}")
+				elif isinstance(item, PhysicalType):
+					typeNode = item._objectVertex
+
+					_LinkSymbolsInExpression(item.Range.LeftBound, package._namespace, typeNode)
+					_LinkSymbolsInExpression(item.Range.RightBound, package._namespace, typeNode)
+				elif isinstance(item, ArrayType):
+					# Resolve dimensions
+					for dimension in item._dimensions:
+						subtype = package._namespace.FindSubtype(dimension)
+						dimension._reference = subtype
+
+						edge = item._objectVertex.EdgeToVertex(subtype._objectVertex)
+						edge["kind"] = ObjectGraphEdgeKind.Subtype
+
+					# Resolve element subtype
+					subtype = package._namespace.FindSubtype(item._elementType)
+					item._elementType._reference = subtype
+
+					edge = item._objectVertex.EdgeToVertex(subtype._objectVertex)
+					edge["kind"] = ObjectGraphEdgeKind.Subtype
+				elif isinstance(item, RecordType):
+					# Resolve each elements subtype
+					for element in item._elements:
+						subtype = package._namespace.FindSubtype(element._subtype)
+						element._subtype._reference = subtype
+
+						edge = item._objectVertex.EdgeToVertex(subtype._objectVertex)
+						edge["kind"] = ObjectGraphEdgeKind.Subtype
+				else:
+					print(f"not handled: {item}")
+
+		for libraryName in ("std", "ieee"):
+			for package in self.GetLibrary(libraryName).IterateDesignUnits(filter=DesignUnitKind.Package):  # type: Package
+				_HandlePackage(package)
+				_LinkItems(package)
+
+		for document in self.IterateDocumentsInCompileOrder():
+			for package in document.IterateDesignUnits(filter=DesignUnitKind.Package):  # type: Package
+				_HandlePackage(package)
+				_LinkItems(package)
+
+	def LinkContexts(self) -> None:
+		"""
+		Resolves and links all items (library clauses, use clauses and nested context references) in contexts.
+
+		It iterates all contexts in the design. Therefore, the library of the context is used as the working library. By
+		default, the working library is implicitly referenced in :data:`_referencedLibraries`. In addition, a new empty
+		dictionary is created in :data:`_referencedPackages` and :data:`_referencedContexts` for that working library.
+
+		At first, all library clauses are resolved (a library clause my have multiple library reference symbols). For each
+		referenced library an entry in :data:`_referencedLibraries` is generated and new empty dictionaries in
+		:data:`_referencedPackages` and :data:`_referencedContexts` for that working library. In addition, a vertex in the
+		dependency graph is added for that relationship.
+
+		At second, all use clauses are resolved (a use clause my have multiple package member reference symbols). For each
+		referenced package,
+		"""
+		for context in self.IterateDesignUnits(DesignUnitKind.Context):  # type: Context
+			# Create entries in _referenced*** for the current working library under its real name.
+			workingLibrary: Library = context.Library
+			libraryNormalizedIdentifier = workingLibrary._normalizedIdentifier
+
+			context._referencedLibraries[libraryNormalizedIdentifier] = self._libraries[libraryNormalizedIdentifier]
+			context._referencedPackages[libraryNormalizedIdentifier] = {}
+			context._referencedContexts[libraryNormalizedIdentifier] = {}
+
+			# Process all library clauses
+			for libraryReference in context._libraryReferences:
+				# A library clause can have multiple comma-separated references
+				for libraryName in libraryReference.Symbols:
+					libraryNormalizedIdentifier = libraryName.Name._normalizedIdentifier
+					try:
+						library = self._libraries[libraryNormalizedIdentifier]
+					except KeyError:
+						raise ReferencedLibraryNotExistingError(context, libraryName)
+						# TODO: add position to these messages
+
+					libraryName.Library = library
+
+					context._referencedLibraries[libraryNormalizedIdentifier] = library
+					context._referencedPackages[libraryNormalizedIdentifier] = {}
+					context._referencedContexts[libraryNormalizedIdentifier] = {}
+					# TODO: warn duplicate library reference
+
+					dependency = context._dependencyVertex.EdgeToVertex(library._dependencyVertex, edgeValue=libraryReference)
+					dependency["kind"] = DependencyGraphEdgeKind.LibraryClause
+
+			# Process all use clauses
+			for packageReference in context.PackageReferences:
+				# A use clause can have multiple comma-separated references
+				for symbol in packageReference.Symbols:  # type: PackageReferenceSymbol
+					packageName = symbol.Name.Prefix
+					libraryName = packageName.Prefix
+
+					libraryNormalizedIdentifier = libraryName._normalizedIdentifier
+					packageNormalizedIdentifier = packageName._normalizedIdentifier
+
+					# In case work is used, resolve to the real library name.
+					if libraryNormalizedIdentifier == "work":
+						library: Library = context._parent
+						libraryNormalizedIdentifier = library._normalizedIdentifier
+					elif libraryNormalizedIdentifier not in context._referencedLibraries:
+						# TODO: This check doesn't trigger if it's the working library.
+						raise VHDLModelException(f"Use clause references library '{libraryName._identifier}', which was not referenced by a library clause.")
+					else:
+						library = self._libraries[libraryNormalizedIdentifier]
+
+					try:
+						package = library._packages[packageNormalizedIdentifier]
+					except KeyError:
+						raise VHDLModelException(f"Package '{packageName._identifier}' not found in {'working ' if libraryName._normalizedIdentifier == 'work' else ''}library '{library._identifier}'.")
+
+					symbol.Package = package
+
+					# TODO: warn duplicate package reference
+					context._referencedPackages[libraryNormalizedIdentifier][packageNormalizedIdentifier] = package
+
+					dependency = context._dependencyVertex.EdgeToVertex(package._dependencyVertex, edgeValue=packageReference)
+					dependency["kind"] = DependencyGraphEdgeKind.UseClause
+
+					# TODO: update the namespace with visible members
+					if isinstance(symbol, AllPackageMembersReferenceSymbol):
+						pass
+
+					elif isinstance(symbol, PackageMemberReferenceSymbol):
+						raise NotImplementedError()
+					else:
+						raise VHDLModelException()
+
+	def LinkArchitectures(self) -> None:
+		"""
+		Link all architectures to corresponding entities in all libraries.
+
+		.. rubric:: Algorithm
+
+		1. Iterate all libraries:
+
+		   1. Iterate all architecture groups (grouped per entity symbol's name).
+		      |rarr| :meth:`pyVHDLModel.Library.LinkArchitectures`
+
+		      * Check if entity symbol's name exists as an entity in this library.
+
+		      1. For each architecture in the same architecture group:
+
+		         * Add architecture to entities architecture dictionary :attr:`pyVHDLModel.DesignUnit.Entity._architectures`.
+		         * Assign found entity to architecture's entity symbol :attr:`pyVHDLModel.DesignUnit.Architecture._entity`
+		         * Set parent namespace of architecture's namespace to the entitie's namespace.
+		         * Add an edge in the dependency graph from the architecture's corresponding dependency vertex to the entity's corresponding dependency vertex.
+
+		.. seealso::
+
+		   :meth:`LinkPackageBodies`
+		     Link all package bodies to corresponding packages in all libraries.
+		"""
+		for library in self._libraries.values():
+			library.LinkArchitectures()
+
+	def LinkPackageBodies(self) -> None:
+		"""
+		Link all package bodies to corresponding packages in all libraries.
+
+		.. rubric:: Algorithm
+
+		1. Iterate all libraries:
+
+		   1. Iterate all package bodies.
+		      |rarr| :meth:`pyVHDLModel.Library.LinkPackageBodies`
+
+		      * Check if package body symbol's name exists as a package in this library.
+		      * Add package body to package :attr:`pyVHDLModel.DesignUnit.Package._packageBody`.
+		      * Assign found package to package body's package symbol :attr:`pyVHDLModel.DesignUnit.PackageBody._package`
+		      * Set parent namespace of package body's namespace to the package's namespace.
+		      * Add an edge in the dependency graph from the package body's corresponding dependency vertex to the package's corresponding dependency vertex.
+
+		.. seealso::
+
+		   :meth:`LinkArchitectures`
+		     Link all architectures to corresponding entities in all libraries.
+		"""
+		for library in self._libraries.values():
+			library.LinkPackageBodies()
+
+	def LinkLibraryReferences(self) -> None:
+		DEFAULT_LIBRARIES = ("std",)
+
+		for designUnit in self.IterateDesignUnits(DesignUnitKind.WithContext):
+			# All primary units supporting a context, have at least one library implicitly referenced
+			if isinstance(designUnit, PrimaryUnit):
+				for libraryIdentifier in DEFAULT_LIBRARIES:
+					referencedLibrary = self._libraries[libraryIdentifier]
+					designUnit._referencedLibraries[libraryIdentifier] = referencedLibrary
+					designUnit._referencedPackages[libraryIdentifier] = {}
+					designUnit._referencedContexts[libraryIdentifier] = {}
+					# TODO: catch KeyError on self._libraries[libName]
+					# TODO: warn duplicate library reference
+
+					dependency = designUnit._dependencyVertex.EdgeToVertex(referencedLibrary._dependencyVertex)
+					dependency["kind"] = DependencyGraphEdgeKind.LibraryClause
+
+				workingLibrary: Library = designUnit.Library
+				libraryIdentifier = workingLibrary.NormalizedIdentifier
+				referencedLibrary = self._libraries[libraryIdentifier]
+
+
+				designUnit._referencedLibraries[libraryIdentifier] = referencedLibrary
+				designUnit._referencedPackages[libraryIdentifier] = {}
+				designUnit._referencedContexts[libraryIdentifier] = {}
+
+				dependency = designUnit._dependencyVertex.EdgeToVertex(referencedLibrary._dependencyVertex)
+				dependency["kind"] = DependencyGraphEdgeKind.LibraryClause
+
+			# All secondary units inherit referenced libraries from their primary units.
+			else:
+				if isinstance(designUnit, Architecture):
+					referencedLibraries = designUnit.Entity.Entity._referencedLibraries
+				elif isinstance(designUnit, PackageBody):
+					referencedLibraries = designUnit.Package.Package._referencedLibraries
+				else:
+					raise VHDLModelException()
+
+				for libraryIdentifier, library in referencedLibraries.items():
+					designUnit._referencedLibraries[libraryIdentifier] = library
+
+			for libraryReference in designUnit._libraryReferences:
+				# A library clause can have multiple comma-separated references
+				for librarySymbol in libraryReference.Symbols:
+					libraryIdentifier = librarySymbol.Name.NormalizedIdentifier
+					try:
+						library = self._libraries[libraryIdentifier]
+					except KeyError:
+						ex = VHDLModelException(f"Library '{librarySymbol.Name.Identifier}' referenced by library clause of design unit '{designUnit.Identifier}' doesn't exist in design.")
+						ex.add_note(f"""Known libraries: '{"', '".join(library for library in self._libraries)}'""")
+						raise ex
+
+					librarySymbol.Library = library
+					designUnit._referencedLibraries[libraryIdentifier] = library
+					designUnit._referencedPackages[libraryIdentifier] = {}
+					designUnit._referencedContexts[libraryIdentifier] = {}
+					# TODO: warn duplicate library reference
+
+					dependency = designUnit._dependencyVertex.EdgeToVertex(library._dependencyVertex, edgeValue=libraryReference)
+					dependency["kind"] = DependencyGraphEdgeKind.LibraryClause
+
+	def LinkPackageReferences(self) -> None:
+		DEFAULT_PACKAGES = (
+			("std", ("standard",)),
+		)
+
+		for designUnit in self.IterateDesignUnits(DesignUnitKind.WithContext):
+			# All primary units supporting a context, have at least one package implicitly referenced
+			if isinstance(designUnit, PrimaryUnit):
+				if designUnit.Library.NormalizedIdentifier != "std" and \
+					designUnit.NormalizedIdentifier != "standard":
+					for lib in DEFAULT_PACKAGES:
+						if lib[0] not in designUnit._referencedLibraries:
+							raise VHDLModelException()
+						for pack in lib[1]:
+							referencedPackage = self._libraries[lib[0]]._packages[pack]
+							designUnit._referencedPackages[lib[0]][pack] = referencedPackage
+							# TODO: catch KeyError on self._libraries[lib[0]]._packages[pack]
+							# TODO: warn duplicate package reference
+
+							dependency = designUnit._dependencyVertex.EdgeToVertex(referencedPackage._dependencyVertex)
+							dependency["kind"] = DependencyGraphEdgeKind.UseClause
+
+			# All secondary units inherit referenced packages from their primary units.
+			else:
+				if isinstance(designUnit, Architecture):
+					referencedPackages = designUnit.Entity.Entity._referencedPackages
+				elif isinstance(designUnit, PackageBody):
+					referencedPackages = designUnit.Package.Package._referencedPackages
+				else:
+					raise VHDLModelException()
+
+				for packageIdentifier, package in referencedPackages.items():
+					designUnit._referencedPackages[packageIdentifier] = package
+
+			for packageReference in designUnit.PackageReferences:
+				# A use clause can have multiple comma-separated references
+				for packageMemberSymbol in packageReference.Symbols:
+					packageName = packageMemberSymbol.Name.Prefix
+					libraryName = packageName.Prefix
+
+					libraryIdentifier = libraryName.NormalizedIdentifier
+					packageIdentifier = packageName.NormalizedIdentifier
+
+					# In case work is used, resolve to the real library name.
+					if libraryIdentifier == "work":
+						library: Library = designUnit.Library
+						libraryIdentifier = library.NormalizedIdentifier
+					elif libraryIdentifier not in designUnit._referencedLibraries:
+						# TODO: This check doesn't trigger if it's the working library.
+						raise VHDLModelException(f"Use clause references library '{libraryName.Identifier}', which was not referenced by a library clause.")
+					else:
+						library = self._libraries[libraryIdentifier]
+
+					try:
+						package = library._packages[packageIdentifier]
+					except KeyError:
+						ex = VHDLModelException(f"Package '{packageName.Identifier}' not found in {'working ' if libraryName.NormalizedIdentifier == 'work' else ''}library '{library.Identifier}'.")
+						ex.add_note(f"Caused in design unit '{designUnit}' in file '{designUnit.Document}'.")
+						raise ex
+
+					packageMemberSymbol.Package = package
+
+					# TODO: warn duplicate package reference
+					designUnit._referencedPackages[libraryIdentifier][packageIdentifier] = package
+
+					dependency = designUnit._dependencyVertex.EdgeToVertex(package._dependencyVertex, edgeValue=packageReference)
+					dependency["kind"] = DependencyGraphEdgeKind.UseClause
+
+					# TODO: update the namespace with visible members
+					if isinstance(packageMemberSymbol, AllPackageMembersReferenceSymbol):
+						for componentIdentifier, component in package._components.items():
+							designUnit._namespace._elements[componentIdentifier] = component
+
+					elif isinstance(packageMemberSymbol, PackageMemberReferenceSymbol):
+						raise NotImplementedError()
+					else:
+						raise VHDLModelException()
+
+	def LinkContextReferences(self) -> None:
+		for designUnit in self.IterateDesignUnits():
+			for contextReference in designUnit._contextReferences:
+				# A context reference can have multiple comma-separated references
+				for contextSymbol in contextReference.Symbols:
+					libraryName = contextSymbol.Name.Prefix
+
+					libraryIdentifier = libraryName.NormalizedIdentifier
+					contextIdentifier = contextSymbol.Name.NormalizedIdentifier
+
+					# In case work is used, resolve to the real library name.
+					if libraryIdentifier == "work":
+						referencedLibrary = designUnit.Library
+						libraryIdentifier = referencedLibrary.NormalizedIdentifier
+					elif libraryIdentifier not in designUnit._referencedLibraries:
+						# TODO: This check doesn't trigger if it's the working library.
+						raise VHDLModelException(f"Context reference references library '{libraryName.Identifier}', which was not referenced by a library clause.")
+					else:
+						referencedLibrary = self._libraries[libraryIdentifier]
+
+					try:
+						referencedContext = referencedLibrary._contexts[contextIdentifier]
+					except KeyError:
+						raise VHDLModelException(f"Context '{contextSymbol.Name.Identifier}' not found in {'working ' if libraryName.NormalizedIdentifier == 'work' else ''}library '{referencedLibrary.Identifier}'.")
+
+					contextSymbol.Package = referencedContext
+
+					# TODO: warn duplicate referencedContext reference
+					designUnit._referencedContexts[libraryIdentifier][contextIdentifier] = referencedContext
+
+					dependency = designUnit._dependencyVertex.EdgeToVertex(referencedContext._dependencyVertex, edgeValue=contextReference)
+					dependency["kind"] = DependencyGraphEdgeKind.ContextReference
+
+		for vertex in self._dependencyGraph.IterateTopologically():
+			if vertex["kind"] is DependencyGraphVertexKind.Context:
+				context: Context = vertex.Value
+				for designUnitVertex in vertex.IteratePredecessorVertices():
+					designUnit: DesignUnit = designUnitVertex.Value
+					for libraryIdentifier, library in context._referencedLibraries.items():
+						# if libraryIdentifier in designUnit._referencedLibraries:
+						# 	raise VHDLModelException(f"Referenced library '{library.Identifier}' already exists in references for design unit '{designUnit.Identifier}'.")
+
+						designUnit._referencedLibraries[libraryIdentifier] = library
+						designUnit._referencedPackages[libraryIdentifier] = {}
+
+					for libraryIdentifier, packages in context._referencedPackages.items():
+						for packageIdentifier, package in packages.items():
+							if packageIdentifier in designUnit._referencedPackages:
+								raise VHDLModelException(f"Referenced package '{package.Identifier}' already exists in references for design unit '{designUnit.Identifier}'.")
+
+							designUnit._referencedPackages[libraryIdentifier][packageIdentifier] = package
+
+	def LinkComponents(self) -> None:
+		for package in self.IterateDesignUnits(DesignUnitKind.Package):  # type: Package
+			library = package._parent
+			for component in package._components.values():
+				try:
+					entity = library._entities[component.NormalizedIdentifier]
+				except KeyError:
+					print(f"Entity '{component.Identifier}' not found for component '{component.Identifier}' in library '{library.Identifier}'.")
+
+				component.Entity = entity
+
+				# QUESTION: Add link in dependency graph as dashed line from component to entity?
+				#           Currently, component has no _dependencyVertex field
+
+	def LinkInstantiations(self) -> None:
+		for architecture in self.IterateDesignUnits(DesignUnitKind.Architecture):  # type: Architecture
+			for instance in architecture.IterateInstantiations():
+				if isinstance(instance, EntityInstantiation):
+					libraryName = instance.Entity.Name.Prefix
+					libraryIdentifier = libraryName.Identifier
+					normalizedLibraryIdentifier = libraryName.NormalizedIdentifier
+					if normalizedLibraryIdentifier == "work":
+						libraryIdentifier = architecture.Library.Identifier
+						normalizedLibraryIdentifier = architecture.Library.NormalizedIdentifier
+					elif normalizedLibraryIdentifier not in architecture._referencedLibraries:
+						ex = VHDLModelException(f"Referenced library '{libraryIdentifier}' in direct entity instantiation '{instance.Label}: entity {instance.Entity.Prefix.Identifier}.{instance.Entity.Identifier}' not found in architecture '{architecture!r}'.")
+						ex.add_note(f"Add a library reference to the architecture or entity using a library clause like: 'library {libraryIdentifier};'.")
+						raise ex
+
+					try:
+						library = self._libraries[normalizedLibraryIdentifier]
+					except KeyError:
+						ex = VHDLModelException(f"Referenced library '{libraryIdentifier}' in direct entity instantiation '{instance.Label}: entity {instance.Entity.Prefix.Identifier}.{instance.Entity.Identifier}' not found in design.")
+						ex.add_note(f"No design units were parsed into library '{libraryIdentifier}'. Thus it doesn't exist in design.")
+						raise ex
+
+					try:
+						entity = library._entities[instance.Entity.Name.NormalizedIdentifier]
+					except KeyError:
+						ex = VHDLModelException(f"Referenced entity '{instance.Entity.Name.Identifier}' in direct entity instantiation '{instance.Label}: entity {instance.Entity.Name.Prefix.Identifier}.{instance.Entity.Name.Identifier}' not found in {'working ' if instance.Entity.Name.Prefix.NormalizedIdentifier == 'work' else ''}library '{libraryIdentifier}'.")
+						libs = [library.Identifier for library in self._libraries.values() for entityIdentifier in library._entities.keys() if entityIdentifier == instance.Entity.Name.NormalizedIdentifier]
+						if libs:
+							ex.add_note(f"Found entity '{instance.Entity!s}' in other libraries: {', '.join(libs)}")
+						raise ex
+
+					instance.Entity.Entity = entity
+
+					dependency = architecture._dependencyVertex.EdgeToVertex(entity._dependencyVertex, edgeValue=instance)
+					dependency["kind"] = DependencyGraphEdgeKind.EntityInstantiation
+
+				elif isinstance(instance, ComponentInstantiation):
+					component = architecture._namespace.FindComponent(instance.Component)
+
+					instance.Component.Component = component
+
+					dependency = architecture._dependencyVertex.EdgeToVertex(component.Entity._dependencyVertex, edgeValue=instance)
+					dependency["kind"] = DependencyGraphEdgeKind.ComponentInstantiation
+
+				elif isinstance(instance, ConfigurationInstantiation):
+					# pass
+					print(instance.Label, instance.Configuration)
+
+	def IndexPackages(self) -> None:
+		"""
+		Index all declared items in all packages in all libraries.
+
+		.. rubric:: Algorithm
+
+		1. Iterate all libraries:
+
+		   1. Iterate all packages |br|
+		      |rarr| :meth:`pyVHDLModel.Library.IndexPackages`
+
+		      * Index all declared items in that package. |br|
+		        |rarr| :meth:`pyVHDLModel.DesignUnit.Package.IndexDeclaredItems`
+
+		.. seealso::
+
+		   :meth:`IndexPackageBodies`
+		     Index all declared items in all package bodies in all libraries.
+		   :meth:`IndexEntities`
+		     Index all declared items in all entities in all libraries.
+		   :meth:`IndexArchitectures`
+		     Index all declared items in all architectures in all libraries.
+		"""
+		for library in self._libraries.values():
+			library.IndexPackages()
+
+	def IndexPackageBodies(self) -> None:
+		"""
+		Index all declared items in all packages in all libraries.
+
+		.. rubric:: Algorithm
+
+		1. Iterate all libraries:
+
+		   1. Iterate all packages |br|
+		      |rarr| :meth:`pyVHDLModel.Library.IndexPackageBodies`
+
+		      * Index all declared items in that package body. |br|
+		        |rarr| :meth:`pyVHDLModel.DesignUnit.PackageBody.IndexDeclaredItems`
+
+		.. seealso::
+
+		   :meth:`IndexPackages`
+		     Index all declared items in all packages in all libraries.
+		   :meth:`IndexEntities`
+		     Index all declared items in all entities in all libraries.
+		   :meth:`IndexArchitectures`
+		     Index all declared items in all architectures in all libraries.
+		"""
+		for library in self._libraries.values():
+			library.IndexPackageBodies()
+
+	def IndexEntities(self) -> None:
+		"""
+		Index all declared items in all packages in all libraries.
+
+		.. rubric:: Algorithm
+
+		1. Iterate all libraries:
+
+		   1. Iterate all packages |br|
+		      |rarr| :meth:`pyVHDLModel.Library.IndexEntities`
+
+		      * Index all declared items in that entity. |br|
+		        |rarr| :meth:`pyVHDLModel.DesignUnit.Entity.IndexDeclaredItems`
+
+		.. seealso::
+
+		   :meth:`IndexPackages`
+		     Index all declared items in all packages in all libraries.
+		   :meth:`IndexPackageBodies`
+		     Index all declared items in all package bodies in all libraries.
+		   :meth:`IndexArchitectures`
+		     Index all declared items in all architectures in all libraries.
+		"""
+		for library in self._libraries.values():
+			library.IndexEntities()
+
+	def IndexArchitectures(self) -> None:
+		"""
+		Index all declared items in all packages in all libraries.
+
+		.. rubric:: Algorithm
+
+		1. Iterate all libraries:
+
+		   1. Iterate all packages |br|
+		      |rarr| :meth:`pyVHDLModel.Library.IndexArchitectures`
+
+		      * Index all declared items in that architecture. |br|
+		        |rarr| :meth:`pyVHDLModel.DesignUnit.Architecture.IndexDeclaredItems`
+
+		.. seealso::
+
+		   :meth:`IndexPackages`
+		     Index all declared items in all packages in all libraries.
+		   :meth:`IndexPackageBodies`
+		     Index all declared items in all package bodies in all libraries.
+		   :meth:`IndexEntities`
+		     Index all declared items in all entities in all libraries.
+		"""
+		for library in self._libraries.values():
+			library.IndexArchitectures()
+
+	def CreateHierarchyGraph(self) -> None:
+		"""
+		Create the hierarchy graph from dependency graph.
+
+		.. rubric:: Algorithm
+
+		1. Iterate all vertices corresponding to entities and architectures in the dependency graph:
+
+		   * Copy these vertices to the hierarchy graph and create a bidirectional linking. |br|
+		     In addition, set the referenced design unit's :attr:`~pyVHDLModel.Document._hierarchyVertex` field to reference the copied vertex.
+
+		     * Add a key-value-pair called ``hierarchyVertex`` to the dependency graph's vertex.
+		     * Add a key-value-pair called ``dependencyVertex`` to the hierarchy graph's vertex.
+
+		2. Iterate all architectures ...
+
+		   .. todo:: Design::CreateHierarchyGraph describe algorithm
+
+		   1. Iterate all outbound edges
+
+		      .. todo:: Design::CreateHierarchyGraph describe algorithm
+		"""
+		# Copy all entity and architecture vertices from dependency graph to hierarchy graph and double-link them
+		entityArchitectureFilter = lambda v: v["kind"] in DependencyGraphVertexKind.Entity | DependencyGraphVertexKind.Architecture
+		for vertex in self._dependencyGraph.IterateVertices(predicate=entityArchitectureFilter):
+			hierarchyVertex = vertex.Copy(self._hierarchyGraph, copyDict=True, linkingKeyToOriginalVertex="dependencyVertex", linkingKeyFromOriginalVertex="hierarchyVertex")
+			vertex.Value._hierarchyVertex = hierarchyVertex
+
+		# Copy implementation edges from
+		for hierarchyArchitectureVertex in self._hierarchyGraph.IterateVertices(predicate=lambda v: v["kind"] is DependencyGraphVertexKind.Architecture):
+			for dependencyEdge in hierarchyArchitectureVertex["dependencyVertex"].IterateOutboundEdges():
+				kind: DependencyGraphEdgeKind = dependencyEdge["kind"]
+				if DependencyGraphEdgeKind.Implementation in kind:
+					hierarchyDestinationVertex = dependencyEdge.Destination["hierarchyVertex"]
+					newEdge = hierarchyArchitectureVertex.EdgeFromVertex(hierarchyDestinationVertex)
+				elif DependencyGraphEdgeKind.Instantiation in kind:
+					hierarchyDestinationVertex = dependencyEdge.Destination["hierarchyVertex"]
+
+					# FIXME: avoid parallel edges, to graph can be converted to a tree until "real" hierarchy is computed (unrole generics and blocks)
+					if hierarchyArchitectureVertex.HasEdgeToDestination(hierarchyDestinationVertex):
+						continue
+
+					newEdge = hierarchyArchitectureVertex.EdgeToVertex(hierarchyDestinationVertex)
+				else:
+					continue
+
+				newEdge["kind"] = kind
+
+	def ComputeCompileOrder(self) -> None:
+		def predicate(edge: Edge) -> bool:
+			return (
+				DependencyGraphEdgeKind.Implementation in edge["kind"] or
+				DependencyGraphEdgeKind.Instantiation in edge["kind"] or
+				DependencyGraphEdgeKind.UseClause in edge["kind"] or
+				DependencyGraphEdgeKind.ContextReference in edge["kind"]
+			) and edge.Destination["predefined"] is False
+
+		for edge in self._dependencyGraph.IterateEdges(predicate=predicate):
+			sourceDocument:      Document = edge.Source.Value.Document
+			destinationDocument: Document = edge.Destination.Value.Document
+
+			sourceVertex =      sourceDocument._compileOrderVertex
+			destinationVertex = destinationDocument._compileOrderVertex
+
+			# Don't add self-edges
+			if sourceVertex is destinationVertex:
+				continue
+			# Don't add parallel edges
+			elif sourceVertex.HasEdgeToDestination(destinationVertex):
+				continue
+
+			e = sourceVertex.EdgeToVertex(destinationVertex)
+			e["kind"] = DependencyGraphEdgeKind.CompileOrder
+
+			e = sourceVertex["dependencyVertex"].EdgeToVertex(destinationVertex["dependencyVertex"])
+			e["kind"] = DependencyGraphEdgeKind.CompileOrder
+
+	def IterateDocumentsInCompileOrder(self) -> Generator['Document', None, None]:
+		"""
+		Iterate all document in compile-order.
+
+		.. rubric:: Algorithm
+
+		* Check if compile-order graph was populated with vertices and its vertices are linked by edges.
+
+		1. Iterate compile-order graph in topological order. |br|
+		   :meth:`pyTooling.Graph.Graph.IterateTopologically`
+
+		   * yield the compiler-order vertex' referenced document.
+
+		:returns:                   A generator to iterate all documents in compile-order in the design.
+		:raises VHDLModelException: If compile-order was not computed.
+
+		.. seealso::
+
+		   .. todo:: missing text
+
+		      :meth:`pyVHDLModel.Design.ComputeCompileOrder`
+
+		"""
+		if self._compileOrderGraph.EdgeCount < self._compileOrderGraph.VertexCount - 1:
+			raise VHDLModelException(f"Compile order is not yet computed from dependency graph.")
+
+		for compileOrderNode in self._compileOrderGraph.IterateTopologically():
+			yield compileOrderNode.Value
+
+	def GetUnusedDesignUnits(self) -> List[DesignUnit]:
+		raise NotImplementedError()
+
+	def __repr__(self) -> str:
+		"""
+		Formats a representation of the design.
+
+		**Format:** ``Document: 'my_design'``
+
+		:returns: String representation of the design.
+		"""
+		return f"Design: {self._name}"
+
+	__str__ = __repr__
+
+
+@export
+class Library(ModelEntity, NamedEntityMixin):
+	"""A ``Library`` represents a VHDL library. It contains all *primary* and *secondary* design units."""
+
+	_contexts:       Dict[str, Context]                  #: Dictionary of all contexts defined in a library.
+	_configurations: Dict[str, Configuration]            #: Dictionary of all configurations defined in a library.
+	_entities:       Dict[str, Entity]                   #: Dictionary of all entities defined in a library.
+	_architectures:  Dict[str, Dict[str, Architecture]]  #: Dictionary of all architectures defined in a library.
+	_packages:       Dict[str, Package]                  #: Dictionary of all packages defined in a library.
+	_packageBodies:  Dict[str, PackageBody]              #: Dictionary of all package bodies defined in a library.
+
+	_dependencyVertex: Vertex[None, None, str, Union['Library', DesignUnit], None, None, None, None, None, None, None, None, None, None, None, None, None]  #: Reference to the vertex in the dependency graph representing the library. |br| This reference is set by :meth:`~pyVHDLModel.Design.CreateDependencyGraph`.
+
+	def __init__(self, identifier: str, parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+		NamedEntityMixin.__init__(self, identifier)
+
+		self._contexts =        {}
+		self._configurations =  {}
+		self._entities =        {}
+		self._architectures =   {}
+		self._packages =        {}
+		self._packageBodies =   {}
+
+		self._dependencyVertex = None
+
+	@readonly
+	def Contexts(self) -> Dict[str, Context]:
+		"""Returns a list of all context declarations declared in this library."""
+		return self._contexts
+
+	@readonly
+	def Configurations(self) -> Dict[str, Configuration]:
+		"""Returns a list of all configuration declarations declared in this library."""
+		return self._configurations
+
+	@readonly
+	def Entities(self) -> Dict[str, Entity]:
+		"""Returns a list of all entity declarations declared in this library."""
+		return self._entities
+
+	@readonly
+	def Architectures(self) -> Dict[str, Dict[str, Architecture]]:
+		"""Returns a list of all architectures declarations declared in this library."""
+		return self._architectures
+
+	@readonly
+	def Packages(self) -> Dict[str, Package]:
+		"""Returns a list of all package declarations declared in this library."""
+		return self._packages
+
+	@readonly
+	def PackageBodies(self) -> Dict[str, PackageBody]:
+		"""Returns a list of all package body declarations declared in this library."""
+		return self._packageBodies
+
+	@readonly
+	def DependencyVertex(self) -> Vertex:
+		"""
+		Read-only property to access the corresponding dependency vertex (:attr:`_dependencyVertex`).
+
+		The dependency vertex references this library by its value field.
+
+		:returns: The corresponding dependency vertex.
+		"""
+		return self._dependencyVertex
+
+	def IterateDesignUnits(self, filter: DesignUnitKind = DesignUnitKind.All) -> Generator[DesignUnit, None, None]:
+		"""
+		Iterate all design units in the library.
+
+		A union of :class:`DesignUnitKind` values can be given to filter the returned result for suitable design units.
+
+		.. rubric:: Algorithm
+
+		1. Iterate all contexts in that library.
+		2. Iterate all packages in that library.
+		3. Iterate all package bodies in that library.
+		4. Iterate all entites in that library.
+		5. Iterate all architectures in that library.
+		6. Iterate all configurations in that library.
+
+		:param filter: An enumeration with possibly multiple flags to filter the returned design units.
+		:returns:      A generator to iterate all matched design units in the library.
+
+		.. seealso::
+
+		   :meth:`pyVHDLModel.Design.IterateDesignUnits`
+		     Iterate all design units in the design.
+		   :meth:`pyVHDLModel.Document.IterateDesignUnits`
+		     Iterate all design units in the document.
+		"""
+		if DesignUnitKind.Context in filter:
+			for context in self._contexts.values():
+				yield context
+
+		if DesignUnitKind.Package in filter:
+			for package in self._packages.values():
+				yield package
+
+		if DesignUnitKind.PackageBody in filter:
+			for packageBody in self._packageBodies.values():
+				yield packageBody
+
+		if DesignUnitKind.Entity in filter:
+			for entity in self._entities.values():
+				yield entity
+
+		if DesignUnitKind.Architecture in filter:
+			for architectures in self._architectures.values():
+				for architecture in architectures.values():
+					yield architecture
+
+		if DesignUnitKind.Configuration in filter:
+			for configuration in self._configurations.values():
+				yield configuration
+
+		# for verificationProperty in self._verificationUnits.values():
+		# 	yield verificationProperty
+		# for verificationUnit in self._verificationProperties.values():
+		# 	yield entity
+		# for verificationMode in self._verificationModes.values():
+		# 	yield verificationMode
+
+	def LinkArchitectures(self) -> None:
+		"""
+		Link all architectures to corresponding entities.
+
+		.. rubric:: Algorithm
+
+		1. Iterate all architecture groups (grouped per entity symbol's name).
+
+		   * Check if entity symbol's name exists as an entity in this library.
+
+		   1. For each architecture in the same architecture group:
+
+		      * Add architecture to entities architecture dictionary :attr:`pyVHDLModel.DesignUnit.Entity._architectures`.
+		      * Assign found entity to architecture's entity symbol :attr:`pyVHDLModel.DesignUnit.Architecture._entity`
+		      * Set parent namespace of architecture's namespace to the entitie's namespace.
+		      * Add an edge in the dependency graph from the architecture's corresponding dependency vertex to the entity's corresponding dependency vertex.
+
+		:raises VHDLModelException: If entity name doesn't exist.
+		:raises VHDLModelException: If architecture name already exists for entity.
+
+		.. seealso::
+
+		   :meth:`LinkPackageBodies`
+		     Link all package bodies to corresponding packages.
+		"""
+		for entityName, architecturesPerEntity in self._architectures.items():
+			if entityName not in self._entities:
+				architectureNames = "', '".join(architecturesPerEntity.keys())
+				raise VHDLModelException(f"Entity '{entityName}' referenced by architecture(s) '{architectureNames}' doesn't exist in library '{self._identifier}'.")
+			# TODO: search in other libraries to find that entity.
+			# TODO: add code position
+
+			entity = self._entities[entityName]
+			for architecture in architecturesPerEntity.values():
+				if architecture._normalizedIdentifier in entity._architectures:
+					raise VHDLModelException(f"Architecture '{architecture._identifier}' already exists for entity '{entity._identifier}'.")
+				# TODO: add code position of existing and current
+
+				entity._architectures[architecture._normalizedIdentifier] = architecture
+				architecture._entity.Entity = entity
+				architecture._namespace._parentNamespace = entity._namespace
+
+				# add "architecture -> entity" relation in dependency graph
+				dependency = architecture._dependencyVertex.EdgeToVertex(entity._dependencyVertex)
+				dependency["kind"] = DependencyGraphEdgeKind.EntityImplementation
+
+	def LinkPackageBodies(self) -> None:
+		"""
+		Link all package bodies to corresponding packages.
+
+		.. rubric:: Algorithm
+
+		1. Iterate all package bodies.
+
+		   * Check if package body symbol's name exists as a package in this library.
+		   * Add package body to package :attr:`pyVHDLModel.DesignUnit.Package._packageBody`.
+		   * Assign found package to package body's package symbol :attr:`pyVHDLModel.DesignUnit.PackageBody._package`
+		   * Set parent namespace of package body's namespace to the package's namespace.
+		   * Add an edge in the dependency graph from the package body's corresponding dependency vertex to the package's corresponding dependency vertex.
+
+		:raises VHDLModelException: If package name doesn't exist.
+
+		.. seealso::
+
+		   :meth:`LinkArchitectures`
+		     Link all architectures to corresponding entities.
+		"""
+		for packageBodyName, packageBody in self._packageBodies.items():
+			if packageBodyName not in self._packages:
+				raise VHDLModelException(f"Package '{packageBodyName}' referenced by package body '{packageBodyName}' doesn't exist in library '{self._identifier}'.")
+
+			package = self._packages[packageBodyName]
+			package._packageBody = packageBody    # TODO: add warning if package had already a body, which is now replaced
+			packageBody._package.Package = package
+			packageBody._namespace._parentNamespace = package._namespace
+
+			# add "package body -> package" relation in dependency graph
+			dependency = packageBody._dependencyVertex.EdgeToVertex(package._dependencyVertex)
+			dependency["kind"] = DependencyGraphEdgeKind.PackageImplementation
+
+	def IndexPackages(self) -> None:
+		"""
+		Index declared items in all packages.
+
+		.. rubric:: Algorithm
+
+		1. Iterate all packages:
+
+		   * Index all declared items. |br|
+		     |rarr| :meth:`pyVHDLModel.DesignUnit.Package.IndexDeclaredItems`
+
+		.. seealso::
+
+		   :meth:`IndexPackageBodies`
+		     Index all declared items in a package body.
+		   :meth:`IndexEntities`
+		     Index all declared items in an entity.
+		   :meth:`IndexArchitectures`
+		     Index all declared items in an architecture.
+		"""
+		for package in self._packages.values():
+			if isinstance(package, Package):
+				package.IndexDeclaredItems()
+
+	def IndexPackageBodies(self) -> None:
+		"""
+		Index declared items in all package bodies.
+
+		.. rubric:: Algorithm
+
+		1. Iterate all package bodies:
+
+		   * Index all declared items. |br|
+		     |rarr| :meth:`pyVHDLModel.DesignUnit.PackageBody.IndexDeclaredItems`
+
+		.. seealso::
+
+		   :meth:`IndexPackages`
+		     Index all declared items in a package.
+		   :meth:`IndexEntities`
+		     Index all declared items in an entity.
+		   :meth:`IndexArchitectures`
+		     Index all declared items in an architecture.
+		"""
+		for packageBody in self._packageBodies.values():
+			packageBody.IndexDeclaredItems()
+
+	def IndexEntities(self) -> None:
+		"""
+		Index declared items in all entities.
+
+		.. rubric:: Algorithm
+
+		1. Iterate all entities:
+
+		   * Index all declared items. |br|
+		     |rarr| :meth:`pyVHDLModel.DesignUnit.Entity.IndexDeclaredItems`
+
+		.. seealso::
+
+		   :meth:`IndexPackages`
+		     Index all declared items in a package.
+		   :meth:`IndexPackageBodies`
+		     Index all declared items in a package body.
+		   :meth:`IndexArchitectures`
+		     Index all declared items in an architecture.
+		"""
+		for entity in self._entities.values():
+			entity.IndexDeclaredItems()
+
+	def IndexArchitectures(self) -> None:
+		"""
+		Index declared items in all architectures.
+
+		.. rubric:: Algorithm
+
+		1. Iterate all architectures:
+
+		   * Index all declared items. |br|
+		     |rarr| :meth:`pyVHDLModel.DesignUnit.Architecture.IndexDeclaredItems`
+
+		.. seealso::
+
+		   :meth:`IndexPackages`
+		     Index all declared items in a package.
+		   :meth:`IndexPackageBodies`
+		     Index all declared items in a package body.
+		   :meth:`IndexEntities`
+		     Index all declared items in an entity.
+		"""
+		for architectures in self._architectures.values():
+			for architecture in architectures.values():
+				architecture.IndexDeclaredItems()
+				architecture.IndexStatements()
+
+	def __repr__(self) -> str:
+		"""
+		Formats a representation of the library.
+
+		**Format:** ``Library: 'my_library'``
+
+		:returns: String representation of the library.
+		"""
+		return f"Library: '{self._identifier}'"
+
+	__str__ = __repr__
+
+
+@export
+class Document(ModelEntity, DocumentedEntityMixin):
+	"""A ``Document`` represents a sourcefile. It contains *primary* and *secondary* design units."""
+
+	_path:                   Path                                #: path to the document. ``None`` if virtual document.
+	_designUnits:            List[DesignUnit]                    #: List of all design units defined in a document.
+	_contexts:               Dict[str, Context]                  #: Dictionary of all contexts defined in a document.
+	_configurations:         Dict[str, Configuration]            #: Dictionary of all configurations defined in a document.
+	_entities:               Dict[str, Entity]                   #: Dictionary of all entities defined in a document.
+	_architectures:          Dict[str, Dict[str, Architecture]]  #: Dictionary of all architectures defined in a document.
+	_packages:               Dict[str, Package]                  #: Dictionary of all packages defined in a document.
+	_packageBodies:          Dict[str, PackageBody]              #: Dictionary of all package bodies defined in a document.
+	_verificationUnits:      Dict[str, VerificationUnit]         #: Dictionary of all PSL verification units defined in a document.
+	_verificationProperties: Dict[str, VerificationProperty]     #: Dictionary of all PSL verification properties defined in a document.
+	_verificationModes:      Dict[str, VerificationMode]         #: Dictionary of all PSL verification modes defined in a document.
+
+	_dependencyVertex:       Vertex[None, None, None, 'Document', None, None, None, None, None, None, None, None, None, None, None, None, None]  #: Reference to the vertex in the dependency graph representing the document. |br| This reference is set by :meth:`~pyVHDLModel.Design.CreateCompileOrderGraph`.
+	_compileOrderVertex:     Vertex[None, None, None, 'Document', None, None, None, None, None, None, None, None, None, None, None, None, None]  #: Reference to the vertex in the compile-order graph representing the document. |br| This reference is set by :meth:`~pyVHDLModel.Design.CreateCompileOrderGraph`.
+
+	def __init__(self, path: Path, documentation: Nullable[str] = None, parent: ModelEntity = None) -> None:
+		super().__init__(parent)
+		DocumentedEntityMixin.__init__(self, documentation)
+
+		self._path =                   path
+		self._designUnits =            []
+		self._contexts =               {}
+		self._configurations =         {}
+		self._entities =               {}
+		self._architectures =          {}
+		self._packages =               {}
+		self._packageBodies =          {}
+		self._verificationUnits =      {}
+		self._verificationProperties = {}
+		self._verificationModes =      {}
+
+		self._dependencyVertex =   None
+		self._compileOrderVertex = None
+
+	def _AddEntity(self, item: Entity) -> None:
+		"""
+		Add an entity to the document's lists of design units.
+
+		:param item:                Entity object to be added to the document.
+		:raises TypeError:          If parameter 'item' is not of type :class:`~pyVHDLModel.DesignUnits.Entity`.
+		:raises VHDLModelException: If entity name already exists in document.
+		"""
+		if not isinstance(item, Entity):
+			ex = TypeError(f"Parameter 'item' is not of type 'Entity'.")
+			if version_info >= (3, 11):  # pragma: no cover
+				ex.add_note(f"Got type '{getFullyQualifiedName(item)}'.")
+			raise ex
+
+		identifier = item._normalizedIdentifier
+		if identifier in self._entities:
+			# TODO: use a more specific exception
+			raise VHDLModelException(f"An entity '{item._identifier}' already exists in this document.")
+
+		self._entities[identifier] = item
+		self._designUnits.append(item)
+		item._document = self
+
+	def _AddArchitecture(self, item: Architecture) -> None:
+		"""
+		Add an architecture to the document's lists of design units.
+
+		:param item:                Architecture object to be added to the document.
+		:raises TypeError:          If parameter 'item' is not of type :class:`~pyVHDLModel.DesignUnits.Architecture`.
+		:raises VHDLModelException: If architecture name already exists for the referenced entity name in document.
+		"""
+		if not isinstance(item, Architecture):
+			ex = TypeError(f"Parameter 'item' is not of type 'Architecture'.")
+			if version_info >= (3, 11):  # pragma: no cover
+				ex.add_note(f"Got type '{getFullyQualifiedName(item)}'.")
+			raise ex
+
+		entity = item._entity.Name
+		entityIdentifier = entity._normalizedIdentifier
+		try:
+			architectures = self._architectures[entityIdentifier]
+			if item._normalizedIdentifier in architectures:
+				# TODO: use a more specific exception
+				# FIXME: this is allowed and should be a warning or a strict mode.
+				raise VHDLModelException(f"An architecture '{item._identifier}' for entity '{entity._identifier}' already exists in this document.")
+
+			architectures[item.Identifier] = item
+		except KeyError:
+			self._architectures[entityIdentifier] = {item._identifier: item}
+
+		self._designUnits.append(item)
+		item._document = self
+
+	def _AddPackage(self, item: Package) -> None:
+		"""
+		Add a package to the document's lists of design units.
+
+		:param item:                Package object to be added to the document.
+		:raises TypeError:          If parameter 'item' is not of type :class:`~pyVHDLModel.DesignUnits.Package`.
+		:raises VHDLModelException: If package name already exists in document.
+		"""
+		if not isinstance(item, (Package, PackageInstantiation)):
+			ex = TypeError(f"Parameter 'item' is not of type 'Package' or 'PackageInstantiation'.")
+			if version_info >= (3, 11):  # pragma: no cover
+				ex.add_note(f"Got type '{getFullyQualifiedName(item)}'.")
+			raise ex
+
+		identifier = item._normalizedIdentifier
+		if identifier in self._packages:
+			# TODO: use a more specific exception
+			raise VHDLModelException(f"A package '{item._identifier}' already exists in this document.")
+
+		self._packages[identifier] = item
+		self._designUnits.append(item)
+		item._document = self
+
+	def _AddPackageBody(self, item: PackageBody) -> None:
+		"""
+		Add a package body to the document's lists of design units.
+
+		:param item:                Package body object to be added to the document.
+		:raises TypeError:          If parameter 'item' is not of type :class:`~pyVHDLModel.DesignUnits.PackageBody`.
+		:raises VHDLModelException: If package body name already exists in document.
+		"""
+		if not isinstance(item, PackageBody):
+			ex = TypeError(f"Parameter 'item' is not of type 'PackageBody'.")
+			if version_info >= (3, 11):  # pragma: no cover
+				ex.add_note(f"Got type '{getFullyQualifiedName(item)}'.")
+			raise ex
+
+		identifier = item._normalizedIdentifier
+		if identifier in self._packageBodies:
+			# TODO: use a more specific exception
+			raise VHDLModelException(f"A package body '{item._identifier}' already exists in this document.")
+
+		self._packageBodies[identifier] = item
+		self._designUnits.append(item)
+		item._document = self
+
+	def _AddContext(self, item: Context) -> None:
+		"""
+		Add a context to the document's lists of design units.
+
+		:param item:                Context object to be added to the document.
+		:raises TypeError:          If parameter 'item' is not of type :class:`~pyVHDLModel.DesignUnits.Context`.
+		:raises VHDLModelException: If context name already exists in document.
+		"""
+		if not isinstance(item, Context):
+			ex = TypeError(f"Parameter 'item' is not of type 'Context'.")
+			if version_info >= (3, 11):  # pragma: no cover
+				ex.add_note(f"Got type '{getFullyQualifiedName(item)}'.")
+			raise ex
+
+		identifier = item._normalizedIdentifier
+		if identifier in self._contexts:
+			# TODO: use a more specific exception
+			raise VHDLModelException(f"A context '{item._identifier}' already exists in this document.")
+
+		self._contexts[identifier] = item
+		self._designUnits.append(item)
+		item._document = self
+
+	def _AddConfiguration(self, item: Configuration) -> None:
+		"""
+		Add a configuration to the document's lists of design units.
+
+		:param item:                Configuration object to be added to the document.
+		:raises TypeError:          If parameter 'item' is not of type :class:`~pyVHDLModel.DesignUnits.Configuration`.
+		:raises VHDLModelException: If configuration name already exists in document.
+		"""
+		if not isinstance(item, Configuration):
+			ex = TypeError(f"Parameter 'item' is not of type 'Configuration'.")
+			if version_info >= (3, 11):  # pragma: no cover
+				ex.add_note(f"Got type '{getFullyQualifiedName(item)}'.")
+			raise ex
+
+		identifier = item._normalizedIdentifier
+		if identifier in self._configurations:
+			# TODO: use a more specific exception
+			raise VHDLModelException(f"A configuration '{item._identifier}' already exists in this document.")
+
+		self._configurations[identifier] = item
+		self._designUnits.append(item)
+		item._document = self
+
+	def _AddVerificationUnit(self, item: VerificationUnit) -> None:
+		if not isinstance(item, VerificationUnit):
+			ex = TypeError(f"Parameter 'item' is not of type 'VerificationUnit'.")
+			if version_info >= (3, 11):  # pragma: no cover
+				ex.add_note(f"Got type '{getFullyQualifiedName(item)}'.")
+			raise ex
+
+		identifier = item._normalizedIdentifier
+		if identifier in self._verificationUnits:
+			raise ValueError(f"A verification unit '{item._identifier}' already exists in this document.")
+
+		self._verificationUnits[identifier] = item
+		self._designUnits.append(item)
+		item._document = self
+
+	def _AddVerificationProperty(self, item: VerificationProperty) -> None:
+		if not isinstance(item, VerificationProperty):
+			ex = TypeError(f"Parameter 'item' is not of type 'VerificationProperty'.")
+			if version_info >= (3, 11):  # pragma: no cover
+				ex.add_note(f"Got type '{getFullyQualifiedName(item)}'.")
+			raise ex
+
+		identifier = item.NormalizedIdentifier
+		if identifier in self._verificationProperties:
+			raise ValueError(f"A verification property '{item.Identifier}' already exists in this document.")
+
+		self._verificationProperties[identifier] = item
+		self._designUnits.append(item)
+		item._document = self
+
+	def _AddVerificationMode(self, item: VerificationMode) -> None:
+		if not isinstance(item, VerificationMode):
+			ex = TypeError(f"Parameter 'item' is not of type 'VerificationMode'.")
+			if version_info >= (3, 11):  # pragma: no cover
+				ex.add_note(f"Got type '{getFullyQualifiedName(item)}'.")
+			raise ex
+
+		identifier = item.NormalizedIdentifier
+		if identifier in self._verificationModes:
+			raise ValueError(f"A verification mode '{item.Identifier}' already exists in this document.")
+
+		self._verificationModes[identifier] = item
+		self._designUnits.append(item)
+		item._document = self
+
+	def _AddDesignUnit(self, item: DesignUnit) -> None:
+		"""
+		Add a design unit to the document's lists of design units.
+
+		:param item:                Configuration object to be added to the document.
+		:raises TypeError:          If parameter 'item' is not of type :class:`~pyVHDLModel.DesignUnits.DesignUnit`.
+		:raises ValueError:         If parameter 'item' is an unknown :class:`~pyVHDLModel.DesignUnits.DesignUnit`.
+		:raises VHDLModelException: If configuration name already exists in document.
+		"""
+		if not isinstance(item, DesignUnit):
+			ex = TypeError(f"Parameter 'item' is not of type 'DesignUnit'.")
+			if version_info >= (3, 11):  # pragma: no cover
+				ex.add_note(f"Got type '{getFullyQualifiedName(item)}'.")
+			raise ex
+
+		if isinstance(item, Entity):
+			self._AddEntity(item)
+		elif isinstance(item, Architecture):
+			self._AddArchitecture(item)
+		elif isinstance(item, Package):
+			self._AddPackage(item)
+		elif isinstance(item, PackageBody):
+			self._AddPackageBody(item)
+		elif isinstance(item, Context):
+			self._AddContext(item)
+		elif isinstance(item, Configuration):
+			self._AddConfiguration(item)
+		elif isinstance(item, VerificationUnit):
+			self._AddVerificationUnit(item)
+		elif isinstance(item, VerificationProperty):
+			self._AddVerificationProperty(item)
+		elif isinstance(item, VerificationMode):
+			self._AddVerificationMode(item)
+		else:
+			ex = ValueError(f"Parameter 'item' is an unknown 'DesignUnit'.")
+			if version_info >= (3, 11):  # pragma: no cover
+				ex.add_note(f"Got type '{getFullyQualifiedName(item)}'.")
+			raise ex
+
+	@readonly
+	def Path(self) -> Path:
+		"""
+		Read-only property to access the document's path (:attr:`_path`).
+
+		:returns: The path of this document.
+		"""
+		return self._path
+
+	@readonly
+	def DesignUnits(self) -> List[DesignUnit]:
+		"""
+		Read-only property to access a list of all design units declarations found in this document (:attr:`_designUnits`).
+
+		:returns: List of all design units.
+		"""
+		return self._designUnits
+
+	@readonly
+	def Contexts(self) -> Dict[str, Context]:
+		"""
+		Read-only property to access a list of all context declarations found in this document (:attr:`_contexts`).
+
+		:returns: List of all contexts.
+		"""
+		return self._contexts
+
+	@readonly
+	def Configurations(self) -> Dict[str, Configuration]:
+		"""
+		Read-only property to access a list of all configuration declarations found in this document (:attr:`_configurations`).
+
+		:returns: List of all configurations.
+		"""
+		return self._configurations
+
+	@readonly
+	def Entities(self) -> Dict[str, Entity]:
+		"""
+		Read-only property to access a list of all entity declarations found in this document (:attr:`_entities`).
+
+		:returns: List of all entities.
+		"""
+		return self._entities
+
+	@readonly
+	def Architectures(self) -> Dict[str, Dict[str, Architecture]]:
+		"""
+		Read-only property to access a list of all architecture declarations found in this document (:attr:`_architectures`).
+
+		:returns: List of all architectures.
+		"""
+		return self._architectures
+
+	@readonly
+	def Packages(self) -> Dict[str, Package]:
+		"""
+		Read-only property to access a list of all package declarations found in this document (:attr:`_packages`).
+
+		:returns: List of all packages.
+		"""
+		return self._packages
+
+	@readonly
+	def PackageBodies(self) -> Dict[str, PackageBody]:
+		"""
+		Read-only property to access a list of all package body declarations found in this document (:attr:`_packageBodies`).
+
+		:returns: List of all package bodies.
+		"""
+		return self._packageBodies
+
+	@readonly
+	def VerificationUnits(self) -> Dict[str, VerificationUnit]:
+		"""
+		Read-only property to access a list of all verification unit declarations found in this document (:attr:`_verificationUnits`).
+
+		:returns: List of all verification units.
+		"""
+		return self._verificationUnits
+
+	@readonly
+	def VerificationProperties(self) -> Dict[str, VerificationProperty]:
+		"""
+		Read-only property to access a list of all verification properties declarations found in this document (:attr:`_verificationProperties`).
+
+		:returns: List of all verification properties.
+		"""
+		return self._verificationProperties
+
+	@readonly
+	def VerificationModes(self) -> Dict[str, VerificationMode]:
+		"""
+		Read-only property to access a list of all verification modes declarations found in this document (:attr:`_verificationModes`).
+
+		:returns: List of all verification modes.
+		"""
+		return self._verificationModes
+
+	@readonly
+	def CompileOrderVertex(self) -> Vertex[None, None, None, 'Document', None, None, None, None, None, None, None, None, None, None, None, None, None]:
+		"""
+		Read-only property to access the corresponding compile-order vertex (:attr:`_compileOrderVertex`).
+
+		The compile-order vertex references this document by its value field.
+
+		:returns: The corresponding compile-order vertex.
+		"""
+		return self._compileOrderVertex
+
+	def IterateDesignUnits(self, filter: DesignUnitKind = DesignUnitKind.All) -> Generator[DesignUnit, None, None]:
+		"""
+		Iterate all design units in the document.
+
+		A union of :class:`DesignUnitKind` values can be given to filter the returned result for suitable design units.
+
+		.. rubric:: Algorithm
+
+		* If contexts are selected in the filter:
+
+		  1. Iterate all contexts in that library.
+
+		* If packages are selected in the filter:
+
+		  1. Iterate all packages in that library.
+
+		* If package bodies are selected in the filter:
+
+		  1. Iterate all package bodies in that library.
+
+		* If entites are selected in the filter:
+
+		  1. Iterate all entites in that library.
+
+		* If architectures are selected in the filter:
+
+		  1. Iterate all architectures in that library.
+
+		* If configurations are selected in the filter:
+
+		  1. Iterate all configurations in that library.
+
+		:param filter: An enumeration with possibly multiple flags to filter the returned design units.
+		:returns:      A generator to iterate all matched design units in the document.
+
+		.. seealso::
+
+		   :meth:`pyVHDLModel.Design.IterateDesignUnits`
+		     Iterate all design units in the design.
+		   :meth:`pyVHDLModel.Library.IterateDesignUnits`
+		     Iterate all design units in the library.
+		"""
+		if DesignUnitKind.Context in filter:
+			for context in self._contexts.values():
+				yield context
+
+		if DesignUnitKind.Package in filter:
+			for package in self._packages.values():
+				yield package
+
+		if DesignUnitKind.PackageBody in filter:
+			for packageBody in self._packageBodies.values():
+				yield packageBody
+
+		if DesignUnitKind.Entity in filter:
+			for entity in self._entities.values():
+				yield entity
+
+		if DesignUnitKind.Architecture in filter:
+			for architectures in self._architectures.values():
+				for architecture in architectures.values():
+					yield architecture
+
+		if DesignUnitKind.Configuration in filter:
+			for configuration in self._configurations.values():
+				yield configuration
+
+		# for verificationProperty in self._verificationUnits.values():
+		# 	yield verificationProperty
+		# for verificationUnit in self._verificationProperties.values():
+		# 	yield entity
+		# for verificationMode in self._verificationModes.values():
+		# 	yield verificationMode
+
+	def __repr__(self) -> str:
+		"""
+		Formats a representation of the document.
+
+		**Format:** ``Document: 'path/to/file.vhdl'``
+
+		:returns: String representation of the document.
+		"""
+		return f"Document: '{self._path}'"
+
+	__str__ = __repr__
+
+ + diff --git a/typing/index.html b/typing/index.html new file mode 100644 index 000000000..3e9a2fed8 --- /dev/null +++ b/typing/index.html @@ -0,0 +1,139 @@ + + + + + + +

Mypy Type Check Coverage Summary

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary from index
FileImprecisionLines
Total6.95% imprecise9743 LOC
pyVHDLModel12.39% imprecise2575 LOC
pyVHDLModel.Association0.93% imprecise108 LOC
pyVHDLModel.Base0.66% imprecise452 LOC
pyVHDLModel.Common3.12% imprecise128 LOC
pyVHDLModel.Concurrent4.22% imprecise877 LOC
pyVHDLModel.Declaration0.53% imprecise190 LOC
pyVHDLModel.DesignUnit7.04% imprecise781 LOC
pyVHDLModel.Exception0.28% imprecise359 LOC
pyVHDLModel.Expression1.78% imprecise788 LOC
pyVHDLModel.IEEE10.66% imprecise422 LOC
pyVHDLModel.Instantiation0.00% imprecise101 LOC
pyVHDLModel.Interface0.00% imprecise212 LOC
pyVHDLModel.Name3.95% imprecise228 LOC
pyVHDLModel.Namespace24.66% imprecise146 LOC
pyVHDLModel.Object2.03% imprecise246 LOC
pyVHDLModel.PSLModel0.00% imprecise73 LOC
pyVHDLModel.Predefined12.61% imprecise119 LOC
pyVHDLModel.Regions15.46% imprecise194 LOC
pyVHDLModel.STD8.70% imprecise253 LOC
pyVHDLModel.Sequential5.02% imprecise498 LOC
pyVHDLModel.Subprogram3.01% imprecise133 LOC
pyVHDLModel.Symbol6.65% imprecise481 LOC
pyVHDLModel.Type5.01% imprecise379 LOC
+ + diff --git a/typing/mypy-html.css b/typing/mypy-html.css new file mode 100644 index 000000000..ec2bdf9c9 --- /dev/null +++ b/typing/mypy-html.css @@ -0,0 +1,104 @@ +/* CSS for type check coverage reports */ + +/* + Used by both summary and file. +*/ +body { + font-family: "Helvetica Neue", sans-serif; +} + +/* + Used only by summary. +*/ + +h1 { + text-align: center; + font-size: 135%; + margin: 20px; +} + +table.summary { + border-collapse: collapse; + margin-left: 7%; + margin-right: 7%; + width: 85%; +} + +table caption { + margin: 1em; +} + +table.summary, tr.summary, th.summary, td.summary { + border: 1px solid #aaa; +} + +th.summary, td.summary { + padding: 0.4em; +} + +td.summary a { + text-decoration: none; +} + +.summary-quality-0 { + background-color: #dfd; +} + +.summary-quality-1 { + background-color: #ffa; +} + +.summary-quality-2 { + background-color: #faa; +} + +td.summary-filename, th.summary-filename { + text-align: left; +} + +td.summary-filename { + width: 50%; +} + +.summary-precision { + text-align: center; +} + +.summary-lines { + text-align: center; +} + +/* + Used only by file. +*/ + +td.table-lines { + text-align: right; + padding-right: 0.5em; +} + +td.table-code { } + +span.lineno { + text-align: right; +} + +a:link.lineno, a:visited.lineno { + color: #999; text-decoration: none; +} + +a:hover.lineno, a:active.lineno { + color: #000; text-decoration: underline; +} + +.line-empty, .line-precise { + background-color: #dfd; +} + +.line-imprecise { + background-color: #ffa; +} + +.line-any, .line-unanalyzed { + background-color: #faa; +} diff --git a/unittests/index.html b/unittests/index.html new file mode 100644 index 000000000..a78f0b30b --- /dev/null +++ b/unittests/index.html @@ -0,0 +1,776 @@ + + + + + + + Unittest Summary Report — pyVHDLModel 0.29.0 documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+
+ +
+
+
+
+ +
+

Unittest Summary Report

+

Unittest report generated with pytest.

+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Testsuite / Testcase

Testcases

Skipped

Errored

Failed

Passed

Assertions

Runtime (HH:MM:SS.sss)

✅tests

56

0

0

0

56

00:00:00.031

  ✅unit

56

0

0

0

56

00:00:00.031

    ✅Analyze

12

0

0

0

12

00:00:00.031

      ✅VHDLLibrary

12

0

0

0

12

00:00:00.031

        ✅test_Analyze

0

00:00:00.031

        ✅test_CreateHierarchyGraph

0

00:00:00.005

        ✅test_DependencyGraph

0

00:00:00.013

        ✅test_IndexArchitectures

0

00:00:00.004

        ✅test_IndexPackages

0

00:00:00.004

        ✅test_LinkArchitectures

0

00:00:00.004

        ✅test_LinkContextReferences

0

00:00:00.006

        ✅test_LinkContexts

0

00:00:00.005

        ✅test_LinkInstantiations

0

00:00:00.004

        ✅test_LinkLibraryReferences

0

00:00:00.005

        ✅test_LinkPackageBodies

0

00:00:00.004

        ✅test_LinkPackageReferences

0

00:00:00.007

    ✅Instantiate

44

0

0

0

44

00:00:00.001

      ✅Names

5

0

0

0

5

00:00:00.001

        ✅test_AllName

0

00:00:00.001

        ✅test_AttributeName

0

00:00:00.001

        ✅test_SelectedName_1

0

00:00:00.001

        ✅test_SelectedName_2

0

00:00:00.001

        ✅test_SimpleName

0

00:00:00.001

      ✅SimpleInstance

14

0

0

0

14

00:00:00.001

        ✅test_Architecture

0

00:00:00.001

        ✅test_Array

0

00:00:00.001

        ✅test_Configuration

0

00:00:00.001

        ✅test_Context

0

00:00:00.001

        ✅test_Design

0

00:00:00.001

        ✅test_Document

0

00:00:00.001

        ✅test_Entity

0

00:00:00.001

        ✅test_Integer

0

00:00:00.001

        ✅test_Library

0

00:00:00.001

        ✅test_Package

0

00:00:00.001

        ✅test_PackageBody

0

00:00:00.001

        ✅test_Real

0

00:00:00.001

        ✅test_Record

0

00:00:00.001

        ✅test_Subtype

0

00:00:00.001

      ✅Symbols

11

0

0

0

11

00:00:00.001

        ✅test_AllPackageMembersReferenceSymbol

0

00:00:00.001

        ✅test_ComponentInstantiationSymbol

0

00:00:00.001

        ✅test_ConfigurationInstantiationSymbol

0

00:00:00.001

        ✅test_ContextReferenceSymbol

0

00:00:00.001

        ✅test_EntityInstantiationSymbol

0

00:00:00.001

        ✅test_LibraryReferenceSymbol

0

00:00:00.001

        ✅test_PackageMemberReferenceSymbol

0

00:00:00.001

        ✅test_PackageReferenceSymbol

0

00:00:00.001

        ✅test_PackageSymbol

0

00:00:00.001

        ✅test_SelectedEntitySymbol

0

00:00:00.001

        ✅test_SimpleEntitySymbol

0

00:00:00.001

      ✅VHDLDocument

8

0

0

0

8

00:00:00.001

        ✅test_Architecture

0

00:00:00.001

        ✅test_Configuration

0

00:00:00.001

        ✅test_Context

0

00:00:00.001

        ✅test_DesignUnits

0

00:00:00.001

        ✅test_Documentation

0

00:00:00.001

        ✅test_Entity

0

00:00:00.001

        ✅test_Package

0

00:00:00.001

        ✅test_PackageBody

0

00:00:00.001

      ✅VHDLLibrary

6

0

0

0

6

00:00:00.001

        ✅test_AddDocument

0

00:00:00.001

        ✅test_AddLibrary

0

00:00:00.001

        ✅test_GetLibrary

0

00:00:00.001

        ✅test_IeeeLibrary

0

00:00:00.002

        ✅test_IeeeSynopsysLibrary

0

00:00:00.002

        ✅test_StdLibrary

0

00:00:00.003

+
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file