replaced TbUtilPkg.Create... with ClockResetPkg.Create...

JimLewis · JimLewis · commit e8aebae692db · 2024-07-06T20:41:42.000-07:00
diff --git a/Axi4/testbench/TbAxi4.vhd b/Axi4/testbench/TbAxi4.vhd
@@ -133,15 +133,15 @@ begin
 
   ------------------------------------------------------------
   -- create Clock
-  Osvvm.TbUtilPkg.CreateClock (
+  Osvvm.ClockResetPkg.CreateClock (
   ------------------------------------------------------------
     Clk        => Clk,
     Period     => Tperiod_Clk
   )  ;
 
   ------------------------------------------------------------
   -- create nReset
-  Osvvm.TbUtilPkg.CreateReset (
+  Osvvm.ClockResetPkg.CreateReset (
   ------------------------------------------------------------
     Reset       => nReset,
     ResetActive => '0',
diff --git a/Axi4/testbench/TbAxi4Memory.vhd b/Axi4/testbench/TbAxi4Memory.vhd
@@ -118,15 +118,15 @@ begin
 
   ------------------------------------------------------------
   -- create Clock
-  Osvvm.TbUtilPkg.CreateClock (
+  Osvvm.ClockResetPkg.CreateClock (
   ------------------------------------------------------------
     Clk        => Clk,
     Period     => Tperiod_Clk
   )  ;
 
   ------------------------------------------------------------
   -- create nReset
-  Osvvm.TbUtilPkg.CreateReset (
+  Osvvm.ClockResetPkg.CreateReset (
   ------------------------------------------------------------
     Reset       => nReset,
     ResetActive => '0',
diff --git a/Axi4/testbenchVti/TbAxi4.vhd b/Axi4/testbenchVti/TbAxi4.vhd
@@ -107,13 +107,13 @@ architecture TestHarness of TbAxi4 is
 begin
 
   -- create Clock
-  Osvvm.TbUtilPkg.CreateClock (
+  Osvvm.ClockResetPkg.CreateClock (
     Clk        => Clk,
     Period     => Tperiod_Clk
   )  ;
 
   -- create nReset
-  Osvvm.TbUtilPkg.CreateReset (
+  Osvvm.ClockResetPkg.CreateReset (
     Reset       => nReset,
     ResetActive => '0',
     Clk         => Clk,
diff --git a/Axi4/testbenchVti/TbAxi4Memory.vhd b/Axi4/testbenchVti/TbAxi4Memory.vhd
@@ -107,13 +107,13 @@ architecture TestHarness of TbAxi4Memory is
 begin
 
   -- create Clock
-  Osvvm.TbUtilPkg.CreateClock (
+  Osvvm.ClockResetPkg.CreateClock (
     Clk        => Clk,
     Period     => Tperiod_Clk
   )  ;
 
   -- create nReset
-  Osvvm.TbUtilPkg.CreateReset (
+  Osvvm.ClockResetPkg.CreateReset (
     Reset       => nReset,
     ResetActive => '0',
     Clk         => Clk,
diff --git a/Axi4/testbench_MultipleMemory/TbAxi4_MultipleMemory.vhd b/Axi4/testbench_MultipleMemory/TbAxi4_MultipleMemory.vhd
@@ -119,13 +119,13 @@ architecture TestHarness of TbAxi4_MultipleMemory is
 begin
 
   -- create Clock
-  Osvvm.TbUtilPkg.CreateClock (
+  Osvvm.ClockResetPkg.CreateClock (
     Clk        => Clk,
     Period     => Tperiod_Clk
   )  ;
 
   -- create nReset
-  Osvvm.TbUtilPkg.CreateReset (
+  Osvvm.ClockResetPkg.CreateReset (
     Reset       => nReset,
     ResetActive => '0',
     Clk         => Clk,
diff --git a/Axi4/testbench_MultipleMemory/TbAxi4_MultipleMemory_Generate.vhd b/Axi4/testbench_MultipleMemory/TbAxi4_MultipleMemory_Generate.vhd
@@ -121,13 +121,13 @@ architecture TestHarness of TbAxi4_MultipleMemory is
 begin
 
   -- create Clock
-  Osvvm.TbUtilPkg.CreateClock (
+  Osvvm.ClockResetPkg.CreateClock (
     Clk        => Clk,
     Period     => Tperiod_Clk
   )  ;
 
   -- create nReset
-  Osvvm.TbUtilPkg.CreateReset (
+  Osvvm.ClockResetPkg.CreateReset (
     Reset       => nReset,
     ResetActive => '0',
     Clk         => Clk,
diff --git a/Axi4/testbench_interrupt/TbAxi4Memory.vhd b/Axi4/testbench_interrupt/TbAxi4Memory.vhd
@@ -134,15 +134,15 @@ begin
 
   -- create Clock
   ------------------------------------------------------------
-  Osvvm.TbUtilPkg.CreateClock (
+  Osvvm.ClockResetPkg.CreateClock (
   ------------------------------------------------------------
     Clk        => Clk,
     Period     => Tperiod_Clk
   )  ;
 
   -- create nReset
   ------------------------------------------------------------
-  Osvvm.TbUtilPkg.CreateReset (
+  Osvvm.ClockResetPkg.CreateReset (
   ------------------------------------------------------------
     Reset       => nReset,
     ResetActive => '0',
diff --git a/Axi4/testbench_xilinx/TbAxi4.vhd b/Axi4/testbench_xilinx/TbAxi4.vhd
@@ -132,13 +132,13 @@ architecture TestHarness of TbAxi4 is
 begin
 
   -- create Clock
-  Osvvm.TbUtilPkg.CreateClock (
+  Osvvm.ClockResetPkg.CreateClock (
     Clk        => Clk,
     Period     => Tperiod_Clk
   )  ;
 
   -- create nReset
-  Osvvm.TbUtilPkg.CreateReset (
+  Osvvm.ClockResetPkg.CreateReset (
     Reset       => nReset,
     ResetActive => '0',
     Clk         => Clk,
diff --git a/Axi4/testbench_xilinx/TbAxi4Memory.vhd b/Axi4/testbench_xilinx/TbAxi4Memory.vhd
@@ -140,13 +140,13 @@ architecture TestHarness of TbAxi4Memory is
 begin
 
   -- create Clock
-  Osvvm.TbUtilPkg.CreateClock (
+  Osvvm.ClockResetPkg.CreateClock (
     Clk        => Clk,
     Period     => Tperiod_Clk
   )  ;
 
   -- create nReset
-  Osvvm.TbUtilPkg.CreateReset (
+  Osvvm.ClockResetPkg.CreateReset (
     Reset       => nReset,
     ResetActive => '0',
     Clk         => Clk,
diff --git a/Axi4Lite/testbench/TbAxi4.vhd b/Axi4Lite/testbench/TbAxi4.vhd
@@ -96,13 +96,13 @@ architecture TestHarness of TbAxi4 is
 begin
 
   -- create Clock
-  Osvvm.TbUtilPkg.CreateClock (
+  Osvvm.ClockResetPkg.CreateClock (
     Clk        => Clk,
     Period     => Tperiod_Clk
   )  ;
 
   -- create nReset
-  Osvvm.TbUtilPkg.CreateReset (
+  Osvvm.ClockResetPkg.CreateReset (
     Reset       => nReset,
     ResetActive => '0',
     Clk         => Clk,
diff --git a/Axi4Lite/testbench/TbAxi4Memory.vhd b/Axi4Lite/testbench/TbAxi4Memory.vhd
@@ -96,13 +96,13 @@ architecture TestHarness of TbAxi4Memory is
 begin
 
   -- create Clock
-  Osvvm.TbUtilPkg.CreateClock (
+  Osvvm.ClockResetPkg.CreateClock (
     Clk        => Clk,
     Period     => Tperiod_Clk
   )  ;
 
   -- create nReset
-  Osvvm.TbUtilPkg.CreateReset (
+  Osvvm.ClockResetPkg.CreateReset (
     Reset       => nReset,
     ResetActive => '0',
     Clk         => Clk,
diff --git a/AxiStream/testbench/TbStream.vhd b/AxiStream/testbench/TbStream.vhd
@@ -137,13 +137,13 @@ begin
     ) ;
 
   -- create Clock 
-  Osvvm.TbUtilPkg.CreateClock ( 
+  Osvvm.ClockResetPkg.CreateClock ( 
     Clk        => Clk, 
     Period     => Tperiod_Clk 
   )  ; 
   
   -- create nReset 
-  Osvvm.TbUtilPkg.CreateReset ( 
+  Osvvm.ClockResetPkg.CreateReset ( 
     Reset       => nReset,
     ResetActive => '0',
     Clk         => Clk,
diff --git a/AxiStream/testbenchVti/TbStream.vhd b/AxiStream/testbenchVti/TbStream.vhd
@@ -79,13 +79,13 @@ architecture TestHarness of TbStream is
 begin
 
   -- create Clock 
-  Osvvm.TbUtilPkg.CreateClock ( 
+  Osvvm.ClockResetPkg.CreateClock ( 
     Clk        => Clk, 
     Period     => Tperiod_Clk 
   )  ; 
   
   -- create nReset 
-  Osvvm.TbUtilPkg.CreateReset ( 
+  Osvvm.ClockResetPkg.CreateReset ( 
     Reset       => nReset,
     ResetActive => '0',
     Clk         => Clk,
diff --git a/AxiStream/testbenchVti_Alt/TbStream.vhd b/AxiStream/testbenchVti_Alt/TbStream.vhd
@@ -83,13 +83,13 @@ architecture TestHarness of TbStream is
 begin
 
   -- create Clock 
-  Osvvm.TbUtilPkg.CreateClock ( 
+  Osvvm.ClockResetPkg.CreateClock ( 
     Clk        => Clk, 
     Period     => Tperiod_Clk 
   )  ; 
   
   -- create nReset 
-  Osvvm.TbUtilPkg.CreateReset ( 
+  Osvvm.ClockResetPkg.CreateReset ( 
     Reset       => nReset,
     ResetActive => '0',
     Clk         => Clk,
diff --git a/AxiStream/testbench_xilinx/TbStream.vhd b/AxiStream/testbench_xilinx/TbStream.vhd
@@ -137,13 +137,13 @@ begin
     ) ;
 
   -- create Clock 
-  Osvvm.TbUtilPkg.CreateClock ( 
+  Osvvm.ClockResetPkg.CreateClock ( 
     Clk        => Clk, 
     Period     => Tperiod_Clk 
   )  ; 
   
   -- create nReset 
-  Osvvm.TbUtilPkg.CreateReset ( 
+  Osvvm.ClockResetPkg.CreateReset ( 
     Reset       => nReset,
     ResetActive => '0',
     Clk         => Clk,
