False errors reported in PSL statements

[JakubFranek]

Hello,

I am using the vhdl-ls linter as integrated inside TerosHDL extension in VS Code.

I have a VHDL file, which I attach here: clock_enable_generator.txt (I had to change the extension to .txt because GitHub does not allow .vhd extensions).

The file had no vhdl-ls linter errors until I added these two statements:

1. default clock is rising_edge(i_clk);
2. pulse_clk_count : assert always {reg_counter = COUNTER_MAX - 1} | => {o_clk_ena = '1'} report "o_clk_ena pulse not activated when expected" severity failure;

Both of these two lines produce the following errors:

I believe these are false errors as these PSL-like statements are valid in VHDL-2008 and the code runs fine by GHDL.

Are PSL-like statements not supported by vhdl-ls yet?

Please let me know if you need further information. Thank you for your assistance.

Kind regards
Jakub

[Schottkyc137]

Are PSL-like statements not supported by vhdl-ls yet?

Yes, PSL is not supported yet, unfortunately.

[JakubFranek]

That is unfortunate. Thank you for your answer.

[JakubFranek]

Follow up question. Is there perhaps some kind of a comment keyword that I could wrap arround PSL code so that VHDL LS does not consider the code that is wrapped and therefore does not produce false errors?

Something like this:

-- vhdl_ls off
PSL statements here
-- vhdl_ls on