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| 1 | +// Copyright (c) 2016-2017 Utero OS Developers. See the COPYRIGHT |
| 2 | +// file at the top-level directory of this distribution. |
| 3 | +// |
| 4 | +// Licensed under the Apache License, Version 2.0 <LICENSE-APACHE or |
| 5 | +// http://www.apache.org/licenses/LICENSE-2.0> or the MIT license |
| 6 | +// <LICENSE-MIT or http://opensource.org/licenses/MIT>, at your |
| 7 | +// option. This file may not be copied, modified, or distributed |
| 8 | +// except according to those terms. |
| 9 | +// |
| 10 | +// The part of this file was taken from: |
| 11 | +// https://github.com/RWTH-OS/eduOS/blob/master/arch/x86/include/asm/processor.h |
| 12 | + |
| 13 | +#ifndef ASM_PROCESSOR_H |
| 14 | +#define ASM_PROCESSOR_H |
| 15 | + |
| 16 | +#include <asm/stddef.h> |
| 17 | + |
| 18 | +// rdtsc (Read-time stamp counter) |
| 19 | +// return the 64-bit time stamp value |
| 20 | +inline static uint64_t |
| 21 | +rdtsc(void) |
| 22 | +{ |
| 23 | + uint64_t lo, hi; |
| 24 | + asm volatile("rdtsc" : "=a"(lo), "=d"(hi)); |
| 25 | + return (hi << 32 | lo); |
| 26 | +} |
| 27 | + |
| 28 | +// wbinvd asm instruction(Write back and invalidate cache) |
| 29 | +inline static void |
| 30 | +flush_cache(void) |
| 31 | +{ |
| 32 | + asm volatile("wbinvd" ::: "memory"); |
| 33 | +} |
| 34 | + |
| 35 | +// invd asm instruction (Invalidate internal caches - without writing back) |
| 36 | +inline static void |
| 37 | +invalid_cache(void) |
| 38 | +{ |
| 39 | + asm volatile("invd"); |
| 40 | +} |
| 41 | + |
| 42 | +// NOTE: mb, rmb, wmb will be moved to arch/x86_64/c/processor.c |
| 43 | +// and used via extern func_memory_barrier (mb|rmb|wmb) |
| 44 | + |
| 45 | +// mb (Memory barrier) |
| 46 | +// mfence asm instruction (Memory Fence - Serializes load and store operations) |
| 47 | +inline static void |
| 48 | +mb(void) |
| 49 | +{ |
| 50 | + asm volatile("mfence" ::: "memory"); |
| 51 | +} |
| 52 | + |
| 53 | +// rmb (Read memory barrier) |
| 54 | +// lfence asm instruction (Load Fence - Serializes load operations) |
| 55 | +inline static void |
| 56 | +rmb(void) |
| 57 | +{ |
| 58 | + asm volatile("lfence" ::: "memory"); |
| 59 | +} |
| 60 | + |
| 61 | +// wmb (Write memory barrier) |
| 62 | +// sfence asm instruction (Store Fence - Serializes store operations) |
| 63 | +inline static void |
| 64 | +wmb(void) |
| 65 | +{ |
| 66 | + asm volatile("sfence" ::: "memory"); |
| 67 | +} |
| 68 | + |
| 69 | +// search the most significant bit |
| 70 | +// bsr (Bit Scan Reverse) asm instruction |
| 71 | +static inline size_t |
| 72 | +msb(size_t i) |
| 73 | +{ |
| 74 | + size_t ret; |
| 75 | + |
| 76 | + if (!i) { |
| 77 | + return (sizeof(size_t) * 8); |
| 78 | + } |
| 79 | + asm volatile("bsr %1, %0" : "=r"(ret) : "r"(i) : "cc"); |
| 80 | + |
| 81 | + return ret; |
| 82 | +} |
| 83 | + |
| 84 | +// search the least significant bit |
| 85 | +// bsf (Bit Scan Forward) asm instruction |
| 86 | +static inline size_t |
| 87 | +lsb(size_t i) |
| 88 | +{ |
| 89 | + size_t ret; |
| 90 | + |
| 91 | + if (!i) { |
| 92 | + return (sizeof(size_t) * 8); |
| 93 | + } |
| 94 | + asm volatile("bsf %1, %0" : "=r"(ret) : "r"(i) : "cc"); |
| 95 | + |
| 96 | + return ret; |
| 97 | +} |
| 98 | + |
| 99 | +// A one-instruction-do-nothing |
| 100 | +#define NOP1 asm volatile("nop") |
| 101 | +// A two-instruction-do-nothing |
| 102 | +#define NOP2 asm volatile("nop;nop") |
| 103 | +// A four-instruction-do-nothing |
| 104 | +#define NOP4 asm volatile("nop;nop;nop;nop") |
| 105 | +// A eight-instruction-do-nothing |
| 106 | +#define NOP8 asm volatile("nop;nop;nop;nop;nop;nop;nop;nop") |
| 107 | + |
| 108 | +#endif /* end of include guard: ASM_PROCESSOR_H */ |
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